8 void register_machines(void)
10 qemu_register_machine(&pc_machine
);
11 qemu_register_machine(&isapc_machine
);
14 static void cpu_put_seg(QEMUFile
*f
, SegmentCache
*dt
)
16 qemu_put_be32(f
, dt
->selector
);
17 qemu_put_betl(f
, dt
->base
);
18 qemu_put_be32(f
, dt
->limit
);
19 qemu_put_be32(f
, dt
->flags
);
22 static void cpu_get_seg(QEMUFile
*f
, SegmentCache
*dt
)
24 dt
->selector
= qemu_get_be32(f
);
25 dt
->base
= qemu_get_betl(f
);
26 dt
->limit
= qemu_get_be32(f
);
27 dt
->flags
= qemu_get_be32(f
);
30 void cpu_save(QEMUFile
*f
, void *opaque
)
32 CPUState
*env
= opaque
;
33 uint16_t fptag
, fpus
, fpuc
, fpregs_format
;
38 for(i
= 0; i
< CPU_NB_REGS
; i
++)
39 qemu_put_betls(f
, &env
->regs
[i
]);
40 qemu_put_betls(f
, &env
->eip
);
41 qemu_put_betls(f
, &env
->eflags
);
42 hflags
= env
->hflags
; /* XXX: suppress most of the redundant hflags */
43 qemu_put_be32s(f
, &hflags
);
47 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
49 for(i
= 0; i
< 8; i
++) {
50 fptag
|= ((!env
->fptags
[i
]) << i
);
53 qemu_put_be16s(f
, &fpuc
);
54 qemu_put_be16s(f
, &fpus
);
55 qemu_put_be16s(f
, &fptag
);
62 qemu_put_be16s(f
, &fpregs_format
);
64 for(i
= 0; i
< 8; i
++) {
69 /* we save the real CPU data (in case of MMX usage only 'mant'
70 contains the MMX register */
71 cpu_get_fp80(&mant
, &exp
, env
->fpregs
[i
].d
);
72 qemu_put_be64(f
, mant
);
73 qemu_put_be16(f
, exp
);
76 /* if we use doubles for float emulation, we save the doubles to
77 avoid losing information in case of MMX usage. It can give
78 problems if the image is restored on a CPU where long
79 doubles are used instead. */
80 qemu_put_be64(f
, env
->fpregs
[i
].mmx
.MMX_Q(0));
84 for(i
= 0; i
< 6; i
++)
85 cpu_put_seg(f
, &env
->segs
[i
]);
86 cpu_put_seg(f
, &env
->ldt
);
87 cpu_put_seg(f
, &env
->tr
);
88 cpu_put_seg(f
, &env
->gdt
);
89 cpu_put_seg(f
, &env
->idt
);
91 qemu_put_be32s(f
, &env
->sysenter_cs
);
92 qemu_put_betls(f
, &env
->sysenter_esp
);
93 qemu_put_betls(f
, &env
->sysenter_eip
);
95 qemu_put_betls(f
, &env
->cr
[0]);
96 qemu_put_betls(f
, &env
->cr
[2]);
97 qemu_put_betls(f
, &env
->cr
[3]);
98 qemu_put_betls(f
, &env
->cr
[4]);
100 for(i
= 0; i
< 8; i
++)
101 qemu_put_betls(f
, &env
->dr
[i
]);
104 a20_mask
= (int32_t) env
->a20_mask
;
105 qemu_put_sbe32s(f
, &a20_mask
);
108 qemu_put_be32s(f
, &env
->mxcsr
);
109 for(i
= 0; i
< CPU_NB_REGS
; i
++) {
110 qemu_put_be64s(f
, &env
->xmm_regs
[i
].XMM_Q(0));
111 qemu_put_be64s(f
, &env
->xmm_regs
[i
].XMM_Q(1));
115 qemu_put_be64s(f
, &env
->efer
);
116 qemu_put_be64s(f
, &env
->star
);
117 qemu_put_be64s(f
, &env
->lstar
);
118 qemu_put_be64s(f
, &env
->cstar
);
119 qemu_put_be64s(f
, &env
->fmask
);
120 qemu_put_be64s(f
, &env
->kernelgsbase
);
122 qemu_put_be32s(f
, &env
->smbase
);
124 qemu_put_be64s(f
, &env
->pat
);
125 qemu_put_be32s(f
, &env
->hflags2
);
127 qemu_put_be64s(f
, &env
->vm_hsave
);
128 qemu_put_be64s(f
, &env
->vm_vmcb
);
129 qemu_put_be64s(f
, &env
->tsc_offset
);
130 qemu_put_be64s(f
, &env
->intercept
);
131 qemu_put_be16s(f
, &env
->intercept_cr_read
);
132 qemu_put_be16s(f
, &env
->intercept_cr_write
);
133 qemu_put_be16s(f
, &env
->intercept_dr_read
);
134 qemu_put_be16s(f
, &env
->intercept_dr_write
);
135 qemu_put_be32s(f
, &env
->intercept_exceptions
);
136 qemu_put_8s(f
, &env
->v_tpr
);
139 #ifdef USE_X86LDOUBLE
140 /* XXX: add that in a FPU generic layer */
141 union x86_longdouble
{
146 #define MANTD1(fp) (fp & ((1LL << 52) - 1))
147 #define EXPBIAS1 1023
148 #define EXPD1(fp) ((fp >> 52) & 0x7FF)
149 #define SIGND1(fp) ((fp >> 32) & 0x80000000)
151 static void fp64_to_fp80(union x86_longdouble
*p
, uint64_t temp
)
155 p
->mant
= (MANTD1(temp
) << 11) | (1LL << 63);
156 /* exponent + sign */
157 e
= EXPD1(temp
) - EXPBIAS1
+ 16383;
158 e
|= SIGND1(temp
) >> 16;
163 int cpu_load(QEMUFile
*f
, void *opaque
, int version_id
)
165 CPUState
*env
= opaque
;
168 uint16_t fpus
, fpuc
, fptag
, fpregs_format
;
171 if (version_id
!= 3 && version_id
!= 4 && version_id
!= 5
172 && version_id
!= 6 && version_id
!= 7)
174 for(i
= 0; i
< CPU_NB_REGS
; i
++)
175 qemu_get_betls(f
, &env
->regs
[i
]);
176 qemu_get_betls(f
, &env
->eip
);
177 qemu_get_betls(f
, &env
->eflags
);
178 qemu_get_be32s(f
, &hflags
);
180 qemu_get_be16s(f
, &fpuc
);
181 qemu_get_be16s(f
, &fpus
);
182 qemu_get_be16s(f
, &fptag
);
183 qemu_get_be16s(f
, &fpregs_format
);
185 /* NOTE: we cannot always restore the FPU state if the image come
186 from a host with a different 'USE_X86LDOUBLE' define. We guess
187 if we are in an MMX state to restore correctly in that case. */
188 guess_mmx
= ((fptag
== 0xff) && (fpus
& 0x3800) == 0);
189 for(i
= 0; i
< 8; i
++) {
193 switch(fpregs_format
) {
195 mant
= qemu_get_be64(f
);
196 exp
= qemu_get_be16(f
);
197 #ifdef USE_X86LDOUBLE
198 env
->fpregs
[i
].d
= cpu_set_fp80(mant
, exp
);
202 env
->fpregs
[i
].mmx
.MMX_Q(0) = mant
;
204 env
->fpregs
[i
].d
= cpu_set_fp80(mant
, exp
);
208 mant
= qemu_get_be64(f
);
209 #ifdef USE_X86LDOUBLE
211 union x86_longdouble
*p
;
213 p
= (void *)&env
->fpregs
[i
];
218 fp64_to_fp80(p
, mant
);
222 env
->fpregs
[i
].mmx
.MMX_Q(0) = mant
;
231 /* XXX: restore FPU round state */
232 env
->fpstt
= (fpus
>> 11) & 7;
233 env
->fpus
= fpus
& ~0x3800;
235 for(i
= 0; i
< 8; i
++) {
236 env
->fptags
[i
] = (fptag
>> i
) & 1;
239 for(i
= 0; i
< 6; i
++)
240 cpu_get_seg(f
, &env
->segs
[i
]);
241 cpu_get_seg(f
, &env
->ldt
);
242 cpu_get_seg(f
, &env
->tr
);
243 cpu_get_seg(f
, &env
->gdt
);
244 cpu_get_seg(f
, &env
->idt
);
246 qemu_get_be32s(f
, &env
->sysenter_cs
);
247 if (version_id
>= 7) {
248 qemu_get_betls(f
, &env
->sysenter_esp
);
249 qemu_get_betls(f
, &env
->sysenter_eip
);
251 env
->sysenter_esp
= qemu_get_be32(f
);
252 env
->sysenter_eip
= qemu_get_be32(f
);
255 qemu_get_betls(f
, &env
->cr
[0]);
256 qemu_get_betls(f
, &env
->cr
[2]);
257 qemu_get_betls(f
, &env
->cr
[3]);
258 qemu_get_betls(f
, &env
->cr
[4]);
260 for(i
= 0; i
< 8; i
++)
261 qemu_get_betls(f
, &env
->dr
[i
]);
262 cpu_breakpoint_remove_all(env
, BP_CPU
);
263 cpu_watchpoint_remove_all(env
, BP_CPU
);
264 for (i
= 0; i
< 4; i
++)
265 hw_breakpoint_insert(env
, i
);
268 qemu_get_sbe32s(f
, &a20_mask
);
269 env
->a20_mask
= a20_mask
;
271 qemu_get_be32s(f
, &env
->mxcsr
);
272 for(i
= 0; i
< CPU_NB_REGS
; i
++) {
273 qemu_get_be64s(f
, &env
->xmm_regs
[i
].XMM_Q(0));
274 qemu_get_be64s(f
, &env
->xmm_regs
[i
].XMM_Q(1));
278 qemu_get_be64s(f
, &env
->efer
);
279 qemu_get_be64s(f
, &env
->star
);
280 qemu_get_be64s(f
, &env
->lstar
);
281 qemu_get_be64s(f
, &env
->cstar
);
282 qemu_get_be64s(f
, &env
->fmask
);
283 qemu_get_be64s(f
, &env
->kernelgsbase
);
285 if (version_id
>= 4) {
286 qemu_get_be32s(f
, &env
->smbase
);
288 if (version_id
>= 5) {
289 qemu_get_be64s(f
, &env
->pat
);
290 qemu_get_be32s(f
, &env
->hflags2
);
292 qemu_get_be32s(f
, &env
->halted
);
294 qemu_get_be64s(f
, &env
->vm_hsave
);
295 qemu_get_be64s(f
, &env
->vm_vmcb
);
296 qemu_get_be64s(f
, &env
->tsc_offset
);
297 qemu_get_be64s(f
, &env
->intercept
);
298 qemu_get_be16s(f
, &env
->intercept_cr_read
);
299 qemu_get_be16s(f
, &env
->intercept_cr_write
);
300 qemu_get_be16s(f
, &env
->intercept_dr_read
);
301 qemu_get_be16s(f
, &env
->intercept_dr_write
);
302 qemu_get_be32s(f
, &env
->intercept_exceptions
);
303 qemu_get_8s(f
, &env
->v_tpr
);
305 /* XXX: ensure compatiblity for halted bit ? */
306 /* XXX: compute redundant hflags bits */
307 env
->hflags
= hflags
;