2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 static const char * const tcg_target_reg_names
[TCG_TARGET_NB_REGS
] = {
46 static const int tcg_target_reg_alloc_order
[] = {
65 static const int tcg_target_call_iarg_regs
[6] = {
74 static const int tcg_target_call_oarg_regs
[2] = {
79 static uint8_t *tb_ret_addr
;
81 static void patch_reloc(uint8_t *code_ptr
, int type
,
82 tcg_target_long value
, tcg_target_long addend
)
87 if (value
!= (uint32_t)value
)
89 *(uint32_t *)code_ptr
= value
;
92 if (value
!= (int32_t)value
)
94 *(uint32_t *)code_ptr
= value
;
97 value
-= (long)code_ptr
;
98 if (value
!= (int32_t)value
)
100 *(uint32_t *)code_ptr
= value
;
107 /* maximum number of register used for input function arguments */
108 static inline int tcg_target_get_call_iarg_regs_count(int flags
)
113 /* parse target specific constraints */
114 static int target_parse_constraint(TCGArgConstraint
*ct
, const char **pct_str
)
121 ct
->ct
|= TCG_CT_REG
;
122 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RAX
);
125 ct
->ct
|= TCG_CT_REG
;
126 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RBX
);
129 ct
->ct
|= TCG_CT_REG
;
130 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RCX
);
133 ct
->ct
|= TCG_CT_REG
;
134 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RDX
);
137 ct
->ct
|= TCG_CT_REG
;
138 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RSI
);
141 ct
->ct
|= TCG_CT_REG
;
142 tcg_regset_set_reg(ct
->u
.regs
, TCG_REG_RDI
);
145 ct
->ct
|= TCG_CT_REG
;
146 tcg_regset_set32(ct
->u
.regs
, 0, 0xf);
149 ct
->ct
|= TCG_CT_REG
;
150 tcg_regset_set32(ct
->u
.regs
, 0, 0xffff);
152 case 'L': /* qemu_ld/st constraint */
153 ct
->ct
|= TCG_CT_REG
;
154 tcg_regset_set32(ct
->u
.regs
, 0, 0xffff);
155 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_RSI
);
156 tcg_regset_reset_reg(ct
->u
.regs
, TCG_REG_RDI
);
159 ct
->ct
|= TCG_CT_CONST_S32
;
162 ct
->ct
|= TCG_CT_CONST_U32
;
172 /* test if a constant matches the constraint */
173 static inline int tcg_target_const_match(tcg_target_long val
,
174 const TCGArgConstraint
*arg_ct
)
178 if (ct
& TCG_CT_CONST
)
180 else if ((ct
& TCG_CT_CONST_S32
) && val
== (int32_t)val
)
182 else if ((ct
& TCG_CT_CONST_U32
) && val
== (uint32_t)val
)
219 #define P_EXT 0x100 /* 0x0f opcode prefix */
220 #define P_REXW 0x200 /* set rex.w = 1 */
221 #define P_REXB 0x400 /* force rex use for byte registers */
223 static const uint8_t tcg_cond_to_jcc
[10] = {
224 [TCG_COND_EQ
] = JCC_JE
,
225 [TCG_COND_NE
] = JCC_JNE
,
226 [TCG_COND_LT
] = JCC_JL
,
227 [TCG_COND_GE
] = JCC_JGE
,
228 [TCG_COND_LE
] = JCC_JLE
,
229 [TCG_COND_GT
] = JCC_JG
,
230 [TCG_COND_LTU
] = JCC_JB
,
231 [TCG_COND_GEU
] = JCC_JAE
,
232 [TCG_COND_LEU
] = JCC_JBE
,
233 [TCG_COND_GTU
] = JCC_JA
,
236 static inline void tcg_out_opc(TCGContext
*s
, int opc
, int r
, int rm
, int x
)
239 rex
= ((opc
>> 6) & 0x8) | ((r
>> 1) & 0x4) |
240 ((x
>> 2) & 2) | ((rm
>> 3) & 1);
241 if (rex
|| (opc
& P_REXB
)) {
242 tcg_out8(s
, rex
| 0x40);
249 static inline void tcg_out_modrm(TCGContext
*s
, int opc
, int r
, int rm
)
251 tcg_out_opc(s
, opc
, r
, rm
, 0);
252 tcg_out8(s
, 0xc0 | ((r
& 7) << 3) | (rm
& 7));
255 /* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
256 static inline void tcg_out_modrm_offset(TCGContext
*s
, int opc
, int r
, int rm
,
257 tcg_target_long offset
)
261 tcg_out_opc(s
, opc
, r
, 0, 0);
262 val
= offset
- ((tcg_target_long
)s
->code_ptr
+ 5 + (-rm
- 1));
263 if (val
== (int32_t)val
) {
265 tcg_out8(s
, 0x05 | ((r
& 7) << 3));
267 } else if (offset
== (int32_t)offset
) {
268 tcg_out8(s
, 0x04 | ((r
& 7) << 3));
269 tcg_out8(s
, 0x25); /* sib */
270 tcg_out32(s
, offset
);
274 } else if (offset
== 0 && (rm
& 7) != TCG_REG_RBP
) {
275 tcg_out_opc(s
, opc
, r
, rm
, 0);
276 if ((rm
& 7) == TCG_REG_RSP
) {
277 tcg_out8(s
, 0x04 | ((r
& 7) << 3));
280 tcg_out8(s
, 0x00 | ((r
& 7) << 3) | (rm
& 7));
282 } else if ((int8_t)offset
== offset
) {
283 tcg_out_opc(s
, opc
, r
, rm
, 0);
284 if ((rm
& 7) == TCG_REG_RSP
) {
285 tcg_out8(s
, 0x44 | ((r
& 7) << 3));
288 tcg_out8(s
, 0x40 | ((r
& 7) << 3) | (rm
& 7));
292 tcg_out_opc(s
, opc
, r
, rm
, 0);
293 if ((rm
& 7) == TCG_REG_RSP
) {
294 tcg_out8(s
, 0x84 | ((r
& 7) << 3));
297 tcg_out8(s
, 0x80 | ((r
& 7) << 3) | (rm
& 7));
299 tcg_out32(s
, offset
);
303 #if defined(CONFIG_SOFTMMU)
304 /* XXX: incomplete. index must be different from ESP */
305 static void tcg_out_modrm_offset2(TCGContext
*s
, int opc
, int r
, int rm
,
306 int index
, int shift
,
307 tcg_target_long offset
)
312 if (offset
== 0 && (rm
& 7) != TCG_REG_RBP
) {
314 } else if (offset
== (int8_t)offset
) {
316 } else if (offset
== (int32_t)offset
) {
322 tcg_out_opc(s
, opc
, r
, rm
, 0);
323 if ((rm
& 7) == TCG_REG_RSP
) {
324 tcg_out8(s
, mod
| ((r
& 7) << 3) | 0x04);
325 tcg_out8(s
, 0x04 | (rm
& 7));
327 tcg_out8(s
, mod
| ((r
& 7) << 3) | (rm
& 7));
330 tcg_out_opc(s
, opc
, r
, rm
, index
);
331 tcg_out8(s
, mod
| ((r
& 7) << 3) | 0x04);
332 tcg_out8(s
, (shift
<< 6) | ((index
& 7) << 3) | (rm
& 7));
336 } else if (mod
== 0x80) {
337 tcg_out32(s
, offset
);
342 static inline void tcg_out_mov(TCGContext
*s
, int ret
, int arg
)
344 tcg_out_modrm(s
, 0x8b | P_REXW
, ret
, arg
);
347 static inline void tcg_out_movi(TCGContext
*s
, TCGType type
,
348 int ret
, tcg_target_long arg
)
351 tcg_out_modrm(s
, 0x01 | (ARITH_XOR
<< 3), ret
, ret
); /* xor r0,r0 */
352 } else if (arg
== (uint32_t)arg
|| type
== TCG_TYPE_I32
) {
353 tcg_out_opc(s
, 0xb8 + (ret
& 7), 0, ret
, 0);
355 } else if (arg
== (int32_t)arg
) {
356 tcg_out_modrm(s
, 0xc7 | P_REXW
, 0, ret
);
359 tcg_out_opc(s
, (0xb8 + (ret
& 7)) | P_REXW
, 0, ret
, 0);
361 tcg_out32(s
, arg
>> 32);
365 static inline void tcg_out_ld(TCGContext
*s
, TCGType type
, int ret
,
366 int arg1
, tcg_target_long arg2
)
368 if (type
== TCG_TYPE_I32
)
369 tcg_out_modrm_offset(s
, 0x8b, ret
, arg1
, arg2
); /* movl */
371 tcg_out_modrm_offset(s
, 0x8b | P_REXW
, ret
, arg1
, arg2
); /* movq */
374 static inline void tcg_out_st(TCGContext
*s
, TCGType type
, int arg
,
375 int arg1
, tcg_target_long arg2
)
377 if (type
== TCG_TYPE_I32
)
378 tcg_out_modrm_offset(s
, 0x89, arg
, arg1
, arg2
); /* movl */
380 tcg_out_modrm_offset(s
, 0x89 | P_REXW
, arg
, arg1
, arg2
); /* movq */
383 static inline void tgen_arithi32(TCGContext
*s
, int c
, int r0
, int32_t val
)
385 if (val
== (int8_t)val
) {
386 tcg_out_modrm(s
, 0x83, c
, r0
);
388 } else if (c
== ARITH_AND
&& val
== 0xffu
) {
390 tcg_out_modrm(s
, 0xb6 | P_EXT
| P_REXB
, r0
, r0
);
391 } else if (c
== ARITH_AND
&& val
== 0xffffu
) {
393 tcg_out_modrm(s
, 0xb7 | P_EXT
, r0
, r0
);
395 tcg_out_modrm(s
, 0x81, c
, r0
);
400 static inline void tgen_arithi64(TCGContext
*s
, int c
, int r0
, int64_t val
)
402 if (val
== (int8_t)val
) {
403 tcg_out_modrm(s
, 0x83 | P_REXW
, c
, r0
);
405 } else if (c
== ARITH_AND
&& val
== 0xffu
) {
407 tcg_out_modrm(s
, 0xb6 | P_EXT
| P_REXW
, r0
, r0
);
408 } else if (c
== ARITH_AND
&& val
== 0xffffu
) {
410 tcg_out_modrm(s
, 0xb7 | P_EXT
| P_REXW
, r0
, r0
);
411 } else if (c
== ARITH_AND
&& val
== 0xffffffffu
) {
412 /* 32-bit mov zero extends */
413 tcg_out_modrm(s
, 0x8b, r0
, r0
);
414 } else if (val
== (int32_t)val
) {
415 tcg_out_modrm(s
, 0x81 | P_REXW
, c
, r0
);
417 } else if (c
== ARITH_AND
&& val
== (uint32_t)val
) {
418 tcg_out_modrm(s
, 0x81, c
, r0
);
425 static void tcg_out_addi(TCGContext
*s
, int reg
, tcg_target_long val
)
428 tgen_arithi64(s
, ARITH_ADD
, reg
, val
);
431 static void tcg_out_jxx(TCGContext
*s
, int opc
, int label_index
)
434 TCGLabel
*l
= &s
->labels
[label_index
];
437 val
= l
->u
.value
- (tcg_target_long
)s
->code_ptr
;
439 if ((int8_t)val1
== val1
) {
443 tcg_out8(s
, 0x70 + opc
);
448 tcg_out32(s
, val
- 5);
451 tcg_out8(s
, 0x80 + opc
);
452 tcg_out32(s
, val
- 6);
460 tcg_out8(s
, 0x80 + opc
);
462 tcg_out_reloc(s
, s
->code_ptr
, R_386_PC32
, label_index
, -4);
467 static void tcg_out_brcond(TCGContext
*s
, int cond
,
468 TCGArg arg1
, TCGArg arg2
, int const_arg2
,
469 int label_index
, int rexw
)
474 tcg_out_modrm(s
, 0x85 | rexw
, arg1
, arg1
);
477 tgen_arithi64(s
, ARITH_CMP
, arg1
, arg2
);
479 tgen_arithi32(s
, ARITH_CMP
, arg1
, arg2
);
482 tcg_out_modrm(s
, 0x01 | (ARITH_CMP
<< 3) | rexw
, arg2
, arg1
);
484 tcg_out_jxx(s
, tcg_cond_to_jcc
[cond
], label_index
);
487 #if defined(CONFIG_SOFTMMU)
489 #include "../../softmmu_defs.h"
491 static void *qemu_ld_helpers
[4] = {
498 static void *qemu_st_helpers
[4] = {
506 static void tcg_out_qemu_ld(TCGContext
*s
, const TCGArg
*args
,
509 int addr_reg
, data_reg
, r0
, r1
, mem_index
, s_bits
, bswap
, rexw
;
510 #if defined(CONFIG_SOFTMMU)
511 uint8_t *label1_ptr
, *label2_ptr
;
522 #if TARGET_LONG_BITS == 32
527 #if defined(CONFIG_SOFTMMU)
529 tcg_out_modrm(s
, 0x8b | rexw
, r1
, addr_reg
);
532 tcg_out_modrm(s
, 0x8b | rexw
, r0
, addr_reg
);
534 tcg_out_modrm(s
, 0xc1 | rexw
, 5, r1
); /* shr $x, r1 */
535 tcg_out8(s
, TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
);
537 tcg_out_modrm(s
, 0x81 | rexw
, 4, r0
); /* andl $x, r0 */
538 tcg_out32(s
, TARGET_PAGE_MASK
| ((1 << s_bits
) - 1));
540 tcg_out_modrm(s
, 0x81, 4, r1
); /* andl $x, r1 */
541 tcg_out32(s
, (CPU_TLB_SIZE
- 1) << CPU_TLB_ENTRY_BITS
);
543 /* lea offset(r1, env), r1 */
544 tcg_out_modrm_offset2(s
, 0x8d | P_REXW
, r1
, r1
, TCG_AREG0
, 0,
545 offsetof(CPUState
, tlb_table
[mem_index
][0].addr_read
));
548 tcg_out_modrm_offset(s
, 0x3b | rexw
, r0
, r1
, 0);
551 tcg_out_modrm(s
, 0x8b | rexw
, r0
, addr_reg
);
554 tcg_out8(s
, 0x70 + JCC_JE
);
555 label1_ptr
= s
->code_ptr
;
558 /* XXX: move that code at the end of the TB */
559 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_RSI
, mem_index
);
561 tcg_out32(s
, (tcg_target_long
)qemu_ld_helpers
[s_bits
] -
562 (tcg_target_long
)s
->code_ptr
- 4);
567 tcg_out_modrm(s
, 0xbe | P_EXT
| P_REXW
, data_reg
, TCG_REG_RAX
);
571 tcg_out_modrm(s
, 0xbf | P_EXT
| P_REXW
, data_reg
, TCG_REG_RAX
);
575 tcg_out_modrm(s
, 0x63 | P_REXW
, data_reg
, TCG_REG_RAX
);
579 tcg_out_modrm(s
, 0xb6 | P_EXT
| P_REXW
, data_reg
, TCG_REG_RAX
);
583 tcg_out_modrm(s
, 0xb7 | P_EXT
| P_REXW
, data_reg
, TCG_REG_RAX
);
588 tcg_out_modrm(s
, 0x8b, data_reg
, TCG_REG_RAX
);
591 tcg_out_mov(s
, data_reg
, TCG_REG_RAX
);
597 label2_ptr
= s
->code_ptr
;
601 *label1_ptr
= s
->code_ptr
- label1_ptr
- 1;
604 tcg_out_modrm_offset(s
, 0x03 | P_REXW
, r0
, r1
, offsetof(CPUTLBEntry
, addend
) -
605 offsetof(CPUTLBEntry
, addr_read
));
610 #ifdef TARGET_WORDS_BIGENDIAN
618 tcg_out_modrm_offset(s
, 0xb6 | P_EXT
, data_reg
, r0
, 0);
622 tcg_out_modrm_offset(s
, 0xbe | P_EXT
| rexw
, data_reg
, r0
, 0);
626 tcg_out_modrm_offset(s
, 0xb7 | P_EXT
, data_reg
, r0
, 0);
628 /* rolw $8, data_reg */
630 tcg_out_modrm(s
, 0xc1, 0, data_reg
);
637 tcg_out_modrm_offset(s
, 0xb7 | P_EXT
, data_reg
, r0
, 0);
638 /* rolw $8, data_reg */
640 tcg_out_modrm(s
, 0xc1, 0, data_reg
);
643 /* movswX data_reg, data_reg */
644 tcg_out_modrm(s
, 0xbf | P_EXT
| rexw
, data_reg
, data_reg
);
647 tcg_out_modrm_offset(s
, 0xbf | P_EXT
| rexw
, data_reg
, r0
, 0);
651 /* movl (r0), data_reg */
652 tcg_out_modrm_offset(s
, 0x8b, data_reg
, r0
, 0);
655 tcg_out_opc(s
, (0xc8 + (data_reg
& 7)) | P_EXT
, 0, data_reg
, 0);
660 /* movl (r0), data_reg */
661 tcg_out_modrm_offset(s
, 0x8b, data_reg
, r0
, 0);
663 tcg_out_opc(s
, (0xc8 + (data_reg
& 7)) | P_EXT
, 0, data_reg
, 0);
665 tcg_out_modrm(s
, 0x63 | P_REXW
, data_reg
, data_reg
);
668 tcg_out_modrm_offset(s
, 0x63 | P_REXW
, data_reg
, r0
, 0);
672 /* movq (r0), data_reg */
673 tcg_out_modrm_offset(s
, 0x8b | P_REXW
, data_reg
, r0
, 0);
676 tcg_out_opc(s
, (0xc8 + (data_reg
& 7)) | P_EXT
| P_REXW
, 0, data_reg
, 0);
683 #if defined(CONFIG_SOFTMMU)
685 *label2_ptr
= s
->code_ptr
- label2_ptr
- 1;
689 static void tcg_out_qemu_st(TCGContext
*s
, const TCGArg
*args
,
692 int addr_reg
, data_reg
, r0
, r1
, mem_index
, s_bits
, bswap
, rexw
;
693 #if defined(CONFIG_SOFTMMU)
694 uint8_t *label1_ptr
, *label2_ptr
;
706 #if TARGET_LONG_BITS == 32
711 #if defined(CONFIG_SOFTMMU)
713 tcg_out_modrm(s
, 0x8b | rexw
, r1
, addr_reg
);
716 tcg_out_modrm(s
, 0x8b | rexw
, r0
, addr_reg
);
718 tcg_out_modrm(s
, 0xc1 | rexw
, 5, r1
); /* shr $x, r1 */
719 tcg_out8(s
, TARGET_PAGE_BITS
- CPU_TLB_ENTRY_BITS
);
721 tcg_out_modrm(s
, 0x81 | rexw
, 4, r0
); /* andl $x, r0 */
722 tcg_out32(s
, TARGET_PAGE_MASK
| ((1 << s_bits
) - 1));
724 tcg_out_modrm(s
, 0x81, 4, r1
); /* andl $x, r1 */
725 tcg_out32(s
, (CPU_TLB_SIZE
- 1) << CPU_TLB_ENTRY_BITS
);
727 /* lea offset(r1, env), r1 */
728 tcg_out_modrm_offset2(s
, 0x8d | P_REXW
, r1
, r1
, TCG_AREG0
, 0,
729 offsetof(CPUState
, tlb_table
[mem_index
][0].addr_write
));
732 tcg_out_modrm_offset(s
, 0x3b | rexw
, r0
, r1
, 0);
735 tcg_out_modrm(s
, 0x8b | rexw
, r0
, addr_reg
);
738 tcg_out8(s
, 0x70 + JCC_JE
);
739 label1_ptr
= s
->code_ptr
;
742 /* XXX: move that code at the end of the TB */
746 tcg_out_modrm(s
, 0xb6 | P_EXT
| P_REXB
, TCG_REG_RSI
, data_reg
);
750 tcg_out_modrm(s
, 0xb7 | P_EXT
, TCG_REG_RSI
, data_reg
);
754 tcg_out_modrm(s
, 0x8b, TCG_REG_RSI
, data_reg
);
758 tcg_out_mov(s
, TCG_REG_RSI
, data_reg
);
761 tcg_out_movi(s
, TCG_TYPE_I32
, TCG_REG_RDX
, mem_index
);
763 tcg_out32(s
, (tcg_target_long
)qemu_st_helpers
[s_bits
] -
764 (tcg_target_long
)s
->code_ptr
- 4);
768 label2_ptr
= s
->code_ptr
;
772 *label1_ptr
= s
->code_ptr
- label1_ptr
- 1;
775 tcg_out_modrm_offset(s
, 0x03 | P_REXW
, r0
, r1
, offsetof(CPUTLBEntry
, addend
) -
776 offsetof(CPUTLBEntry
, addr_write
));
781 #ifdef TARGET_WORDS_BIGENDIAN
789 tcg_out_modrm_offset(s
, 0x88 | P_REXB
, data_reg
, r0
, 0);
793 tcg_out_modrm(s
, 0x8b, r1
, data_reg
); /* movl */
794 tcg_out8(s
, 0x66); /* rolw $8, %ecx */
795 tcg_out_modrm(s
, 0xc1, 0, r1
);
801 tcg_out_modrm_offset(s
, 0x89, data_reg
, r0
, 0);
805 tcg_out_modrm(s
, 0x8b, r1
, data_reg
); /* movl */
807 tcg_out_opc(s
, (0xc8 + r1
) | P_EXT
, 0, r1
, 0);
811 tcg_out_modrm_offset(s
, 0x89, data_reg
, r0
, 0);
815 tcg_out_mov(s
, r1
, data_reg
);
817 tcg_out_opc(s
, (0xc8 + r1
) | P_EXT
| P_REXW
, 0, r1
, 0);
821 tcg_out_modrm_offset(s
, 0x89 | P_REXW
, data_reg
, r0
, 0);
827 #if defined(CONFIG_SOFTMMU)
829 *label2_ptr
= s
->code_ptr
- label2_ptr
- 1;
833 static inline void tcg_out_op(TCGContext
*s
, int opc
, const TCGArg
*args
,
834 const int *const_args
)
839 case INDEX_op_exit_tb
:
840 tcg_out_movi(s
, TCG_TYPE_PTR
, TCG_REG_RAX
, args
[0]);
841 tcg_out8(s
, 0xe9); /* jmp tb_ret_addr */
842 tcg_out32(s
, tb_ret_addr
- s
->code_ptr
- 4);
844 case INDEX_op_goto_tb
:
845 if (s
->tb_jmp_offset
) {
846 /* direct jump method */
847 tcg_out8(s
, 0xe9); /* jmp im */
848 s
->tb_jmp_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
851 /* indirect jump method */
853 tcg_out_modrm_offset(s
, 0xff, 4, -1,
854 (tcg_target_long
)(s
->tb_next
+
857 s
->tb_next_offset
[args
[0]] = s
->code_ptr
- s
->code_buf
;
862 tcg_out32(s
, args
[0] - (tcg_target_long
)s
->code_ptr
- 4);
864 tcg_out_modrm(s
, 0xff, 2, args
[0]);
870 tcg_out32(s
, args
[0] - (tcg_target_long
)s
->code_ptr
- 4);
872 tcg_out_modrm(s
, 0xff, 4, args
[0]);
876 tcg_out_jxx(s
, JCC_JMP
, args
[0]);
878 case INDEX_op_movi_i32
:
879 tcg_out_movi(s
, TCG_TYPE_I32
, args
[0], (uint32_t)args
[1]);
881 case INDEX_op_movi_i64
:
882 tcg_out_movi(s
, TCG_TYPE_I64
, args
[0], args
[1]);
884 case INDEX_op_ld8u_i32
:
885 case INDEX_op_ld8u_i64
:
887 tcg_out_modrm_offset(s
, 0xb6 | P_EXT
, args
[0], args
[1], args
[2]);
889 case INDEX_op_ld8s_i32
:
891 tcg_out_modrm_offset(s
, 0xbe | P_EXT
, args
[0], args
[1], args
[2]);
893 case INDEX_op_ld8s_i64
:
895 tcg_out_modrm_offset(s
, 0xbe | P_EXT
| P_REXW
, args
[0], args
[1], args
[2]);
897 case INDEX_op_ld16u_i32
:
898 case INDEX_op_ld16u_i64
:
900 tcg_out_modrm_offset(s
, 0xb7 | P_EXT
, args
[0], args
[1], args
[2]);
902 case INDEX_op_ld16s_i32
:
904 tcg_out_modrm_offset(s
, 0xbf | P_EXT
, args
[0], args
[1], args
[2]);
906 case INDEX_op_ld16s_i64
:
908 tcg_out_modrm_offset(s
, 0xbf | P_EXT
| P_REXW
, args
[0], args
[1], args
[2]);
910 case INDEX_op_ld_i32
:
911 case INDEX_op_ld32u_i64
:
913 tcg_out_modrm_offset(s
, 0x8b, args
[0], args
[1], args
[2]);
915 case INDEX_op_ld32s_i64
:
917 tcg_out_modrm_offset(s
, 0x63 | P_REXW
, args
[0], args
[1], args
[2]);
919 case INDEX_op_ld_i64
:
921 tcg_out_modrm_offset(s
, 0x8b | P_REXW
, args
[0], args
[1], args
[2]);
924 case INDEX_op_st8_i32
:
925 case INDEX_op_st8_i64
:
927 tcg_out_modrm_offset(s
, 0x88 | P_REXB
, args
[0], args
[1], args
[2]);
929 case INDEX_op_st16_i32
:
930 case INDEX_op_st16_i64
:
933 tcg_out_modrm_offset(s
, 0x89, args
[0], args
[1], args
[2]);
935 case INDEX_op_st_i32
:
936 case INDEX_op_st32_i64
:
938 tcg_out_modrm_offset(s
, 0x89, args
[0], args
[1], args
[2]);
940 case INDEX_op_st_i64
:
942 tcg_out_modrm_offset(s
, 0x89 | P_REXW
, args
[0], args
[1], args
[2]);
945 case INDEX_op_sub_i32
:
948 case INDEX_op_and_i32
:
951 case INDEX_op_or_i32
:
954 case INDEX_op_xor_i32
:
957 case INDEX_op_add_i32
:
961 tgen_arithi32(s
, c
, args
[0], args
[2]);
963 tcg_out_modrm(s
, 0x01 | (c
<< 3), args
[2], args
[0]);
967 case INDEX_op_sub_i64
:
970 case INDEX_op_and_i64
:
973 case INDEX_op_or_i64
:
976 case INDEX_op_xor_i64
:
979 case INDEX_op_add_i64
:
983 tgen_arithi64(s
, c
, args
[0], args
[2]);
985 tcg_out_modrm(s
, 0x01 | (c
<< 3) | P_REXW
, args
[2], args
[0]);
989 case INDEX_op_mul_i32
:
993 if (val
== (int8_t)val
) {
994 tcg_out_modrm(s
, 0x6b, args
[0], args
[0]);
997 tcg_out_modrm(s
, 0x69, args
[0], args
[0]);
1001 tcg_out_modrm(s
, 0xaf | P_EXT
, args
[0], args
[2]);
1004 case INDEX_op_mul_i64
:
1005 if (const_args
[2]) {
1008 if (val
== (int8_t)val
) {
1009 tcg_out_modrm(s
, 0x6b | P_REXW
, args
[0], args
[0]);
1012 tcg_out_modrm(s
, 0x69 | P_REXW
, args
[0], args
[0]);
1016 tcg_out_modrm(s
, 0xaf | P_EXT
| P_REXW
, args
[0], args
[2]);
1019 case INDEX_op_div2_i32
:
1020 tcg_out_modrm(s
, 0xf7, 7, args
[4]);
1022 case INDEX_op_divu2_i32
:
1023 tcg_out_modrm(s
, 0xf7, 6, args
[4]);
1025 case INDEX_op_div2_i64
:
1026 tcg_out_modrm(s
, 0xf7 | P_REXW
, 7, args
[4]);
1028 case INDEX_op_divu2_i64
:
1029 tcg_out_modrm(s
, 0xf7 | P_REXW
, 6, args
[4]);
1032 case INDEX_op_shl_i32
:
1035 if (const_args
[2]) {
1037 tcg_out_modrm(s
, 0xd1, c
, args
[0]);
1039 tcg_out_modrm(s
, 0xc1, c
, args
[0]);
1040 tcg_out8(s
, args
[2]);
1043 tcg_out_modrm(s
, 0xd3, c
, args
[0]);
1046 case INDEX_op_shr_i32
:
1049 case INDEX_op_sar_i32
:
1053 case INDEX_op_shl_i64
:
1056 if (const_args
[2]) {
1058 tcg_out_modrm(s
, 0xd1 | P_REXW
, c
, args
[0]);
1060 tcg_out_modrm(s
, 0xc1 | P_REXW
, c
, args
[0]);
1061 tcg_out8(s
, args
[2]);
1064 tcg_out_modrm(s
, 0xd3 | P_REXW
, c
, args
[0]);
1067 case INDEX_op_shr_i64
:
1070 case INDEX_op_sar_i64
:
1074 case INDEX_op_brcond_i32
:
1075 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
1078 case INDEX_op_brcond_i64
:
1079 tcg_out_brcond(s
, args
[2], args
[0], args
[1], const_args
[1],
1083 case INDEX_op_bswap_i32
:
1084 tcg_out_opc(s
, (0xc8 + (args
[0] & 7)) | P_EXT
, 0, args
[0], 0);
1086 case INDEX_op_bswap_i64
:
1087 tcg_out_opc(s
, (0xc8 + (args
[0] & 7)) | P_EXT
| P_REXW
, 0, args
[0], 0);
1090 case INDEX_op_neg_i32
:
1091 tcg_out_modrm(s
, 0xf7, 3, args
[0]);
1093 case INDEX_op_neg_i64
:
1094 tcg_out_modrm(s
, 0xf7 | P_REXW
, 3, args
[0]);
1097 case INDEX_op_ext8s_i32
:
1098 tcg_out_modrm(s
, 0xbe | P_EXT
| P_REXB
, args
[0], args
[1]);
1100 case INDEX_op_ext16s_i32
:
1101 tcg_out_modrm(s
, 0xbf | P_EXT
, args
[0], args
[1]);
1103 case INDEX_op_ext8s_i64
:
1104 tcg_out_modrm(s
, 0xbe | P_EXT
| P_REXW
, args
[0], args
[1]);
1106 case INDEX_op_ext16s_i64
:
1107 tcg_out_modrm(s
, 0xbf | P_EXT
| P_REXW
, args
[0], args
[1]);
1109 case INDEX_op_ext32s_i64
:
1110 tcg_out_modrm(s
, 0x63 | P_REXW
, args
[0], args
[1]);
1113 case INDEX_op_qemu_ld8u
:
1114 tcg_out_qemu_ld(s
, args
, 0);
1116 case INDEX_op_qemu_ld8s
:
1117 tcg_out_qemu_ld(s
, args
, 0 | 4);
1119 case INDEX_op_qemu_ld16u
:
1120 tcg_out_qemu_ld(s
, args
, 1);
1122 case INDEX_op_qemu_ld16s
:
1123 tcg_out_qemu_ld(s
, args
, 1 | 4);
1125 case INDEX_op_qemu_ld32u
:
1126 tcg_out_qemu_ld(s
, args
, 2);
1128 case INDEX_op_qemu_ld32s
:
1129 tcg_out_qemu_ld(s
, args
, 2 | 4);
1131 case INDEX_op_qemu_ld64
:
1132 tcg_out_qemu_ld(s
, args
, 3);
1135 case INDEX_op_qemu_st8
:
1136 tcg_out_qemu_st(s
, args
, 0);
1138 case INDEX_op_qemu_st16
:
1139 tcg_out_qemu_st(s
, args
, 1);
1141 case INDEX_op_qemu_st32
:
1142 tcg_out_qemu_st(s
, args
, 2);
1144 case INDEX_op_qemu_st64
:
1145 tcg_out_qemu_st(s
, args
, 3);
1153 static int tcg_target_callee_save_regs
[] = {
1158 /* TCG_REG_R14, */ /* currently used for the global env, so no
1163 static inline void tcg_out_push(TCGContext
*s
, int reg
)
1165 tcg_out_opc(s
, (0x50 + (reg
& 7)), 0, reg
, 0);
1168 static inline void tcg_out_pop(TCGContext
*s
, int reg
)
1170 tcg_out_opc(s
, (0x58 + (reg
& 7)), 0, reg
, 0);
1173 /* Generate global QEMU prologue and epilogue code */
1174 void tcg_target_qemu_prologue(TCGContext
*s
)
1176 int i
, frame_size
, push_size
, stack_addend
;
1179 /* save all callee saved registers */
1180 for(i
= 0; i
< ARRAY_SIZE(tcg_target_callee_save_regs
); i
++) {
1181 tcg_out_push(s
, tcg_target_callee_save_regs
[i
]);
1184 /* reserve some stack space */
1185 push_size
= 8 + ARRAY_SIZE(tcg_target_callee_save_regs
) * 8;
1186 frame_size
= push_size
+ TCG_STATIC_CALL_ARGS_SIZE
;
1187 frame_size
= (frame_size
+ TCG_TARGET_STACK_ALIGN
- 1) &
1188 ~(TCG_TARGET_STACK_ALIGN
- 1);
1189 stack_addend
= frame_size
- push_size
;
1190 tcg_out_addi(s
, TCG_REG_RSP
, -stack_addend
);
1192 tcg_out_modrm(s
, 0xff, 4, TCG_REG_RDI
); /* jmp *%rdi */
1195 tb_ret_addr
= s
->code_ptr
;
1196 tcg_out_addi(s
, TCG_REG_RSP
, stack_addend
);
1197 for(i
= ARRAY_SIZE(tcg_target_callee_save_regs
) - 1; i
>= 0; i
--) {
1198 tcg_out_pop(s
, tcg_target_callee_save_regs
[i
]);
1200 tcg_out8(s
, 0xc3); /* ret */
1203 static const TCGTargetOpDef x86_64_op_defs
[] = {
1204 { INDEX_op_exit_tb
, { } },
1205 { INDEX_op_goto_tb
, { } },
1206 { INDEX_op_call
, { "ri" } }, /* XXX: might need a specific constant constraint */
1207 { INDEX_op_jmp
, { "ri" } }, /* XXX: might need a specific constant constraint */
1208 { INDEX_op_br
, { } },
1210 { INDEX_op_mov_i32
, { "r", "r" } },
1211 { INDEX_op_movi_i32
, { "r" } },
1212 { INDEX_op_ld8u_i32
, { "r", "r" } },
1213 { INDEX_op_ld8s_i32
, { "r", "r" } },
1214 { INDEX_op_ld16u_i32
, { "r", "r" } },
1215 { INDEX_op_ld16s_i32
, { "r", "r" } },
1216 { INDEX_op_ld_i32
, { "r", "r" } },
1217 { INDEX_op_st8_i32
, { "r", "r" } },
1218 { INDEX_op_st16_i32
, { "r", "r" } },
1219 { INDEX_op_st_i32
, { "r", "r" } },
1221 { INDEX_op_add_i32
, { "r", "0", "ri" } },
1222 { INDEX_op_mul_i32
, { "r", "0", "ri" } },
1223 { INDEX_op_div2_i32
, { "a", "d", "0", "1", "r" } },
1224 { INDEX_op_divu2_i32
, { "a", "d", "0", "1", "r" } },
1225 { INDEX_op_sub_i32
, { "r", "0", "ri" } },
1226 { INDEX_op_and_i32
, { "r", "0", "ri" } },
1227 { INDEX_op_or_i32
, { "r", "0", "ri" } },
1228 { INDEX_op_xor_i32
, { "r", "0", "ri" } },
1230 { INDEX_op_shl_i32
, { "r", "0", "ci" } },
1231 { INDEX_op_shr_i32
, { "r", "0", "ci" } },
1232 { INDEX_op_sar_i32
, { "r", "0", "ci" } },
1234 { INDEX_op_brcond_i32
, { "r", "ri" } },
1236 { INDEX_op_mov_i64
, { "r", "r" } },
1237 { INDEX_op_movi_i64
, { "r" } },
1238 { INDEX_op_ld8u_i64
, { "r", "r" } },
1239 { INDEX_op_ld8s_i64
, { "r", "r" } },
1240 { INDEX_op_ld16u_i64
, { "r", "r" } },
1241 { INDEX_op_ld16s_i64
, { "r", "r" } },
1242 { INDEX_op_ld32u_i64
, { "r", "r" } },
1243 { INDEX_op_ld32s_i64
, { "r", "r" } },
1244 { INDEX_op_ld_i64
, { "r", "r" } },
1245 { INDEX_op_st8_i64
, { "r", "r" } },
1246 { INDEX_op_st16_i64
, { "r", "r" } },
1247 { INDEX_op_st32_i64
, { "r", "r" } },
1248 { INDEX_op_st_i64
, { "r", "r" } },
1250 { INDEX_op_add_i64
, { "r", "0", "re" } },
1251 { INDEX_op_mul_i64
, { "r", "0", "re" } },
1252 { INDEX_op_div2_i64
, { "a", "d", "0", "1", "r" } },
1253 { INDEX_op_divu2_i64
, { "a", "d", "0", "1", "r" } },
1254 { INDEX_op_sub_i64
, { "r", "0", "re" } },
1255 { INDEX_op_and_i64
, { "r", "0", "reZ" } },
1256 { INDEX_op_or_i64
, { "r", "0", "re" } },
1257 { INDEX_op_xor_i64
, { "r", "0", "re" } },
1259 { INDEX_op_shl_i64
, { "r", "0", "ci" } },
1260 { INDEX_op_shr_i64
, { "r", "0", "ci" } },
1261 { INDEX_op_sar_i64
, { "r", "0", "ci" } },
1263 { INDEX_op_brcond_i64
, { "r", "re" } },
1265 { INDEX_op_bswap_i32
, { "r", "0" } },
1266 { INDEX_op_bswap_i64
, { "r", "0" } },
1268 { INDEX_op_neg_i32
, { "r", "0" } },
1269 { INDEX_op_neg_i64
, { "r", "0" } },
1271 { INDEX_op_ext8s_i32
, { "r", "r"} },
1272 { INDEX_op_ext16s_i32
, { "r", "r"} },
1273 { INDEX_op_ext8s_i64
, { "r", "r"} },
1274 { INDEX_op_ext16s_i64
, { "r", "r"} },
1275 { INDEX_op_ext32s_i64
, { "r", "r"} },
1277 { INDEX_op_qemu_ld8u
, { "r", "L" } },
1278 { INDEX_op_qemu_ld8s
, { "r", "L" } },
1279 { INDEX_op_qemu_ld16u
, { "r", "L" } },
1280 { INDEX_op_qemu_ld16s
, { "r", "L" } },
1281 { INDEX_op_qemu_ld32u
, { "r", "L" } },
1282 { INDEX_op_qemu_ld32s
, { "r", "L" } },
1283 { INDEX_op_qemu_ld64
, { "r", "L" } },
1285 { INDEX_op_qemu_st8
, { "L", "L" } },
1286 { INDEX_op_qemu_st16
, { "L", "L" } },
1287 { INDEX_op_qemu_st32
, { "L", "L" } },
1288 { INDEX_op_qemu_st64
, { "L", "L", "L" } },
1293 void tcg_target_init(TCGContext
*s
)
1296 if ((1 << CPU_TLB_ENTRY_BITS
) != sizeof(CPUTLBEntry
))
1299 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I32
], 0, 0xffff);
1300 tcg_regset_set32(tcg_target_available_regs
[TCG_TYPE_I64
], 0, 0xffff);
1301 tcg_regset_set32(tcg_target_call_clobber_regs
, 0,
1302 (1 << TCG_REG_RDI
) |
1303 (1 << TCG_REG_RSI
) |
1304 (1 << TCG_REG_RDX
) |
1305 (1 << TCG_REG_RCX
) |
1308 (1 << TCG_REG_RAX
) |
1309 (1 << TCG_REG_R10
) |
1310 (1 << TCG_REG_R11
));
1312 tcg_regset_clear(s
->reserved_regs
);
1313 tcg_regset_set_reg(s
->reserved_regs
, TCG_REG_RSP
);
1315 tcg_add_target_add_op_defs(x86_64_op_defs
);