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[qemu/mini2440.git] / hw / sm501.c
blob54d176b83fa7b9c39b85b7be447956436acfa717
1 /*
2 * QEMU SM501 Device
4 * Copyright (c) 2008 Shin-ichiro KAWASAKI
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include <stdio.h>
26 #include <assert.h>
27 #include "hw.h"
28 #include "pc.h"
29 #include "console.h"
30 #include "devices.h"
33 * Status: 2008/11/02
34 * - Minimum implementation for Linux console : mmio regs and CRT layer.
35 * - Always updates full screen.
37 * TODO:
38 * - Panel support
39 * - Hardware cursor support
40 * - Touch panel support
41 * - USB support
42 * - UART support
43 * - Performance tuning
46 //#define DEBUG_SM501
47 //#define DEBUG_BITBLT
49 #ifdef DEBUG_SM501
50 #define SM501_DPRINTF(fmt...) printf(fmt)
51 #else
52 #define SM501_DPRINTF(fmt...) do {} while(0)
53 #endif
56 #define MMIO_BASE_OFFSET 0x3e00000
58 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
60 /* System Configuration area */
61 /* System config base */
62 #define SM501_SYS_CONFIG (0x000000)
64 /* config 1 */
65 #define SM501_SYSTEM_CONTROL (0x000000)
67 #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
68 #define SM501_SYSCTRL_MEM_TRISTATE (1<<1)
69 #define SM501_SYSCTRL_CRT_TRISTATE (1<<2)
71 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
72 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
73 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
74 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
75 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
77 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1<<6)
78 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
79 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1<<11)
80 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
82 /* miscellaneous control */
84 #define SM501_MISC_CONTROL (0x000004)
86 #define SM501_MISC_BUS_SH (0x0)
87 #define SM501_MISC_BUS_PCI (0x1)
88 #define SM501_MISC_BUS_XSCALE (0x2)
89 #define SM501_MISC_BUS_NEC (0x6)
90 #define SM501_MISC_BUS_MASK (0x7)
92 #define SM501_MISC_VR_62MB (1<<3)
93 #define SM501_MISC_CDR_RESET (1<<7)
94 #define SM501_MISC_USB_LB (1<<8)
95 #define SM501_MISC_USB_SLAVE (1<<9)
96 #define SM501_MISC_BL_1 (1<<10)
97 #define SM501_MISC_MC (1<<11)
98 #define SM501_MISC_DAC_POWER (1<<12)
99 #define SM501_MISC_IRQ_INVERT (1<<16)
100 #define SM501_MISC_SH (1<<17)
102 #define SM501_MISC_HOLD_EMPTY (0<<18)
103 #define SM501_MISC_HOLD_8 (1<<18)
104 #define SM501_MISC_HOLD_16 (2<<18)
105 #define SM501_MISC_HOLD_24 (3<<18)
106 #define SM501_MISC_HOLD_32 (4<<18)
107 #define SM501_MISC_HOLD_MASK (7<<18)
109 #define SM501_MISC_FREQ_12 (1<<24)
110 #define SM501_MISC_PNL_24BIT (1<<25)
111 #define SM501_MISC_8051_LE (1<<26)
115 #define SM501_GPIO31_0_CONTROL (0x000008)
116 #define SM501_GPIO63_32_CONTROL (0x00000C)
117 #define SM501_DRAM_CONTROL (0x000010)
119 /* command list */
120 #define SM501_ARBTRTN_CONTROL (0x000014)
122 /* command list */
123 #define SM501_COMMAND_LIST_STATUS (0x000024)
125 /* interrupt debug */
126 #define SM501_RAW_IRQ_STATUS (0x000028)
127 #define SM501_RAW_IRQ_CLEAR (0x000028)
128 #define SM501_IRQ_STATUS (0x00002C)
129 #define SM501_IRQ_MASK (0x000030)
130 #define SM501_DEBUG_CONTROL (0x000034)
132 /* power management */
133 #define SM501_POWERMODE_P2X_SRC (1<<29)
134 #define SM501_POWERMODE_V2X_SRC (1<<20)
135 #define SM501_POWERMODE_M_SRC (1<<12)
136 #define SM501_POWERMODE_M1_SRC (1<<4)
138 #define SM501_CURRENT_GATE (0x000038)
139 #define SM501_CURRENT_CLOCK (0x00003C)
140 #define SM501_POWER_MODE_0_GATE (0x000040)
141 #define SM501_POWER_MODE_0_CLOCK (0x000044)
142 #define SM501_POWER_MODE_1_GATE (0x000048)
143 #define SM501_POWER_MODE_1_CLOCK (0x00004C)
144 #define SM501_SLEEP_MODE_GATE (0x000050)
145 #define SM501_POWER_MODE_CONTROL (0x000054)
147 /* power gates for units within the 501 */
148 #define SM501_GATE_HOST (0)
149 #define SM501_GATE_MEMORY (1)
150 #define SM501_GATE_DISPLAY (2)
151 #define SM501_GATE_2D_ENGINE (3)
152 #define SM501_GATE_CSC (4)
153 #define SM501_GATE_ZVPORT (5)
154 #define SM501_GATE_GPIO (6)
155 #define SM501_GATE_UART0 (7)
156 #define SM501_GATE_UART1 (8)
157 #define SM501_GATE_SSP (10)
158 #define SM501_GATE_USB_HOST (11)
159 #define SM501_GATE_USB_GADGET (12)
160 #define SM501_GATE_UCONTROLLER (17)
161 #define SM501_GATE_AC97 (18)
163 /* panel clock */
164 #define SM501_CLOCK_P2XCLK (24)
165 /* crt clock */
166 #define SM501_CLOCK_V2XCLK (16)
167 /* main clock */
168 #define SM501_CLOCK_MCLK (8)
169 /* SDRAM controller clock */
170 #define SM501_CLOCK_M1XCLK (0)
172 /* config 2 */
173 #define SM501_PCI_MASTER_BASE (0x000058)
174 #define SM501_ENDIAN_CONTROL (0x00005C)
175 #define SM501_DEVICEID (0x000060)
176 /* 0x050100A0 */
178 #define SM501_DEVICEID_SM501 (0x05010000)
179 #define SM501_DEVICEID_IDMASK (0xffff0000)
180 #define SM501_DEVICEID_REVMASK (0x000000ff)
182 #define SM501_PLLCLOCK_COUNT (0x000064)
183 #define SM501_MISC_TIMING (0x000068)
184 #define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
186 #define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
188 /* GPIO base */
189 #define SM501_GPIO (0x010000)
190 #define SM501_GPIO_DATA_LOW (0x00)
191 #define SM501_GPIO_DATA_HIGH (0x04)
192 #define SM501_GPIO_DDR_LOW (0x08)
193 #define SM501_GPIO_DDR_HIGH (0x0C)
194 #define SM501_GPIO_IRQ_SETUP (0x10)
195 #define SM501_GPIO_IRQ_STATUS (0x14)
196 #define SM501_GPIO_IRQ_RESET (0x14)
198 /* I2C controller base */
199 #define SM501_I2C (0x010040)
200 #define SM501_I2C_BYTE_COUNT (0x00)
201 #define SM501_I2C_CONTROL (0x01)
202 #define SM501_I2C_STATUS (0x02)
203 #define SM501_I2C_RESET (0x02)
204 #define SM501_I2C_SLAVE_ADDRESS (0x03)
205 #define SM501_I2C_DATA (0x04)
207 /* SSP base */
208 #define SM501_SSP (0x020000)
210 /* Uart 0 base */
211 #define SM501_UART0 (0x030000)
213 /* Uart 1 base */
214 #define SM501_UART1 (0x030020)
216 /* USB host port base */
217 #define SM501_USB_HOST (0x040000)
219 /* USB slave/gadget base */
220 #define SM501_USB_GADGET (0x060000)
222 /* USB slave/gadget data port base */
223 #define SM501_USB_GADGET_DATA (0x070000)
225 /* Display controller/video engine base */
226 #define SM501_DC (0x080000)
228 /* common defines for the SM501 address registers */
229 #define SM501_ADDR_FLIP (1<<31)
230 #define SM501_ADDR_EXT (1<<27)
231 #define SM501_ADDR_CS1 (1<<26)
232 #define SM501_ADDR_MASK (0x3f << 26)
234 #define SM501_FIFO_MASK (0x3 << 16)
235 #define SM501_FIFO_1 (0x0 << 16)
236 #define SM501_FIFO_3 (0x1 << 16)
237 #define SM501_FIFO_7 (0x2 << 16)
238 #define SM501_FIFO_11 (0x3 << 16)
240 /* common registers for panel and the crt */
241 #define SM501_OFF_DC_H_TOT (0x000)
242 #define SM501_OFF_DC_V_TOT (0x008)
243 #define SM501_OFF_DC_H_SYNC (0x004)
244 #define SM501_OFF_DC_V_SYNC (0x00C)
246 #define SM501_DC_PANEL_CONTROL (0x000)
248 #define SM501_DC_PANEL_CONTROL_FPEN (1<<27)
249 #define SM501_DC_PANEL_CONTROL_BIAS (1<<26)
250 #define SM501_DC_PANEL_CONTROL_DATA (1<<25)
251 #define SM501_DC_PANEL_CONTROL_VDD (1<<24)
252 #define SM501_DC_PANEL_CONTROL_DP (1<<23)
254 #define SM501_DC_PANEL_CONTROL_TFT_888 (0<<21)
255 #define SM501_DC_PANEL_CONTROL_TFT_333 (1<<21)
256 #define SM501_DC_PANEL_CONTROL_TFT_444 (2<<21)
258 #define SM501_DC_PANEL_CONTROL_DE (1<<20)
260 #define SM501_DC_PANEL_CONTROL_LCD_TFT (0<<18)
261 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
262 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
264 #define SM501_DC_PANEL_CONTROL_CP (1<<14)
265 #define SM501_DC_PANEL_CONTROL_VSP (1<<13)
266 #define SM501_DC_PANEL_CONTROL_HSP (1<<12)
267 #define SM501_DC_PANEL_CONTROL_CK (1<<9)
268 #define SM501_DC_PANEL_CONTROL_TE (1<<8)
269 #define SM501_DC_PANEL_CONTROL_VPD (1<<7)
270 #define SM501_DC_PANEL_CONTROL_VP (1<<6)
271 #define SM501_DC_PANEL_CONTROL_HPD (1<<5)
272 #define SM501_DC_PANEL_CONTROL_HP (1<<4)
273 #define SM501_DC_PANEL_CONTROL_GAMMA (1<<3)
274 #define SM501_DC_PANEL_CONTROL_EN (1<<2)
276 #define SM501_DC_PANEL_CONTROL_8BPP (0<<0)
277 #define SM501_DC_PANEL_CONTROL_16BPP (1<<0)
278 #define SM501_DC_PANEL_CONTROL_32BPP (2<<0)
281 #define SM501_DC_PANEL_PANNING_CONTROL (0x004)
282 #define SM501_DC_PANEL_COLOR_KEY (0x008)
283 #define SM501_DC_PANEL_FB_ADDR (0x00C)
284 #define SM501_DC_PANEL_FB_OFFSET (0x010)
285 #define SM501_DC_PANEL_FB_WIDTH (0x014)
286 #define SM501_DC_PANEL_FB_HEIGHT (0x018)
287 #define SM501_DC_PANEL_TL_LOC (0x01C)
288 #define SM501_DC_PANEL_BR_LOC (0x020)
289 #define SM501_DC_PANEL_H_TOT (0x024)
290 #define SM501_DC_PANEL_H_SYNC (0x028)
291 #define SM501_DC_PANEL_V_TOT (0x02C)
292 #define SM501_DC_PANEL_V_SYNC (0x030)
293 #define SM501_DC_PANEL_CUR_LINE (0x034)
295 #define SM501_DC_VIDEO_CONTROL (0x040)
296 #define SM501_DC_VIDEO_FB0_ADDR (0x044)
297 #define SM501_DC_VIDEO_FB_WIDTH (0x048)
298 #define SM501_DC_VIDEO_FB0_LAST_ADDR (0x04C)
299 #define SM501_DC_VIDEO_TL_LOC (0x050)
300 #define SM501_DC_VIDEO_BR_LOC (0x054)
301 #define SM501_DC_VIDEO_SCALE (0x058)
302 #define SM501_DC_VIDEO_INIT_SCALE (0x05C)
303 #define SM501_DC_VIDEO_YUV_CONSTANTS (0x060)
304 #define SM501_DC_VIDEO_FB1_ADDR (0x064)
305 #define SM501_DC_VIDEO_FB1_LAST_ADDR (0x068)
307 #define SM501_DC_VIDEO_ALPHA_CONTROL (0x080)
308 #define SM501_DC_VIDEO_ALPHA_FB_ADDR (0x084)
309 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0x088)
310 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0x08C)
311 #define SM501_DC_VIDEO_ALPHA_TL_LOC (0x090)
312 #define SM501_DC_VIDEO_ALPHA_BR_LOC (0x094)
313 #define SM501_DC_VIDEO_ALPHA_SCALE (0x098)
314 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
315 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
316 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0x0A4)
318 #define SM501_DC_PANEL_HWC_BASE (0x0F0)
319 #define SM501_DC_PANEL_HWC_ADDR (0x0F0)
320 #define SM501_DC_PANEL_HWC_LOC (0x0F4)
321 #define SM501_DC_PANEL_HWC_COLOR_1_2 (0x0F8)
322 #define SM501_DC_PANEL_HWC_COLOR_3 (0x0FC)
324 #define SM501_HWC_EN (1<<31)
326 #define SM501_OFF_HWC_ADDR (0x00)
327 #define SM501_OFF_HWC_LOC (0x04)
328 #define SM501_OFF_HWC_COLOR_1_2 (0x08)
329 #define SM501_OFF_HWC_COLOR_3 (0x0C)
331 #define SM501_DC_ALPHA_CONTROL (0x100)
332 #define SM501_DC_ALPHA_FB_ADDR (0x104)
333 #define SM501_DC_ALPHA_FB_OFFSET (0x108)
334 #define SM501_DC_ALPHA_TL_LOC (0x10C)
335 #define SM501_DC_ALPHA_BR_LOC (0x110)
336 #define SM501_DC_ALPHA_CHROMA_KEY (0x114)
337 #define SM501_DC_ALPHA_COLOR_LOOKUP (0x118)
339 #define SM501_DC_CRT_CONTROL (0x200)
341 #define SM501_DC_CRT_CONTROL_TVP (1<<15)
342 #define SM501_DC_CRT_CONTROL_CP (1<<14)
343 #define SM501_DC_CRT_CONTROL_VSP (1<<13)
344 #define SM501_DC_CRT_CONTROL_HSP (1<<12)
345 #define SM501_DC_CRT_CONTROL_VS (1<<11)
346 #define SM501_DC_CRT_CONTROL_BLANK (1<<10)
347 #define SM501_DC_CRT_CONTROL_SEL (1<<9)
348 #define SM501_DC_CRT_CONTROL_TE (1<<8)
349 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
350 #define SM501_DC_CRT_CONTROL_GAMMA (1<<3)
351 #define SM501_DC_CRT_CONTROL_ENABLE (1<<2)
353 #define SM501_DC_CRT_CONTROL_8BPP (0<<0)
354 #define SM501_DC_CRT_CONTROL_16BPP (1<<0)
355 #define SM501_DC_CRT_CONTROL_32BPP (2<<0)
357 #define SM501_DC_CRT_FB_ADDR (0x204)
358 #define SM501_DC_CRT_FB_OFFSET (0x208)
359 #define SM501_DC_CRT_H_TOT (0x20C)
360 #define SM501_DC_CRT_H_SYNC (0x210)
361 #define SM501_DC_CRT_V_TOT (0x214)
362 #define SM501_DC_CRT_V_SYNC (0x218)
363 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
364 #define SM501_DC_CRT_CUR_LINE (0x220)
365 #define SM501_DC_CRT_MONITOR_DETECT (0x224)
367 #define SM501_DC_CRT_HWC_BASE (0x230)
368 #define SM501_DC_CRT_HWC_ADDR (0x230)
369 #define SM501_DC_CRT_HWC_LOC (0x234)
370 #define SM501_DC_CRT_HWC_COLOR_1_2 (0x238)
371 #define SM501_DC_CRT_HWC_COLOR_3 (0x23C)
373 #define SM501_DC_PANEL_PALETTE (0x400)
375 #define SM501_DC_VIDEO_PALETTE (0x800)
377 #define SM501_DC_CRT_PALETTE (0xC00)
379 /* Zoom Video port base */
380 #define SM501_ZVPORT (0x090000)
382 /* AC97/I2S base */
383 #define SM501_AC97 (0x0A0000)
385 /* 8051 micro controller base */
386 #define SM501_UCONTROLLER (0x0B0000)
388 /* 8051 micro controller SRAM base */
389 #define SM501_UCONTROLLER_SRAM (0x0C0000)
391 /* DMA base */
392 #define SM501_DMA (0x0D0000)
394 /* 2d engine base */
395 #define SM501_2D_ENGINE (0x100000)
396 #define SM501_2D_SOURCE (0x00)
397 #define SM501_2D_DESTINATION (0x04)
398 #define SM501_2D_DIMENSION (0x08)
399 #define SM501_2D_CONTROL (0x0C)
400 #define SM501_2D_PITCH (0x10)
401 #define SM501_2D_FOREGROUND (0x14)
402 #define SM501_2D_BACKGROUND (0x18)
403 #define SM501_2D_STRETCH (0x1C)
404 #define SM501_2D_COLOR_COMPARE (0x20)
405 #define SM501_2D_COLOR_COMPARE_MASK (0x24)
406 #define SM501_2D_MASK (0x28)
407 #define SM501_2D_CLIP_TL (0x2C)
408 #define SM501_2D_CLIP_BR (0x30)
409 #define SM501_2D_MONO_PATTERN_LOW (0x34)
410 #define SM501_2D_MONO_PATTERN_HIGH (0x38)
411 #define SM501_2D_WINDOW_WIDTH (0x3C)
412 #define SM501_2D_SOURCE_BASE (0x40)
413 #define SM501_2D_DESTINATION_BASE (0x44)
414 #define SM501_2D_ALPHA (0x48)
415 #define SM501_2D_WRAP (0x4C)
416 #define SM501_2D_STATUS (0x50)
418 #define SM501_CSC_Y_SOURCE_BASE (0xC8)
419 #define SM501_CSC_CONSTANTS (0xCC)
420 #define SM501_CSC_Y_SOURCE_X (0xD0)
421 #define SM501_CSC_Y_SOURCE_Y (0xD4)
422 #define SM501_CSC_U_SOURCE_BASE (0xD8)
423 #define SM501_CSC_V_SOURCE_BASE (0xDC)
424 #define SM501_CSC_SOURCE_DIMENSION (0xE0)
425 #define SM501_CSC_SOURCE_PITCH (0xE4)
426 #define SM501_CSC_DESTINATION (0xE8)
427 #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
428 #define SM501_CSC_DESTINATION_PITCH (0xF0)
429 #define SM501_CSC_SCALE_FACTOR (0xF4)
430 #define SM501_CSC_DESTINATION_BASE (0xF8)
431 #define SM501_CSC_CONTROL (0xFC)
433 /* 2d engine data port base */
434 #define SM501_2D_ENGINE_DATA (0x110000)
436 /* end of register definitions */
439 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
440 static const uint32_t sm501_mem_local_size[] = {
441 [0] = 4*1024*1024,
442 [1] = 8*1024*1024,
443 [2] = 16*1024*1024,
444 [3] = 32*1024*1024,
445 [4] = 64*1024*1024,
446 [5] = 2*1024*1024,
448 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
450 typedef struct SM501State {
451 /* graphic console status */
452 DisplayState *ds;
453 QEMUConsole *console;
455 /* status & internal resources */
456 target_phys_addr_t base;
457 uint32_t local_mem_size_index;
458 uint8_t * local_mem;
459 uint32_t last_width;
460 uint32_t last_height;
462 /* mmio registers */
463 uint32_t system_control;
464 uint32_t misc_control;
465 uint32_t gpio_31_0_control;
466 uint32_t gpio_63_32_control;
467 uint32_t dram_control;
468 uint32_t irq_mask;
469 uint32_t misc_timing;
470 uint32_t power_mode_control;
472 uint32_t uart0_ier;
473 uint32_t uart0_lcr;
474 uint32_t uart0_mcr;
475 uint32_t uart0_scr;
477 uint8_t dc_palette[0x400 * 3];
479 uint32_t dc_panel_control;
480 uint32_t dc_panel_panning_control;
481 uint32_t dc_panel_fb_addr;
482 uint32_t dc_panel_fb_offset;
483 uint32_t dc_panel_fb_width;
484 uint32_t dc_panel_fb_height;
485 uint32_t dc_panel_tl_location;
486 uint32_t dc_panel_br_location;
487 uint32_t dc_panel_h_total;
488 uint32_t dc_panel_h_sync;
489 uint32_t dc_panel_v_total;
490 uint32_t dc_panel_v_sync;
492 uint32_t dc_panel_hwc_addr;
493 uint32_t dc_panel_hwc_location;
494 uint32_t dc_panel_hwc_color_1_2;
495 uint32_t dc_panel_hwc_color_3;
497 uint32_t dc_crt_control;
498 uint32_t dc_crt_fb_addr;
499 uint32_t dc_crt_fb_offset;
500 uint32_t dc_crt_h_total;
501 uint32_t dc_crt_h_sync;
502 uint32_t dc_crt_v_total;
503 uint32_t dc_crt_v_sync;
505 uint32_t dc_crt_hwc_addr;
506 uint32_t dc_crt_hwc_location;
507 uint32_t dc_crt_hwc_color_1_2;
508 uint32_t dc_crt_hwc_color_3;
510 } SM501State;
512 static uint32_t get_local_mem_size_index(uint32_t size)
514 uint32_t norm_size = 0;
515 int i, index = 0;
517 for (i = 0; i < sizeof(sm501_mem_local_size)/sizeof(uint32_t); i++) {
518 uint32_t new_size = sm501_mem_local_size[i];
519 if (new_size >= size) {
520 if (norm_size == 0 || norm_size > new_size) {
521 norm_size = new_size;
522 index = i;
527 return index;
530 static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
532 SM501State * s = (SM501State *)opaque;
533 uint32_t ret = 0;
534 SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
536 switch(addr) {
537 case SM501_SYSTEM_CONTROL:
538 ret = s->system_control;
539 break;
540 case SM501_MISC_CONTROL:
541 ret = s->misc_control;
542 break;
543 case SM501_GPIO31_0_CONTROL:
544 ret = s->gpio_31_0_control;
545 break;
546 case SM501_GPIO63_32_CONTROL:
547 ret = s->gpio_63_32_control;
548 break;
549 case SM501_DEVICEID:
550 ret = 0x050100A0;
551 break;
552 case SM501_DRAM_CONTROL:
553 ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
554 break;
555 case SM501_IRQ_MASK:
556 ret = s->irq_mask;
557 break;
558 case SM501_MISC_TIMING:
559 /* TODO : simulate gate control */
560 ret = s->misc_timing;
561 break;
562 case SM501_CURRENT_GATE:
563 /* TODO : simulate gate control */
564 ret = 0x00021807;
565 break;
566 case SM501_CURRENT_CLOCK:
567 ret = 0x2A1A0A09;
568 break;
569 case SM501_POWER_MODE_CONTROL:
570 ret = s->power_mode_control;
571 break;
573 default:
574 printf("sm501 system config : not implemented register read."
575 " addr=%x\n", (int)addr);
576 assert(0);
579 return ret;
582 static void sm501_system_config_write(void *opaque,
583 target_phys_addr_t addr, uint32_t value)
585 SM501State * s = (SM501State *)opaque;
586 SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
587 addr, value);
589 switch(addr) {
590 case SM501_SYSTEM_CONTROL:
591 s->system_control = value & 0xE300B8F7;
592 break;
593 case SM501_MISC_CONTROL:
594 s->misc_control = value & 0xFF7FFF20;
595 break;
596 case SM501_GPIO31_0_CONTROL:
597 s->gpio_31_0_control = value;
598 break;
599 case SM501_GPIO63_32_CONTROL:
600 s->gpio_63_32_control = value;
601 break;
602 case SM501_DRAM_CONTROL:
603 s->local_mem_size_index = (value >> 13) & 0x7;
604 /* rODO : check validity of size change */
605 s->dram_control |= value & 0x7FFFFFC3;
606 break;
607 case SM501_IRQ_MASK:
608 s->irq_mask = value;
609 break;
610 case SM501_MISC_TIMING:
611 s->misc_timing = value & 0xF31F1FFF;
612 break;
613 case SM501_POWER_MODE_0_GATE:
614 case SM501_POWER_MODE_1_GATE:
615 case SM501_POWER_MODE_0_CLOCK:
616 case SM501_POWER_MODE_1_CLOCK:
617 /* TODO : simulate gate & clock control */
618 break;
619 case SM501_POWER_MODE_CONTROL:
620 s->power_mode_control = value & 0x00000003;
621 break;
623 default:
624 printf("sm501 system config : not implemented register write."
625 " addr=%x, val=%x\n", (int)addr, value);
626 assert(0);
630 static CPUReadMemoryFunc *sm501_system_config_readfn[] = {
631 NULL,
632 NULL,
633 &sm501_system_config_read,
636 static CPUWriteMemoryFunc *sm501_system_config_writefn[] = {
637 NULL,
638 NULL,
639 &sm501_system_config_write,
642 static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
644 SM501State * s = (SM501State *)opaque;
645 SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
647 /* TODO : consider BYTE/WORD access */
648 /* TODO : consider endian */
650 assert(0 <= addr && addr < 0x400 * 3);
651 return *(uint32_t*)&s->dc_palette[addr];
654 static void sm501_palette_write(void *opaque,
655 target_phys_addr_t addr, uint32_t value)
657 SM501State * s = (SM501State *)opaque;
658 SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
659 (int)addr, value);
661 /* TODO : consider BYTE/WORD access */
662 /* TODO : consider endian */
664 assert(0 <= addr && addr < 0x400 * 3);
665 *(uint32_t*)&s->dc_palette[addr] = value;
668 static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr)
670 SM501State * s = (SM501State *)opaque;
671 uint32_t ret = 0;
672 SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
674 switch(addr) {
676 case SM501_DC_PANEL_CONTROL:
677 ret = s->dc_panel_control;
678 break;
679 case SM501_DC_PANEL_PANNING_CONTROL:
680 ret = s->dc_panel_panning_control;
681 break;
682 case SM501_DC_PANEL_FB_ADDR:
683 ret = s->dc_panel_fb_addr;
684 break;
685 case SM501_DC_PANEL_FB_OFFSET:
686 ret = s->dc_panel_fb_offset;
687 break;
688 case SM501_DC_PANEL_FB_WIDTH:
689 ret = s->dc_panel_fb_width;
690 break;
691 case SM501_DC_PANEL_FB_HEIGHT:
692 ret = s->dc_panel_fb_height;
693 break;
694 case SM501_DC_PANEL_TL_LOC:
695 ret = s->dc_panel_tl_location;
696 break;
697 case SM501_DC_PANEL_BR_LOC:
698 ret = s->dc_panel_br_location;
699 break;
701 case SM501_DC_PANEL_H_TOT:
702 ret = s->dc_panel_h_total;
703 break;
704 case SM501_DC_PANEL_H_SYNC:
705 ret = s->dc_panel_h_sync;
706 break;
707 case SM501_DC_PANEL_V_TOT:
708 ret = s->dc_panel_v_total;
709 break;
710 case SM501_DC_PANEL_V_SYNC:
711 ret = s->dc_panel_v_sync;
712 break;
714 case SM501_DC_CRT_CONTROL:
715 ret = s->dc_crt_control;
716 break;
717 case SM501_DC_CRT_FB_ADDR:
718 ret = s->dc_crt_fb_addr;
719 break;
720 case SM501_DC_CRT_FB_OFFSET:
721 ret = s->dc_crt_fb_offset;
722 break;
723 case SM501_DC_CRT_H_TOT:
724 ret = s->dc_crt_h_total;
725 break;
726 case SM501_DC_CRT_H_SYNC:
727 ret = s->dc_crt_h_sync;
728 break;
729 case SM501_DC_CRT_V_TOT:
730 ret = s->dc_crt_v_total;
731 break;
732 case SM501_DC_CRT_V_SYNC:
733 ret = s->dc_crt_v_sync;
734 break;
736 case SM501_DC_CRT_HWC_ADDR:
737 ret = s->dc_crt_hwc_addr;
738 break;
739 case SM501_DC_CRT_HWC_LOC:
740 ret = s->dc_crt_hwc_addr;
741 break;
742 case SM501_DC_CRT_HWC_COLOR_1_2:
743 ret = s->dc_crt_hwc_addr;
744 break;
745 case SM501_DC_CRT_HWC_COLOR_3:
746 ret = s->dc_crt_hwc_addr;
747 break;
749 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4:
750 ret = sm501_palette_read(opaque, addr - SM501_DC_PANEL_PALETTE);
751 break;
753 default:
754 printf("sm501 disp ctrl : not implemented register read."
755 " addr=%x\n", (int)addr);
756 assert(0);
759 return ret;
762 static void sm501_disp_ctrl_write(void *opaque,
763 target_phys_addr_t addr,
764 uint32_t value)
766 SM501State * s = (SM501State *)opaque;
767 SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
768 addr, value);
770 switch(addr) {
771 case SM501_DC_PANEL_CONTROL:
772 s->dc_panel_control = value & 0x0FFF73FF;
773 break;
774 case SM501_DC_PANEL_PANNING_CONTROL:
775 s->dc_panel_panning_control = value & 0xFF3FFF3F;
776 break;
777 case SM501_DC_PANEL_FB_ADDR:
778 s->dc_panel_fb_addr = value & 0x8FFFFFF0;
779 break;
780 case SM501_DC_PANEL_FB_OFFSET:
781 s->dc_panel_fb_offset = value & 0x3FF03FF0;
782 break;
783 case SM501_DC_PANEL_FB_WIDTH:
784 s->dc_panel_fb_width = value & 0x0FFF0FFF;
785 break;
786 case SM501_DC_PANEL_FB_HEIGHT:
787 s->dc_panel_fb_height = value & 0x0FFF0FFF;
788 break;
789 case SM501_DC_PANEL_TL_LOC:
790 s->dc_panel_tl_location = value & 0x07FF07FF;
791 break;
792 case SM501_DC_PANEL_BR_LOC:
793 s->dc_panel_br_location = value & 0x07FF07FF;
794 break;
796 case SM501_DC_PANEL_H_TOT:
797 s->dc_panel_h_total = value & 0x0FFF0FFF;
798 break;
799 case SM501_DC_PANEL_H_SYNC:
800 s->dc_panel_h_sync = value & 0x00FF0FFF;
801 break;
802 case SM501_DC_PANEL_V_TOT:
803 s->dc_panel_v_total = value & 0x0FFF0FFF;
804 break;
805 case SM501_DC_PANEL_V_SYNC:
806 s->dc_panel_v_sync = value & 0x003F0FFF;
807 break;
809 case SM501_DC_PANEL_HWC_ADDR:
810 s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
811 break;
812 case SM501_DC_PANEL_HWC_LOC:
813 s->dc_panel_hwc_addr = value & 0x0FFF0FFF;
814 break;
815 case SM501_DC_PANEL_HWC_COLOR_1_2:
816 s->dc_panel_hwc_addr = value;
817 break;
818 case SM501_DC_PANEL_HWC_COLOR_3:
819 s->dc_panel_hwc_addr = value & 0x0000FFFF;
820 break;
822 case SM501_DC_CRT_CONTROL:
823 s->dc_crt_control = value & 0x0003FFFF;
824 break;
825 case SM501_DC_CRT_FB_ADDR:
826 s->dc_crt_fb_addr = value & 0x8FFFFFF0;
827 break;
828 case SM501_DC_CRT_FB_OFFSET:
829 s->dc_crt_fb_offset = value & 0x3FF03FF0;
830 break;
831 case SM501_DC_CRT_H_TOT:
832 s->dc_crt_h_total = value & 0x0FFF0FFF;
833 break;
834 case SM501_DC_CRT_H_SYNC:
835 s->dc_crt_h_sync = value & 0x00FF0FFF;
836 break;
837 case SM501_DC_CRT_V_TOT:
838 s->dc_crt_v_total = value & 0x0FFF0FFF;
839 break;
840 case SM501_DC_CRT_V_SYNC:
841 s->dc_crt_v_sync = value & 0x003F0FFF;
842 break;
844 case SM501_DC_CRT_HWC_ADDR:
845 s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
846 break;
847 case SM501_DC_CRT_HWC_LOC:
848 s->dc_crt_hwc_addr = value & 0x0FFF0FFF;
849 break;
850 case SM501_DC_CRT_HWC_COLOR_1_2:
851 s->dc_crt_hwc_addr = value;
852 break;
853 case SM501_DC_CRT_HWC_COLOR_3:
854 s->dc_crt_hwc_addr = value & 0x0000FFFF;
855 break;
857 case SM501_DC_PANEL_PALETTE ... SM501_DC_PANEL_PALETTE + 0x400*3 - 4:
858 sm501_palette_write(opaque, addr - SM501_DC_PANEL_PALETTE, value);
859 break;
861 default:
862 printf("sm501 disp ctrl : not implemented register write."
863 " addr=%x, val=%x\n", (int)addr, value);
864 assert(0);
868 static CPUReadMemoryFunc *sm501_disp_ctrl_readfn[] = {
869 NULL,
870 NULL,
871 &sm501_disp_ctrl_read,
874 static CPUWriteMemoryFunc *sm501_disp_ctrl_writefn[] = {
875 NULL,
876 NULL,
877 &sm501_disp_ctrl_write,
880 /* draw line functions for all console modes */
882 #include "pixel_ops.h"
884 typedef void draw_line_func(uint8_t *d, const uint8_t *s,
885 int width, const uint32_t *pal);
887 #define DEPTH 8
888 #include "sm501_template.h"
890 #define DEPTH 15
891 #include "sm501_template.h"
893 #define BGR_FORMAT
894 #define DEPTH 15
895 #include "sm501_template.h"
897 #define DEPTH 16
898 #include "sm501_template.h"
900 #define BGR_FORMAT
901 #define DEPTH 16
902 #include "sm501_template.h"
904 #define DEPTH 32
905 #include "sm501_template.h"
907 #define BGR_FORMAT
908 #define DEPTH 32
909 #include "sm501_template.h"
911 static draw_line_func * draw_line8_funcs[] = {
912 draw_line8_8,
913 draw_line8_15,
914 draw_line8_16,
915 draw_line8_32,
916 draw_line8_32bgr,
917 draw_line8_15bgr,
918 draw_line8_16bgr,
921 static draw_line_func * draw_line16_funcs[] = {
922 draw_line16_8,
923 draw_line16_15,
924 draw_line16_16,
925 draw_line16_32,
926 draw_line16_32bgr,
927 draw_line16_15bgr,
928 draw_line16_16bgr,
931 static draw_line_func * draw_line32_funcs[] = {
932 draw_line32_8,
933 draw_line32_15,
934 draw_line32_16,
935 draw_line32_32,
936 draw_line32_32bgr,
937 draw_line32_15bgr,
938 draw_line32_16bgr,
941 static inline int get_depth_index(DisplayState *s)
943 switch(s->depth) {
944 default:
945 case 8:
946 return 0;
947 case 15:
948 if (s->bgr)
949 return 5;
950 else
951 return 1;
952 case 16:
953 if (s->bgr)
954 return 6;
955 else
956 return 2;
957 case 32:
958 if (s->bgr)
959 return 4;
960 else
961 return 3;
965 static void sm501_draw_crt(SM501State * s)
967 int y;
968 int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
969 int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
971 uint8_t * src = s->local_mem;
972 int src_bpp = 0;
973 int dst_bpp = s->ds->depth / 8 + (s->ds->depth % 8 ? 1 : 0);
974 uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE
975 - SM501_DC_PANEL_PALETTE];
976 int ds_depth_index = get_depth_index(s->ds);
977 draw_line_func * draw_line = NULL;
978 int full_update = 0;
979 int y_start = -1;
980 int page_min = 0x7fffffff;
981 int page_max = -1;
983 /* choose draw_line function */
984 switch (s->dc_crt_control & 3) {
985 case SM501_DC_CRT_CONTROL_8BPP:
986 src_bpp = 1;
987 draw_line = draw_line8_funcs[ds_depth_index];
988 break;
989 case SM501_DC_CRT_CONTROL_16BPP:
990 src_bpp = 2;
991 draw_line = draw_line16_funcs[ds_depth_index];
992 break;
993 case SM501_DC_CRT_CONTROL_32BPP:
994 src_bpp = 4;
995 draw_line = draw_line32_funcs[ds_depth_index];
996 break;
997 default:
998 printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
999 s->dc_crt_control);
1000 assert(0);
1001 break;
1004 /* adjust console size */
1005 if (s->last_width != width || s->last_height != height) {
1006 qemu_console_resize(s->console, width, height);
1007 s->last_width = width;
1008 s->last_height = height;
1009 full_update = 1;
1012 /* draw each line according to conditions */
1013 for (y = 0; y < height; y++) {
1014 int update = full_update;
1015 uint8_t * line_end = &src[width * src_bpp - 1];
1016 int page0 = (src - phys_ram_base) & TARGET_PAGE_MASK;
1017 int page1 = (line_end - phys_ram_base) & TARGET_PAGE_MASK;
1018 int page;
1020 /* check dirty flags for each line */
1021 for (page = page0; page <= page1; page += TARGET_PAGE_SIZE)
1022 if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG))
1023 update = 1;
1025 /* draw line and change status */
1026 if (update) {
1027 draw_line(&s->ds->data[y * width * dst_bpp], src, width, palette);
1028 if (y_start < 0)
1029 y_start = y;
1030 if (page0 < page_min)
1031 page_min = page0;
1032 if (page1 > page_max)
1033 page_max = page1;
1034 } else {
1035 if (y_start >= 0) {
1036 /* flush to display */
1037 dpy_update(s->ds, 0, y_start, width, y - y_start);
1038 y_start = -1;
1042 src += width * src_bpp;
1045 /* complete flush to display */
1046 if (y_start >= 0)
1047 dpy_update(s->ds, 0, y_start, width, y - y_start);
1049 /* clear dirty flags */
1050 if (page_max != -1)
1051 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1052 VGA_DIRTY_FLAG);
1055 static void sm501_update_display(void *opaque)
1057 SM501State * s = (SM501State *)opaque;
1059 if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
1060 sm501_draw_crt(s);
1063 void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
1064 uint32_t local_mem_bytes, CharDriverState *chr)
1066 SM501State * s;
1067 int sm501_system_config_index;
1068 int sm501_disp_ctrl_index;
1070 /* allocate management data region */
1071 s = (SM501State *)qemu_mallocz(sizeof(SM501State));
1072 s->base = base;
1073 s->local_mem_size_index
1074 = get_local_mem_size_index(local_mem_bytes);
1075 SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
1076 s->local_mem_size_index);
1077 s->system_control = 0x00100000;
1078 s->misc_control = 0x00001000; /* assumes SH, active=low */
1079 s->dc_panel_control = 0x00010000;
1080 s->dc_crt_control = 0x00010000;
1081 s->ds = ds;
1083 /* allocate local memory */
1084 s->local_mem = (uint8 *)phys_ram_base + local_mem_base;
1085 cpu_register_physical_memory(base, local_mem_bytes, local_mem_base);
1087 /* map mmio */
1088 sm501_system_config_index
1089 = cpu_register_io_memory(0, sm501_system_config_readfn,
1090 sm501_system_config_writefn, s);
1091 cpu_register_physical_memory(base + MMIO_BASE_OFFSET,
1092 0x6c, sm501_system_config_index);
1093 sm501_disp_ctrl_index = cpu_register_io_memory(0, sm501_disp_ctrl_readfn,
1094 sm501_disp_ctrl_writefn, s);
1095 cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC,
1096 0x1000, sm501_disp_ctrl_index);
1098 /* bridge to serial emulation module */
1099 if (chr)
1100 serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
1101 0, /* TODO : chain irq to IRL */
1102 115200, chr, 1);
1104 /* create qemu graphic console */
1105 s->console = graphic_console_init(s->ds, sm501_update_display, NULL,
1106 NULL, NULL, s);