hw/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "qemu-char.h"
  27 #include "isa.h"
  28 #include "pc.h"
  29 #include "qemu-timer.h"
  30
  31 //#define DEBUG_SERIAL
  32
  33 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  34
  35 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  36 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  37 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  38 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  39
  40 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  41 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  42
  43 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  44 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  45 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  46 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  47 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  48
  49 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  50 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  51
  52 /*
  53  * These are the definitions for the Modem Control Register
  54  */
  55 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  56 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  57 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  58 #define UART_MCR_RTS    0x02    /* RTS complement */
  59 #define UART_MCR_DTR    0x01    /* DTR complement */
  60
  61 /*
  62  * These are the definitions for the Modem Status Register
  63  */
  64 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  65 #define UART_MSR_RI     0x40    /* Ring Indicator */
  66 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  67 #define UART_MSR_CTS    0x10    /* Clear to Send */
  68 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  69 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  70 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  71 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  72 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  73
  74 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  75 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  76 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  77 #define UART_LSR_FE     0x08    /* Frame error indicator */
  78 #define UART_LSR_PE     0x04    /* Parity error indicator */
  79 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  80 #define UART_LSR_DR     0x01    /* Receiver data ready */
  81 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  82
  83 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  84
  85 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  86 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  87 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  88 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  89
  90 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  91 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  92 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  93 #define UART_FCR_FE         0x01    /* FIFO Enable */
  94
  95 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
  96
  97 #define XMIT_FIFO           0
  98 #define RECV_FIFO           1
  99 #define MAX_XMIT_RETRY      4
 100
 101 struct SerialFIFO {
 102     uint8_t data[UART_FIFO_LENGTH];
 103     uint8_t count;
 104     uint8_t itl;                        /* Interrupt Trigger Level */
 105     uint8_t tail;
 106     uint8_t head;
 107 } typedef SerialFIFO;
 108
 109 struct SerialState {
 110     uint16_t divider;
 111     uint8_t rbr; /* receive register */
 112     uint8_t thr; /* transmit holding register */
 113     uint8_t tsr; /* transmit shift register */
 114     uint8_t ier;
 115     uint8_t iir; /* read only */
 116     uint8_t lcr;
 117     uint8_t mcr;
 118     uint8_t lsr; /* read only */
 119     uint8_t msr; /* read only */
 120     uint8_t scr;
 121     uint8_t fcr;
 122     /* NOTE: this hidden state is necessary for tx irq generation as
 123        it can be reset while reading iir */
 124     int thr_ipending;
 125     qemu_irq irq;
 126     CharDriverState *chr;
 127     int last_break_enable;
 128     target_phys_addr_t base;
 129     int it_shift;
 130     int baudbase;
 131     int tsr_retry;
 132
 133     uint64_t last_xmit_ts;              /* Time when the last byte was successfully sent out of the tsr */
 134     SerialFIFO recv_fifo;
 135     SerialFIFO xmit_fifo;
 136
 137     struct QEMUTimer *fifo_timeout_timer;
 138     int timeout_ipending;                   /* timeout interrupt pending state */
 139     struct QEMUTimer *transmit_timer;
 140
 141
 142     uint64_t char_transmit_time;               /* time to transmit a char in ticks*/
 143     int poll_msl;
 144
 145     struct QEMUTimer *modem_status_poll;
 146 };
 147
 148 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 149
 150 static void fifo_clear(SerialState *s, int fifo)
 151 {
 152     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 153     memset(f->data, 0, UART_FIFO_LENGTH);
 154     f->count = 0;
 155     f->head = 0;
 156     f->tail = 0;
 157 }
 158
 159 static int fifo_put(SerialState *s, int fifo, uint8_t chr)
 160 {
 161     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 162
 163     f->data[f->head++] = chr;
 164
 165     if (f->head == UART_FIFO_LENGTH)
 166         f->head = 0;
 167     f->count++;
 168
 169     return 1;
 170 }
 171
 172 static uint8_t fifo_get(SerialState *s, int fifo)
 173 {
 174     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 175     uint8_t c;
 176
 177     if(f->count == 0)
 178         return 0;
 179
 180     c = f->data[f->tail++];
 181     if (f->tail == UART_FIFO_LENGTH)
 182         f->tail = 0;
 183     f->count--;
 184
 185     return c;
 186 }
 187
 188 static void serial_update_irq(SerialState *s)
 189 {
 190     uint8_t tmp_iir = UART_IIR_NO_INT;
 191
 192     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 193         tmp_iir = UART_IIR_RLSI;
 194     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 195         tmp_iir = UART_IIR_CTI;
 196     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR)) {
 197         if (!(s->fcr & UART_FCR_FE)) {
 198            tmp_iir = UART_IIR_RDI;
 199         } else if (s->recv_fifo.count >= s->recv_fifo.itl) {
 200            tmp_iir = UART_IIR_RDI;
 201         }
 202     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 203         tmp_iir = UART_IIR_THRI;
 204     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 205         tmp_iir = UART_IIR_MSI;
 206     }
 207
 208     s->iir = tmp_iir | (s->iir & 0xF0);
 209
 210     if (tmp_iir != UART_IIR_NO_INT) {
 211         qemu_irq_raise(s->irq);
 212     } else {
 213         qemu_irq_lower(s->irq);
 214     }
 215 }
 216
 217 static void serial_update_parameters(SerialState *s)
 218 {
 219     int speed, parity, data_bits, stop_bits, frame_size;
 220     QEMUSerialSetParams ssp;
 221
 222     if (s->divider == 0)
 223         return;
 224
 225     frame_size = 1;
 226     if (s->lcr & 0x08) {
 227         if (s->lcr & 0x10)
 228             parity = 'E';
 229         else
 230             parity = 'O';
 231     } else {
 232             parity = 'N';
 233             frame_size = 0;
 234     }
 235     if (s->lcr & 0x04)
 236         stop_bits = 2;
 237     else
 238         stop_bits = 1;
 239
 240     data_bits = (s->lcr & 0x03) + 5;
 241     frame_size += data_bits + stop_bits;
 242     speed = s->baudbase / s->divider;
 243     ssp.speed = speed;
 244     ssp.parity = parity;
 245     ssp.data_bits = data_bits;
 246     ssp.stop_bits = stop_bits;
 247     s->char_transmit_time =  (ticks_per_sec / speed) * frame_size;
 248     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 249 #if 0
 250     printf("speed=%d parity=%c data=%d stop=%d\n",
 251            speed, parity, data_bits, stop_bits);
 252 #endif
 253 }
 254
 255 static void serial_update_msl(SerialState *s)
 256 {
 257     uint8_t omsr;
 258     int flags;
 259
 260     qemu_del_timer(s->modem_status_poll);
 261
 262     if (qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 263         s->poll_msl = -1;
 264         return;
 265     }
 266
 267     omsr = s->msr;
 268
 269     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 270     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 271     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 272     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 273
 274     if (s->msr != omsr) {
 275          /* Set delta bits */
 276          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 277          /* UART_MSR_TERI only if change was from 1 -> 0 */
 278          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 279              s->msr &= ~UART_MSR_TERI;
 280          serial_update_irq(s);
 281     }
 282
 283     /* The real 16550A apparently has a 250ns response latency to line status changes.
 284        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 285
 286     if (s->poll_msl)
 287         qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + ticks_per_sec / 100);
 288 }
 289
 290 static void serial_xmit(void *opaque)
 291 {
 292     SerialState *s = opaque;
 293     uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
 294
 295     if (s->tsr_retry <= 0) {
 296         if (s->fcr & UART_FCR_FE) {
 297             s->tsr = fifo_get(s,XMIT_FIFO);
 298             if (!s->xmit_fifo.count)
 299                 s->lsr |= UART_LSR_THRE;
 300         } else {
 301             s->tsr = s->thr;
 302             s->lsr |= UART_LSR_THRE;
 303         }
 304     }
 305
 306     if (s->mcr & UART_MCR_LOOP) {
 307         /* in loopback mode, say that we just received a char */
 308         serial_receive1(s, &s->tsr, 1);
 309     } else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) {
 310         if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
 311             s->tsr_retry++;
 312             qemu_mod_timer(s->transmit_timer,  new_xmit_ts + s->char_transmit_time);
 313             return;
 314         } else if (s->poll_msl < 0) {
 315             /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
 316             drop any further failed writes instantly, until we get one that goes through.
 317             This is to prevent guests that log to unconnected pipes or pty's from stalling. */
 318             s->tsr_retry = -1;
 319         }
 320     }
 321     else {
 322         s->tsr_retry = 0;
 323     }
 324
 325     s->last_xmit_ts = qemu_get_clock(vm_clock);
 326     if (!(s->lsr & UART_LSR_THRE))
 327         qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
 328
 329     if (s->lsr & UART_LSR_THRE) {
 330         s->lsr |= UART_LSR_TEMT;
 331         s->thr_ipending = 1;
 332         serial_update_irq(s);
 333     }
 334 }
 335
 336
 337 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 338 {
 339     SerialState *s = opaque;
 340
 341     addr &= 7;
 342 #ifdef DEBUG_SERIAL
 343     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
 344 #endif
 345     switch(addr) {
 346     default:
 347     case 0:
 348         if (s->lcr & UART_LCR_DLAB) {
 349             s->divider = (s->divider & 0xff00) | val;
 350             serial_update_parameters(s);
 351         } else {
 352             s->thr = (uint8_t) val;
 353             if(s->fcr & UART_FCR_FE) {
 354                   fifo_put(s, XMIT_FIFO, s->thr);
 355             s->thr_ipending = 0;
 356                   s->lsr &= ~UART_LSR_TEMT;
 357             s->lsr &= ~UART_LSR_THRE;
 358             serial_update_irq(s);
 359             } else {
 360                   s->thr_ipending = 0;
 361                   s->lsr &= ~UART_LSR_THRE;
 362                   serial_update_irq(s);
 363             }
 364             serial_xmit(s);
 365         }
 366         break;
 367     case 1:
 368         if (s->lcr & UART_LCR_DLAB) {
 369             s->divider = (s->divider & 0x00ff) | (val << 8);
 370             serial_update_parameters(s);
 371         } else {
 372             s->ier = val & 0x0f;
 373             /* If the backend device is a real serial port, turn polling of the modem
 374                status lines on physical port on or off depending on UART_IER_MSI state */
 375             if (s->poll_msl >= 0) {
 376                 if (s->ier & UART_IER_MSI) {
 377                      s->poll_msl = 1;
 378                      serial_update_msl(s);
 379                 } else {
 380                      qemu_del_timer(s->modem_status_poll);
 381                      s->poll_msl = 0;
 382                 }
 383             }
 384             if (s->lsr & UART_LSR_THRE) {
 385                 s->thr_ipending = 1;
 386                 serial_update_irq(s);
 387             }
 388         }
 389         break;
 390     case 2:
 391         val = val & 0xFF;
 392
 393         if (s->fcr == val)
 394             break;
 395
 396         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 397         if ((val ^ s->fcr) & UART_FCR_FE)
 398             val |= UART_FCR_XFR | UART_FCR_RFR;
 399
 400         /* FIFO clear */
 401
 402         if (val & UART_FCR_RFR) {
 403             qemu_del_timer(s->fifo_timeout_timer);
 404             s->timeout_ipending=0;
 405             fifo_clear(s,RECV_FIFO);
 406         }
 407
 408         if (val & UART_FCR_XFR) {
 409             fifo_clear(s,XMIT_FIFO);
 410         }
 411
 412         if (val & UART_FCR_FE) {
 413             s->iir |= UART_IIR_FE;
 414             /* Set RECV_FIFO trigger Level */
 415             switch (val & 0xC0) {
 416             case UART_FCR_ITL_1:
 417                 s->recv_fifo.itl = 1;
 418                 break;
 419             case UART_FCR_ITL_2:
 420                 s->recv_fifo.itl = 4;
 421                 break;
 422             case UART_FCR_ITL_3:
 423                 s->recv_fifo.itl = 8;
 424                 break;
 425             case UART_FCR_ITL_4:
 426                 s->recv_fifo.itl = 14;
 427                 break;
 428             }
 429         } else
 430             s->iir &= ~UART_IIR_FE;
 431
 432         /* Set fcr - or at least the bits in it that are supposed to "stick" */
 433         s->fcr = val & 0xC9;
 434         serial_update_irq(s);
 435         break;
 436     case 3:
 437         {
 438             int break_enable;
 439             s->lcr = val;
 440             serial_update_parameters(s);
 441             break_enable = (val >> 6) & 1;
 442             if (break_enable != s->last_break_enable) {
 443                 s->last_break_enable = break_enable;
 444                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 445                                &break_enable);
 446             }
 447         }
 448         break;
 449     case 4:
 450         {
 451             int flags;
 452             int old_mcr = s->mcr;
 453             s->mcr = val & 0x1f;
 454             if (val & UART_MCR_LOOP)
 455                 break;
 456
 457             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 458
 459                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 460
 461                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 462
 463                 if (val & UART_MCR_RTS)
 464                     flags |= CHR_TIOCM_RTS;
 465                 if (val & UART_MCR_DTR)
 466                     flags |= CHR_TIOCM_DTR;
 467
 468                 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 469                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 470                    from the device/computer at the other end of the serial line */
 471                 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time);
 472             }
 473         }
 474         break;
 475     case 5:
 476         break;
 477     case 6:
 478         break;
 479     case 7:
 480         s->scr = val;
 481         break;
 482     }
 483 }
 484
 485 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 486 {
 487     SerialState *s = opaque;
 488     uint32_t ret;
 489
 490     addr &= 7;
 491     switch(addr) {
 492     default:
 493     case 0:
 494         if (s->lcr & UART_LCR_DLAB) {
 495             ret = s->divider & 0xff;
 496         } else {
 497             if(s->fcr & UART_FCR_FE) {
 498                 ret = fifo_get(s,RECV_FIFO);
 499                 if (s->recv_fifo.count == 0)
 500                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 501                 else
 502                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 503                 s->timeout_ipending = 0;
 504             } else {
 505                 ret = s->rbr;
 506                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 507             }
 508             serial_update_irq(s);
 509             if (!(s->mcr & UART_MCR_LOOP)) {
 510                 /* in loopback mode, don't receive any data */
 511                 qemu_chr_accept_input(s->chr);
 512             }
 513         }
 514         break;
 515     case 1:
 516         if (s->lcr & UART_LCR_DLAB) {
 517             ret = (s->divider >> 8) & 0xff;
 518         } else {
 519             ret = s->ier;
 520         }
 521         break;
 522     case 2:
 523         ret = s->iir;
 524             s->thr_ipending = 0;
 525         serial_update_irq(s);
 526         break;
 527     case 3:
 528         ret = s->lcr;
 529         break;
 530     case 4:
 531         ret = s->mcr;
 532         break;
 533     case 5:
 534         ret = s->lsr;
 535         /* Clear break interrupt */
 536         if (s->lsr & UART_LSR_BI) {
 537             s->lsr &= ~UART_LSR_BI;
 538             serial_update_irq(s);
 539         }
 540         break;
 541     case 6:
 542         if (s->mcr & UART_MCR_LOOP) {
 543             /* in loopback, the modem output pins are connected to the
 544                inputs */
 545             ret = (s->mcr & 0x0c) << 4;
 546             ret |= (s->mcr & 0x02) << 3;
 547             ret |= (s->mcr & 0x01) << 5;
 548         } else {
 549             if (s->poll_msl >= 0)
 550                 serial_update_msl(s);
 551             ret = s->msr;
 552             /* Clear delta bits & msr int after read, if they were set */
 553             if (s->msr & UART_MSR_ANY_DELTA) {
 554                 s->msr &= 0xF0;
 555                 serial_update_irq(s);
 556             }
 557         }
 558         break;
 559     case 7:
 560         ret = s->scr;
 561         break;
 562     }
 563 #ifdef DEBUG_SERIAL
 564     printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
 565 #endif
 566     return ret;
 567 }
 568
 569 static int serial_can_receive(SerialState *s)
 570 {
 571     if(s->fcr & UART_FCR_FE) {
 572         if(s->recv_fifo.count < UART_FIFO_LENGTH)
 573         /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
 574         advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
 575         effectively overriding the ITL that the guest has set. */
 576              return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
 577         else
 578              return 0;
 579     } else {
 580     return !(s->lsr & UART_LSR_DR);
 581     }
 582 }
 583
 584 static void serial_receive_break(SerialState *s)
 585 {
 586     s->rbr = 0;
 587     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 588     serial_update_irq(s);
 589 }
 590
 591 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 592 static void fifo_timeout_int (void *opaque) {
 593     SerialState *s = opaque;
 594     if (s->recv_fifo.count) {
 595         s->timeout_ipending = 1;
 596         serial_update_irq(s);
 597     }
 598 }
 599
 600 static int serial_can_receive1(void *opaque)
 601 {
 602     SerialState *s = opaque;
 603     return serial_can_receive(s);
 604 }
 605
 606 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 607 {
 608     SerialState *s = opaque;
 609     if(s->fcr & UART_FCR_FE) {
 610         int i;
 611         for (i = 0; i < size; i++) {
 612             fifo_put(s, RECV_FIFO, buf[i]);
 613         }
 614         s->lsr |= UART_LSR_DR;
 615         /* call the timeout receive callback in 4 char transmit time */
 616         qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
 617     } else {
 618         s->rbr = buf[0];
 619         s->lsr |= UART_LSR_DR;
 620     }
 621     serial_update_irq(s);
 622 }
 623
 624 static void serial_event(void *opaque, int event)
 625 {
 626     SerialState *s = opaque;
 627 #ifdef DEBUG_SERIAL
 628     printf("serial: event %x\n", event);
 629 #endif
 630     if (event == CHR_EVENT_BREAK)
 631         serial_receive_break(s);
 632 }
 633
 634 static void serial_save(QEMUFile *f, void *opaque)
 635 {
 636     SerialState *s = opaque;
 637
 638     qemu_put_be16s(f,&s->divider);
 639     qemu_put_8s(f,&s->rbr);
 640     qemu_put_8s(f,&s->ier);
 641     qemu_put_8s(f,&s->iir);
 642     qemu_put_8s(f,&s->lcr);
 643     qemu_put_8s(f,&s->mcr);
 644     qemu_put_8s(f,&s->lsr);
 645     qemu_put_8s(f,&s->msr);
 646     qemu_put_8s(f,&s->scr);
 647     qemu_put_8s(f,&s->fcr);
 648 }
 649
 650 static int serial_load(QEMUFile *f, void *opaque, int version_id)
 651 {
 652     SerialState *s = opaque;
 653     uint8_t fcr = 0;
 654
 655     if(version_id > 3)
 656         return -EINVAL;
 657
 658     if (version_id >= 2)
 659         qemu_get_be16s(f, &s->divider);
 660     else
 661         s->divider = qemu_get_byte(f);
 662     qemu_get_8s(f,&s->rbr);
 663     qemu_get_8s(f,&s->ier);
 664     qemu_get_8s(f,&s->iir);
 665     qemu_get_8s(f,&s->lcr);
 666     qemu_get_8s(f,&s->mcr);
 667     qemu_get_8s(f,&s->lsr);
 668     qemu_get_8s(f,&s->msr);
 669     qemu_get_8s(f,&s->scr);
 670
 671     if (version_id >= 3)
 672         qemu_get_8s(f,&fcr);
 673
 674     /* Initialize fcr via setter to perform essential side-effects */
 675     serial_ioport_write(s, 0x02, fcr);
 676     return 0;
 677 }
 678
 679 static void serial_reset(void *opaque)
 680 {
 681     SerialState *s = opaque;
 682
 683     s->rbr = 0;
 684     s->ier = 0;
 685     s->iir = UART_IIR_NO_INT;
 686     s->lcr = 0;
 687     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 688     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 689     /* Default to 9600 baud, no parity, one stop bit */
 690     s->divider = 0x0C;
 691     s->mcr = UART_MCR_OUT2;
 692     s->scr = 0;
 693     s->tsr_retry = 0;
 694     s->char_transmit_time = (ticks_per_sec / 9600) * 9;
 695     s->poll_msl = 0;
 696
 697     fifo_clear(s,RECV_FIFO);
 698     fifo_clear(s,XMIT_FIFO);
 699
 700     s->last_xmit_ts = qemu_get_clock(vm_clock);
 701
 702     s->thr_ipending = 0;
 703     s->last_break_enable = 0;
 704     qemu_irq_lower(s->irq);
 705 }
 706
 707 static void serial_init_core(SerialState *s, qemu_irq irq, int baudbase,
 708                              CharDriverState *chr)
 709 {
 710     s->irq = irq;
 711     s->baudbase = baudbase;
 712     s->chr = chr;
 713
 714     s->modem_status_poll = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
 715
 716     s->fifo_timeout_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
 717     s->transmit_timer = qemu_new_timer(vm_clock, (QEMUTimerCB *) serial_xmit, s);
 718
 719     qemu_register_reset(serial_reset, s);
 720     serial_reset(s);
 721
 722 }
 723
 724 /* If fd is zero, it means that the serial device uses the console */
 725 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 726                          CharDriverState *chr)
 727 {
 728     SerialState *s;
 729
 730     s = qemu_mallocz(sizeof(SerialState));
 731     if (!s)
 732         return NULL;
 733
 734     serial_init_core(s, irq, baudbase, chr);
 735
 736     register_savevm("serial", base, 3, serial_save, serial_load, s);
 737
 738     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 739     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 740     qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
 741                           serial_event, s);
 742     return s;
 743 }
 744
 745 /* Memory mapped interface */
 746 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
 747 {
 748     SerialState *s = opaque;
 749
 750     return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
 751 }
 752
 753 void serial_mm_writeb (void *opaque,
 754                        target_phys_addr_t addr, uint32_t value)
 755 {
 756     SerialState *s = opaque;
 757
 758     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
 759 }
 760
 761 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
 762 {
 763     SerialState *s = opaque;
 764     uint32_t val;
 765
 766     val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
 767 #ifdef TARGET_WORDS_BIGENDIAN
 768     val = bswap16(val);
 769 #endif
 770     return val;
 771 }
 772
 773 void serial_mm_writew (void *opaque,
 774                        target_phys_addr_t addr, uint32_t value)
 775 {
 776     SerialState *s = opaque;
 777 #ifdef TARGET_WORDS_BIGENDIAN
 778     value = bswap16(value);
 779 #endif
 780     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
 781 }
 782
 783 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
 784 {
 785     SerialState *s = opaque;
 786     uint32_t val;
 787
 788     val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
 789 #ifdef TARGET_WORDS_BIGENDIAN
 790     val = bswap32(val);
 791 #endif
 792     return val;
 793 }
 794
 795 void serial_mm_writel (void *opaque,
 796                        target_phys_addr_t addr, uint32_t value)
 797 {
 798     SerialState *s = opaque;
 799 #ifdef TARGET_WORDS_BIGENDIAN
 800     value = bswap32(value);
 801 #endif
 802     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
 803 }
 804
 805 static CPUReadMemoryFunc *serial_mm_read[] = {
 806     &serial_mm_readb,
 807     &serial_mm_readw,
 808     &serial_mm_readl,
 809 };
 810
 811 static CPUWriteMemoryFunc *serial_mm_write[] = {
 812     &serial_mm_writeb,
 813     &serial_mm_writew,
 814     &serial_mm_writel,
 815 };
 816
 817 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 818                              qemu_irq irq, int baudbase,
 819                              CharDriverState *chr, int ioregister)
 820 {
 821     SerialState *s;
 822     int s_io_memory;
 823
 824     s = qemu_mallocz(sizeof(SerialState));
 825     if (!s)
 826         return NULL;
 827
 828     s->base = base;
 829     s->it_shift = it_shift;
 830
 831     serial_init_core(s, irq, baudbase, chr);
 832     register_savevm("serial", base, 3, serial_save, serial_load, s);
 833
 834     if (ioregister) {
 835         s_io_memory = cpu_register_io_memory(0, serial_mm_read,
 836                                              serial_mm_write, s);
 837         cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 838     }
 839     qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
 840                           serial_event, s);
 841     serial_update_msl(s);
 842     return s;
 843 }