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Fix dots per clock value, cleanup and "optimize"
[qemu/mini2440.git] / tcg / arm / tcg-target.c
blobdee1ebca59efb2c492b0c867dfc7bd45e83255d7
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Andrzej Zaborowski
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
25 "%r0",
26 "%r1",
27 "%r2",
28 "%r3",
29 "%r4",
30 "%r5",
31 "%r6",
32 "%r7",
33 "%r8",
34 "%r9",
35 "%r10",
36 "%r11",
37 "%r12",
38 "%r13",
39 "%r14",
40 };
41
42 int tcg_target_reg_alloc_order[] = {
43 TCG_REG_R0,
44 TCG_REG_R1,
45 TCG_REG_R2,
46 TCG_REG_R3,
47 TCG_REG_R4,
48 TCG_REG_R5,
49 TCG_REG_R6,
50 TCG_REG_R7,
51 TCG_REG_R8,
52 TCG_REG_R9,
53 TCG_REG_R10,
54 TCG_REG_R11,
55 TCG_REG_R12,
56 TCG_REG_R13,
57 TCG_REG_R14,
58 };
59
60 const int tcg_target_call_iarg_regs[4] = {
61 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
62 };
63 const int tcg_target_call_oarg_regs[2] = {
64 TCG_REG_R0, TCG_REG_R1
65 };
66
67 static void patch_reloc(uint8_t *code_ptr, int type,
68 tcg_target_long value, tcg_target_long addend)
69 {
70 switch (type) {
71 case R_ARM_ABS32:
72 *(uint32_t *) code_ptr = value;
73 break;
74
75 case R_ARM_CALL:
76 case R_ARM_JUMP24:
77 default:
78 tcg_abort();
79
80 case R_ARM_PC24:
81 *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & 0xff000000) |
82 (((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff);
83 break;
84 }
85 }
86
87 /* maximum number of register used for input function arguments */
88 static inline int tcg_target_get_call_iarg_regs_count(int flags)
89 {
90 return 4;
91 }
92
93 /* parse target specific constraints */
94 int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
95 {
96 const char *ct_str;
97
98 ct_str = *pct_str;
99 switch (ct_str[0]) {
100 case 'r':
101 #ifndef CONFIG_SOFTMMU
102 case 'd':
103 case 'D':
104 case 'x':
105 case 'X':
106 #endif
107 ct->ct |= TCG_CT_REG;
108 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
109 break;
110
111 #ifdef CONFIG_SOFTMMU
112 /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */
113 case 'x':
114 ct->ct |= TCG_CT_REG;
115 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
116 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
117 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
118 break;
119
120 /* qemu_ld64 data_reg */
121 case 'd':
122 ct->ct |= TCG_CT_REG;
123 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
124 /* r1 is still needed to load data_reg2, so don't use it. */
125 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
126 break;
127
128 /* qemu_ld/st64 data_reg2 */
129 case 'D':
130 ct->ct |= TCG_CT_REG;
131 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
132 /* r0, r1 and optionally r2 will be overwritten by the address
133 * and the low word of data, so don't use these. */
134 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
135 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
136 # if TARGET_LONG_BITS == 64
137 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
138 # endif
139 break;
140
141 # if TARGET_LONG_BITS == 64
142 /* qemu_ld/st addr_reg2 */
143 case 'X':
144 ct->ct |= TCG_CT_REG;
145 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
146 /* r0 will be overwritten by the low word of base, so don't use it. */
147 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
148 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
149 break;
150 # endif
151 #endif
152
153 case '1':
154 ct->ct |= TCG_CT_REG;
155 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
156 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
157 break;
158
159 case '2':
160 ct->ct |= TCG_CT_REG;
161 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
162 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
163 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
164 break;
165
166 default:
167 return -1;
168 }
169 ct_str++;
170 *pct_str = ct_str;
171
172 return 0;
173 }
174
175 /* Test if a constant matches the constraint.
176 * TODO: define constraints for:
177 *
178 * ldr/str offset: between -0xfff and 0xfff
179 * ldrh/strh offset: between -0xff and 0xff
180 * mov operand2: values represented with x << (2 * y), x < 0x100
181 * add, sub, eor...: ditto
182 */
183 static inline int tcg_target_const_match(tcg_target_long val,
184 const TCGArgConstraint *arg_ct)
185 {
186 int ct;
187 ct = arg_ct->ct;
188 if (ct & TCG_CT_CONST)
189 return 1;
190 else
191 return 0;
192 }
193
194 enum arm_data_opc_e {
195 ARITH_AND = 0x0,
196 ARITH_EOR = 0x1,
197 ARITH_SUB = 0x2,
198 ARITH_RSB = 0x3,
199 ARITH_ADD = 0x4,
200 ARITH_ADC = 0x5,
201 ARITH_SBC = 0x6,
202 ARITH_RSC = 0x7,
203 ARITH_TST = 0x8,
204 ARITH_CMP = 0xa,
205 ARITH_CMN = 0xb,
206 ARITH_ORR = 0xc,
207 ARITH_MOV = 0xd,
208 ARITH_BIC = 0xe,
209 ARITH_MVN = 0xf,
210 };
211
212 #define TO_CPSR(opc) \
213 ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
214
215 #define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
216 #define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
217 #define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
218 #define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
219 #define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
220 #define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
221 #define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
222 #define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
223
224 enum arm_cond_code_e {
225 COND_EQ = 0x0,
226 COND_NE = 0x1,
227 COND_CS = 0x2, /* Unsigned greater or equal */
228 COND_CC = 0x3, /* Unsigned less than */
229 COND_MI = 0x4, /* Negative */
230 COND_PL = 0x5, /* Zero or greater */
231 COND_VS = 0x6, /* Overflow */
232 COND_VC = 0x7, /* No overflow */
233 COND_HI = 0x8, /* Unsigned greater than */
234 COND_LS = 0x9, /* Unsigned less or equal */
235 COND_GE = 0xa,
236 COND_LT = 0xb,
237 COND_GT = 0xc,
238 COND_LE = 0xd,
239 COND_AL = 0xe,
240 };
241
242 static const uint8_t tcg_cond_to_arm_cond[10] = {
243 [TCG_COND_EQ] = COND_EQ,
244 [TCG_COND_NE] = COND_NE,
245 [TCG_COND_LT] = COND_LT,
246 [TCG_COND_GE] = COND_GE,
247 [TCG_COND_LE] = COND_LE,
248 [TCG_COND_GT] = COND_GT,
249 /* unsigned */
250 [TCG_COND_LTU] = COND_CC,
251 [TCG_COND_GEU] = COND_CS,
252 [TCG_COND_LEU] = COND_LS,
253 [TCG_COND_GTU] = COND_HI,
254 };
255
256 static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
257 {
258 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
259 }
260
261 static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
262 {
263 tcg_out32(s, (cond << 28) | 0x0a000000 |
264 (((offset - 8) >> 2) & 0x00ffffff));
265 }
266
267 static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
268 {
269 #ifdef WORDS_BIGENDIAN
270 tcg_out8(s, (cond << 4) | 0x0a);
271 s->code_ptr += 3;
272 #else
273 s->code_ptr += 3;
274 tcg_out8(s, (cond << 4) | 0x0a);
275 #endif
276 }
277
278 static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
279 {
280 tcg_out32(s, (cond << 28) | 0x0b000000 |
281 (((offset - 8) >> 2) & 0x00ffffff));
282 }
283
284 static inline void tcg_out_dat_reg(TCGContext *s,
285 int cond, int opc, int rd, int rn, int rm, int shift)
286 {
287 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
288 (rn << 16) | (rd << 12) | shift | rm);
289 }
290
291 static inline void tcg_out_dat_reg2(TCGContext *s,
292 int cond, int opc0, int opc1, int rd0, int rd1,
293 int rn0, int rn1, int rm0, int rm1, int shift)
294 {
295 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
296 (rn0 << 16) | (rd0 << 12) | shift | rm0);
297 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
298 (rn1 << 16) | (rd1 << 12) | shift | rm1);
299 }
300
301 static inline void tcg_out_dat_imm(TCGContext *s,
302 int cond, int opc, int rd, int rn, int im)
303 {
304 tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
305 (rn << 16) | (rd << 12) | im);
306 }
307
308 static inline void tcg_out_movi32(TCGContext *s,
309 int cond, int rd, int32_t arg)
310 {
311 int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8);
312
313 /* TODO: This is very suboptimal, we can easily have a constant
314 * pool somewhere after all the instructions. */
315
316 if (arg < 0 && arg > -0x100)
317 return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
318
319 if (offset < 0x100 && offset > -0x100)
320 return offset >= 0 ?
321 tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
322 tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
323
324 tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
325 if (arg & 0x0000ff00)
326 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
327 ((arg >> 8) & 0xff) | 0xc00);
328 if (arg & 0x00ff0000)
329 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
330 ((arg >> 16) & 0xff) | 0x800);
331 if (arg & 0xff000000)
332 tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
333 ((arg >> 24) & 0xff) | 0x400);
334 }
335
336 static inline void tcg_out_mul32(TCGContext *s,
337 int cond, int rd, int rs, int rm)
338 {
339 if (rd != rm)
340 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
341 (rs << 8) | 0x90 | rm);
342 else if (rd != rs)
343 tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
344 (rm << 8) | 0x90 | rs);
345 else {
346 tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
347 (rs << 8) | 0x90 | rm);
348 tcg_out_dat_reg(s, cond, ARITH_MOV,
349 rd, 0, 8, SHIFT_IMM_LSL(0));
350 }
351 }
352
353 static inline void tcg_out_umull32(TCGContext *s,
354 int cond, int rd0, int rd1, int rs, int rm)
355 {
356 if (rd0 != rm && rd1 != rm)
357 tcg_out32(s, (cond << 28) | 0x800090 |
358 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
359 else if (rd0 != rs && rd1 != rs)
360 tcg_out32(s, (cond << 28) | 0x800090 |
361 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
362 else {
363 tcg_out_dat_reg(s, cond, ARITH_MOV,
364 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
365 tcg_out32(s, (cond << 28) | 0x800098 |
366 (rd1 << 16) | (rd0 << 12) | (rs << 8));
367 }
368 }
369
370 static inline void tcg_out_smull32(TCGContext *s,
371 int cond, int rd0, int rd1, int rs, int rm)
372 {
373 if (rd0 != rm && rd1 != rm)
374 tcg_out32(s, (cond << 28) | 0xc00090 |
375 (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
376 else if (rd0 != rs && rd1 != rs)
377 tcg_out32(s, (cond << 28) | 0xc00090 |
378 (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
379 else {
380 tcg_out_dat_reg(s, cond, ARITH_MOV,
381 TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
382 tcg_out32(s, (cond << 28) | 0xc00098 |
383 (rd1 << 16) | (rd0 << 12) | (rs << 8));
384 }
385 }
386
387 static inline void tcg_out_ld32_12(TCGContext *s, int cond,
388 int rd, int rn, tcg_target_long im)
389 {
390 if (im >= 0)
391 tcg_out32(s, (cond << 28) | 0x05900000 |
392 (rn << 16) | (rd << 12) | (im & 0xfff));
393 else
394 tcg_out32(s, (cond << 28) | 0x05100000 |
395 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
396 }
397
398 static inline void tcg_out_st32_12(TCGContext *s, int cond,
399 int rd, int rn, tcg_target_long im)
400 {
401 if (im >= 0)
402 tcg_out32(s, (cond << 28) | 0x05800000 |
403 (rn << 16) | (rd << 12) | (im & 0xfff));
404 else
405 tcg_out32(s, (cond << 28) | 0x05000000 |
406 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
407 }
408
409 static inline void tcg_out_ld32_r(TCGContext *s, int cond,
410 int rd, int rn, int rm)
411 {
412 tcg_out32(s, (cond << 28) | 0x07900000 |
413 (rn << 16) | (rd << 12) | rm);
414 }
415
416 static inline void tcg_out_st32_r(TCGContext *s, int cond,
417 int rd, int rn, int rm)
418 {
419 tcg_out32(s, (cond << 28) | 0x07800000 |
420 (rn << 16) | (rd << 12) | rm);
421 }
422
423 /* Register pre-increment with base writeback. */
424 static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
425 int rd, int rn, int rm)
426 {
427 tcg_out32(s, (cond << 28) | 0x07b00000 |
428 (rn << 16) | (rd << 12) | rm);
429 }
430
431 static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
432 int rd, int rn, int rm)
433 {
434 tcg_out32(s, (cond << 28) | 0x07a00000 |
435 (rn << 16) | (rd << 12) | rm);
436 }
437
438 static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
439 int rd, int rn, tcg_target_long im)
440 {
441 if (im >= 0)
442 tcg_out32(s, (cond << 28) | 0x01d000b0 |
443 (rn << 16) | (rd << 12) |
444 ((im & 0xf0) << 4) | (im & 0xf));
445 else
446 tcg_out32(s, (cond << 28) | 0x015000b0 |
447 (rn << 16) | (rd << 12) |
448 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
449 }
450
451 static inline void tcg_out_st16u_8(TCGContext *s, int cond,
452 int rd, int rn, tcg_target_long im)
453 {
454 if (im >= 0)
455 tcg_out32(s, (cond << 28) | 0x01c000b0 |
456 (rn << 16) | (rd << 12) |
457 ((im & 0xf0) << 4) | (im & 0xf));
458 else
459 tcg_out32(s, (cond << 28) | 0x014000b0 |
460 (rn << 16) | (rd << 12) |
461 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
462 }
463
464 static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
465 int rd, int rn, int rm)
466 {
467 tcg_out32(s, (cond << 28) | 0x019000b0 |
468 (rn << 16) | (rd << 12) | rm);
469 }
470
471 static inline void tcg_out_st16u_r(TCGContext *s, int cond,
472 int rd, int rn, int rm)
473 {
474 tcg_out32(s, (cond << 28) | 0x018000b0 |
475 (rn << 16) | (rd << 12) | rm);
476 }
477
478 static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
479 int rd, int rn, tcg_target_long im)
480 {
481 if (im >= 0)
482 tcg_out32(s, (cond << 28) | 0x01d000f0 |
483 (rn << 16) | (rd << 12) |
484 ((im & 0xf0) << 4) | (im & 0xf));
485 else
486 tcg_out32(s, (cond << 28) | 0x015000f0 |
487 (rn << 16) | (rd << 12) |
488 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
489 }
490
491 static inline void tcg_out_st16s_8(TCGContext *s, int cond,
492 int rd, int rn, tcg_target_long im)
493 {
494 if (im >= 0)
495 tcg_out32(s, (cond << 28) | 0x01c000f0 |
496 (rn << 16) | (rd << 12) |
497 ((im & 0xf0) << 4) | (im & 0xf));
498 else
499 tcg_out32(s, (cond << 28) | 0x014000f0 |
500 (rn << 16) | (rd << 12) |
501 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
502 }
503
504 static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
505 int rd, int rn, int rm)
506 {
507 tcg_out32(s, (cond << 28) | 0x019000f0 |
508 (rn << 16) | (rd << 12) | rm);
509 }
510
511 static inline void tcg_out_st16s_r(TCGContext *s, int cond,
512 int rd, int rn, int rm)
513 {
514 tcg_out32(s, (cond << 28) | 0x018000f0 |
515 (rn << 16) | (rd << 12) | rm);
516 }
517
518 static inline void tcg_out_ld8_12(TCGContext *s, int cond,
519 int rd, int rn, tcg_target_long im)
520 {
521 if (im >= 0)
522 tcg_out32(s, (cond << 28) | 0x05d00000 |
523 (rn << 16) | (rd << 12) | (im & 0xfff));
524 else
525 tcg_out32(s, (cond << 28) | 0x05500000 |
526 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
527 }
528
529 static inline void tcg_out_st8_12(TCGContext *s, int cond,
530 int rd, int rn, tcg_target_long im)
531 {
532 if (im >= 0)
533 tcg_out32(s, (cond << 28) | 0x05c00000 |
534 (rn << 16) | (rd << 12) | (im & 0xfff));
535 else
536 tcg_out32(s, (cond << 28) | 0x05400000 |
537 (rn << 16) | (rd << 12) | ((-im) & 0xfff));
538 }
539
540 static inline void tcg_out_ld8_r(TCGContext *s, int cond,
541 int rd, int rn, int rm)
542 {
543 tcg_out32(s, (cond << 28) | 0x07d00000 |
544 (rn << 16) | (rd << 12) | rm);
545 }
546
547 static inline void tcg_out_st8_r(TCGContext *s, int cond,
548 int rd, int rn, int rm)
549 {
550 tcg_out32(s, (cond << 28) | 0x07c00000 |
551 (rn << 16) | (rd << 12) | rm);
552 }
553
554 static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
555 int rd, int rn, tcg_target_long im)
556 {
557 if (im >= 0)
558 tcg_out32(s, (cond << 28) | 0x01d000d0 |
559 (rn << 16) | (rd << 12) |
560 ((im & 0xf0) << 4) | (im & 0xf));
561 else
562 tcg_out32(s, (cond << 28) | 0x015000d0 |
563 (rn << 16) | (rd << 12) |
564 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
565 }
566
567 static inline void tcg_out_st8s_8(TCGContext *s, int cond,
568 int rd, int rn, tcg_target_long im)
569 {
570 if (im >= 0)
571 tcg_out32(s, (cond << 28) | 0x01c000d0 |
572 (rn << 16) | (rd << 12) |
573 ((im & 0xf0) << 4) | (im & 0xf));
574 else
575 tcg_out32(s, (cond << 28) | 0x014000d0 |
576 (rn << 16) | (rd << 12) |
577 (((-im) & 0xf0) << 4) | ((-im) & 0xf));
578 }
579
580 static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
581 int rd, int rn, int rm)
582 {
583 tcg_out32(s, (cond << 28) | 0x019000d0 |
584 (rn << 16) | (rd << 12) | rm);
585 }
586
587 static inline void tcg_out_st8s_r(TCGContext *s, int cond,
588 int rd, int rn, int rm)
589 {
590 tcg_out32(s, (cond << 28) | 0x018000d0 |
591 (rn << 16) | (rd << 12) | rm);
592 }
593
594 static inline void tcg_out_ld32u(TCGContext *s, int cond,
595 int rd, int rn, int32_t offset)
596 {
597 if (offset > 0xfff || offset < -0xfff) {
598 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
599 tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
600 } else
601 tcg_out_ld32_12(s, cond, rd, rn, offset);
602 }
603
604 static inline void tcg_out_st32(TCGContext *s, int cond,
605 int rd, int rn, int32_t offset)
606 {
607 if (offset > 0xfff || offset < -0xfff) {
608 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
609 tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
610 } else
611 tcg_out_st32_12(s, cond, rd, rn, offset);
612 }
613
614 static inline void tcg_out_ld16u(TCGContext *s, int cond,
615 int rd, int rn, int32_t offset)
616 {
617 if (offset > 0xff || offset < -0xff) {
618 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
619 tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
620 } else
621 tcg_out_ld16u_8(s, cond, rd, rn, offset);
622 }
623
624 static inline void tcg_out_ld16s(TCGContext *s, int cond,
625 int rd, int rn, int32_t offset)
626 {
627 if (offset > 0xff || offset < -0xff) {
628 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
629 tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
630 } else
631 tcg_out_ld16s_8(s, cond, rd, rn, offset);
632 }
633
634 static inline void tcg_out_st16u(TCGContext *s, int cond,
635 int rd, int rn, int32_t offset)
636 {
637 if (offset > 0xff || offset < -0xff) {
638 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
639 tcg_out_st16u_r(s, cond, rd, rn, TCG_REG_R8);
640 } else
641 tcg_out_st16u_8(s, cond, rd, rn, offset);
642 }
643
644 static inline void tcg_out_ld8u(TCGContext *s, int cond,
645 int rd, int rn, int32_t offset)
646 {
647 if (offset > 0xfff || offset < -0xfff) {
648 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
649 tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
650 } else
651 tcg_out_ld8_12(s, cond, rd, rn, offset);
652 }
653
654 static inline void tcg_out_ld8s(TCGContext *s, int cond,
655 int rd, int rn, int32_t offset)
656 {
657 if (offset > 0xff || offset < -0xff) {
658 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
659 tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
660 } else
661 tcg_out_ld8s_8(s, cond, rd, rn, offset);
662 }
663
664 static inline void tcg_out_st8u(TCGContext *s, int cond,
665 int rd, int rn, int32_t offset)
666 {
667 if (offset > 0xfff || offset < -0xfff) {
668 tcg_out_movi32(s, cond, TCG_REG_R8, offset);
669 tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
670 } else
671 tcg_out_st8_12(s, cond, rd, rn, offset);
672 }
673
674 static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
675 {
676 int32_t val;
677
678 val = addr - (tcg_target_long) s->code_ptr;
679 if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
680 tcg_out_b(s, cond, val);
681 else {
682 #if 1
683 tcg_abort();
684 #else
685 if (cond == COND_AL) {
686 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
687 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
688 } else {
689 tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
690 tcg_out_dat_reg(s, cond, ARITH_ADD,
691 15, 15, TCG_REG_R8, SHIFT_IMM_LSL(0));
692 }
693 #endif
694 }
695 }
696
697 static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
698 {
699 int32_t val;
700
701 #ifdef SAVE_LR
702 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0));
703 #endif
704
705 val = addr - (tcg_target_long) s->code_ptr;
706 if (val < 0x01fffffd && val > -0x01fffffd)
707 tcg_out_bl(s, cond, val);
708 else {
709 #if 1
710 tcg_abort();
711 #else
712 if (cond == COND_AL) {
713 tcg_out_dat_imm(s, cond, ARITH_ADD, 14, 15, 4);
714 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
715 tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
716 } else {
717 tcg_out_movi32(s, cond, TCG_REG_R9, addr);
718 tcg_out_dat_imm(s, cond, ARITH_MOV, 14, 0, 15);
719 tcg_out_bx(s, cond, TCG_REG_R9);
720 }
721 #endif
722 }
723
724 #ifdef SAVE_LR
725 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
726 #endif
727 }
728
729 static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
730 {
731 #ifdef SAVE_LR
732 tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0));
733 #endif
734 /* TODO: on ARMv5 and ARMv6 replace with tcg_out_blx(s, cond, arg); */
735 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 15, SHIFT_IMM_LSL(0));
736 tcg_out_bx(s, cond, arg);
737 #ifdef SAVE_LR
738 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
739 #endif
740 }
741
742 static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
743 {
744 TCGLabel *l = &s->labels[label_index];
745
746 if (l->has_value)
747 tcg_out_goto(s, cond, l->u.value);
748 else if (cond == COND_AL) {
749 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
750 tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
751 s->code_ptr += 4;
752 } else {
753 /* Probably this should be preferred even for COND_AL... */
754 tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
755 tcg_out_b_noaddr(s, cond);
756 }
757 }
758
759 static void tcg_out_div_helper(TCGContext *s, int cond, const TCGArg *args,
760 void *helper_div, void *helper_rem, int shift)
761 {
762 int div_reg = args[0];
763 int rem_reg = args[1];
764
765 /* stmdb sp!, { r0 - r3, ip, lr } */
766 /* (Note that we need an even number of registers as per EABI) */
767 tcg_out32(s, (cond << 28) | 0x092d500f);
768
769 tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0));
770 tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0));
771 tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0));
772 tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift);
773
774 tcg_out_call(s, cond, (uint32_t) helper_div);
775 tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 0, SHIFT_IMM_LSL(0));
776
777 /* ldmia sp, { r0 - r3, fp, lr } */
778 tcg_out32(s, (cond << 28) | 0x089d500f);
779
780 tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0));
781 tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0));
782 tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0));
783 tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift);
784
785 tcg_out_call(s, cond, (uint32_t) helper_rem);
786
787 tcg_out_dat_reg(s, cond, ARITH_MOV, rem_reg, 0, 0, SHIFT_IMM_LSL(0));
788 tcg_out_dat_reg(s, cond, ARITH_MOV, div_reg, 0, 8, SHIFT_IMM_LSL(0));
789
790 /* ldr r0, [sp], #4 */
791 if (rem_reg != 0 && div_reg != 0)
792 tcg_out32(s, (cond << 28) | 0x04bd0004);
793 /* ldr r1, [sp], #4 */
794 if (rem_reg != 1 && div_reg != 1)
795 tcg_out32(s, (cond << 28) | 0x04bd1004);
796 /* ldr r2, [sp], #4 */
797 if (rem_reg != 2 && div_reg != 2)
798 tcg_out32(s, (cond << 28) | 0x04bd2004);
799 /* ldr r3, [sp], #4 */
800 if (rem_reg != 3 && div_reg != 3)
801 tcg_out32(s, (cond << 28) | 0x04bd3004);
802 /* ldr ip, [sp], #4 */
803 if (rem_reg != 12 && div_reg != 12)
804 tcg_out32(s, (cond << 28) | 0x04bdc004);
805 /* ldr lr, [sp], #4 */
806 if (rem_reg != 14 && div_reg != 14)
807 tcg_out32(s, (cond << 28) | 0x04bde004);
808 }
809
810 #ifdef CONFIG_SOFTMMU
811
812 #include "../../softmmu_defs.h"
813
814 static void *qemu_ld_helpers[4] = {
815 __ldb_mmu,
816 __ldw_mmu,
817 __ldl_mmu,
818 __ldq_mmu,
819 };
820
821 static void *qemu_st_helpers[4] = {
822 __stb_mmu,
823 __stw_mmu,
824 __stl_mmu,
825 __stq_mmu,
826 };
827 #endif
828
829 #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
830
831 static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
832 const TCGArg *args, int opc)
833 {
834 int addr_reg, data_reg, data_reg2;
835 #ifdef CONFIG_SOFTMMU
836 int mem_index, s_bits;
837 # if TARGET_LONG_BITS == 64
838 int addr_reg2;
839 # endif
840 uint32_t *label_ptr;
841 #endif
842
843 data_reg = *args++;
844 if (opc == 3)
845 data_reg2 = *args++;
846 else
847 data_reg2 = 0; /* surpress warning */
848 addr_reg = *args++;
849 #if TARGET_LONG_BITS == 64
850 addr_reg2 = *args++;
851 #endif
852 #ifdef CONFIG_SOFTMMU
853 mem_index = *args;
854 s_bits = opc & 3;
855
856 /* Should generate something like the following:
857 * shr r8, addr_reg, #TARGET_PAGE_BITS
858 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
859 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
860 */
861 # if CPU_TLB_BITS > 8
862 # error
863 # endif
864 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
865 8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
866 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
867 0, 8, CPU_TLB_SIZE - 1);
868 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
869 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
870 /* In the
871 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
872 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
873 * not exceed otherwise, so use an
874 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
875 * before.
876 */
877 if (mem_index)
878 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
879 (mem_index << (TLB_SHIFT & 1)) |
880 ((16 - (TLB_SHIFT >> 1)) << 8));
881 tcg_out_ld32_12(s, COND_AL, 1, 0,
882 offsetof(CPUState, tlb_table[0][0].addr_read));
883 tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
884 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
885 /* Check alignment. */
886 if (s_bits)
887 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
888 0, addr_reg, (1 << s_bits) - 1);
889 # if TARGET_LONG_BITS == 64
890 /* XXX: possibly we could use a block data load or writeback in
891 * the first access. */
892 tcg_out_ld32_12(s, COND_EQ, 1, 0,
893 offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
894 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
895 0, 1, addr_reg2, SHIFT_IMM_LSL(0));
896 # endif
897 tcg_out_ld32_12(s, COND_EQ, 1, 0,
898 offsetof(CPUState, tlb_table[0][0].addend));
899
900 switch (opc) {
901 case 0:
902 tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, 1);
903 break;
904 case 0 | 4:
905 tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, 1);
906 break;
907 case 1:
908 tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, 1);
909 break;
910 case 1 | 4:
911 tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, 1);
912 break;
913 case 2:
914 default:
915 tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, 1);
916 break;
917 case 3:
918 tcg_out_ld32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
919 tcg_out_ld32_12(s, COND_EQ, data_reg2, 1, 4);
920 break;
921 }
922
923 label_ptr = (void *) s->code_ptr;
924 tcg_out_b(s, COND_EQ, 8);
925
926 # ifdef SAVE_LR
927 tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
928 # endif
929
930 /* TODO: move this code to where the constants pool will be */
931 if (addr_reg)
932 tcg_out_dat_reg(s, cond, ARITH_MOV,
933 0, 0, addr_reg, SHIFT_IMM_LSL(0));
934 # if TARGET_LONG_BITS == 32
935 tcg_out_dat_imm(s, cond, ARITH_MOV, 1, 0, mem_index);
936 # else
937 if (addr_reg2 != 1)
938 tcg_out_dat_reg(s, cond, ARITH_MOV,
939 1, 0, addr_reg2, SHIFT_IMM_LSL(0));
940 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
941 # endif
942 tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] -
943 (tcg_target_long) s->code_ptr);
944
945 switch (opc) {
946 case 0 | 4:
947 tcg_out_dat_reg(s, cond, ARITH_MOV,
948 0, 0, 0, SHIFT_IMM_LSL(24));
949 tcg_out_dat_reg(s, cond, ARITH_MOV,
950 data_reg, 0, 0, SHIFT_IMM_ASR(24));
951 break;
952 case 1 | 4:
953 tcg_out_dat_reg(s, cond, ARITH_MOV,
954 0, 0, 0, SHIFT_IMM_LSL(16));
955 tcg_out_dat_reg(s, cond, ARITH_MOV,
956 data_reg, 0, 0, SHIFT_IMM_ASR(16));
957 break;
958 case 0:
959 case 1:
960 case 2:
961 default:
962 if (data_reg)
963 tcg_out_dat_reg(s, cond, ARITH_MOV,
964 data_reg, 0, 0, SHIFT_IMM_LSL(0));
965 break;
966 case 3:
967 if (data_reg != 0)
968 tcg_out_dat_reg(s, cond, ARITH_MOV,
969 data_reg, 0, 0, SHIFT_IMM_LSL(0));
970 if (data_reg2 != 1)
971 tcg_out_dat_reg(s, cond, ARITH_MOV,
972 data_reg2, 0, 1, SHIFT_IMM_LSL(0));
973 break;
974 }
975
976 # ifdef SAVE_LR
977 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
978 # endif
979
980 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
981 #else
982 switch (opc) {
983 case 0:
984 tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
985 break;
986 case 0 | 4:
987 tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
988 break;
989 case 1:
990 tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
991 break;
992 case 1 | 4:
993 tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
994 break;
995 case 2:
996 default:
997 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
998 break;
999 case 3:
1000 /* TODO: use block load -
1001 * check that data_reg2 > data_reg or the other way */
1002 tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1003 tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1004 break;
1005 }
1006 #endif
1007 }
1008
1009 static inline void tcg_out_qemu_st(TCGContext *s, int cond,
1010 const TCGArg *args, int opc)
1011 {
1012 int addr_reg, data_reg, data_reg2;
1013 #ifdef CONFIG_SOFTMMU
1014 int mem_index, s_bits;
1015 # if TARGET_LONG_BITS == 64
1016 int addr_reg2;
1017 # endif
1018 uint32_t *label_ptr;
1019 #endif
1020
1021 data_reg = *args++;
1022 if (opc == 3)
1023 data_reg2 = *args++;
1024 else
1025 data_reg2 = 0; /* surpress warning */
1026 addr_reg = *args++;
1027 #if TARGET_LONG_BITS == 64
1028 addr_reg2 = *args++;
1029 #endif
1030 #ifdef CONFIG_SOFTMMU
1031 mem_index = *args;
1032 s_bits = opc & 3;
1033
1034 /* Should generate something like the following:
1035 * shr r8, addr_reg, #TARGET_PAGE_BITS
1036 * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1037 * add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1038 */
1039 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1040 8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
1041 tcg_out_dat_imm(s, COND_AL, ARITH_AND,
1042 0, 8, CPU_TLB_SIZE - 1);
1043 tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
1044 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
1045 /* In the
1046 * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1047 * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1048 * not exceed otherwise, so use an
1049 * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1050 * before.
1051 */
1052 if (mem_index)
1053 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
1054 (mem_index << (TLB_SHIFT & 1)) |
1055 ((16 - (TLB_SHIFT >> 1)) << 8));
1056 tcg_out_ld32_12(s, COND_AL, 1, 0,
1057 offsetof(CPUState, tlb_table[0][0].addr_write));
1058 tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
1059 0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
1060 /* Check alignment. */
1061 if (s_bits)
1062 tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1063 0, addr_reg, (1 << s_bits) - 1);
1064 # if TARGET_LONG_BITS == 64
1065 /* XXX: possibly we could use a block data load or writeback in
1066 * the first access. */
1067 tcg_out_ld32_12(s, COND_EQ, 1, 0,
1068 offsetof(CPUState, tlb_table[0][0].addr_write)
1069 + 4);
1070 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
1071 0, 1, addr_reg2, SHIFT_IMM_LSL(0));
1072 # endif
1073 tcg_out_ld32_12(s, COND_EQ, 1, 0,
1074 offsetof(CPUState, tlb_table[0][0].addend));
1075
1076 switch (opc) {
1077 case 0:
1078 tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, 1);
1079 break;
1080 case 0 | 4:
1081 tcg_out_st8s_r(s, COND_EQ, data_reg, addr_reg, 1);
1082 break;
1083 case 1:
1084 tcg_out_st16u_r(s, COND_EQ, data_reg, addr_reg, 1);
1085 break;
1086 case 1 | 4:
1087 tcg_out_st16s_r(s, COND_EQ, data_reg, addr_reg, 1);
1088 break;
1089 case 2:
1090 default:
1091 tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, 1);
1092 break;
1093 case 3:
1094 tcg_out_st32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
1095 tcg_out_st32_12(s, COND_EQ, data_reg2, 1, 4);
1096 break;
1097 }
1098
1099 label_ptr = (void *) s->code_ptr;
1100 tcg_out_b(s, COND_EQ, 8);
1101
1102 /* TODO: move this code to where the constants pool will be */
1103 if (addr_reg)
1104 tcg_out_dat_reg(s, cond, ARITH_MOV,
1105 0, 0, addr_reg, SHIFT_IMM_LSL(0));
1106 # if TARGET_LONG_BITS == 32
1107 switch (opc) {
1108 case 0:
1109 tcg_out_dat_imm(s, cond, ARITH_AND, 1, data_reg, 0xff);
1110 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1111 break;
1112 case 1:
1113 tcg_out_dat_reg(s, cond, ARITH_MOV,
1114 1, 0, data_reg, SHIFT_IMM_LSL(16));
1115 tcg_out_dat_reg(s, cond, ARITH_MOV,
1116 1, 0, 1, SHIFT_IMM_LSR(16));
1117 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1118 break;
1119 case 2:
1120 if (data_reg != 1)
1121 tcg_out_dat_reg(s, cond, ARITH_MOV,
1122 1, 0, data_reg, SHIFT_IMM_LSL(0));
1123 tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1124 break;
1125 case 3:
1126 if (data_reg != 1)
1127 tcg_out_dat_reg(s, cond, ARITH_MOV,
1128 1, 0, data_reg, SHIFT_IMM_LSL(0));
1129 if (data_reg2 != 2)
1130 tcg_out_dat_reg(s, cond, ARITH_MOV,
1131 2, 0, data_reg2, SHIFT_IMM_LSL(0));
1132 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1133 break;
1134 }
1135 # else
1136 if (addr_reg2 != 1)
1137 tcg_out_dat_reg(s, cond, ARITH_MOV,
1138 1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1139 switch (opc) {
1140 case 0:
1141 tcg_out_dat_imm(s, cond, ARITH_AND, 2, data_reg, 0xff);
1142 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1143 break;
1144 case 1:
1145 tcg_out_dat_reg(s, cond, ARITH_MOV,
1146 2, 0, data_reg, SHIFT_IMM_LSL(16));
1147 tcg_out_dat_reg(s, cond, ARITH_MOV,
1148 2, 0, 2, SHIFT_IMM_LSR(16));
1149 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1150 break;
1151 case 2:
1152 if (data_reg != 2)
1153 tcg_out_dat_reg(s, cond, ARITH_MOV,
1154 2, 0, data_reg, SHIFT_IMM_LSL(0));
1155 tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1156 break;
1157 case 3:
1158 tcg_out_dat_imm(s, cond, ARITH_MOV, 8, 0, mem_index);
1159 tcg_out32(s, (cond << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1160 if (data_reg != 2)
1161 tcg_out_dat_reg(s, cond, ARITH_MOV,
1162 2, 0, data_reg, SHIFT_IMM_LSL(0));
1163 if (data_reg2 != 3)
1164 tcg_out_dat_reg(s, cond, ARITH_MOV,
1165 3, 0, data_reg2, SHIFT_IMM_LSL(0));
1166 break;
1167 }
1168 # endif
1169
1170 # ifdef SAVE_LR
1171 tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
1172 # endif
1173
1174 tcg_out_bl(s, cond, (tcg_target_long) qemu_st_helpers[s_bits] -
1175 (tcg_target_long) s->code_ptr);
1176 # if TARGET_LONG_BITS == 64
1177 if (opc == 3)
1178 tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 0x10);
1179 # endif
1180
1181 # ifdef SAVE_LR
1182 tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
1183 # endif
1184
1185 *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
1186 #else
1187 switch (opc) {
1188 case 0:
1189 tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1190 break;
1191 case 0 | 4:
1192 tcg_out_st8s_8(s, COND_AL, data_reg, addr_reg, 0);
1193 break;
1194 case 1:
1195 tcg_out_st16u_8(s, COND_AL, data_reg, addr_reg, 0);
1196 break;
1197 case 1 | 4:
1198 tcg_out_st16s_8(s, COND_AL, data_reg, addr_reg, 0);
1199 break;
1200 case 2:
1201 default:
1202 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1203 break;
1204 case 3:
1205 /* TODO: use block store -
1206 * check that data_reg2 > data_reg or the other way */
1207 tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1208 tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1209 break;
1210 }
1211 #endif
1212 }
1213
1214 static uint8_t *tb_ret_addr;
1215
1216 static inline void tcg_out_op(TCGContext *s, int opc,
1217 const TCGArg *args, const int *const_args)
1218 {
1219 int c;
1220
1221 switch (opc) {
1222 case INDEX_op_exit_tb:
1223 #ifdef SAVE_LR
1224 if (args[0] >> 8)
1225 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
1226 else
1227 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
1228 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 15, 0, 14, SHIFT_IMM_LSL(0));
1229 if (args[0] >> 8)
1230 tcg_out32(s, args[0]);
1231 #else
1232 if (args[0] >> 8)
1233 tcg_out_ld32_12(s, COND_AL, 0, 15, 0);
1234 else
1235 tcg_out_dat_imm(s, COND_AL, ARITH_MOV, 0, 0, args[0]);
1236 tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1237 if (args[0] >> 8)
1238 tcg_out32(s, args[0]);
1239 #endif
1240 break;
1241 case INDEX_op_goto_tb:
1242 if (s->tb_jmp_offset) {
1243 /* Direct jump method */
1244 #if 1
1245 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1246 tcg_out_b(s, COND_AL, 8);
1247 #else
1248 tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
1249 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1250 tcg_out32(s, 0);
1251 #endif
1252 } else {
1253 /* Indirect jump method */
1254 #if 1
1255 c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1256 if (c > 0xfff || c < -0xfff) {
1257 tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1258 (tcg_target_long) (s->tb_next + args[0]));
1259 tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1260 } else
1261 tcg_out_ld32_12(s, COND_AL, 15, 15, c);
1262 #else
1263 tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
1264 tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1265 tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1266 #endif
1267 }
1268 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1269 break;
1270 case INDEX_op_call:
1271 if (const_args[0])
1272 tcg_out_call(s, COND_AL, args[0]);
1273 else
1274 tcg_out_callr(s, COND_AL, args[0]);
1275 break;
1276 case INDEX_op_jmp:
1277 if (const_args[0])
1278 tcg_out_goto(s, COND_AL, args[0]);
1279 else
1280 tcg_out_bx(s, COND_AL, args[0]);
1281 break;
1282 case INDEX_op_br:
1283 tcg_out_goto_label(s, COND_AL, args[0]);
1284 break;
1285
1286 case INDEX_op_ld8u_i32:
1287 tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1288 break;
1289 case INDEX_op_ld8s_i32:
1290 tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1291 break;
1292 case INDEX_op_ld16u_i32:
1293 tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1294 break;
1295 case INDEX_op_ld16s_i32:
1296 tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1297 break;
1298 case INDEX_op_ld_i32:
1299 tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1300 break;
1301 case INDEX_op_st8_i32:
1302 tcg_out_st8u(s, COND_AL, args[0], args[1], args[2]);
1303 break;
1304 case INDEX_op_st16_i32:
1305 tcg_out_st16u(s, COND_AL, args[0], args[1], args[2]);
1306 break;
1307 case INDEX_op_st_i32:
1308 tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1309 break;
1310
1311 case INDEX_op_mov_i32:
1312 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1313 args[0], 0, args[1], SHIFT_IMM_LSL(0));
1314 break;
1315 case INDEX_op_movi_i32:
1316 tcg_out_movi32(s, COND_AL, args[0], args[1]);
1317 break;
1318 case INDEX_op_add_i32:
1319 c = ARITH_ADD;
1320 goto gen_arith;
1321 case INDEX_op_sub_i32:
1322 c = ARITH_SUB;
1323 goto gen_arith;
1324 case INDEX_op_and_i32:
1325 c = ARITH_AND;
1326 goto gen_arith;
1327 case INDEX_op_or_i32:
1328 c = ARITH_ORR;
1329 goto gen_arith;
1330 case INDEX_op_xor_i32:
1331 c = ARITH_EOR;
1332 /* Fall through. */
1333 gen_arith:
1334 tcg_out_dat_reg(s, COND_AL, c,
1335 args[0], args[1], args[2], SHIFT_IMM_LSL(0));
1336 break;
1337 case INDEX_op_add2_i32:
1338 tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1339 args[0], args[1], args[2], args[3],
1340 args[4], args[5], SHIFT_IMM_LSL(0));
1341 break;
1342 case INDEX_op_sub2_i32:
1343 tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1344 args[0], args[1], args[2], args[3],
1345 args[4], args[5], SHIFT_IMM_LSL(0));
1346 break;
1347 case INDEX_op_neg_i32:
1348 tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1349 break;
1350 case INDEX_op_mul_i32:
1351 tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1352 break;
1353 case INDEX_op_mulu2_i32:
1354 tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1355 break;
1356 case INDEX_op_div2_i32:
1357 tcg_out_div_helper(s, COND_AL, args,
1358 tcg_helper_div_i64, tcg_helper_rem_i64,
1359 SHIFT_IMM_ASR(31));
1360 break;
1361 case INDEX_op_divu2_i32:
1362 tcg_out_div_helper(s, COND_AL, args,
1363 tcg_helper_divu_i64, tcg_helper_remu_i64,
1364 SHIFT_IMM_LSR(31));
1365 break;
1366 /* XXX: Perhaps args[2] & 0x1f is wrong */
1367 case INDEX_op_shl_i32:
1368 c = const_args[2] ?
1369 SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1370 goto gen_shift32;
1371 case INDEX_op_shr_i32:
1372 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1373 SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1374 goto gen_shift32;
1375 case INDEX_op_sar_i32:
1376 c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1377 SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
1378 /* Fall through. */
1379 gen_shift32:
1380 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1381 break;
1382
1383 case INDEX_op_brcond_i32:
1384 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1385 args[0], args[1], SHIFT_IMM_LSL(0));
1386 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1387 break;
1388 case INDEX_op_brcond2_i32:
1389 /* The resulting conditions are:
1390 * TCG_COND_EQ --> a0 == a2 && a1 == a3,
1391 * TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1392 * TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1393 * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1394 * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1395 * TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1396 */
1397 tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1398 args[1], args[3], SHIFT_IMM_LSL(0));
1399 tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1400 args[0], args[2], SHIFT_IMM_LSL(0));
1401 tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1402 break;
1403
1404 case INDEX_op_qemu_ld8u:
1405 tcg_out_qemu_ld(s, COND_AL, args, 0);
1406 break;
1407 case INDEX_op_qemu_ld8s:
1408 tcg_out_qemu_ld(s, COND_AL, args, 0 | 4);
1409 break;
1410 case INDEX_op_qemu_ld16u:
1411 tcg_out_qemu_ld(s, COND_AL, args, 1);
1412 break;
1413 case INDEX_op_qemu_ld16s:
1414 tcg_out_qemu_ld(s, COND_AL, args, 1 | 4);
1415 break;
1416 case INDEX_op_qemu_ld32u:
1417 tcg_out_qemu_ld(s, COND_AL, args, 2);
1418 break;
1419 case INDEX_op_qemu_ld64:
1420 tcg_out_qemu_ld(s, COND_AL, args, 3);
1421 break;
1422
1423 case INDEX_op_qemu_st8:
1424 tcg_out_qemu_st(s, COND_AL, args, 0);
1425 break;
1426 case INDEX_op_qemu_st16:
1427 tcg_out_qemu_st(s, COND_AL, args, 1);
1428 break;
1429 case INDEX_op_qemu_st32:
1430 tcg_out_qemu_st(s, COND_AL, args, 2);
1431 break;
1432 case INDEX_op_qemu_st64:
1433 tcg_out_qemu_st(s, COND_AL, args, 3);
1434 break;
1435
1436 case INDEX_op_ext8s_i32:
1437 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1438 args[0], 0, args[1], SHIFT_IMM_LSL(24));
1439 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1440 args[0], 0, args[0], SHIFT_IMM_ASR(24));
1441 break;
1442 case INDEX_op_ext16s_i32:
1443 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1444 args[0], 0, args[1], SHIFT_IMM_LSL(16));
1445 tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1446 args[0], 0, args[0], SHIFT_IMM_ASR(16));
1447 break;
1448
1449 default:
1450 tcg_abort();
1451 }
1452 }
1453
1454 static const TCGTargetOpDef arm_op_defs[] = {
1455 { INDEX_op_exit_tb, { } },
1456 { INDEX_op_goto_tb, { } },
1457 { INDEX_op_call, { "ri" } },
1458 { INDEX_op_jmp, { "ri" } },
1459 { INDEX_op_br, { } },
1460
1461 { INDEX_op_mov_i32, { "r", "r" } },
1462 { INDEX_op_movi_i32, { "r" } },
1463
1464 { INDEX_op_ld8u_i32, { "r", "r" } },
1465 { INDEX_op_ld8s_i32, { "r", "r" } },
1466 { INDEX_op_ld16u_i32, { "r", "r" } },
1467 { INDEX_op_ld16s_i32, { "r", "r" } },
1468 { INDEX_op_ld_i32, { "r", "r" } },
1469 { INDEX_op_st8_i32, { "r", "r" } },
1470 { INDEX_op_st16_i32, { "r", "r" } },
1471 { INDEX_op_st_i32, { "r", "r" } },
1472
1473 /* TODO: "r", "r", "ri" */
1474 { INDEX_op_add_i32, { "r", "r", "r" } },
1475 { INDEX_op_sub_i32, { "r", "r", "r" } },
1476 { INDEX_op_mul_i32, { "r", "r", "r" } },
1477 { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1478 { INDEX_op_div2_i32, { "r", "r", "r", "1", "2" } },
1479 { INDEX_op_divu2_i32, { "r", "r", "r", "1", "2" } },
1480 { INDEX_op_and_i32, { "r", "r", "r" } },
1481 { INDEX_op_or_i32, { "r", "r", "r" } },
1482 { INDEX_op_xor_i32, { "r", "r", "r" } },
1483 { INDEX_op_neg_i32, { "r", "r" } },
1484
1485 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1486 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1487 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1488
1489 { INDEX_op_brcond_i32, { "r", "r" } },
1490
1491 /* TODO: "r", "r", "r", "r", "ri", "ri" */
1492 { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1493 { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1494 { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1495
1496 { INDEX_op_qemu_ld8u, { "r", "x", "X" } },
1497 { INDEX_op_qemu_ld8s, { "r", "x", "X" } },
1498 { INDEX_op_qemu_ld16u, { "r", "x", "X" } },
1499 { INDEX_op_qemu_ld16s, { "r", "x", "X" } },
1500 { INDEX_op_qemu_ld32u, { "r", "x", "X" } },
1501 { INDEX_op_qemu_ld64, { "d", "r", "x", "X" } },
1502
1503 { INDEX_op_qemu_st8, { "x", "x", "X" } },
1504 { INDEX_op_qemu_st16, { "x", "x", "X" } },
1505 { INDEX_op_qemu_st32, { "x", "x", "X" } },
1506 { INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
1507
1508 { INDEX_op_ext8s_i32, { "r", "r" } },
1509 { INDEX_op_ext16s_i32, { "r", "r" } },
1510
1511 { -1 },
1512 };
1513
1514 void tcg_target_init(TCGContext *s)
1515 {
1516 /* fail safe */
1517 if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1518 tcg_abort();
1519
1520 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
1521 ((2 << TCG_REG_R14) - 1) & ~(1 << TCG_REG_R8));
1522 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1523 ((2 << TCG_REG_R3) - 1) |
1524 (1 << TCG_REG_R12) | (1 << TCG_REG_R14));
1525
1526 tcg_regset_clear(s->reserved_regs);
1527 #ifdef SAVE_LR
1528 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R14);
1529 #endif
1530 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1531 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
1532
1533 tcg_add_target_add_op_defs(arm_op_defs);
1534 }
1535
1536 static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1537 int arg1, tcg_target_long arg2)
1538 {
1539 tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1540 }
1541
1542 static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1543 int arg1, tcg_target_long arg2)
1544 {
1545 tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1546 }
1547
1548 void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
1549 {
1550 if (val > 0)
1551 if (val < 0x100)
1552 tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1553 else
1554 tcg_abort();
1555 else if (val < 0) {
1556 if (val > -0x100)
1557 tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1558 else
1559 tcg_abort();
1560 }
1561 }
1562
1563 static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
1564 {
1565 tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1566 }
1567
1568 static inline void tcg_out_movi(TCGContext *s, TCGType type,
1569 int ret, tcg_target_long arg)
1570 {
1571 tcg_out_movi32(s, COND_AL, ret, arg);
1572 }
1573
1574 void tcg_target_qemu_prologue(TCGContext *s)
1575 {
1576 /* stmdb sp!, { r9 - r11, lr } */
1577 tcg_out32(s, (COND_AL << 28) | 0x092d4e00);
1578
1579 tcg_out_bx(s, COND_AL, TCG_REG_R0);
1580 tb_ret_addr = s->code_ptr;
1581
1582 /* ldmia sp!, { r9 - r11, pc } */
1583 tcg_out32(s, (COND_AL << 28) | 0x08bd8e00);
1584 }
Samsung s3c2440 and arm920t support for the mini2440 dev board