hw/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL
   8  */
   9
  10 #include "vl.h"
  11 #include "arm_pic.h"
  12
  13 #define KERNEL_ARGS_ADDR 0x100
  14 #define KERNEL_LOAD_ADDR 0x00010000
  15 #define INITRD_LOAD_ADDR 0x00800000
  16
  17 void DMA_run (void)
  18 {
  19 }
  20
  21 typedef struct {
  22     uint32_t flash_offset;
  23     uint32_t cm_osc;
  24     uint32_t cm_ctrl;
  25     uint32_t cm_lock;
  26     uint32_t cm_auxosc;
  27     uint32_t cm_sdram;
  28     uint32_t cm_init;
  29     uint32_t cm_flags;
  30     uint32_t cm_nvflags;
  31     uint32_t int_level;
  32     uint32_t irq_enabled;
  33     uint32_t fiq_enabled;
  34 } integratorcm_state;
  35
  36 static uint8_t integrator_spd[128] = {
  37    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  38    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  39 };
  40
  41 static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
  42 {
  43     integratorcm_state *s = (integratorcm_state *)opaque;
  44     offset -= 0x10000000;
  45     if (offset >= 0x100 && offset < 0x200) {
  46         /* CM_SPD */
  47         if (offset >= 0x180)
  48             return 0;
  49         return integrator_spd[offset >> 2];
  50     }
  51     switch (offset >> 2) {
  52     case 0: /* CM_ID */
  53         return 0x411a3001;
  54     case 1: /* CM_PROC */
  55         return 0;
  56     case 2: /* CM_OSC */
  57         return s->cm_osc;
  58     case 3: /* CM_CTRL */
  59         return s->cm_ctrl;
  60     case 4: /* CM_STAT */
  61         return 0x00100000;
  62     case 5: /* CM_LOCK */
  63         if (s->cm_lock == 0xa05f) {
  64             return 0x1a05f;
  65         } else {
  66             return s->cm_lock;
  67         }
  68     case 6: /* CM_LMBUSCNT */
  69         /* ??? High frequency timer.  */
  70         cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
  71     case 7: /* CM_AUXOSC */
  72         return s->cm_auxosc;
  73     case 8: /* CM_SDRAM */
  74         return s->cm_sdram;
  75     case 9: /* CM_INIT */
  76         return s->cm_init;
  77     case 10: /* CM_REFCT */
  78         /* ??? High frequency timer.  */
  79         cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
  80     case 12: /* CM_FLAGS */
  81         return s->cm_flags;
  82     case 14: /* CM_NVFLAGS */
  83         return s->cm_nvflags;
  84     case 16: /* CM_IRQ_STAT */
  85         return s->int_level & s->irq_enabled;
  86     case 17: /* CM_IRQ_RSTAT */
  87         return s->int_level;
  88     case 18: /* CM_IRQ_ENSET */
  89         return s->irq_enabled;
  90     case 20: /* CM_SOFT_INTSET */
  91         return s->int_level & 1;
  92     case 24: /* CM_FIQ_STAT */
  93         return s->int_level & s->fiq_enabled;
  94     case 25: /* CM_FIQ_RSTAT */
  95         return s->int_level;
  96     case 26: /* CM_FIQ_ENSET */
  97         return s->fiq_enabled;
  98     case 32: /* CM_VOLTAGE_CTL0 */
  99     case 33: /* CM_VOLTAGE_CTL1 */
 100     case 34: /* CM_VOLTAGE_CTL2 */
 101     case 35: /* CM_VOLTAGE_CTL3 */
 102         /* ??? Voltage control unimplemented.  */
 103         return 0;
 104     default:
 105         cpu_abort (cpu_single_env,
 106             "integratorcm_read: Unimplemented offset 0x%x\n", offset);
 107         return 0;
 108     }
 109 }
 110
 111 static void integratorcm_do_remap(integratorcm_state *s, int flash)
 112 {
 113     if (flash) {
 114         cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
 115     } else {
 116         cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
 117     }
 118     //??? tlb_flush (cpu_single_env, 1);
 119 }
 120
 121 static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
 122 {
 123     if (value & 8) {
 124         cpu_abort(cpu_single_env, "Board reset\n");
 125     }
 126     if ((s->cm_init ^ value) & 4) {
 127         integratorcm_do_remap(s, (value & 4) == 0);
 128     }
 129     if ((s->cm_init ^ value) & 1) {
 130         printf("Green LED %s\n", (value & 1) ? "on" : "off");
 131     }
 132     s->cm_init = (s->cm_init & ~ 5) | (value ^ 5);
 133 }
 134
 135 static void integratorcm_update(integratorcm_state *s)
 136 {
 137     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 138        are active.  */
 139     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 140         cpu_abort(cpu_single_env, "Core module interrupt\n");
 141 }
 142
 143 static void integratorcm_write(void *opaque, target_phys_addr_t offset,
 144                                uint32_t value)
 145 {
 146     integratorcm_state *s = (integratorcm_state *)opaque;
 147     offset -= 0x10000000;
 148     switch (offset >> 2) {
 149     case 2: /* CM_OSC */
 150         if (s->cm_lock == 0xa05f)
 151             s->cm_osc = value;
 152         break;
 153     case 3: /* CM_CTRL */
 154         integratorcm_set_ctrl(s, value);
 155         break;
 156     case 5: /* CM_LOCK */
 157         s->cm_lock = value & 0xffff;
 158         break;
 159     case 7: /* CM_AUXOSC */
 160         if (s->cm_lock == 0xa05f)
 161             s->cm_auxosc = value;
 162         break;
 163     case 8: /* CM_SDRAM */
 164         s->cm_sdram = value;
 165         break;
 166     case 9: /* CM_INIT */
 167         /* ??? This can change the memory bus frequency.  */
 168         s->cm_init = value;
 169         break;
 170     case 12: /* CM_FLAGSS */
 171         s->cm_flags |= value;
 172         break;
 173     case 13: /* CM_FLAGSC */
 174         s->cm_flags &= ~value;
 175         break;
 176     case 14: /* CM_NVFLAGSS */
 177         s->cm_nvflags |= value;
 178         break;
 179     case 15: /* CM_NVFLAGSS */
 180         s->cm_nvflags &= ~value;
 181         break;
 182     case 18: /* CM_IRQ_ENSET */
 183         s->irq_enabled |= value;
 184         integratorcm_update(s);
 185         break;
 186     case 19: /* CM_IRQ_ENCLR */
 187         s->irq_enabled &= ~value;
 188         integratorcm_update(s);
 189         break;
 190     case 20: /* CM_SOFT_INTSET */
 191         s->int_level |= (value & 1);
 192         integratorcm_update(s);
 193         break;
 194     case 21: /* CM_SOFT_INTCLR */
 195         s->int_level &= ~(value & 1);
 196         integratorcm_update(s);
 197         break;
 198     case 26: /* CM_FIQ_ENSET */
 199         s->fiq_enabled |= value;
 200         integratorcm_update(s);
 201         break;
 202     case 27: /* CM_FIQ_ENCLR */
 203         s->fiq_enabled &= ~value;
 204         integratorcm_update(s);
 205         break;
 206     case 32: /* CM_VOLTAGE_CTL0 */
 207     case 33: /* CM_VOLTAGE_CTL1 */
 208     case 34: /* CM_VOLTAGE_CTL2 */
 209     case 35: /* CM_VOLTAGE_CTL3 */
 210         /* ??? Voltage control unimplemented.  */
 211         break;
 212     default:
 213         cpu_abort (cpu_single_env,
 214             "integratorcm_write: Unimplemented offset 0x%x\n", offset);
 215         break;
 216     }
 217 }
 218
 219 /* Integrator/CM control registers.  */
 220
 221 static CPUReadMemoryFunc *integratorcm_readfn[] = {
 222    integratorcm_read,
 223    integratorcm_read,
 224    integratorcm_read
 225 };
 226
 227 static CPUWriteMemoryFunc *integratorcm_writefn[] = {
 228    integratorcm_write,
 229    integratorcm_write,
 230    integratorcm_write
 231 };
 232
 233 static void integratorcm_init(int memsz, uint32_t flash_offset)
 234 {
 235     int iomemtype;
 236     integratorcm_state *s;
 237
 238     s = (integratorcm_state *)qemu_mallocz(sizeof(integratorcm_state));
 239     s->cm_osc = 0x01000048;
 240     /* ??? What should the high bits of this value be?  */
 241     s->cm_auxosc = 0x0007feff;
 242     s->cm_sdram = 0x00011122;
 243     if (memsz >= 256) {
 244         integrator_spd[31] = 64;
 245         s->cm_sdram |= 0x10;
 246     } else if (memsz >= 128) {
 247         integrator_spd[31] = 32;
 248         s->cm_sdram |= 0x0c;
 249     } else if (memsz >= 64) {
 250         integrator_spd[31] = 16;
 251         s->cm_sdram |= 0x08;
 252     } else if (memsz >= 32) {
 253         integrator_spd[31] = 4;
 254         s->cm_sdram |= 0x04;
 255     } else {
 256         integrator_spd[31] = 2;
 257     }
 258     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 259     s->cm_init = 0x00000112;
 260     s->flash_offset = flash_offset;
 261
 262     iomemtype = cpu_register_io_memory(0, integratorcm_readfn,
 263                                        integratorcm_writefn, s);
 264     cpu_register_physical_memory(0x10000000, 0x007fffff, iomemtype);
 265     integratorcm_do_remap(s, 1);
 266     /* ??? Save/restore.  */
 267 }
 268
 269 /* Integrator/CP hardware emulation.  */
 270 /* Primary interrupt controller.  */
 271
 272 typedef struct icp_pic_state
 273 {
 274   arm_pic_handler handler;
 275   uint32_t base;
 276   uint32_t level;
 277   uint32_t irq_enabled;
 278   uint32_t fiq_enabled;
 279   void *parent;
 280   int parent_irq;
 281   int parent_fiq;
 282 } icp_pic_state;
 283
 284 static void icp_pic_update(icp_pic_state *s)
 285 {
 286     uint32_t flags;
 287
 288     if (s->parent_irq != -1) {
 289         flags = (s->level & s->irq_enabled);
 290         pic_set_irq_new(s->parent, s->parent_irq, flags != 0);
 291     }
 292     if (s->parent_fiq != -1) {
 293         flags = (s->level & s->fiq_enabled);
 294         pic_set_irq_new(s->parent, s->parent_fiq, flags != 0);
 295     }
 296 }
 297
 298 static void icp_pic_set_irq(void *opaque, int irq, int level)
 299 {
 300     icp_pic_state *s = (icp_pic_state *)opaque;
 301     if (level)
 302         s->level |= 1 << irq;
 303     else
 304         s->level &= ~(1 << irq);
 305     icp_pic_update(s);
 306 }
 307
 308 static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
 309 {
 310     icp_pic_state *s = (icp_pic_state *)opaque;
 311
 312     offset -= s->base;
 313     switch (offset >> 2) {
 314     case 0: /* IRQ_STATUS */
 315         return s->level & s->irq_enabled;
 316     case 1: /* IRQ_RAWSTAT */
 317         return s->level;
 318     case 2: /* IRQ_ENABLESET */
 319         return s->irq_enabled;
 320     case 4: /* INT_SOFTSET */
 321         return s->level & 1;
 322     case 8: /* FRQ_STATUS */
 323         return s->level & s->fiq_enabled;
 324     case 9: /* FRQ_RAWSTAT */
 325         return s->level;
 326     case 10: /* FRQ_ENABLESET */
 327         return s->fiq_enabled;
 328     case 3: /* IRQ_ENABLECLR */
 329     case 5: /* INT_SOFTCLR */
 330     case 11: /* FRQ_ENABLECLR */
 331     default:
 332         printf ("icp_pic_read: Bad register offset 0x%x\n", offset);
 333         return 0;
 334     }
 335 }
 336
 337 static void icp_pic_write(void *opaque, target_phys_addr_t offset,
 338                           uint32_t value)
 339 {
 340     icp_pic_state *s = (icp_pic_state *)opaque;
 341     offset -= s->base;
 342
 343     switch (offset >> 2) {
 344     case 2: /* IRQ_ENABLESET */
 345         s->irq_enabled |= value;
 346         break;
 347     case 3: /* IRQ_ENABLECLR */
 348         s->irq_enabled &= ~value;
 349         break;
 350     case 4: /* INT_SOFTSET */
 351         if (value & 1)
 352             pic_set_irq_new(s, 0, 1);
 353         break;
 354     case 5: /* INT_SOFTCLR */
 355         if (value & 1)
 356             pic_set_irq_new(s, 0, 0);
 357         break;
 358     case 10: /* FRQ_ENABLESET */
 359         s->fiq_enabled |= value;
 360         break;
 361     case 11: /* FRQ_ENABLECLR */
 362         s->fiq_enabled &= ~value;
 363         break;
 364     case 0: /* IRQ_STATUS */
 365     case 1: /* IRQ_RAWSTAT */
 366     case 8: /* FRQ_STATUS */
 367     case 9: /* FRQ_RAWSTAT */
 368     default:
 369         printf ("icp_pic_write: Bad register offset 0x%x\n", offset);
 370         return;
 371     }
 372     icp_pic_update(s);
 373 }
 374
 375 static CPUReadMemoryFunc *icp_pic_readfn[] = {
 376    icp_pic_read,
 377    icp_pic_read,
 378    icp_pic_read
 379 };
 380
 381 static CPUWriteMemoryFunc *icp_pic_writefn[] = {
 382    icp_pic_write,
 383    icp_pic_write,
 384    icp_pic_write
 385 };
 386
 387 static icp_pic_state *icp_pic_init(uint32_t base, void *parent,
 388                                    int parent_irq, int parent_fiq)
 389 {
 390     icp_pic_state *s;
 391     int iomemtype;
 392
 393     s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state));
 394     if (!s)
 395         return NULL;
 396     s->handler = icp_pic_set_irq;
 397     s->base = base;
 398     s->parent = parent;
 399     s->parent_irq = parent_irq;
 400     s->parent_fiq = parent_fiq;
 401     iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
 402                                        icp_pic_writefn, s);
 403     cpu_register_physical_memory(base, 0x007fffff, iomemtype);
 404     /* ??? Save/restore.  */
 405     return s;
 406 }
 407
 408 /* CP control registers.  */
 409 typedef struct {
 410     uint32_t base;
 411 } icp_control_state;
 412
 413 static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
 414 {
 415     icp_control_state *s = (icp_control_state *)opaque;
 416     offset -= s->base;
 417     switch (offset >> 2) {
 418     case 0: /* CP_IDFIELD */
 419         return 0x41034003;
 420     case 1: /* CP_FLASHPROG */
 421         return 0;
 422     case 2: /* CP_INTREG */
 423         return 0;
 424     case 3: /* CP_DECODE */
 425         return 0x11;
 426     default:
 427         cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", offset);
 428         return 0;
 429     }
 430 }
 431
 432 static void icp_control_write(void *opaque, target_phys_addr_t offset,
 433                           uint32_t value)
 434 {
 435     icp_control_state *s = (icp_control_state *)opaque;
 436     offset -= s->base;
 437     switch (offset >> 2) {
 438     case 1: /* CP_FLASHPROG */
 439     case 2: /* CP_INTREG */
 440     case 3: /* CP_DECODE */
 441         /* Nothing interesting implemented yet.  */
 442         break;
 443     default:
 444         cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", offset);
 445     }
 446 }
 447 static CPUReadMemoryFunc *icp_control_readfn[] = {
 448    icp_control_read,
 449    icp_control_read,
 450    icp_control_read
 451 };
 452
 453 static CPUWriteMemoryFunc *icp_control_writefn[] = {
 454    icp_control_write,
 455    icp_control_write,
 456    icp_control_write
 457 };
 458
 459 static void icp_control_init(uint32_t base)
 460 {
 461     int iomemtype;
 462     icp_control_state *s;
 463
 464     s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state));
 465     iomemtype = cpu_register_io_memory(0, icp_control_readfn,
 466                                        icp_control_writefn, s);
 467     cpu_register_physical_memory(base, 0x007fffff, iomemtype);
 468     s->base = base;
 469     /* ??? Save/restore.  */
 470 }
 471
 472
 473 /* The worlds second smallest bootloader.  Set r0-r2, then jump to kernel.  */
 474 static uint32_t bootloader[] = {
 475   0xe3a00000, /* mov     r0, #0 */
 476   0xe3a01013, /* mov     r1, #0x13 */
 477   0xe3811c01, /* orr     r1, r1, #0x100 */
 478   0xe59f2000, /* ldr     r2, [pc, #0] */
 479   0xe59ff000, /* ldr     pc, [pc, #0] */
 480   0, /* Address of kernel args.  Set by integratorcp_init.  */
 481   0  /* Kernel entry point.  Set by integratorcp_init.  */
 482 };
 483
 484 static void set_kernel_args(uint32_t ram_size, int initrd_size,
 485                             const char *kernel_cmdline)
 486 {
 487     uint32_t *p;
 488
 489     p = (uint32_t *)(phys_ram_base + KERNEL_ARGS_ADDR);
 490     /* ATAG_CORE */
 491     stl_raw(p++, 5);
 492     stl_raw(p++, 0x54410001);
 493     stl_raw(p++, 1);
 494     stl_raw(p++, 0x1000);
 495     stl_raw(p++, 0);
 496     /* ATAG_MEM */
 497     stl_raw(p++, 4);
 498     stl_raw(p++, 0x54410002);
 499     stl_raw(p++, ram_size);
 500     stl_raw(p++, 0);
 501     if (initrd_size) {
 502         /* ATAG_INITRD2 */
 503         stl_raw(p++, 4);
 504         stl_raw(p++, 0x54420005);
 505         stl_raw(p++, INITRD_LOAD_ADDR);
 506         stl_raw(p++, initrd_size);
 507     }
 508     if (kernel_cmdline && *kernel_cmdline) {
 509         /* ATAG_CMDLINE */
 510         int cmdline_size;
 511
 512         cmdline_size = strlen(kernel_cmdline);
 513         memcpy (p + 2, kernel_cmdline, cmdline_size + 1);
 514         cmdline_size = (cmdline_size >> 2) + 1;
 515         stl_raw(p++, cmdline_size + 2);
 516         stl_raw(p++, 0x54410009);
 517         p += cmdline_size;
 518     }
 519     /* ATAG_END */
 520     stl_raw(p++, 0);
 521     stl_raw(p++, 0);
 522 }
 523
 524 /* Board init.  */
 525
 526 static void integratorcp_init(int ram_size, int vga_ram_size, int boot_device,
 527                      DisplayState *ds, const char **fd_filename, int snapshot,
 528                      const char *kernel_filename, const char *kernel_cmdline,
 529                      const char *initrd_filename, uint32_t cpuid)
 530 {
 531     CPUState *env;
 532     uint32_t bios_offset;
 533     icp_pic_state *pic;
 534     void *cpu_pic;
 535     int kernel_size;
 536     int initrd_size;
 537     int n;
 538
 539     env = cpu_init();
 540     cpu_arm_set_model(env, cpuid);
 541     bios_offset = ram_size + vga_ram_size;
 542     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 543     /* ??? RAM shoud repeat to fill physical memory space.  */
 544     /* SDRAM at address zero*/
 545     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 546     /* And again at address 0x80000000 */
 547     cpu_register_physical_memory(0x80000000, ram_size, IO_MEM_RAM);
 548
 549     integratorcm_init(ram_size >> 20, bios_offset);
 550     cpu_pic = arm_pic_init_cpu(env);
 551     pic = icp_pic_init(0x14000000, cpu_pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
 552     icp_pic_init(0xca000000, pic, 26, -1);
 553     icp_pit_init(0x13000000, pic, 5);
 554     pl011_init(0x16000000, pic, 1, serial_hds[0]);
 555     pl011_init(0x17000000, pic, 2, serial_hds[1]);
 556     icp_control_init(0xcb000000);
 557     pl050_init(0x18000000, pic, 3, 0);
 558     pl050_init(0x19000000, pic, 4, 1);
 559     if (nd_table[0].vlan) {
 560         if (nd_table[0].model == NULL
 561             || strcmp(nd_table[0].model, "smc91c111") == 0) {
 562             smc91c111_init(&nd_table[0], 0xc8000000, pic, 27);
 563         } else {
 564             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 565             exit (1);
 566         }
 567     }
 568     pl110_init(ds, 0xc0000000, pic, 22, 0);
 569
 570     /* Load the kernel.  */
 571     if (!kernel_filename) {
 572         fprintf(stderr, "Kernel image must be specified\n");
 573         exit(1);
 574     }
 575     kernel_size = load_image(kernel_filename,
 576                              phys_ram_base + KERNEL_LOAD_ADDR);
 577     if (kernel_size < 0) {
 578         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 579         exit(1);
 580     }
 581     if (initrd_filename) {
 582         initrd_size = load_image(initrd_filename,
 583                                  phys_ram_base + INITRD_LOAD_ADDR);
 584         if (initrd_size < 0) {
 585             fprintf(stderr, "qemu: could not load initrd '%s'\n",
 586                     initrd_filename);
 587             exit(1);
 588         }
 589     } else {
 590         initrd_size = 0;
 591     }
 592     bootloader[5] = KERNEL_ARGS_ADDR;
 593     bootloader[6] = KERNEL_LOAD_ADDR;
 594     for (n = 0; n < sizeof(bootloader) / 4; n++)
 595         stl_raw(phys_ram_base + (n * 4), bootloader[n]);
 596     set_kernel_args(ram_size, initrd_size, kernel_cmdline);
 597 }
 598
 599 static void integratorcp926_init(int ram_size, int vga_ram_size,
 600     int boot_device, DisplayState *ds, const char **fd_filename, int snapshot,
 601     const char *kernel_filename, const char *kernel_cmdline,
 602     const char *initrd_filename)
 603 {
 604     integratorcp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
 605                       snapshot, kernel_filename, kernel_cmdline,
 606                       initrd_filename, ARM_CPUID_ARM926);
 607 }
 608
 609 static void integratorcp1026_init(int ram_size, int vga_ram_size,
 610     int boot_device, DisplayState *ds, const char **fd_filename, int snapshot,
 611     const char *kernel_filename, const char *kernel_cmdline,
 612     const char *initrd_filename)
 613 {
 614     integratorcp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename,
 615                       snapshot, kernel_filename, kernel_cmdline,
 616                       initrd_filename, ARM_CPUID_ARM1026);
 617 }
 618
 619 QEMUMachine integratorcp926_machine = {
 620     "integratorcp926",
 621     "ARM Integrator/CP (ARM926EJ-S)",
 622     integratorcp926_init,
 623 };
 624
 625 QEMUMachine integratorcp1026_machine = {
 626     "integratorcp1026",
 627     "ARM Integrator/CP (ARM1026EJ-S)",
 628     integratorcp1026_init,
 629 };