target-mips/exec.h

   1 #if !defined(__QEMU_MIPS_EXEC_H__)
   2 #define __QEMU_MIPS_EXEC_H__
   3
   4 //#define DEBUG_OP
   5
   6 #include "config.h"
   7 #include "mips-defs.h"
   8 #include "dyngen-exec.h"
   9 #include "cpu-defs.h"
  10
  11 register struct CPUMIPSState *env asm(AREG0);
  12
  13 #if TARGET_LONG_BITS > HOST_LONG_BITS
  14 #define T0 (env->t0)
  15 #define T1 (env->t1)
  16 #define T2 (env->t2)
  17 #else
  18 register target_ulong T0 asm(AREG1);
  19 register target_ulong T1 asm(AREG2);
  20 register target_ulong T2 asm(AREG3);
  21 #endif
  22
  23 #if defined (USE_HOST_FLOAT_REGS)
  24 #error "implement me."
  25 #else
  26 #define FDT0 (env->fpu->ft0.fd)
  27 #define FDT1 (env->fpu->ft1.fd)
  28 #define FDT2 (env->fpu->ft2.fd)
  29 #define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
  30 #define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
  31 #define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
  32 #define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
  33 #define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
  34 #define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
  35 #define DT0 (env->fpu->ft0.d)
  36 #define DT1 (env->fpu->ft1.d)
  37 #define DT2 (env->fpu->ft2.d)
  38 #define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
  39 #define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
  40 #define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
  41 #define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
  42 #define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
  43 #define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
  44 #endif
  45
  46 #include "cpu.h"
  47 #include "exec-all.h"
  48
  49 #if !defined(CONFIG_USER_ONLY)
  50 #include "softmmu_exec.h"
  51 #endif /* !defined(CONFIG_USER_ONLY) */
  52
  53 #if defined(TARGET_MIPS64)
  54 #if TARGET_LONG_BITS > HOST_LONG_BITS
  55 void do_dsll (void);
  56 void do_dsll32 (void);
  57 void do_dsra (void);
  58 void do_dsra32 (void);
  59 void do_dsrl (void);
  60 void do_dsrl32 (void);
  61 void do_drotr (void);
  62 void do_drotr32 (void);
  63 void do_dsllv (void);
  64 void do_dsrav (void);
  65 void do_dsrlv (void);
  66 void do_drotrv (void);
  67 void do_dclo (void);
  68 void do_dclz (void);
  69 #endif
  70 #endif
  71
  72 #if HOST_LONG_BITS < 64
  73 void do_div (void);
  74 #endif
  75 #if TARGET_LONG_BITS > HOST_LONG_BITS
  76 void do_mult (void);
  77 void do_multu (void);
  78 void do_madd (void);
  79 void do_maddu (void);
  80 void do_msub (void);
  81 void do_msubu (void);
  82 #endif
  83 #if defined(TARGET_MIPS64)
  84 void do_ddiv (void);
  85 #if TARGET_LONG_BITS > HOST_LONG_BITS
  86 void do_ddivu (void);
  87 #endif
  88 #endif
  89 void do_mfc0_random(void);
  90 void do_mfc0_count(void);
  91 void do_mtc0_entryhi(uint32_t in);
  92 void do_mtc0_status_debug(uint32_t old, uint32_t val);
  93 void do_mtc0_status_irqraise_debug(void);
  94 void dump_fpu(CPUState *env);
  95 void fpu_dump_state(CPUState *env, FILE *f,
  96                     int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
  97                     int flags);
  98 void dump_sc (void);
  99 void do_pmon (int function);
 100
 101 void dump_sc (void);
 102
 103 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 104                                int mmu_idx, int is_softmmu);
 105 void do_interrupt (CPUState *env);
 106 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
 107
 108 void cpu_loop_exit(void);
 109 void do_raise_exception_err (uint32_t exception, int error_code);
 110 void do_raise_exception (uint32_t exception);
 111 void do_raise_exception_direct_err (uint32_t exception, int error_code);
 112 void do_raise_exception_direct (uint32_t exception);
 113
 114 void cpu_dump_state(CPUState *env, FILE *f,
 115                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
 116                     int flags);
 117 void cpu_mips_irqctrl_init (void);
 118 uint32_t cpu_mips_get_random (CPUState *env);
 119 uint32_t cpu_mips_get_count (CPUState *env);
 120 void cpu_mips_store_count (CPUState *env, uint32_t value);
 121 void cpu_mips_store_compare (CPUState *env, uint32_t value);
 122 void cpu_mips_start_count(CPUState *env);
 123 void cpu_mips_stop_count(CPUState *env);
 124 void cpu_mips_update_irq (CPUState *env);
 125 void cpu_mips_clock_init (CPUState *env);
 126 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
 127
 128 void do_cfc1 (int reg);
 129 void do_ctc1 (int reg);
 130
 131 #define FOP_PROTO(op)              \
 132 void do_float_ ## op ## _s(void);  \
 133 void do_float_ ## op ## _d(void);
 134 FOP_PROTO(roundl)
 135 FOP_PROTO(roundw)
 136 FOP_PROTO(truncl)
 137 FOP_PROTO(truncw)
 138 FOP_PROTO(ceill)
 139 FOP_PROTO(ceilw)
 140 FOP_PROTO(floorl)
 141 FOP_PROTO(floorw)
 142 FOP_PROTO(rsqrt)
 143 FOP_PROTO(recip)
 144 #undef FOP_PROTO
 145
 146 #define FOP_PROTO(op)              \
 147 void do_float_ ## op ## _s(void);  \
 148 void do_float_ ## op ## _d(void);  \
 149 void do_float_ ## op ## _ps(void);
 150 FOP_PROTO(add)
 151 FOP_PROTO(sub)
 152 FOP_PROTO(mul)
 153 FOP_PROTO(div)
 154 FOP_PROTO(recip1)
 155 FOP_PROTO(recip2)
 156 FOP_PROTO(rsqrt1)
 157 FOP_PROTO(rsqrt2)
 158 #undef FOP_PROTO
 159
 160 void do_float_cvtd_s(void);
 161 void do_float_cvtd_w(void);
 162 void do_float_cvtd_l(void);
 163 void do_float_cvtl_d(void);
 164 void do_float_cvtl_s(void);
 165 void do_float_cvtps_pw(void);
 166 void do_float_cvtpw_ps(void);
 167 void do_float_cvts_d(void);
 168 void do_float_cvts_w(void);
 169 void do_float_cvts_l(void);
 170 void do_float_cvts_pl(void);
 171 void do_float_cvts_pu(void);
 172 void do_float_cvtw_s(void);
 173 void do_float_cvtw_d(void);
 174
 175 void do_float_addr_ps(void);
 176 void do_float_mulr_ps(void);
 177
 178 #define FOP_PROTO(op)                      \
 179 void do_cmp_d_ ## op(long cc);             \
 180 void do_cmpabs_d_ ## op(long cc);          \
 181 void do_cmp_s_ ## op(long cc);             \
 182 void do_cmpabs_s_ ## op(long cc);          \
 183 void do_cmp_ps_ ## op(long cc);            \
 184 void do_cmpabs_ps_ ## op(long cc);
 185
 186 FOP_PROTO(f)
 187 FOP_PROTO(un)
 188 FOP_PROTO(eq)
 189 FOP_PROTO(ueq)
 190 FOP_PROTO(olt)
 191 FOP_PROTO(ult)
 192 FOP_PROTO(ole)
 193 FOP_PROTO(ule)
 194 FOP_PROTO(sf)
 195 FOP_PROTO(ngle)
 196 FOP_PROTO(seq)
 197 FOP_PROTO(ngl)
 198 FOP_PROTO(lt)
 199 FOP_PROTO(nge)
 200 FOP_PROTO(le)
 201 FOP_PROTO(ngt)
 202 #undef FOP_PROTO
 203
 204 static always_inline void env_to_regs(void)
 205 {
 206 }
 207
 208 static always_inline void regs_to_env(void)
 209 {
 210 }
 211
 212 static always_inline int cpu_halted(CPUState *env)
 213 {
 214     if (!env->halted)
 215         return 0;
 216     if (env->interrupt_request &
 217         (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
 218         env->halted = 0;
 219         return 0;
 220     }
 221     return EXCP_HALTED;
 222 }
 223
 224 static always_inline void compute_hflags(CPUState *env)
 225 {
 226     env->hflags &= ~(MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | MIPS_HFLAG_F64 |
 227                      MIPS_HFLAG_FPU | MIPS_HFLAG_KSU);
 228     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 229         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 230         !(env->hflags & MIPS_HFLAG_DM)) {
 231         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 232     }
 233 #if defined(TARGET_MIPS64)
 234     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 235         (env->CP0_Status & (1 << CP0St_PX)) ||
 236         (env->CP0_Status & (1 << CP0St_UX)))
 237         env->hflags |= MIPS_HFLAG_64;
 238 #endif
 239     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
 240         !(env->hflags & MIPS_HFLAG_KSU))
 241         env->hflags |= MIPS_HFLAG_CP0;
 242     if (env->CP0_Status & (1 << CP0St_CU1))
 243         env->hflags |= MIPS_HFLAG_FPU;
 244     if (env->CP0_Status & (1 << CP0St_FR))
 245         env->hflags |= MIPS_HFLAG_F64;
 246 }
 247
 248 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */