2 * QEMU Sparc SLAVIO aux io port emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 * This is the auxio port, chip control and system control part of
33 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
34 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
36 * This also includes the PMC CPU idle controller.
40 #define MISC_DPRINTF(fmt, args...) \
41 do { printf("MISC: " fmt , ##args); } while (0)
43 #define MISC_DPRINTF(fmt, args...)
46 typedef struct MiscState
{
58 #define SYSCTRL_SIZE 4
60 #define LED_SIZE (LED_MAXADDR + 1)
62 #define MISC_MASK 0x0fff0000
63 #define MISC_LEDS 0x01600000
64 #define MISC_CFG 0x01800000
65 #define MISC_DIAG 0x01a00000
66 #define MISC_MDM 0x01b00000
67 #define MISC_SYS 0x01f00000
71 #define AUX2_PWROFF 0x01
72 #define AUX2_PWRINTCLR 0x02
73 #define AUX2_PWRFAIL 0x20
75 #define CFG_PWRINTEN 0x08
77 #define SYS_RESET 0x01
78 #define SYS_RESETSTAT 0x02
80 static void slavio_misc_update_irq(void *opaque
)
82 MiscState
*s
= opaque
;
84 if ((s
->aux2
& AUX2_PWRFAIL
) && (s
->config
& CFG_PWRINTEN
)) {
85 MISC_DPRINTF("Raise IRQ\n");
86 qemu_irq_raise(s
->irq
);
88 MISC_DPRINTF("Lower IRQ\n");
89 qemu_irq_lower(s
->irq
);
93 static void slavio_misc_reset(void *opaque
)
95 MiscState
*s
= opaque
;
97 // Diagnostic and system control registers not cleared in reset
98 s
->config
= s
->aux1
= s
->aux2
= s
->mctrl
= 0;
101 void slavio_set_power_fail(void *opaque
, int power_failing
)
103 MiscState
*s
= opaque
;
105 MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing
, s
->config
);
106 if (power_failing
&& (s
->config
& CFG_PWRINTEN
)) {
107 s
->aux2
|= AUX2_PWRFAIL
;
109 s
->aux2
&= ~AUX2_PWRFAIL
;
111 slavio_misc_update_irq(s
);
114 static void slavio_cfg_mem_writeb(void *opaque
, target_phys_addr_t addr
,
117 MiscState
*s
= opaque
;
119 MISC_DPRINTF("Write config %2.2x\n", val
& 0xff);
120 s
->config
= val
& 0xff;
121 slavio_misc_update_irq(s
);
124 static uint32_t slavio_cfg_mem_readb(void *opaque
, target_phys_addr_t addr
)
126 MiscState
*s
= opaque
;
130 MISC_DPRINTF("Read config %2.2x\n", ret
);
134 static CPUReadMemoryFunc
*slavio_cfg_mem_read
[3] = {
135 slavio_cfg_mem_readb
,
140 static CPUWriteMemoryFunc
*slavio_cfg_mem_write
[3] = {
141 slavio_cfg_mem_writeb
,
146 static void slavio_diag_mem_writeb(void *opaque
, target_phys_addr_t addr
,
149 MiscState
*s
= opaque
;
151 MISC_DPRINTF("Write diag %2.2x\n", val
& 0xff);
152 s
->diag
= val
& 0xff;
155 static uint32_t slavio_diag_mem_readb(void *opaque
, target_phys_addr_t addr
)
157 MiscState
*s
= opaque
;
161 MISC_DPRINTF("Read diag %2.2x\n", ret
);
165 static CPUReadMemoryFunc
*slavio_diag_mem_read
[3] = {
166 slavio_diag_mem_readb
,
171 static CPUWriteMemoryFunc
*slavio_diag_mem_write
[3] = {
172 slavio_diag_mem_writeb
,
177 static void slavio_mdm_mem_writeb(void *opaque
, target_phys_addr_t addr
,
180 MiscState
*s
= opaque
;
182 MISC_DPRINTF("Write modem control %2.2x\n", val
& 0xff);
183 s
->mctrl
= val
& 0xff;
186 static uint32_t slavio_mdm_mem_readb(void *opaque
, target_phys_addr_t addr
)
188 MiscState
*s
= opaque
;
192 MISC_DPRINTF("Read modem control %2.2x\n", ret
);
196 static CPUReadMemoryFunc
*slavio_mdm_mem_read
[3] = {
197 slavio_mdm_mem_readb
,
202 static CPUWriteMemoryFunc
*slavio_mdm_mem_write
[3] = {
203 slavio_mdm_mem_writeb
,
208 static void slavio_aux1_mem_writeb(void *opaque
, target_phys_addr_t addr
,
211 MiscState
*s
= opaque
;
213 MISC_DPRINTF("Write aux1 %2.2x\n", val
& 0xff);
215 // Send a pulse to floppy terminal count line
217 qemu_irq_raise(s
->fdc_tc
);
218 qemu_irq_lower(s
->fdc_tc
);
222 s
->aux1
= val
& 0xff;
225 static uint32_t slavio_aux1_mem_readb(void *opaque
, target_phys_addr_t addr
)
227 MiscState
*s
= opaque
;
231 MISC_DPRINTF("Read aux1 %2.2x\n", ret
);
236 static CPUReadMemoryFunc
*slavio_aux1_mem_read
[3] = {
237 slavio_aux1_mem_readb
,
242 static CPUWriteMemoryFunc
*slavio_aux1_mem_write
[3] = {
243 slavio_aux1_mem_writeb
,
248 static void slavio_aux2_mem_writeb(void *opaque
, target_phys_addr_t addr
,
251 MiscState
*s
= opaque
;
253 val
&= AUX2_PWRINTCLR
| AUX2_PWROFF
;
254 MISC_DPRINTF("Write aux2 %2.2x\n", val
);
255 val
|= s
->aux2
& AUX2_PWRFAIL
;
256 if (val
& AUX2_PWRINTCLR
) // Clear Power Fail int
259 if (val
& AUX2_PWROFF
)
260 qemu_system_shutdown_request();
261 slavio_misc_update_irq(s
);
264 static uint32_t slavio_aux2_mem_readb(void *opaque
, target_phys_addr_t addr
)
266 MiscState
*s
= opaque
;
270 MISC_DPRINTF("Read aux2 %2.2x\n", ret
);
275 static CPUReadMemoryFunc
*slavio_aux2_mem_read
[3] = {
276 slavio_aux2_mem_readb
,
281 static CPUWriteMemoryFunc
*slavio_aux2_mem_write
[3] = {
282 slavio_aux2_mem_writeb
,
287 static void apc_mem_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
289 MiscState
*s
= opaque
;
291 MISC_DPRINTF("Write power management %2.2x\n", val
& 0xff);
292 qemu_irq_raise(s
->cpu_halt
);
295 static uint32_t apc_mem_readb(void *opaque
, target_phys_addr_t addr
)
299 MISC_DPRINTF("Read power management %2.2x\n", ret
);
303 static CPUReadMemoryFunc
*apc_mem_read
[3] = {
309 static CPUWriteMemoryFunc
*apc_mem_write
[3] = {
315 static uint32_t slavio_sysctrl_mem_readl(void *opaque
, target_phys_addr_t addr
)
317 MiscState
*s
= opaque
;
327 MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx
" = %x\n", addr
,
332 static void slavio_sysctrl_mem_writel(void *opaque
, target_phys_addr_t addr
,
335 MiscState
*s
= opaque
;
337 MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx
" = %x\n", addr
,
341 if (val
& SYS_RESET
) {
342 s
->sysctrl
= SYS_RESETSTAT
;
343 qemu_system_reset_request();
351 static CPUReadMemoryFunc
*slavio_sysctrl_mem_read
[3] = {
354 slavio_sysctrl_mem_readl
,
357 static CPUWriteMemoryFunc
*slavio_sysctrl_mem_write
[3] = {
360 slavio_sysctrl_mem_writel
,
363 static uint32_t slavio_led_mem_readw(void *opaque
, target_phys_addr_t addr
)
365 MiscState
*s
= opaque
;
375 MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx
" = %x\n", addr
,
380 static void slavio_led_mem_writew(void *opaque
, target_phys_addr_t addr
,
383 MiscState
*s
= opaque
;
385 MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx
" = %x\n", addr
,
396 static CPUReadMemoryFunc
*slavio_led_mem_read
[3] = {
398 slavio_led_mem_readw
,
402 static CPUWriteMemoryFunc
*slavio_led_mem_write
[3] = {
404 slavio_led_mem_writew
,
408 static void slavio_misc_save(QEMUFile
*f
, void *opaque
)
410 MiscState
*s
= opaque
;
414 qemu_put_be32s(f
, &tmp
); /* ignored, was IRQ. */
415 qemu_put_8s(f
, &s
->config
);
416 qemu_put_8s(f
, &s
->aux1
);
417 qemu_put_8s(f
, &s
->aux2
);
418 qemu_put_8s(f
, &s
->diag
);
419 qemu_put_8s(f
, &s
->mctrl
);
420 tmp8
= s
->sysctrl
& 0xff;
421 qemu_put_8s(f
, &tmp8
);
424 static int slavio_misc_load(QEMUFile
*f
, void *opaque
, int version_id
)
426 MiscState
*s
= opaque
;
433 qemu_get_be32s(f
, &tmp
);
434 qemu_get_8s(f
, &s
->config
);
435 qemu_get_8s(f
, &s
->aux1
);
436 qemu_get_8s(f
, &s
->aux2
);
437 qemu_get_8s(f
, &s
->diag
);
438 qemu_get_8s(f
, &s
->mctrl
);
439 qemu_get_8s(f
, &tmp8
);
440 s
->sysctrl
= (uint32_t)tmp8
;
444 void *slavio_misc_init(target_phys_addr_t base
, target_phys_addr_t power_base
,
445 target_phys_addr_t aux1_base
,
446 target_phys_addr_t aux2_base
, qemu_irq irq
,
447 qemu_irq cpu_halt
, qemu_irq
**fdc_tc
)
452 s
= qemu_mallocz(sizeof(MiscState
));
457 /* 8 bit registers */
460 io
= cpu_register_io_memory(0, slavio_cfg_mem_read
,
461 slavio_cfg_mem_write
, s
);
462 cpu_register_physical_memory(base
+ MISC_CFG
, MISC_SIZE
, io
);
465 io
= cpu_register_io_memory(0, slavio_diag_mem_read
,
466 slavio_diag_mem_write
, s
);
467 cpu_register_physical_memory(base
+ MISC_DIAG
, MISC_SIZE
, io
);
470 io
= cpu_register_io_memory(0, slavio_mdm_mem_read
,
471 slavio_mdm_mem_write
, s
);
472 cpu_register_physical_memory(base
+ MISC_MDM
, MISC_SIZE
, io
);
474 /* 16 bit registers */
475 io
= cpu_register_io_memory(0, slavio_led_mem_read
,
476 slavio_led_mem_write
, s
);
477 /* ss600mp diag LEDs */
478 cpu_register_physical_memory(base
+ MISC_LEDS
, MISC_SIZE
, io
);
480 /* 32 bit registers */
481 io
= cpu_register_io_memory(0, slavio_sysctrl_mem_read
,
482 slavio_sysctrl_mem_write
, s
);
484 cpu_register_physical_memory(base
+ MISC_SYS
, SYSCTRL_SIZE
, io
);
487 // AUX 1 (Misc System Functions)
489 io
= cpu_register_io_memory(0, slavio_aux1_mem_read
,
490 slavio_aux1_mem_write
, s
);
491 cpu_register_physical_memory(aux1_base
, MISC_SIZE
, io
);
494 // AUX 2 (Software Powerdown Control)
496 io
= cpu_register_io_memory(0, slavio_aux2_mem_read
,
497 slavio_aux2_mem_write
, s
);
498 cpu_register_physical_memory(aux2_base
, MISC_SIZE
, io
);
501 // Power management (APC) XXX: not a Slavio device
503 io
= cpu_register_io_memory(0, apc_mem_read
, apc_mem_write
, s
);
504 cpu_register_physical_memory(power_base
, MISC_SIZE
, io
);
508 s
->cpu_halt
= cpu_halt
;
509 *fdc_tc
= &s
->fdc_tc
;
511 register_savevm("slavio_misc", base
, 1, slavio_misc_save
, slavio_misc_load
,
513 qemu_register_reset(slavio_misc_reset
, s
);
514 slavio_misc_reset(s
);