target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #ifndef CPU_ARM_H
  21 #define CPU_ARM_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define ELF_MACHINE     EM_ARM
  26
  27 #include "cpu-defs.h"
  28
  29 #include "softfloat.h"
  30
  31 #define TARGET_HAS_ICE 1
  32
  33 #define EXCP_UDEF            1   /* undefined instruction */
  34 #define EXCP_SWI             2   /* software interrupt */
  35 #define EXCP_PREFETCH_ABORT  3
  36 #define EXCP_DATA_ABORT      4
  37 #define EXCP_IRQ             5
  38 #define EXCP_FIQ             6
  39 #define EXCP_BKPT            7
  40 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  41 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  42
  43 #define ARMV7M_EXCP_RESET   1
  44 #define ARMV7M_EXCP_NMI     2
  45 #define ARMV7M_EXCP_HARD    3
  46 #define ARMV7M_EXCP_MEM     4
  47 #define ARMV7M_EXCP_BUS     5
  48 #define ARMV7M_EXCP_USAGE   6
  49 #define ARMV7M_EXCP_SVC     11
  50 #define ARMV7M_EXCP_DEBUG   12
  51 #define ARMV7M_EXCP_PENDSV  14
  52 #define ARMV7M_EXCP_SYSTICK 15
  53
  54 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  55                             int srcreg, int operand, uint32_t value);
  56 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  57                                int dstreg, int operand);
  58
  59 struct arm_boot_info;
  60
  61 #define NB_MMU_MODES 2
  62
  63 /* We currently assume float and double are IEEE single and double
  64    precision respectively.
  65    Doing runtime conversions is tricky because VFP registers may contain
  66    integer values (eg. as the result of a FTOSI instruction).
  67    s<2n> maps to the least significant half of d<n>
  68    s<2n+1> maps to the most significant half of d<n>
  69  */
  70
  71 typedef struct CPUARMState {
  72     /* Regs for current mode.  */
  73     uint32_t regs[16];
  74     /* Frequently accessed CPSR bits are stored separately for efficiently.
  75        This contains all the other bits.  Use cpsr_{read,write} to access
  76        the whole CPSR.  */
  77     uint32_t uncached_cpsr;
  78     uint32_t spsr;
  79
  80     /* Banked registers.  */
  81     uint32_t banked_spsr[6];
  82     uint32_t banked_r13[6];
  83     uint32_t banked_r14[6];
  84
  85     /* These hold r8-r12.  */
  86     uint32_t usr_regs[5];
  87     uint32_t fiq_regs[5];
  88
  89     /* cpsr flag cache for faster execution */
  90     uint32_t CF; /* 0 or 1 */
  91     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  92     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
  93     uint32_t ZF; /* Z set if zero.  */
  94     uint32_t QF; /* 0 or 1 */
  95     uint32_t GE; /* cpsr[19:16] */
  96     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
  97     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
  98
  99     /* System control coprocessor (cp15) */
 100     struct {
 101         uint32_t c0_cpuid;
 102         uint32_t c0_cachetype;
 103         uint32_t c0_ccsid[16]; /* Cache size.  */
 104         uint32_t c0_clid; /* Cache level.  */
 105         uint32_t c0_cssel; /* Cache size selection.  */
 106         uint32_t c0_c1[8]; /* Feature registers.  */
 107         uint32_t c0_c2[8]; /* Instruction set registers.  */
 108         uint32_t c1_sys; /* System control register.  */
 109         uint32_t c1_coproc; /* Coprocessor access register.  */
 110         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 111         uint32_t c2_base0; /* MMU translation table base 0.  */
 112         uint32_t c2_base1; /* MMU translation table base 1.  */
 113         uint32_t c2_control; /* MMU translation table base control.  */
 114         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 115         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 116         uint32_t c2_data; /* MPU data cachable bits.  */
 117         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 118         uint32_t c3; /* MMU domain access control register
 119                         MPU write buffer control.  */
 120         uint32_t c5_insn; /* Fault status registers.  */
 121         uint32_t c5_data;
 122         uint32_t c6_region[8]; /* MPU base/size registers.  */
 123         uint32_t c6_insn; /* Fault address registers.  */
 124         uint32_t c6_data;
 125         uint32_t c9_insn; /* Cache lockdown registers.  */
 126         uint32_t c9_data;
 127         uint32_t c13_fcse; /* FCSE PID.  */
 128         uint32_t c13_context; /* Context ID.  */
 129         uint32_t c13_tls1; /* User RW Thread register.  */
 130         uint32_t c13_tls2; /* User RO Thread register.  */
 131         uint32_t c13_tls3; /* Privileged Thread register.  */
 132         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 133         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 134         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 135         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 136         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 137     } cp15;
 138
 139     struct {
 140         uint32_t other_sp;
 141         uint32_t vecbase;
 142         uint32_t basepri;
 143         uint32_t control;
 144         int current_sp;
 145         int exception;
 146         int pending_exception;
 147         void *nvic;
 148     } v7m;
 149
 150     /* Coprocessor IO used by peripherals */
 151     struct {
 152         ARMReadCPFunc *cp_read;
 153         ARMWriteCPFunc *cp_write;
 154         void *opaque;
 155     } cp[15];
 156
 157     /* Thumb-2 EE state.  */
 158     uint32_t teecr;
 159     uint32_t teehbr;
 160
 161     /* Internal CPU feature flags.  */
 162     uint32_t features;
 163
 164     /* Callback for vectored interrupt controller.  */
 165     int (*get_irq_vector)(struct CPUARMState *);
 166     void *irq_opaque;
 167
 168     /* VFP coprocessor state.  */
 169     struct {
 170         float64 regs[32];
 171
 172         uint32_t xregs[16];
 173         /* We store these fpcsr fields separately for convenience.  */
 174         int vec_len;
 175         int vec_stride;
 176
 177         /* scratch space when Tn are not sufficient.  */
 178         uint32_t scratch[8];
 179
 180         float_status fp_status;
 181     } vfp;
 182 #if defined(CONFIG_USER_ONLY)
 183     struct mmon_state *mmon_entry;
 184 #else
 185     uint32_t mmon_addr;
 186 #endif
 187
 188     /* iwMMXt coprocessor state.  */
 189     struct {
 190         uint64_t regs[16];
 191         uint64_t val;
 192
 193         uint32_t cregs[16];
 194     } iwmmxt;
 195
 196 #if defined(CONFIG_USER_ONLY)
 197     /* For usermode syscall translation.  */
 198     int eabi;
 199 #endif
 200
 201     CPU_COMMON
 202
 203     /* These fields after the common ones so they are preserved on reset.  */
 204     struct arm_boot_info *boot_info;
 205 } CPUARMState;
 206
 207 CPUARMState *cpu_arm_init(const char *cpu_model);
 208 void arm_translate_init(void);
 209 int cpu_arm_exec(CPUARMState *s);
 210 void cpu_arm_close(CPUARMState *s);
 211 void do_interrupt(CPUARMState *);
 212 void switch_mode(CPUARMState *, int);
 213 uint32_t do_arm_semihosting(CPUARMState *env);
 214
 215 /* you can call this signal handler from your SIGBUS and SIGSEGV
 216    signal handlers to inform the virtual CPU of exceptions. non zero
 217    is returned if the signal was handled by the virtual CPU.  */
 218 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 219                            void *puc);
 220
 221 void cpu_lock(void);
 222 void cpu_unlock(void);
 223 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls)
 224 {
 225   env->cp15.c13_tls2 = newtls;
 226 }
 227
 228 #define CPSR_M (0x1f)
 229 #define CPSR_T (1 << 5)
 230 #define CPSR_F (1 << 6)
 231 #define CPSR_I (1 << 7)
 232 #define CPSR_A (1 << 8)
 233 #define CPSR_E (1 << 9)
 234 #define CPSR_IT_2_7 (0xfc00)
 235 #define CPSR_GE (0xf << 16)
 236 #define CPSR_RESERVED (0xf << 20)
 237 #define CPSR_J (1 << 24)
 238 #define CPSR_IT_0_1 (3 << 25)
 239 #define CPSR_Q (1 << 27)
 240 #define CPSR_V (1 << 28)
 241 #define CPSR_C (1 << 29)
 242 #define CPSR_Z (1 << 30)
 243 #define CPSR_N (1 << 31)
 244 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 245
 246 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 247 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 248 /* Bits writable in user mode.  */
 249 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 250 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 251 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 252
 253 /* Return the current CPSR value.  */
 254 uint32_t cpsr_read(CPUARMState *env);
 255 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 256 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 257
 258 /* Return the current xPSR value.  */
 259 static inline uint32_t xpsr_read(CPUARMState *env)
 260 {
 261     int ZF;
 262     ZF = (env->ZF == 0);
 263     return (env->NF & 0x80000000) | (ZF << 30)
 264         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 265         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 266         | ((env->condexec_bits & 0xfc) << 8)
 267         | env->v7m.exception;
 268 }
 269
 270 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 271 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 272 {
 273     if (mask & CPSR_NZCV) {
 274         env->ZF = (~val) & CPSR_Z;
 275         env->NF = val;
 276         env->CF = (val >> 29) & 1;
 277         env->VF = (val << 3) & 0x80000000;
 278     }
 279     if (mask & CPSR_Q)
 280         env->QF = ((val & CPSR_Q) != 0);
 281     if (mask & (1 << 24))
 282         env->thumb = ((val & (1 << 24)) != 0);
 283     if (mask & CPSR_IT_0_1) {
 284         env->condexec_bits &= ~3;
 285         env->condexec_bits |= (val >> 25) & 3;
 286     }
 287     if (mask & CPSR_IT_2_7) {
 288         env->condexec_bits &= 3;
 289         env->condexec_bits |= (val >> 8) & 0xfc;
 290     }
 291     if (mask & 0x1ff) {
 292         env->v7m.exception = val & 0x1ff;
 293     }
 294 }
 295
 296 enum arm_cpu_mode {
 297   ARM_CPU_MODE_USR = 0x10,
 298   ARM_CPU_MODE_FIQ = 0x11,
 299   ARM_CPU_MODE_IRQ = 0x12,
 300   ARM_CPU_MODE_SVC = 0x13,
 301   ARM_CPU_MODE_ABT = 0x17,
 302   ARM_CPU_MODE_UND = 0x1b,
 303   ARM_CPU_MODE_SYS = 0x1f
 304 };
 305
 306 /* VFP system registers.  */
 307 #define ARM_VFP_FPSID   0
 308 #define ARM_VFP_FPSCR   1
 309 #define ARM_VFP_MVFR1   6
 310 #define ARM_VFP_MVFR0   7
 311 #define ARM_VFP_FPEXC   8
 312 #define ARM_VFP_FPINST  9
 313 #define ARM_VFP_FPINST2 10
 314
 315 /* iwMMXt coprocessor control registers.  */
 316 #define ARM_IWMMXT_wCID         0
 317 #define ARM_IWMMXT_wCon         1
 318 #define ARM_IWMMXT_wCSSF        2
 319 #define ARM_IWMMXT_wCASF        3
 320 #define ARM_IWMMXT_wCGR0        8
 321 #define ARM_IWMMXT_wCGR1        9
 322 #define ARM_IWMMXT_wCGR2        10
 323 #define ARM_IWMMXT_wCGR3        11
 324
 325 enum arm_features {
 326     ARM_FEATURE_VFP,
 327     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 328     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 329     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 330     ARM_FEATURE_V6,
 331     ARM_FEATURE_V6K,
 332     ARM_FEATURE_V7,
 333     ARM_FEATURE_THUMB2,
 334     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 335     ARM_FEATURE_VFP3,
 336     ARM_FEATURE_NEON,
 337     ARM_FEATURE_DIV,
 338     ARM_FEATURE_M, /* Microcontroller profile.  */
 339     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 340     ARM_FEATURE_THUMB2EE
 341 };
 342
 343 static inline int arm_feature(CPUARMState *env, int feature)
 344 {
 345     return (env->features & (1u << feature)) != 0;
 346 }
 347
 348 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 349
 350 /* Interface between CPU and Interrupt controller.  */
 351 void armv7m_nvic_set_pending(void *opaque, int irq);
 352 int armv7m_nvic_acknowledge_irq(void *opaque);
 353 void armv7m_nvic_complete_irq(void *opaque, int irq);
 354
 355 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 356                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 357                        void *opaque);
 358
 359 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 360    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 361    conventional cores (ie. Application or Realtime profile).  */
 362
 363 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 364 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
 365
 366 #define ARM_CPUID_ARM1026     0x4106a262
 367 #define ARM_CPUID_ARM926      0x41069265
 368 #define ARM_CPUID_ARM946      0x41059461
 369 #define ARM_CPUID_TI915T      0x54029152
 370 #define ARM_CPUID_TI925T      0x54029252
 371 #define ARM_CPUID_PXA250      0x69052100
 372 #define ARM_CPUID_PXA255      0x69052d00
 373 #define ARM_CPUID_PXA260      0x69052903
 374 #define ARM_CPUID_PXA261      0x69052d05
 375 #define ARM_CPUID_PXA262      0x69052d06
 376 #define ARM_CPUID_PXA270      0x69054110
 377 #define ARM_CPUID_PXA270_A0   0x69054110
 378 #define ARM_CPUID_PXA270_A1   0x69054111
 379 #define ARM_CPUID_PXA270_B0   0x69054112
 380 #define ARM_CPUID_PXA270_B1   0x69054113
 381 #define ARM_CPUID_PXA270_C0   0x69054114
 382 #define ARM_CPUID_PXA270_C5   0x69054117
 383 #define ARM_CPUID_ARM1136     0x4117b363
 384 #define ARM_CPUID_ARM1136_R2  0x4107b362
 385 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 386 #define ARM_CPUID_CORTEXA8    0x410fc080
 387 #define ARM_CPUID_CORTEXM3    0x410fc231
 388 #define ARM_CPUID_ANY         0xffffffff
 389
 390 #if defined(CONFIG_USER_ONLY)
 391 #define TARGET_PAGE_BITS 12
 392 #else
 393 /* The ARM MMU allows 1k pages.  */
 394 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 395    architecture revisions.  Maybe a configure option to disable them.  */
 396 #define TARGET_PAGE_BITS 10
 397 #endif
 398
 399 #define CPUState CPUARMState
 400 #define cpu_init cpu_arm_init
 401 #define cpu_exec cpu_arm_exec
 402 #define cpu_gen_code cpu_arm_gen_code
 403 #define cpu_signal_handler cpu_arm_signal_handler
 404 #define cpu_list arm_cpu_list
 405
 406 #define CPU_SAVE_VERSION 1
 407
 408 /* MMU modes definitions */
 409 #define MMU_MODE0_SUFFIX _kernel
 410 #define MMU_MODE1_SUFFIX _user
 411 #define MMU_USER_IDX 1
 412 static inline int cpu_mmu_index (CPUState *env)
 413 {
 414     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 415 }
 416
 417 #if defined(CONFIG_USER_ONLY)
 418 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 419 {
 420     if (newsp)
 421         env->regs[13] = newsp;
 422     env->regs[0] = 0;
 423 }
 424 #endif
 425
 426 #include "cpu-all.h"
 427 #include "exec-all.h"
 428
 429 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 430 {
 431     env->regs[15] = tb->pc;
 432 }
 433
 434 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 435                                         target_ulong *cs_base, int *flags)
 436 {
 437     *pc = env->regs[15];
 438     *cs_base = 0;
 439     *flags = env->thumb | (env->vfp.vec_len << 1)
 440             | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8);
 441     if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
 442         *flags |= (1 << 6);
 443     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
 444         *flags |= (1 << 7);
 445 }
 446
 447 #endif