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Add ARM RealView Emulation Baseboard.
[qemu/mini2440.git] / cpu-exec.c
blob6385639f46f20dcb8b380d8644364c03df1ad5ed
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4))
51 #define reg_T2
52 #endif
53
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
58 {
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61 #endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67 #if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72 #endif
73 longjmp(env->jmp_env, 1);
74 }
75
76
77 static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80 {
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag = 1;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151 }
152
153 static inline TranslationBlock *tb_find_fast(void)
154 {
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162 #if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167 #elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
174 cs_base = 0;
175 pc = env->regs[15];
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
181 #else
182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
184 | env->psrs;
185 #endif
186 cs_base = env->npc;
187 pc = env->pc;
188 #elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193 #elif defined(TARGET_MIPS)
194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
195 cs_base = 0;
196 pc = env->PC;
197 #elif defined(TARGET_SH4)
198 flags = env->sr & (SR_MD | SR_RB);
199 cs_base = 0; /* XXXXX */
200 pc = env->pc;
201 #else
202 #error unsupported CPU
203 #endif
204 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
205 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
206 tb->flags != flags, 0)) {
207 tb = tb_find_slow(pc, cs_base, flags);
208 /* Note: we do it here to avoid a gcc bug on Mac OS X when
209 doing it in tb_find_slow */
210 if (tb_invalidated_flag) {
211 /* as some TB could have been invalidated because
212 of memory exceptions while generating the code, we
213 must recompute the hash index here */
214 T0 = 0;
215 }
216 }
217 return tb;
218 }
219
220
221 /* main execution loop */
222
223 int cpu_exec(CPUState *env1)
224 {
225 int saved_T0, saved_T1;
226 #if defined(reg_T2)
227 int saved_T2;
228 #endif
229 CPUState *saved_env;
230 #if defined(TARGET_I386)
231 #ifdef reg_EAX
232 int saved_EAX;
233 #endif
234 #ifdef reg_ECX
235 int saved_ECX;
236 #endif
237 #ifdef reg_EDX
238 int saved_EDX;
239 #endif
240 #ifdef reg_EBX
241 int saved_EBX;
242 #endif
243 #ifdef reg_ESP
244 int saved_ESP;
245 #endif
246 #ifdef reg_EBP
247 int saved_EBP;
248 #endif
249 #ifdef reg_ESI
250 int saved_ESI;
251 #endif
252 #ifdef reg_EDI
253 int saved_EDI;
254 #endif
255 #elif defined(TARGET_SPARC)
256 #if defined(reg_REGWPTR)
257 uint32_t *saved_regwptr;
258 #endif
259 #endif
260 #if defined(__sparc__) && !defined(HOST_SOLARIS)
261 int saved_i7, tmp_T0;
262 #endif
263 int ret, interrupt_request;
264 void (*gen_func)(void);
265 TranslationBlock *tb;
266 uint8_t *tc_ptr;
267
268 #if defined(TARGET_I386)
269 /* handle exit of HALTED state */
270 if (env1->hflags & HF_HALTED_MASK) {
271 /* disable halt condition */
272 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
273 (env1->eflags & IF_MASK)) {
274 env1->hflags &= ~HF_HALTED_MASK;
275 } else {
276 return EXCP_HALTED;
277 }
278 }
279 #elif defined(TARGET_PPC)
280 if (env1->halted) {
281 if (env1->msr[MSR_EE] &&
282 (env1->interrupt_request &
283 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
284 env1->halted = 0;
285 } else {
286 return EXCP_HALTED;
287 }
288 }
289 #elif defined(TARGET_SPARC)
290 if (env1->halted) {
291 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
292 (env1->psret != 0)) {
293 env1->halted = 0;
294 } else {
295 return EXCP_HALTED;
296 }
297 }
298 #elif defined(TARGET_ARM)
299 if (env1->halted) {
300 /* An interrupt wakes the CPU even if the I and F CPSR bits are
301 set. */
302 if (env1->interrupt_request
303 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
304 env1->halted = 0;
305 } else {
306 return EXCP_HALTED;
307 }
308 }
309 #elif defined(TARGET_MIPS)
310 if (env1->halted) {
311 if (env1->interrupt_request &
312 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
313 env1->halted = 0;
314 } else {
315 return EXCP_HALTED;
316 }
317 }
318 #endif
319
320 cpu_single_env = env1;
321
322 /* first we save global registers */
323 saved_env = env;
324 env = env1;
325 saved_T0 = T0;
326 saved_T1 = T1;
327 #if defined(reg_T2)
328 saved_T2 = T2;
329 #endif
330 #if defined(__sparc__) && !defined(HOST_SOLARIS)
331 /* we also save i7 because longjmp may not restore it */
332 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
333 #endif
334
335 #if defined(TARGET_I386)
336 #ifdef reg_EAX
337 saved_EAX = EAX;
338 #endif
339 #ifdef reg_ECX
340 saved_ECX = ECX;
341 #endif
342 #ifdef reg_EDX
343 saved_EDX = EDX;
344 #endif
345 #ifdef reg_EBX
346 saved_EBX = EBX;
347 #endif
348 #ifdef reg_ESP
349 saved_ESP = ESP;
350 #endif
351 #ifdef reg_EBP
352 saved_EBP = EBP;
353 #endif
354 #ifdef reg_ESI
355 saved_ESI = ESI;
356 #endif
357 #ifdef reg_EDI
358 saved_EDI = EDI;
359 #endif
360
361 env_to_regs();
362 /* put eflags in CPU temporary format */
363 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
364 DF = 1 - (2 * ((env->eflags >> 10) & 1));
365 CC_OP = CC_OP_EFLAGS;
366 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
367 #elif defined(TARGET_ARM)
368 #elif defined(TARGET_SPARC)
369 #if defined(reg_REGWPTR)
370 saved_regwptr = REGWPTR;
371 #endif
372 #elif defined(TARGET_PPC)
373 #elif defined(TARGET_MIPS)
374 #elif defined(TARGET_SH4)
375 /* XXXXX */
376 #else
377 #error unsupported target CPU
378 #endif
379 env->exception_index = -1;
380
381 /* prepare setjmp context for exception handling */
382 for(;;) {
383 if (setjmp(env->jmp_env) == 0) {
384 env->current_tb = NULL;
385 /* if an exception is pending, we execute it here */
386 if (env->exception_index >= 0) {
387 if (env->exception_index >= EXCP_INTERRUPT) {
388 /* exit request from the cpu execution loop */
389 ret = env->exception_index;
390 break;
391 } else if (env->user_mode_only) {
392 /* if user mode only, we simulate a fake exception
393 which will be hanlded outside the cpu execution
394 loop */
395 #if defined(TARGET_I386)
396 do_interrupt_user(env->exception_index,
397 env->exception_is_int,
398 env->error_code,
399 env->exception_next_eip);
400 #endif
401 ret = env->exception_index;
402 break;
403 } else {
404 #if defined(TARGET_I386)
405 /* simulate a real cpu exception. On i386, it can
406 trigger new exceptions, but we do not handle
407 double or triple faults yet. */
408 do_interrupt(env->exception_index,
409 env->exception_is_int,
410 env->error_code,
411 env->exception_next_eip, 0);
412 #elif defined(TARGET_PPC)
413 do_interrupt(env);
414 #elif defined(TARGET_MIPS)
415 do_interrupt(env);
416 #elif defined(TARGET_SPARC)
417 do_interrupt(env->exception_index);
418 #elif defined(TARGET_ARM)
419 do_interrupt(env);
420 #elif defined(TARGET_SH4)
421 do_interrupt(env);
422 #endif
423 }
424 env->exception_index = -1;
425 }
426 #ifdef USE_KQEMU
427 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
428 int ret;
429 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
430 ret = kqemu_cpu_exec(env);
431 /* put eflags in CPU temporary format */
432 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
433 DF = 1 - (2 * ((env->eflags >> 10) & 1));
434 CC_OP = CC_OP_EFLAGS;
435 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
436 if (ret == 1) {
437 /* exception */
438 longjmp(env->jmp_env, 1);
439 } else if (ret == 2) {
440 /* softmmu execution needed */
441 } else {
442 if (env->interrupt_request != 0) {
443 /* hardware interrupt will be executed just after */
444 } else {
445 /* otherwise, we restart */
446 longjmp(env->jmp_env, 1);
447 }
448 }
449 }
450 #endif
451
452 T0 = 0; /* force lookup of first TB */
453 for(;;) {
454 #if defined(__sparc__) && !defined(HOST_SOLARIS)
455 /* g1 can be modified by some libc? functions */
456 tmp_T0 = T0;
457 #endif
458 interrupt_request = env->interrupt_request;
459 if (__builtin_expect(interrupt_request, 0)) {
460 #if defined(TARGET_I386)
461 /* if hardware interrupt pending, we execute it */
462 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
463 (env->eflags & IF_MASK) &&
464 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
465 int intno;
466 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
467 intno = cpu_get_pic_interrupt(env);
468 if (loglevel & CPU_LOG_TB_IN_ASM) {
469 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
470 }
471 do_interrupt(intno, 0, 0, 0, 1);
472 /* ensure that no TB jump will be modified as
473 the program flow was changed */
474 #if defined(__sparc__) && !defined(HOST_SOLARIS)
475 tmp_T0 = 0;
476 #else
477 T0 = 0;
478 #endif
479 }
480 #elif defined(TARGET_PPC)
481 #if 0
482 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
483 cpu_ppc_reset(env);
484 }
485 #endif
486 if (msr_ee != 0) {
487 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
488 /* Raise it */
489 env->exception_index = EXCP_EXTERNAL;
490 env->error_code = 0;
491 do_interrupt(env);
492 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
493 #if defined(__sparc__) && !defined(HOST_SOLARIS)
494 tmp_T0 = 0;
495 #else
496 T0 = 0;
497 #endif
498 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
499 /* Raise it */
500 env->exception_index = EXCP_DECR;
501 env->error_code = 0;
502 do_interrupt(env);
503 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
504 #if defined(__sparc__) && !defined(HOST_SOLARIS)
505 tmp_T0 = 0;
506 #else
507 T0 = 0;
508 #endif
509 }
510 }
511 #elif defined(TARGET_MIPS)
512 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
513 (env->CP0_Status & (1 << CP0St_IE)) &&
514 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
515 !(env->hflags & MIPS_HFLAG_EXL) &&
516 !(env->hflags & MIPS_HFLAG_ERL) &&
517 !(env->hflags & MIPS_HFLAG_DM)) {
518 /* Raise it */
519 env->exception_index = EXCP_EXT_INTERRUPT;
520 env->error_code = 0;
521 do_interrupt(env);
522 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
523 #if defined(__sparc__) && !defined(HOST_SOLARIS)
524 tmp_T0 = 0;
525 #else
526 T0 = 0;
527 #endif
528 }
529 #elif defined(TARGET_SPARC)
530 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
531 (env->psret != 0)) {
532 int pil = env->interrupt_index & 15;
533 int type = env->interrupt_index & 0xf0;
534
535 if (((type == TT_EXTINT) &&
536 (pil == 15 || pil > env->psrpil)) ||
537 type != TT_EXTINT) {
538 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
539 do_interrupt(env->interrupt_index);
540 env->interrupt_index = 0;
541 #if defined(__sparc__) && !defined(HOST_SOLARIS)
542 tmp_T0 = 0;
543 #else
544 T0 = 0;
545 #endif
546 }
547 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
548 //do_interrupt(0, 0, 0, 0, 0);
549 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
550 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
551 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
552 env->halted = 1;
553 env->exception_index = EXCP_HLT;
554 cpu_loop_exit();
555 }
556 #elif defined(TARGET_ARM)
557 if (interrupt_request & CPU_INTERRUPT_FIQ
558 && !(env->uncached_cpsr & CPSR_F)) {
559 env->exception_index = EXCP_FIQ;
560 do_interrupt(env);
561 }
562 if (interrupt_request & CPU_INTERRUPT_HARD
563 && !(env->uncached_cpsr & CPSR_I)) {
564 env->exception_index = EXCP_IRQ;
565 do_interrupt(env);
566 }
567 #elif defined(TARGET_SH4)
568 /* XXXXX */
569 #endif
570 /* Don't use the cached interupt_request value,
571 do_interrupt may have updated the EXITTB flag. */
572 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
573 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
574 /* ensure that no TB jump will be modified as
575 the program flow was changed */
576 #if defined(__sparc__) && !defined(HOST_SOLARIS)
577 tmp_T0 = 0;
578 #else
579 T0 = 0;
580 #endif
581 }
582 if (interrupt_request & CPU_INTERRUPT_EXIT) {
583 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
584 env->exception_index = EXCP_INTERRUPT;
585 cpu_loop_exit();
586 }
587 }
588 #ifdef DEBUG_EXEC
589 if ((loglevel & CPU_LOG_TB_CPU)) {
590 #if defined(TARGET_I386)
591 /* restore flags in standard format */
592 #ifdef reg_EAX
593 env->regs[R_EAX] = EAX;
594 #endif
595 #ifdef reg_EBX
596 env->regs[R_EBX] = EBX;
597 #endif
598 #ifdef reg_ECX
599 env->regs[R_ECX] = ECX;
600 #endif
601 #ifdef reg_EDX
602 env->regs[R_EDX] = EDX;
603 #endif
604 #ifdef reg_ESI
605 env->regs[R_ESI] = ESI;
606 #endif
607 #ifdef reg_EDI
608 env->regs[R_EDI] = EDI;
609 #endif
610 #ifdef reg_EBP
611 env->regs[R_EBP] = EBP;
612 #endif
613 #ifdef reg_ESP
614 env->regs[R_ESP] = ESP;
615 #endif
616 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
617 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
618 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
619 #elif defined(TARGET_ARM)
620 cpu_dump_state(env, logfile, fprintf, 0);
621 #elif defined(TARGET_SPARC)
622 REGWPTR = env->regbase + (env->cwp * 16);
623 env->regwptr = REGWPTR;
624 cpu_dump_state(env, logfile, fprintf, 0);
625 #elif defined(TARGET_PPC)
626 cpu_dump_state(env, logfile, fprintf, 0);
627 #elif defined(TARGET_MIPS)
628 cpu_dump_state(env, logfile, fprintf, 0);
629 #elif defined(TARGET_SH4)
630 cpu_dump_state(env, logfile, fprintf, 0);
631 #else
632 #error unsupported target CPU
633 #endif
634 }
635 #endif
636 tb = tb_find_fast();
637 #ifdef DEBUG_EXEC
638 if ((loglevel & CPU_LOG_EXEC)) {
639 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
640 (long)tb->tc_ptr, tb->pc,
641 lookup_symbol(tb->pc));
642 }
643 #endif
644 #if defined(__sparc__) && !defined(HOST_SOLARIS)
645 T0 = tmp_T0;
646 #endif
647 /* see if we can patch the calling TB. When the TB
648 spans two pages, we cannot safely do a direct
649 jump. */
650 {
651 if (T0 != 0 &&
652 #if USE_KQEMU
653 (env->kqemu_enabled != 2) &&
654 #endif
655 tb->page_addr[1] == -1
656 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
657 && (tb->cflags & CF_CODE_COPY) ==
658 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
659 #endif
660 ) {
661 spin_lock(&tb_lock);
662 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
663 #if defined(USE_CODE_COPY)
664 /* propagates the FP use info */
665 ((TranslationBlock *)(T0 & ~3))->cflags |=
666 (tb->cflags & CF_FP_USED);
667 #endif
668 spin_unlock(&tb_lock);
669 }
670 }
671 tc_ptr = tb->tc_ptr;
672 env->current_tb = tb;
673 /* execute the generated code */
674 gen_func = (void *)tc_ptr;
675 #if defined(__sparc__)
676 __asm__ __volatile__("call %0\n\t"
677 "mov %%o7,%%i0"
678 : /* no outputs */
679 : "r" (gen_func)
680 : "i0", "i1", "i2", "i3", "i4", "i5",
681 "l0", "l1", "l2", "l3", "l4", "l5",
682 "l6", "l7");
683 #elif defined(__arm__)
684 asm volatile ("mov pc, %0\n\t"
685 ".global exec_loop\n\t"
686 "exec_loop:\n\t"
687 : /* no outputs */
688 : "r" (gen_func)
689 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
690 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
691 {
692 if (!(tb->cflags & CF_CODE_COPY)) {
693 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
694 save_native_fp_state(env);
695 }
696 gen_func();
697 } else {
698 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
699 restore_native_fp_state(env);
700 }
701 /* we work with native eflags */
702 CC_SRC = cc_table[CC_OP].compute_all();
703 CC_OP = CC_OP_EFLAGS;
704 asm(".globl exec_loop\n"
705 "\n"
706 "debug1:\n"
707 " pushl %%ebp\n"
708 " fs movl %10, %9\n"
709 " fs movl %11, %%eax\n"
710 " andl $0x400, %%eax\n"
711 " fs orl %8, %%eax\n"
712 " pushl %%eax\n"
713 " popf\n"
714 " fs movl %%esp, %12\n"
715 " fs movl %0, %%eax\n"
716 " fs movl %1, %%ecx\n"
717 " fs movl %2, %%edx\n"
718 " fs movl %3, %%ebx\n"
719 " fs movl %4, %%esp\n"
720 " fs movl %5, %%ebp\n"
721 " fs movl %6, %%esi\n"
722 " fs movl %7, %%edi\n"
723 " fs jmp *%9\n"
724 "exec_loop:\n"
725 " fs movl %%esp, %4\n"
726 " fs movl %12, %%esp\n"
727 " fs movl %%eax, %0\n"
728 " fs movl %%ecx, %1\n"
729 " fs movl %%edx, %2\n"
730 " fs movl %%ebx, %3\n"
731 " fs movl %%ebp, %5\n"
732 " fs movl %%esi, %6\n"
733 " fs movl %%edi, %7\n"
734 " pushf\n"
735 " popl %%eax\n"
736 " movl %%eax, %%ecx\n"
737 " andl $0x400, %%ecx\n"
738 " shrl $9, %%ecx\n"
739 " andl $0x8d5, %%eax\n"
740 " fs movl %%eax, %8\n"
741 " movl $1, %%eax\n"
742 " subl %%ecx, %%eax\n"
743 " fs movl %%eax, %11\n"
744 " fs movl %9, %%ebx\n" /* get T0 value */
745 " popl %%ebp\n"
746 :
747 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
748 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
749 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
750 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
751 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
752 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
753 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
754 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
755 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
756 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
757 "a" (gen_func),
758 "m" (*(uint8_t *)offsetof(CPUState, df)),
759 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
760 : "%ecx", "%edx"
761 );
762 }
763 }
764 #elif defined(__ia64)
765 struct fptr {
766 void *ip;
767 void *gp;
768 } fp;
769
770 fp.ip = tc_ptr;
771 fp.gp = code_gen_buffer + 2 * (1 << 20);
772 (*(void (*)(void)) &fp)();
773 #else
774 gen_func();
775 #endif
776 env->current_tb = NULL;
777 /* reset soft MMU for next block (it can currently
778 only be set by a memory fault) */
779 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
780 if (env->hflags & HF_SOFTMMU_MASK) {
781 env->hflags &= ~HF_SOFTMMU_MASK;
782 /* do not allow linking to another block */
783 T0 = 0;
784 }
785 #endif
786 #if defined(USE_KQEMU)
787 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
788 if (kqemu_is_ok(env) &&
789 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
790 cpu_loop_exit();
791 }
792 #endif
793 }
794 } else {
795 env_to_regs();
796 }
797 } /* for(;;) */
798
799
800 #if defined(TARGET_I386)
801 #if defined(USE_CODE_COPY)
802 if (env->native_fp_regs) {
803 save_native_fp_state(env);
804 }
805 #endif
806 /* restore flags in standard format */
807 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
808
809 /* restore global registers */
810 #ifdef reg_EAX
811 EAX = saved_EAX;
812 #endif
813 #ifdef reg_ECX
814 ECX = saved_ECX;
815 #endif
816 #ifdef reg_EDX
817 EDX = saved_EDX;
818 #endif
819 #ifdef reg_EBX
820 EBX = saved_EBX;
821 #endif
822 #ifdef reg_ESP
823 ESP = saved_ESP;
824 #endif
825 #ifdef reg_EBP
826 EBP = saved_EBP;
827 #endif
828 #ifdef reg_ESI
829 ESI = saved_ESI;
830 #endif
831 #ifdef reg_EDI
832 EDI = saved_EDI;
833 #endif
834 #elif defined(TARGET_ARM)
835 /* XXX: Save/restore host fpu exception state?. */
836 #elif defined(TARGET_SPARC)
837 #if defined(reg_REGWPTR)
838 REGWPTR = saved_regwptr;
839 #endif
840 #elif defined(TARGET_PPC)
841 #elif defined(TARGET_MIPS)
842 #elif defined(TARGET_SH4)
843 /* XXXXX */
844 #else
845 #error unsupported target CPU
846 #endif
847 #if defined(__sparc__) && !defined(HOST_SOLARIS)
848 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
849 #endif
850 T0 = saved_T0;
851 T1 = saved_T1;
852 #if defined(reg_T2)
853 T2 = saved_T2;
854 #endif
855 env = saved_env;
856 /* fail safe : never use cpu_single_env outside cpu_exec() */
857 cpu_single_env = NULL;
858 return ret;
859 }
860
861 /* must only be called from the generated code as an exception can be
862 generated */
863 void tb_invalidate_page_range(target_ulong start, target_ulong end)
864 {
865 /* XXX: cannot enable it yet because it yields to MMU exception
866 where NIP != read address on PowerPC */
867 #if 0
868 target_ulong phys_addr;
869 phys_addr = get_phys_addr_code(env, start);
870 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
871 #endif
872 }
873
874 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
875
876 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
877 {
878 CPUX86State *saved_env;
879
880 saved_env = env;
881 env = s;
882 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
883 selector &= 0xffff;
884 cpu_x86_load_seg_cache(env, seg_reg, selector,
885 (selector << 4), 0xffff, 0);
886 } else {
887 load_seg(seg_reg, selector);
888 }
889 env = saved_env;
890 }
891
892 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
893 {
894 CPUX86State *saved_env;
895
896 saved_env = env;
897 env = s;
898
899 helper_fsave((target_ulong)ptr, data32);
900
901 env = saved_env;
902 }
903
904 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
905 {
906 CPUX86State *saved_env;
907
908 saved_env = env;
909 env = s;
910
911 helper_frstor((target_ulong)ptr, data32);
912
913 env = saved_env;
914 }
915
916 #endif /* TARGET_I386 */
917
918 #if !defined(CONFIG_SOFTMMU)
919
920 #if defined(TARGET_I386)
921
922 /* 'pc' is the host PC at which the exception was raised. 'address' is
923 the effective address of the memory exception. 'is_write' is 1 if a
924 write caused the exception and otherwise 0'. 'old_set' is the
925 signal set which should be restored */
926 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
927 int is_write, sigset_t *old_set,
928 void *puc)
929 {
930 TranslationBlock *tb;
931 int ret;
932
933 if (cpu_single_env)
934 env = cpu_single_env; /* XXX: find a correct solution for multithread */
935 #if defined(DEBUG_SIGNAL)
936 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
937 pc, address, is_write, *(unsigned long *)old_set);
938 #endif
939 /* XXX: locking issue */
940 if (is_write && page_unprotect(h2g(address), pc, puc)) {
941 return 1;
942 }
943
944 /* see if it is an MMU fault */
945 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
946 ((env->hflags & HF_CPL_MASK) == 3), 0);
947 if (ret < 0)
948 return 0; /* not an MMU fault */
949 if (ret == 0)
950 return 1; /* the MMU fault was handled without causing real CPU fault */
951 /* now we have a real cpu fault */
952 tb = tb_find_pc(pc);
953 if (tb) {
954 /* the PC is inside the translated code. It means that we have
955 a virtual CPU fault */
956 cpu_restore_state(tb, env, pc, puc);
957 }
958 if (ret == 1) {
959 #if 0
960 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
961 env->eip, env->cr[2], env->error_code);
962 #endif
963 /* we restore the process signal mask as the sigreturn should
964 do it (XXX: use sigsetjmp) */
965 sigprocmask(SIG_SETMASK, old_set, NULL);
966 raise_exception_err(env->exception_index, env->error_code);
967 } else {
968 /* activate soft MMU for this block */
969 env->hflags |= HF_SOFTMMU_MASK;
970 cpu_resume_from_signal(env, puc);
971 }
972 /* never comes here */
973 return 1;
974 }
975
976 #elif defined(TARGET_ARM)
977 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
978 int is_write, sigset_t *old_set,
979 void *puc)
980 {
981 TranslationBlock *tb;
982 int ret;
983
984 if (cpu_single_env)
985 env = cpu_single_env; /* XXX: find a correct solution for multithread */
986 #if defined(DEBUG_SIGNAL)
987 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
988 pc, address, is_write, *(unsigned long *)old_set);
989 #endif
990 /* XXX: locking issue */
991 if (is_write && page_unprotect(h2g(address), pc, puc)) {
992 return 1;
993 }
994 /* see if it is an MMU fault */
995 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
996 if (ret < 0)
997 return 0; /* not an MMU fault */
998 if (ret == 0)
999 return 1; /* the MMU fault was handled without causing real CPU fault */
1000 /* now we have a real cpu fault */
1001 tb = tb_find_pc(pc);
1002 if (tb) {
1003 /* the PC is inside the translated code. It means that we have
1004 a virtual CPU fault */
1005 cpu_restore_state(tb, env, pc, puc);
1006 }
1007 /* we restore the process signal mask as the sigreturn should
1008 do it (XXX: use sigsetjmp) */
1009 sigprocmask(SIG_SETMASK, old_set, NULL);
1010 cpu_loop_exit();
1011 }
1012 #elif defined(TARGET_SPARC)
1013 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1014 int is_write, sigset_t *old_set,
1015 void *puc)
1016 {
1017 TranslationBlock *tb;
1018 int ret;
1019
1020 if (cpu_single_env)
1021 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1022 #if defined(DEBUG_SIGNAL)
1023 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1024 pc, address, is_write, *(unsigned long *)old_set);
1025 #endif
1026 /* XXX: locking issue */
1027 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1028 return 1;
1029 }
1030 /* see if it is an MMU fault */
1031 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
1032 if (ret < 0)
1033 return 0; /* not an MMU fault */
1034 if (ret == 0)
1035 return 1; /* the MMU fault was handled without causing real CPU fault */
1036 /* now we have a real cpu fault */
1037 tb = tb_find_pc(pc);
1038 if (tb) {
1039 /* the PC is inside the translated code. It means that we have
1040 a virtual CPU fault */
1041 cpu_restore_state(tb, env, pc, puc);
1042 }
1043 /* we restore the process signal mask as the sigreturn should
1044 do it (XXX: use sigsetjmp) */
1045 sigprocmask(SIG_SETMASK, old_set, NULL);
1046 cpu_loop_exit();
1047 }
1048 #elif defined (TARGET_PPC)
1049 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1050 int is_write, sigset_t *old_set,
1051 void *puc)
1052 {
1053 TranslationBlock *tb;
1054 int ret;
1055
1056 if (cpu_single_env)
1057 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1058 #if defined(DEBUG_SIGNAL)
1059 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1060 pc, address, is_write, *(unsigned long *)old_set);
1061 #endif
1062 /* XXX: locking issue */
1063 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1064 return 1;
1065 }
1066
1067 /* see if it is an MMU fault */
1068 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1069 if (ret < 0)
1070 return 0; /* not an MMU fault */
1071 if (ret == 0)
1072 return 1; /* the MMU fault was handled without causing real CPU fault */
1073
1074 /* now we have a real cpu fault */
1075 tb = tb_find_pc(pc);
1076 if (tb) {
1077 /* the PC is inside the translated code. It means that we have
1078 a virtual CPU fault */
1079 cpu_restore_state(tb, env, pc, puc);
1080 }
1081 if (ret == 1) {
1082 #if 0
1083 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1084 env->nip, env->error_code, tb);
1085 #endif
1086 /* we restore the process signal mask as the sigreturn should
1087 do it (XXX: use sigsetjmp) */
1088 sigprocmask(SIG_SETMASK, old_set, NULL);
1089 do_raise_exception_err(env->exception_index, env->error_code);
1090 } else {
1091 /* activate soft MMU for this block */
1092 cpu_resume_from_signal(env, puc);
1093 }
1094 /* never comes here */
1095 return 1;
1096 }
1097
1098 #elif defined (TARGET_MIPS)
1099 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1100 int is_write, sigset_t *old_set,
1101 void *puc)
1102 {
1103 TranslationBlock *tb;
1104 int ret;
1105
1106 if (cpu_single_env)
1107 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1108 #if defined(DEBUG_SIGNAL)
1109 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1110 pc, address, is_write, *(unsigned long *)old_set);
1111 #endif
1112 /* XXX: locking issue */
1113 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1114 return 1;
1115 }
1116
1117 /* see if it is an MMU fault */
1118 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1119 if (ret < 0)
1120 return 0; /* not an MMU fault */
1121 if (ret == 0)
1122 return 1; /* the MMU fault was handled without causing real CPU fault */
1123
1124 /* now we have a real cpu fault */
1125 tb = tb_find_pc(pc);
1126 if (tb) {
1127 /* the PC is inside the translated code. It means that we have
1128 a virtual CPU fault */
1129 cpu_restore_state(tb, env, pc, puc);
1130 }
1131 if (ret == 1) {
1132 #if 0
1133 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1134 env->nip, env->error_code, tb);
1135 #endif
1136 /* we restore the process signal mask as the sigreturn should
1137 do it (XXX: use sigsetjmp) */
1138 sigprocmask(SIG_SETMASK, old_set, NULL);
1139 do_raise_exception_err(env->exception_index, env->error_code);
1140 } else {
1141 /* activate soft MMU for this block */
1142 cpu_resume_from_signal(env, puc);
1143 }
1144 /* never comes here */
1145 return 1;
1146 }
1147
1148 #elif defined (TARGET_SH4)
1149 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1150 int is_write, sigset_t *old_set,
1151 void *puc)
1152 {
1153 TranslationBlock *tb;
1154 int ret;
1155
1156 if (cpu_single_env)
1157 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1158 #if defined(DEBUG_SIGNAL)
1159 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1160 pc, address, is_write, *(unsigned long *)old_set);
1161 #endif
1162 /* XXX: locking issue */
1163 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1164 return 1;
1165 }
1166
1167 /* see if it is an MMU fault */
1168 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1169 if (ret < 0)
1170 return 0; /* not an MMU fault */
1171 if (ret == 0)
1172 return 1; /* the MMU fault was handled without causing real CPU fault */
1173
1174 /* now we have a real cpu fault */
1175 tb = tb_find_pc(pc);
1176 if (tb) {
1177 /* the PC is inside the translated code. It means that we have
1178 a virtual CPU fault */
1179 cpu_restore_state(tb, env, pc, puc);
1180 }
1181 #if 0
1182 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1183 env->nip, env->error_code, tb);
1184 #endif
1185 /* we restore the process signal mask as the sigreturn should
1186 do it (XXX: use sigsetjmp) */
1187 sigprocmask(SIG_SETMASK, old_set, NULL);
1188 cpu_loop_exit();
1189 /* never comes here */
1190 return 1;
1191 }
1192 #else
1193 #error unsupported target CPU
1194 #endif
1195
1196 #if defined(__i386__)
1197
1198 #if defined(USE_CODE_COPY)
1199 static void cpu_send_trap(unsigned long pc, int trap,
1200 struct ucontext *uc)
1201 {
1202 TranslationBlock *tb;
1203
1204 if (cpu_single_env)
1205 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1206 /* now we have a real cpu fault */
1207 tb = tb_find_pc(pc);
1208 if (tb) {
1209 /* the PC is inside the translated code. It means that we have
1210 a virtual CPU fault */
1211 cpu_restore_state(tb, env, pc, uc);
1212 }
1213 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1214 raise_exception_err(trap, env->error_code);
1215 }
1216 #endif
1217
1218 int cpu_signal_handler(int host_signum, struct siginfo *info,
1219 void *puc)
1220 {
1221 struct ucontext *uc = puc;
1222 unsigned long pc;
1223 int trapno;
1224
1225 #ifndef REG_EIP
1226 /* for glibc 2.1 */
1227 #define REG_EIP EIP
1228 #define REG_ERR ERR
1229 #define REG_TRAPNO TRAPNO
1230 #endif
1231 pc = uc->uc_mcontext.gregs[REG_EIP];
1232 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1233 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1234 if (trapno == 0x00 || trapno == 0x05) {
1235 /* send division by zero or bound exception */
1236 cpu_send_trap(pc, trapno, uc);
1237 return 1;
1238 } else
1239 #endif
1240 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1241 trapno == 0xe ?
1242 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1243 &uc->uc_sigmask, puc);
1244 }
1245
1246 #elif defined(__x86_64__)
1247
1248 int cpu_signal_handler(int host_signum, struct siginfo *info,
1249 void *puc)
1250 {
1251 struct ucontext *uc = puc;
1252 unsigned long pc;
1253
1254 pc = uc->uc_mcontext.gregs[REG_RIP];
1255 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1256 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1257 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1258 &uc->uc_sigmask, puc);
1259 }
1260
1261 #elif defined(__powerpc__)
1262
1263 /***********************************************************************
1264 * signal context platform-specific definitions
1265 * From Wine
1266 */
1267 #ifdef linux
1268 /* All Registers access - only for local access */
1269 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1270 /* Gpr Registers access */
1271 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1272 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1273 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1274 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1275 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1276 # define LR_sig(context) REG_sig(link, context) /* Link register */
1277 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1278 /* Float Registers access */
1279 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1280 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1281 /* Exception Registers access */
1282 # define DAR_sig(context) REG_sig(dar, context)
1283 # define DSISR_sig(context) REG_sig(dsisr, context)
1284 # define TRAP_sig(context) REG_sig(trap, context)
1285 #endif /* linux */
1286
1287 #ifdef __APPLE__
1288 # include <sys/ucontext.h>
1289 typedef struct ucontext SIGCONTEXT;
1290 /* All Registers access - only for local access */
1291 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1292 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1293 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1294 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1295 /* Gpr Registers access */
1296 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1297 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1298 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1299 # define CTR_sig(context) REG_sig(ctr, context)
1300 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1301 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1302 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1303 /* Float Registers access */
1304 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1305 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1306 /* Exception Registers access */
1307 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1308 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1309 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1310 #endif /* __APPLE__ */
1311
1312 int cpu_signal_handler(int host_signum, struct siginfo *info,
1313 void *puc)
1314 {
1315 struct ucontext *uc = puc;
1316 unsigned long pc;
1317 int is_write;
1318
1319 pc = IAR_sig(uc);
1320 is_write = 0;
1321 #if 0
1322 /* ppc 4xx case */
1323 if (DSISR_sig(uc) & 0x00800000)
1324 is_write = 1;
1325 #else
1326 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1327 is_write = 1;
1328 #endif
1329 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1330 is_write, &uc->uc_sigmask, puc);
1331 }
1332
1333 #elif defined(__alpha__)
1334
1335 int cpu_signal_handler(int host_signum, struct siginfo *info,
1336 void *puc)
1337 {
1338 struct ucontext *uc = puc;
1339 uint32_t *pc = uc->uc_mcontext.sc_pc;
1340 uint32_t insn = *pc;
1341 int is_write = 0;
1342
1343 /* XXX: need kernel patch to get write flag faster */
1344 switch (insn >> 26) {
1345 case 0x0d: // stw
1346 case 0x0e: // stb
1347 case 0x0f: // stq_u
1348 case 0x24: // stf
1349 case 0x25: // stg
1350 case 0x26: // sts
1351 case 0x27: // stt
1352 case 0x2c: // stl
1353 case 0x2d: // stq
1354 case 0x2e: // stl_c
1355 case 0x2f: // stq_c
1356 is_write = 1;
1357 }
1358
1359 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1360 is_write, &uc->uc_sigmask, puc);
1361 }
1362 #elif defined(__sparc__)
1363
1364 int cpu_signal_handler(int host_signum, struct siginfo *info,
1365 void *puc)
1366 {
1367 uint32_t *regs = (uint32_t *)(info + 1);
1368 void *sigmask = (regs + 20);
1369 unsigned long pc;
1370 int is_write;
1371 uint32_t insn;
1372
1373 /* XXX: is there a standard glibc define ? */
1374 pc = regs[1];
1375 /* XXX: need kernel patch to get write flag faster */
1376 is_write = 0;
1377 insn = *(uint32_t *)pc;
1378 if ((insn >> 30) == 3) {
1379 switch((insn >> 19) & 0x3f) {
1380 case 0x05: // stb
1381 case 0x06: // sth
1382 case 0x04: // st
1383 case 0x07: // std
1384 case 0x24: // stf
1385 case 0x27: // stdf
1386 case 0x25: // stfsr
1387 is_write = 1;
1388 break;
1389 }
1390 }
1391 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1392 is_write, sigmask, NULL);
1393 }
1394
1395 #elif defined(__arm__)
1396
1397 int cpu_signal_handler(int host_signum, struct siginfo *info,
1398 void *puc)
1399 {
1400 struct ucontext *uc = puc;
1401 unsigned long pc;
1402 int is_write;
1403
1404 pc = uc->uc_mcontext.gregs[R15];
1405 /* XXX: compute is_write */
1406 is_write = 0;
1407 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1408 is_write,
1409 &uc->uc_sigmask, puc);
1410 }
1411
1412 #elif defined(__mc68000)
1413
1414 int cpu_signal_handler(int host_signum, struct siginfo *info,
1415 void *puc)
1416 {
1417 struct ucontext *uc = puc;
1418 unsigned long pc;
1419 int is_write;
1420
1421 pc = uc->uc_mcontext.gregs[16];
1422 /* XXX: compute is_write */
1423 is_write = 0;
1424 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1425 is_write,
1426 &uc->uc_sigmask, puc);
1427 }
1428
1429 #elif defined(__ia64)
1430
1431 #ifndef __ISR_VALID
1432 /* This ought to be in <bits/siginfo.h>... */
1433 # define __ISR_VALID 1
1434 #endif
1435
1436 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1437 {
1438 struct ucontext *uc = puc;
1439 unsigned long ip;
1440 int is_write = 0;
1441
1442 ip = uc->uc_mcontext.sc_ip;
1443 switch (host_signum) {
1444 case SIGILL:
1445 case SIGFPE:
1446 case SIGSEGV:
1447 case SIGBUS:
1448 case SIGTRAP:
1449 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1450 /* ISR.W (write-access) is bit 33: */
1451 is_write = (info->si_isr >> 33) & 1;
1452 break;
1453
1454 default:
1455 break;
1456 }
1457 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1458 is_write,
1459 &uc->uc_sigmask, puc);
1460 }
1461
1462 #elif defined(__s390__)
1463
1464 int cpu_signal_handler(int host_signum, struct siginfo *info,
1465 void *puc)
1466 {
1467 struct ucontext *uc = puc;
1468 unsigned long pc;
1469 int is_write;
1470
1471 pc = uc->uc_mcontext.psw.addr;
1472 /* XXX: compute is_write */
1473 is_write = 0;
1474 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1475 is_write,
1476 &uc->uc_sigmask, puc);
1477 }
1478
1479 #else
1480
1481 #error host CPU specific signal handler needed
1482
1483 #endif
1484
1485 #endif /* !defined(CONFIG_SOFTMMU) */
Samsung s3c2440 and arm920t support for the mini2440 dev board