hw/omap_mmc.c

   1 /*
   2  * OMAP on-chip MMC/SD host emulation.
   3  *
   4  * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21 #include "hw.h"
  22 #include "omap.h"
  23 #include "sd.h"
  24
  25 struct omap_mmc_s {
  26     qemu_irq irq;
  27     qemu_irq *dma;
  28     qemu_irq coverswitch;
  29     omap_clk clk;
  30     SDState *card;
  31     uint16_t last_cmd;
  32     uint16_t sdio;
  33     uint16_t rsp[8];
  34     uint32_t arg;
  35     int lines;
  36     int dw;
  37     int mode;
  38     int enable;
  39     int be;
  40     int rev;
  41     uint16_t status;
  42     uint16_t mask;
  43     uint8_t cto;
  44     uint16_t dto;
  45     int clkdiv;
  46     uint16_t fifo[32];
  47     int fifo_start;
  48     int fifo_len;
  49     uint16_t blen;
  50     uint16_t blen_counter;
  51     uint16_t nblk;
  52     uint16_t nblk_counter;
  53     int tx_dma;
  54     int rx_dma;
  55     int af_level;
  56     int ae_level;
  57
  58     int ddir;
  59     int transfer;
  60
  61     int cdet_wakeup;
  62     int cdet_enable;
  63     int cdet_state;
  64     qemu_irq cdet;
  65 };
  66
  67 static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
  68 {
  69     qemu_set_irq(s->irq, !!(s->status & s->mask));
  70 }
  71
  72 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
  73 {
  74     if (!host->transfer && !host->fifo_len) {
  75         host->status &= 0xf3ff;
  76         return;
  77     }
  78
  79     if (host->fifo_len > host->af_level && host->ddir) {
  80         if (host->rx_dma) {
  81             host->status &= 0xfbff;
  82             qemu_irq_raise(host->dma[1]);
  83         } else
  84             host->status |= 0x0400;
  85     } else {
  86         host->status &= 0xfbff;
  87         qemu_irq_lower(host->dma[1]);
  88     }
  89
  90     if (host->fifo_len < host->ae_level && !host->ddir) {
  91         if (host->tx_dma) {
  92             host->status &= 0xf7ff;
  93             qemu_irq_raise(host->dma[0]);
  94         } else
  95             host->status |= 0x0800;
  96     } else {
  97         qemu_irq_lower(host->dma[0]);
  98         host->status &= 0xf7ff;
  99     }
 100 }
 101
 102 typedef enum {
 103     sd_nore = 0,        /* no response */
 104     sd_r1,              /* normal response command */
 105     sd_r2,              /* CID, CSD registers */
 106     sd_r3,              /* OCR register */
 107     sd_r6 = 6,          /* Published RCA response */
 108     sd_r1b = -1,
 109 } sd_rsp_type_t;
 110
 111 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
 112                 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
 113 {
 114     uint32_t rspstatus, mask;
 115     int rsplen, timeout;
 116     struct sd_request_s request;
 117     uint8_t response[16];
 118
 119     if (init && cmd == 0) {
 120         host->status |= 0x0001;
 121         return;
 122     }
 123
 124     if (resptype == sd_r1 && busy)
 125         resptype = sd_r1b;
 126
 127     if (type == sd_adtc) {
 128         host->fifo_start = 0;
 129         host->fifo_len = 0;
 130         host->transfer = 1;
 131         host->ddir = dir;
 132     } else
 133         host->transfer = 0;
 134     timeout = 0;
 135     mask = 0;
 136     rspstatus = 0;
 137
 138     request.cmd = cmd;
 139     request.arg = host->arg;
 140     request.crc = 0; /* FIXME */
 141
 142     rsplen = sd_do_command(host->card, &request, response);
 143
 144     /* TODO: validate CRCs */
 145     switch (resptype) {
 146     case sd_nore:
 147         rsplen = 0;
 148         break;
 149
 150     case sd_r1:
 151     case sd_r1b:
 152         if (rsplen < 4) {
 153             timeout = 1;
 154             break;
 155         }
 156         rsplen = 4;
 157
 158         mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
 159                 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
 160                 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
 161                 CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
 162                 CID_CSD_OVERWRITE;
 163         if (host->sdio & (1 << 13))
 164             mask |= AKE_SEQ_ERROR;
 165         rspstatus = (response[0] << 24) | (response[1] << 16) |
 166                 (response[2] << 8) | (response[3] << 0);
 167         break;
 168
 169     case sd_r2:
 170         if (rsplen < 16) {
 171             timeout = 1;
 172             break;
 173         }
 174         rsplen = 16;
 175         break;
 176
 177     case sd_r3:
 178         if (rsplen < 4) {
 179             timeout = 1;
 180             break;
 181         }
 182         rsplen = 4;
 183
 184         rspstatus = (response[0] << 24) | (response[1] << 16) |
 185                 (response[2] << 8) | (response[3] << 0);
 186         if (rspstatus & 0x80000000)
 187             host->status &= 0xe000;
 188         else
 189             host->status |= 0x1000;
 190         break;
 191
 192     case sd_r6:
 193         if (rsplen < 4) {
 194             timeout = 1;
 195             break;
 196         }
 197         rsplen = 4;
 198
 199         mask = 0xe000 | AKE_SEQ_ERROR;
 200         rspstatus = (response[2] << 8) | (response[3] << 0);
 201     }
 202
 203     if (rspstatus & mask)
 204         host->status |= 0x4000;
 205     else
 206         host->status &= 0xb000;
 207
 208     if (rsplen)
 209         for (rsplen = 0; rsplen < 8; rsplen ++)
 210             host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
 211                     (response[(rsplen << 1) | 0] << 8);
 212
 213     if (timeout)
 214         host->status |= 0x0080;
 215     else if (cmd == 12)
 216         host->status |= 0x0005; /* Makes it more real */
 217     else
 218         host->status |= 0x0001;
 219 }
 220
 221 static void omap_mmc_transfer(struct omap_mmc_s *host)
 222 {
 223     uint8_t value;
 224
 225     if (!host->transfer)
 226         return;
 227
 228     while (1) {
 229         if (host->ddir) {
 230             if (host->fifo_len > host->af_level)
 231                 break;
 232
 233             value = sd_read_data(host->card);
 234             host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
 235             if (-- host->blen_counter) {
 236                 value = sd_read_data(host->card);
 237                 host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
 238                         value << 8;
 239                 host->blen_counter --;
 240             }
 241
 242             host->fifo_len ++;
 243         } else {
 244             if (!host->fifo_len)
 245                 break;
 246
 247             value = host->fifo[host->fifo_start] & 0xff;
 248             sd_write_data(host->card, value);
 249             if (-- host->blen_counter) {
 250                 value = host->fifo[host->fifo_start] >> 8;
 251                 sd_write_data(host->card, value);
 252                 host->blen_counter --;
 253             }
 254
 255             host->fifo_start ++;
 256             host->fifo_len --;
 257             host->fifo_start &= 31;
 258         }
 259
 260         if (host->blen_counter == 0) {
 261             host->nblk_counter --;
 262             host->blen_counter = host->blen;
 263
 264             if (host->nblk_counter == 0) {
 265                 host->nblk_counter = host->nblk;
 266                 host->transfer = 0;
 267                 host->status |= 0x0008;
 268                 break;
 269             }
 270         }
 271     }
 272 }
 273
 274 static void omap_mmc_update(void *opaque)
 275 {
 276     struct omap_mmc_s *s = opaque;
 277     omap_mmc_transfer(s);
 278     omap_mmc_fifolevel_update(s);
 279     omap_mmc_interrupts_update(s);
 280 }
 281
 282 void omap_mmc_reset(struct omap_mmc_s *host)
 283 {
 284     host->last_cmd = 0;
 285     memset(host->rsp, 0, sizeof(host->rsp));
 286     host->arg = 0;
 287     host->dw = 0;
 288     host->mode = 0;
 289     host->enable = 0;
 290     host->status = 0;
 291     host->mask = 0;
 292     host->cto = 0;
 293     host->dto = 0;
 294     host->fifo_len = 0;
 295     host->blen = 0;
 296     host->blen_counter = 0;
 297     host->nblk = 0;
 298     host->nblk_counter = 0;
 299     host->tx_dma = 0;
 300     host->rx_dma = 0;
 301     host->ae_level = 0x00;
 302     host->af_level = 0x1f;
 303     host->transfer = 0;
 304     host->cdet_wakeup = 0;
 305     host->cdet_enable = 0;
 306     qemu_set_irq(host->coverswitch, host->cdet_state);
 307     host->clkdiv = 0;
 308 }
 309
 310 static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
 311 {
 312     uint16_t i;
 313     struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
 314     offset &= OMAP_MPUI_REG_MASK;
 315
 316     switch (offset) {
 317     case 0x00:  /* MMC_CMD */
 318         return s->last_cmd;
 319
 320     case 0x04:  /* MMC_ARGL */
 321         return s->arg & 0x0000ffff;
 322
 323     case 0x08:  /* MMC_ARGH */
 324         return s->arg >> 16;
 325
 326     case 0x0c:  /* MMC_CON */
 327         return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) |
 328                 (s->be << 10) | s->clkdiv;
 329
 330     case 0x10:  /* MMC_STAT */
 331         return s->status;
 332
 333     case 0x14:  /* MMC_IE */
 334         return s->mask;
 335
 336     case 0x18:  /* MMC_CTO */
 337         return s->cto;
 338
 339     case 0x1c:  /* MMC_DTO */
 340         return s->dto;
 341
 342     case 0x20:  /* MMC_DATA */
 343         /* TODO: support 8-bit access */
 344         i = s->fifo[s->fifo_start];
 345         if (s->fifo_len == 0) {
 346             printf("MMC: FIFO underrun\n");
 347             return i;
 348         }
 349         s->fifo_start ++;
 350         s->fifo_len --;
 351         s->fifo_start &= 31;
 352         omap_mmc_transfer(s);
 353         omap_mmc_fifolevel_update(s);
 354         omap_mmc_interrupts_update(s);
 355         return i;
 356
 357     case 0x24:  /* MMC_BLEN */
 358         return s->blen_counter;
 359
 360     case 0x28:  /* MMC_NBLK */
 361         return s->nblk_counter;
 362
 363     case 0x2c:  /* MMC_BUF */
 364         return (s->rx_dma << 15) | (s->af_level << 8) |
 365             (s->tx_dma << 7) | s->ae_level;
 366
 367     case 0x30:  /* MMC_SPI */
 368         return 0x0000;
 369     case 0x34:  /* MMC_SDIO */
 370         return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
 371     case 0x38:  /* MMC_SYST */
 372         return 0x0000;
 373
 374     case 0x3c:  /* MMC_REV */
 375         return s->rev;
 376
 377     case 0x40:  /* MMC_RSP0 */
 378     case 0x44:  /* MMC_RSP1 */
 379     case 0x48:  /* MMC_RSP2 */
 380     case 0x4c:  /* MMC_RSP3 */
 381     case 0x50:  /* MMC_RSP4 */
 382     case 0x54:  /* MMC_RSP5 */
 383     case 0x58:  /* MMC_RSP6 */
 384     case 0x5c:  /* MMC_RSP7 */
 385         return s->rsp[(offset - 0x40) >> 2];
 386
 387     /* OMAP2-specific */
 388     case 0x60:  /* MMC_IOSR */
 389     case 0x64:  /* MMC_SYSC */
 390         return 0;
 391     case 0x68:  /* MMC_SYSS */
 392         return 1;                                               /* RSTD */
 393     }
 394
 395     OMAP_BAD_REG(offset);
 396     return 0;
 397 }
 398
 399 static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
 400                 uint32_t value)
 401 {
 402     int i;
 403     struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
 404     offset &= OMAP_MPUI_REG_MASK;
 405
 406     switch (offset) {
 407     case 0x00:  /* MMC_CMD */
 408         if (!s->enable)
 409             break;
 410
 411         s->last_cmd = value;
 412         for (i = 0; i < 8; i ++)
 413             s->rsp[i] = 0x0000;
 414         omap_mmc_command(s, value & 63, (value >> 15) & 1,
 415                 (sd_cmd_type_t) ((value >> 12) & 3),
 416                 (value >> 11) & 1,
 417                 (sd_rsp_type_t) ((value >> 8) & 7),
 418                 (value >> 7) & 1);
 419         omap_mmc_update(s);
 420         break;
 421
 422     case 0x04:  /* MMC_ARGL */
 423         s->arg &= 0xffff0000;
 424         s->arg |= 0x0000ffff & value;
 425         break;
 426
 427     case 0x08:  /* MMC_ARGH */
 428         s->arg &= 0x0000ffff;
 429         s->arg |= value << 16;
 430         break;
 431
 432     case 0x0c:  /* MMC_CON */
 433         s->dw = (value >> 15) & 1;
 434         s->mode = (value >> 12) & 3;
 435         s->enable = (value >> 11) & 1;
 436         s->be = (value >> 10) & 1;
 437         s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
 438         if (s->mode != 0)
 439             printf("SD mode %i unimplemented!\n", s->mode);
 440         if (s->be != 0)
 441             printf("SD FIFO byte sex unimplemented!\n");
 442         if (s->dw != 0 && s->lines < 4)
 443             printf("4-bit SD bus enabled\n");
 444         if (!s->enable)
 445             omap_mmc_reset(s);
 446         break;
 447
 448     case 0x10:  /* MMC_STAT */
 449         s->status &= ~value;
 450         omap_mmc_interrupts_update(s);
 451         break;
 452
 453     case 0x14:  /* MMC_IE */
 454         s->mask = value & 0x7fff;
 455         omap_mmc_interrupts_update(s);
 456         break;
 457
 458     case 0x18:  /* MMC_CTO */
 459         s->cto = value & 0xff;
 460         if (s->cto > 0xfd && s->rev <= 1)
 461             printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
 462         break;
 463
 464     case 0x1c:  /* MMC_DTO */
 465         s->dto = value & 0xffff;
 466         break;
 467
 468     case 0x20:  /* MMC_DATA */
 469         /* TODO: support 8-bit access */
 470         if (s->fifo_len == 32)
 471             break;
 472         s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
 473         s->fifo_len ++;
 474         omap_mmc_transfer(s);
 475         omap_mmc_fifolevel_update(s);
 476         omap_mmc_interrupts_update(s);
 477         break;
 478
 479     case 0x24:  /* MMC_BLEN */
 480         s->blen = (value & 0x07ff) + 1;
 481         s->blen_counter = s->blen;
 482         break;
 483
 484     case 0x28:  /* MMC_NBLK */
 485         s->nblk = (value & 0x07ff) + 1;
 486         s->nblk_counter = s->nblk;
 487         s->blen_counter = s->blen;
 488         break;
 489
 490     case 0x2c:  /* MMC_BUF */
 491         s->rx_dma = (value >> 15) & 1;
 492         s->af_level = (value >> 8) & 0x1f;
 493         s->tx_dma = (value >> 7) & 1;
 494         s->ae_level = value & 0x1f;
 495
 496         if (s->rx_dma)
 497             s->status &= 0xfbff;
 498         if (s->tx_dma)
 499             s->status &= 0xf7ff;
 500         omap_mmc_fifolevel_update(s);
 501         omap_mmc_interrupts_update(s);
 502         break;
 503
 504     /* SPI, SDIO and TEST modes unimplemented */
 505     case 0x30:  /* MMC_SPI (OMAP1 only) */
 506         break;
 507     case 0x34:  /* MMC_SDIO */
 508         s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
 509         s->cdet_wakeup = (value >> 9) & 1;
 510         s->cdet_enable = (value >> 2) & 1;
 511         break;
 512     case 0x38:  /* MMC_SYST */
 513         break;
 514
 515     case 0x3c:  /* MMC_REV */
 516     case 0x40:  /* MMC_RSP0 */
 517     case 0x44:  /* MMC_RSP1 */
 518     case 0x48:  /* MMC_RSP2 */
 519     case 0x4c:  /* MMC_RSP3 */
 520     case 0x50:  /* MMC_RSP4 */
 521     case 0x54:  /* MMC_RSP5 */
 522     case 0x58:  /* MMC_RSP6 */
 523     case 0x5c:  /* MMC_RSP7 */
 524         OMAP_RO_REG(offset);
 525         break;
 526
 527     /* OMAP2-specific */
 528     case 0x60:  /* MMC_IOSR */
 529         if (value & 0xf)
 530             printf("MMC: SDIO bits used!\n");
 531         break;
 532     case 0x64:  /* MMC_SYSC */
 533         if (value & (1 << 2))                                   /* SRTS */
 534             omap_mmc_reset(s);
 535         break;
 536     case 0x68:  /* MMC_SYSS */
 537         OMAP_RO_REG(offset);
 538         break;
 539
 540     default:
 541         OMAP_BAD_REG(offset);
 542     }
 543 }
 544
 545 static CPUReadMemoryFunc *omap_mmc_readfn[] = {
 546     omap_badwidth_read16,
 547     omap_mmc_read,
 548     omap_badwidth_read16,
 549 };
 550
 551 static CPUWriteMemoryFunc *omap_mmc_writefn[] = {
 552     omap_badwidth_write16,
 553     omap_mmc_write,
 554     omap_badwidth_write16,
 555 };
 556
 557 static void omap_mmc_cover_cb(void *opaque, int line, int level)
 558 {
 559     struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
 560
 561     if (!host->cdet_state && level) {
 562         host->status |= 0x0002;
 563         omap_mmc_interrupts_update(host);
 564         if (host->cdet_wakeup)
 565             /* TODO: Assert wake-up */;
 566     }
 567
 568     if (host->cdet_state != level) {
 569         qemu_set_irq(host->coverswitch, level);
 570         host->cdet_state = level;
 571     }
 572 }
 573
 574 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
 575                 BlockDriverState *bd,
 576                 qemu_irq irq, qemu_irq dma[], omap_clk clk)
 577 {
 578     int iomemtype;
 579     struct omap_mmc_s *s = (struct omap_mmc_s *)
 580             qemu_mallocz(sizeof(struct omap_mmc_s));
 581
 582     s->irq = irq;
 583     s->dma = dma;
 584     s->clk = clk;
 585     s->lines = 1;       /* TODO: needs to be settable per-board */
 586     s->rev = 1;
 587
 588     omap_mmc_reset(s);
 589
 590     iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
 591                     omap_mmc_writefn, s);
 592     cpu_register_physical_memory(base, 0x800, iomemtype);
 593
 594     /* Instantiate the storage */
 595     s->card = sd_init(bd, 0);
 596
 597     return s;
 598 }
 599
 600 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
 601                 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
 602                 omap_clk fclk, omap_clk iclk)
 603 {
 604     int iomemtype;
 605     struct omap_mmc_s *s = (struct omap_mmc_s *)
 606             qemu_mallocz(sizeof(struct omap_mmc_s));
 607
 608     s->irq = irq;
 609     s->dma = dma;
 610     s->clk = fclk;
 611     s->lines = 4;
 612     s->rev = 2;
 613
 614     omap_mmc_reset(s);
 615
 616     iomemtype = l4_register_io_memory(0, omap_mmc_readfn,
 617                     omap_mmc_writefn, s);
 618     omap_l4_attach(ta, 0, iomemtype);
 619
 620     /* Instantiate the storage */
 621     s->card = sd_init(bd, 0);
 622
 623     s->cdet = qemu_allocate_irqs(omap_mmc_cover_cb, s, 1)[0];
 624     sd_set_cb(s->card, 0, s->cdet);
 625
 626     return s;
 627 }
 628
 629 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
 630 {
 631     if (s->cdet) {
 632         sd_set_cb(s->card, ro, s->cdet);
 633         s->coverswitch = cover;
 634         qemu_set_irq(cover, s->cdet_state);
 635     } else
 636         sd_set_cb(s->card, ro, cover);
 637 }
 638
 639 void omap_mmc_enable(struct omap_mmc_s *s, int enable)
 640 {
 641     sd_enable(s->card, enable);
 642 }