target-i386/cpu.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_I386_H
  21 #define CPU_I386_H
  22
  23 #include "config.h"
  24
  25 #ifdef TARGET_X86_64
  26 #define TARGET_LONG_BITS 64
  27 #else
  28 #define TARGET_LONG_BITS 32
  29 #endif
  30
  31 /* target supports implicit self modifying code */
  32 #define TARGET_HAS_SMC
  33 /* support for self modifying code even if the modified instruction is
  34    close to the modifying instruction */
  35 #define TARGET_HAS_PRECISE_SMC
  36
  37 #define TARGET_HAS_ICE 1
  38
  39 #ifdef TARGET_X86_64
  40 #define ELF_MACHINE     EM_X86_64
  41 #else
  42 #define ELF_MACHINE     EM_386
  43 #endif
  44
  45 #include "cpu-defs.h"
  46
  47 #include "softfloat.h"
  48
  49 #define R_EAX 0
  50 #define R_ECX 1
  51 #define R_EDX 2
  52 #define R_EBX 3
  53 #define R_ESP 4
  54 #define R_EBP 5
  55 #define R_ESI 6
  56 #define R_EDI 7
  57
  58 #define R_AL 0
  59 #define R_CL 1
  60 #define R_DL 2
  61 #define R_BL 3
  62 #define R_AH 4
  63 #define R_CH 5
  64 #define R_DH 6
  65 #define R_BH 7
  66
  67 #define R_ES 0
  68 #define R_CS 1
  69 #define R_SS 2
  70 #define R_DS 3
  71 #define R_FS 4
  72 #define R_GS 5
  73
  74 /* segment descriptor fields */
  75 #define DESC_G_MASK     (1 << 23)
  76 #define DESC_B_SHIFT    22
  77 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  78 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
  79 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
  80 #define DESC_AVL_MASK   (1 << 20)
  81 #define DESC_P_MASK     (1 << 15)
  82 #define DESC_DPL_SHIFT  13
  83 #define DESC_DPL_MASK   (1 << DESC_DPL_SHIFT)
  84 #define DESC_S_MASK     (1 << 12)
  85 #define DESC_TYPE_SHIFT 8
  86 #define DESC_A_MASK     (1 << 8)
  87
  88 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
  89 #define DESC_C_MASK     (1 << 10) /* code: conforming */
  90 #define DESC_R_MASK     (1 << 9)  /* code: readable */
  91
  92 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
  93 #define DESC_W_MASK     (1 << 9)  /* data: writable */
  94
  95 #define DESC_TSS_BUSY_MASK (1 << 9)
  96
  97 /* eflags masks */
  98 #define CC_C    0x0001
  99 #define CC_P    0x0004
 100 #define CC_A    0x0010
 101 #define CC_Z    0x0040
 102 #define CC_S    0x0080
 103 #define CC_O    0x0800
 104
 105 #define TF_SHIFT   8
 106 #define IOPL_SHIFT 12
 107 #define VM_SHIFT   17
 108
 109 #define TF_MASK                 0x00000100
 110 #define IF_MASK                 0x00000200
 111 #define DF_MASK                 0x00000400
 112 #define IOPL_MASK               0x00003000
 113 #define NT_MASK                 0x00004000
 114 #define RF_MASK                 0x00010000
 115 #define VM_MASK                 0x00020000
 116 #define AC_MASK                 0x00040000
 117 #define VIF_MASK                0x00080000
 118 #define VIP_MASK                0x00100000
 119 #define ID_MASK                 0x00200000
 120
 121 /* hidden flags - used internally by qemu to represent additional cpu
 122    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
 123    redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
 124    position to ease oring with eflags. */
 125 /* current cpl */
 126 #define HF_CPL_SHIFT         0
 127 /* true if soft mmu is being used */
 128 #define HF_SOFTMMU_SHIFT     2
 129 /* true if hardware interrupts must be disabled for next instruction */
 130 #define HF_INHIBIT_IRQ_SHIFT 3
 131 /* 16 or 32 segments */
 132 #define HF_CS32_SHIFT        4
 133 #define HF_SS32_SHIFT        5
 134 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
 135 #define HF_ADDSEG_SHIFT      6
 136 /* copy of CR0.PE (protected mode) */
 137 #define HF_PE_SHIFT          7
 138 #define HF_TF_SHIFT          8 /* must be same as eflags */
 139 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
 140 #define HF_EM_SHIFT         10
 141 #define HF_TS_SHIFT         11
 142 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 143 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 144 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
 145 #define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
 146 #define HF_VM_SHIFT         17 /* must be same as eflags */
 147 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 148 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
 149 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
 150
 151 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 152 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
 153 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
 154 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
 155 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
 156 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
 157 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
 158 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
 159 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
 160 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
 161 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
 162 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 163 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 164 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
 165 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 166 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 167 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 168 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
 169 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
 170
 171 /* hflags2 */
 172
 173 #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
 174 #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
 175 #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
 176 #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
 177
 178 #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
 179 #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT)
 180 #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
 181 #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
 182
 183 #define CR0_PE_SHIFT 0
 184 #define CR0_MP_SHIFT 1
 185
 186 #define CR0_PE_MASK  (1 << 0)
 187 #define CR0_MP_MASK  (1 << 1)
 188 #define CR0_EM_MASK  (1 << 2)
 189 #define CR0_TS_MASK  (1 << 3)
 190 #define CR0_ET_MASK  (1 << 4)
 191 #define CR0_NE_MASK  (1 << 5)
 192 #define CR0_WP_MASK  (1 << 16)
 193 #define CR0_AM_MASK  (1 << 18)
 194 #define CR0_PG_MASK  (1 << 31)
 195
 196 #define CR4_VME_MASK  (1 << 0)
 197 #define CR4_PVI_MASK  (1 << 1)
 198 #define CR4_TSD_MASK  (1 << 2)
 199 #define CR4_DE_MASK   (1 << 3)
 200 #define CR4_PSE_MASK  (1 << 4)
 201 #define CR4_PAE_MASK  (1 << 5)
 202 #define CR4_PGE_MASK  (1 << 7)
 203 #define CR4_PCE_MASK  (1 << 8)
 204 #define CR4_OSFXSR_SHIFT 9
 205 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
 206 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
 207
 208 #define DR6_BD          (1 << 13)
 209 #define DR6_BS          (1 << 14)
 210 #define DR6_BT          (1 << 15)
 211 #define DR6_FIXED_1     0xffff0ff0
 212
 213 #define DR7_GD          (1 << 13)
 214 #define DR7_TYPE_SHIFT  16
 215 #define DR7_LEN_SHIFT   18
 216 #define DR7_FIXED_1     0x00000400
 217
 218 #define PG_PRESENT_BIT  0
 219 #define PG_RW_BIT       1
 220 #define PG_USER_BIT     2
 221 #define PG_PWT_BIT      3
 222 #define PG_PCD_BIT      4
 223 #define PG_ACCESSED_BIT 5
 224 #define PG_DIRTY_BIT    6
 225 #define PG_PSE_BIT      7
 226 #define PG_GLOBAL_BIT   8
 227 #define PG_NX_BIT       63
 228
 229 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 230 #define PG_RW_MASK       (1 << PG_RW_BIT)
 231 #define PG_USER_MASK     (1 << PG_USER_BIT)
 232 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 233 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 234 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 235 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 236 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 237 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 238 #define PG_NX_MASK       (1LL << PG_NX_BIT)
 239
 240 #define PG_ERROR_W_BIT     1
 241
 242 #define PG_ERROR_P_MASK    0x01
 243 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 244 #define PG_ERROR_U_MASK    0x04
 245 #define PG_ERROR_RSVD_MASK 0x08
 246 #define PG_ERROR_I_D_MASK  0x10
 247
 248 #define MSR_IA32_TSC                    0x10
 249 #define MSR_IA32_APICBASE               0x1b
 250 #define MSR_IA32_APICBASE_BSP           (1<<8)
 251 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 252 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 253
 254 #define MSR_IA32_SYSENTER_CS            0x174
 255 #define MSR_IA32_SYSENTER_ESP           0x175
 256 #define MSR_IA32_SYSENTER_EIP           0x176
 257
 258 #define MSR_MCG_CAP                     0x179
 259 #define MSR_MCG_STATUS                  0x17a
 260 #define MSR_MCG_CTL                     0x17b
 261
 262 #define MSR_IA32_PERF_STATUS            0x198
 263
 264 #define MSR_PAT                         0x277
 265
 266 #define MSR_EFER                        0xc0000080
 267
 268 #define MSR_EFER_SCE   (1 << 0)
 269 #define MSR_EFER_LME   (1 << 8)
 270 #define MSR_EFER_LMA   (1 << 10)
 271 #define MSR_EFER_NXE   (1 << 11)
 272 #define MSR_EFER_SVME  (1 << 12)
 273 #define MSR_EFER_FFXSR (1 << 14)
 274
 275 #define MSR_STAR                        0xc0000081
 276 #define MSR_LSTAR                       0xc0000082
 277 #define MSR_CSTAR                       0xc0000083
 278 #define MSR_FMASK                       0xc0000084
 279 #define MSR_FSBASE                      0xc0000100
 280 #define MSR_GSBASE                      0xc0000101
 281 #define MSR_KERNELGSBASE                0xc0000102
 282
 283 #define MSR_VM_HSAVE_PA                 0xc0010117
 284
 285 /* cpuid_features bits */
 286 #define CPUID_FP87 (1 << 0)
 287 #define CPUID_VME  (1 << 1)
 288 #define CPUID_DE   (1 << 2)
 289 #define CPUID_PSE  (1 << 3)
 290 #define CPUID_TSC  (1 << 4)
 291 #define CPUID_MSR  (1 << 5)
 292 #define CPUID_PAE  (1 << 6)
 293 #define CPUID_MCE  (1 << 7)
 294 #define CPUID_CX8  (1 << 8)
 295 #define CPUID_APIC (1 << 9)
 296 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
 297 #define CPUID_MTRR (1 << 12)
 298 #define CPUID_PGE  (1 << 13)
 299 #define CPUID_MCA  (1 << 14)
 300 #define CPUID_CMOV (1 << 15)
 301 #define CPUID_PAT  (1 << 16)
 302 #define CPUID_PSE36   (1 << 17)
 303 #define CPUID_PN   (1 << 18)
 304 #define CPUID_CLFLUSH (1 << 19)
 305 #define CPUID_DTS (1 << 21)
 306 #define CPUID_ACPI (1 << 22)
 307 #define CPUID_MMX  (1 << 23)
 308 #define CPUID_FXSR (1 << 24)
 309 #define CPUID_SSE  (1 << 25)
 310 #define CPUID_SSE2 (1 << 26)
 311 #define CPUID_SS (1 << 27)
 312 #define CPUID_HT (1 << 28)
 313 #define CPUID_TM (1 << 29)
 314 #define CPUID_IA64 (1 << 30)
 315 #define CPUID_PBE (1 << 31)
 316
 317 #define CPUID_EXT_SSE3     (1 << 0)
 318 #define CPUID_EXT_DTES64   (1 << 2)
 319 #define CPUID_EXT_MONITOR  (1 << 3)
 320 #define CPUID_EXT_DSCPL    (1 << 4)
 321 #define CPUID_EXT_VMX      (1 << 5)
 322 #define CPUID_EXT_SMX      (1 << 6)
 323 #define CPUID_EXT_EST      (1 << 7)
 324 #define CPUID_EXT_TM2      (1 << 8)
 325 #define CPUID_EXT_SSSE3    (1 << 9)
 326 #define CPUID_EXT_CID      (1 << 10)
 327 #define CPUID_EXT_CX16     (1 << 13)
 328 #define CPUID_EXT_XTPR     (1 << 14)
 329 #define CPUID_EXT_PDCM     (1 << 15)
 330 #define CPUID_EXT_DCA      (1 << 18)
 331 #define CPUID_EXT_SSE41    (1 << 19)
 332 #define CPUID_EXT_SSE42    (1 << 20)
 333 #define CPUID_EXT_X2APIC   (1 << 21)
 334 #define CPUID_EXT_MOVBE    (1 << 22)
 335 #define CPUID_EXT_POPCNT   (1 << 23)
 336 #define CPUID_EXT_XSAVE    (1 << 26)
 337 #define CPUID_EXT_OSXSAVE  (1 << 27)
 338
 339 #define CPUID_EXT2_SYSCALL (1 << 11)
 340 #define CPUID_EXT2_MP      (1 << 19)
 341 #define CPUID_EXT2_NX      (1 << 20)
 342 #define CPUID_EXT2_MMXEXT  (1 << 22)
 343 #define CPUID_EXT2_FFXSR   (1 << 25)
 344 #define CPUID_EXT2_PDPE1GB (1 << 26)
 345 #define CPUID_EXT2_RDTSCP  (1 << 27)
 346 #define CPUID_EXT2_LM      (1 << 29)
 347 #define CPUID_EXT2_3DNOWEXT (1 << 30)
 348 #define CPUID_EXT2_3DNOW   (1 << 31)
 349
 350 #define CPUID_EXT3_LAHF_LM (1 << 0)
 351 #define CPUID_EXT3_CMP_LEG (1 << 1)
 352 #define CPUID_EXT3_SVM     (1 << 2)
 353 #define CPUID_EXT3_EXTAPIC (1 << 3)
 354 #define CPUID_EXT3_CR8LEG  (1 << 4)
 355 #define CPUID_EXT3_ABM     (1 << 5)
 356 #define CPUID_EXT3_SSE4A   (1 << 6)
 357 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
 358 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
 359 #define CPUID_EXT3_OSVW    (1 << 9)
 360 #define CPUID_EXT3_IBS     (1 << 10)
 361 #define CPUID_EXT3_SKINIT  (1 << 12)
 362
 363 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
 364 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
 365 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
 366
 367 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
 368 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
 369 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
 370
 371 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
 372 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
 373
 374 #define EXCP00_DIVZ     0
 375 #define EXCP01_DB       1
 376 #define EXCP02_NMI      2
 377 #define EXCP03_INT3     3
 378 #define EXCP04_INTO     4
 379 #define EXCP05_BOUND    5
 380 #define EXCP06_ILLOP    6
 381 #define EXCP07_PREX     7
 382 #define EXCP08_DBLE     8
 383 #define EXCP09_XERR     9
 384 #define EXCP0A_TSS      10
 385 #define EXCP0B_NOSEG    11
 386 #define EXCP0C_STACK    12
 387 #define EXCP0D_GPF      13
 388 #define EXCP0E_PAGE     14
 389 #define EXCP10_COPR     16
 390 #define EXCP11_ALGN     17
 391 #define EXCP12_MCHK     18
 392
 393 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
 394                                  for syscall instruction */
 395
 396 enum {
 397     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 398     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
 399
 400     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
 401     CC_OP_MULW,
 402     CC_OP_MULL,
 403     CC_OP_MULQ,
 404
 405     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 406     CC_OP_ADDW,
 407     CC_OP_ADDL,
 408     CC_OP_ADDQ,
 409
 410     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 411     CC_OP_ADCW,
 412     CC_OP_ADCL,
 413     CC_OP_ADCQ,
 414
 415     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 416     CC_OP_SUBW,
 417     CC_OP_SUBL,
 418     CC_OP_SUBQ,
 419
 420     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 421     CC_OP_SBBW,
 422     CC_OP_SBBL,
 423     CC_OP_SBBQ,
 424
 425     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 426     CC_OP_LOGICW,
 427     CC_OP_LOGICL,
 428     CC_OP_LOGICQ,
 429
 430     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 431     CC_OP_INCW,
 432     CC_OP_INCL,
 433     CC_OP_INCQ,
 434
 435     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 436     CC_OP_DECW,
 437     CC_OP_DECL,
 438     CC_OP_DECQ,
 439
 440     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
 441     CC_OP_SHLW,
 442     CC_OP_SHLL,
 443     CC_OP_SHLQ,
 444
 445     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 446     CC_OP_SARW,
 447     CC_OP_SARL,
 448     CC_OP_SARQ,
 449
 450     CC_OP_NB,
 451 };
 452
 453 #ifdef FLOATX80
 454 #define USE_X86LDOUBLE
 455 #endif
 456
 457 #ifdef USE_X86LDOUBLE
 458 typedef floatx80 CPU86_LDouble;
 459 #else
 460 typedef float64 CPU86_LDouble;
 461 #endif
 462
 463 typedef struct SegmentCache {
 464     uint32_t selector;
 465     target_ulong base;
 466     uint32_t limit;
 467     uint32_t flags;
 468 } SegmentCache;
 469
 470 typedef union {
 471     uint8_t _b[16];
 472     uint16_t _w[8];
 473     uint32_t _l[4];
 474     uint64_t _q[2];
 475     float32 _s[4];
 476     float64 _d[2];
 477 } XMMReg;
 478
 479 typedef union {
 480     uint8_t _b[8];
 481     uint16_t _w[4];
 482     uint32_t _l[2];
 483     float32 _s[2];
 484     uint64_t q;
 485 } MMXReg;
 486
 487 #ifdef WORDS_BIGENDIAN
 488 #define XMM_B(n) _b[15 - (n)]
 489 #define XMM_W(n) _w[7 - (n)]
 490 #define XMM_L(n) _l[3 - (n)]
 491 #define XMM_S(n) _s[3 - (n)]
 492 #define XMM_Q(n) _q[1 - (n)]
 493 #define XMM_D(n) _d[1 - (n)]
 494
 495 #define MMX_B(n) _b[7 - (n)]
 496 #define MMX_W(n) _w[3 - (n)]
 497 #define MMX_L(n) _l[1 - (n)]
 498 #define MMX_S(n) _s[1 - (n)]
 499 #else
 500 #define XMM_B(n) _b[n]
 501 #define XMM_W(n) _w[n]
 502 #define XMM_L(n) _l[n]
 503 #define XMM_S(n) _s[n]
 504 #define XMM_Q(n) _q[n]
 505 #define XMM_D(n) _d[n]
 506
 507 #define MMX_B(n) _b[n]
 508 #define MMX_W(n) _w[n]
 509 #define MMX_L(n) _l[n]
 510 #define MMX_S(n) _s[n]
 511 #endif
 512 #define MMX_Q(n) q
 513
 514 #ifdef TARGET_X86_64
 515 #define CPU_NB_REGS 16
 516 #else
 517 #define CPU_NB_REGS 8
 518 #endif
 519
 520 #define NB_MMU_MODES 2
 521
 522 typedef struct CPUX86State {
 523     /* standard registers */
 524     target_ulong regs[CPU_NB_REGS];
 525     target_ulong eip;
 526     target_ulong eflags; /* eflags register. During CPU emulation, CC
 527                         flags and DF are set to zero because they are
 528                         stored elsewhere */
 529
 530     /* emulator internal eflags handling */
 531     target_ulong cc_src;
 532     target_ulong cc_dst;
 533     uint32_t cc_op;
 534     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 535     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
 536                         are known at translation time. */
 537     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
 538
 539     /* segments */
 540     SegmentCache segs[6]; /* selector values */
 541     SegmentCache ldt;
 542     SegmentCache tr;
 543     SegmentCache gdt; /* only base and limit are used */
 544     SegmentCache idt; /* only base and limit are used */
 545
 546     target_ulong cr[5]; /* NOTE: cr1 is unused */
 547     uint64_t a20_mask;
 548
 549     /* FPU state */
 550     unsigned int fpstt; /* top of stack index */
 551     unsigned int fpus;
 552     unsigned int fpuc;
 553     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 554     union {
 555 #ifdef USE_X86LDOUBLE
 556         CPU86_LDouble d __attribute__((aligned(16)));
 557 #else
 558         CPU86_LDouble d;
 559 #endif
 560         MMXReg mmx;
 561     } fpregs[8];
 562
 563     /* emulator internal variables */
 564     float_status fp_status;
 565     CPU86_LDouble ft0;
 566
 567     float_status mmx_status; /* for 3DNow! float ops */
 568     float_status sse_status;
 569     uint32_t mxcsr;
 570     XMMReg xmm_regs[CPU_NB_REGS];
 571     XMMReg xmm_t0;
 572     MMXReg mmx_t0;
 573     target_ulong cc_tmp; /* temporary for rcr/rcl */
 574
 575     /* sysenter registers */
 576     uint32_t sysenter_cs;
 577     target_ulong sysenter_esp;
 578     target_ulong sysenter_eip;
 579     uint64_t efer;
 580     uint64_t star;
 581
 582     uint64_t vm_hsave;
 583     uint64_t vm_vmcb;
 584     uint64_t tsc_offset;
 585     uint64_t intercept;
 586     uint16_t intercept_cr_read;
 587     uint16_t intercept_cr_write;
 588     uint16_t intercept_dr_read;
 589     uint16_t intercept_dr_write;
 590     uint32_t intercept_exceptions;
 591     uint8_t v_tpr;
 592
 593 #ifdef TARGET_X86_64
 594     target_ulong lstar;
 595     target_ulong cstar;
 596     target_ulong fmask;
 597     target_ulong kernelgsbase;
 598 #endif
 599
 600     uint64_t tsc;
 601
 602     uint64_t pat;
 603
 604     /* exception/interrupt handling */
 605     int error_code;
 606     int exception_is_int;
 607     target_ulong exception_next_eip;
 608     target_ulong dr[8]; /* debug registers */
 609     union {
 610         CPUBreakpoint *cpu_breakpoint[4];
 611         CPUWatchpoint *cpu_watchpoint[4];
 612     }; /* break/watchpoints for dr[0..3] */
 613     uint32_t smbase;
 614     int old_exception;  /* exception in flight */
 615
 616     CPU_COMMON
 617
 618     /* processor features (e.g. for CPUID insn) */
 619     uint32_t cpuid_level;
 620     uint32_t cpuid_vendor1;
 621     uint32_t cpuid_vendor2;
 622     uint32_t cpuid_vendor3;
 623     uint32_t cpuid_version;
 624     uint32_t cpuid_features;
 625     uint32_t cpuid_ext_features;
 626     uint32_t cpuid_xlevel;
 627     uint32_t cpuid_model[12];
 628     uint32_t cpuid_ext2_features;
 629     uint32_t cpuid_ext3_features;
 630     uint32_t cpuid_apic_id;
 631
 632 #ifdef USE_KQEMU
 633     int kqemu_enabled;
 634     int last_io_time;
 635 #endif
 636
 637     /* For KVM */
 638     uint64_t interrupt_bitmap[256 / 64];
 639
 640     /* in order to simplify APIC support, we leave this pointer to the
 641        user */
 642     struct APICState *apic_state;
 643 } CPUX86State;
 644
 645 CPUX86State *cpu_x86_init(const char *cpu_model);
 646 int cpu_x86_exec(CPUX86State *s);
 647 void cpu_x86_close(CPUX86State *s);
 648 void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
 649                                                  ...));
 650 int cpu_get_pic_interrupt(CPUX86State *s);
 651 /* MSDOS compatibility mode FPU exception support */
 652 void cpu_set_ferr(CPUX86State *s);
 653
 654 /* this function must always be used to load data in the segment
 655    cache: it synchronizes the hflags with the segment cache values */
 656 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
 657                                           int seg_reg, unsigned int selector,
 658                                           target_ulong base,
 659                                           unsigned int limit,
 660                                           unsigned int flags)
 661 {
 662     SegmentCache *sc;
 663     unsigned int new_hflags;
 664
 665     sc = &env->segs[seg_reg];
 666     sc->selector = selector;
 667     sc->base = base;
 668     sc->limit = limit;
 669     sc->flags = flags;
 670
 671     /* update the hidden flags */
 672     {
 673         if (seg_reg == R_CS) {
 674 #ifdef TARGET_X86_64
 675             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
 676                 /* long mode */
 677                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 678                 env->hflags &= ~(HF_ADDSEG_MASK);
 679             } else
 680 #endif
 681             {
 682                 /* legacy / compatibility case */
 683                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
 684                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
 685                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
 686                     new_hflags;
 687             }
 688         }
 689         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
 690             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
 691         if (env->hflags & HF_CS64_MASK) {
 692             /* zero base assumed for DS, ES and SS in long mode */
 693         } else if (!(env->cr[0] & CR0_PE_MASK) ||
 694                    (env->eflags & VM_MASK) ||
 695                    !(env->hflags & HF_CS32_MASK)) {
 696             /* XXX: try to avoid this test. The problem comes from the
 697                fact that is real mode or vm86 mode we only modify the
 698                'base' and 'selector' fields of the segment cache to go
 699                faster. A solution may be to force addseg to one in
 700                translate-i386.c. */
 701             new_hflags |= HF_ADDSEG_MASK;
 702         } else {
 703             new_hflags |= ((env->segs[R_DS].base |
 704                             env->segs[R_ES].base |
 705                             env->segs[R_SS].base) != 0) <<
 706                 HF_ADDSEG_SHIFT;
 707         }
 708         env->hflags = (env->hflags &
 709                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
 710     }
 711 }
 712
 713 /* wrapper, just in case memory mappings must be changed */
 714 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 715 {
 716 #if HF_CPL_MASK == 3
 717     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
 718 #else
 719 #error HF_CPL_MASK is hardcoded
 720 #endif
 721 }
 722
 723 /* op_helper.c */
 724 /* used for debug or cpu save/restore */
 725 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
 726 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
 727
 728 /* cpu-exec.c */
 729 /* the following helpers are only usable in user mode simulation as
 730    they can trigger unexpected exceptions */
 731 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 732 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
 733 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
 734
 735 /* you can call this signal handler from your SIGBUS and SIGSEGV
 736    signal handlers to inform the virtual CPU of exceptions. non zero
 737    is returned if the signal was handled by the virtual CPU.  */
 738 int cpu_x86_signal_handler(int host_signum, void *pinfo,
 739                            void *puc);
 740
 741 /* helper.c */
 742 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
 743                              int is_write, int mmu_idx, int is_softmmu);
 744 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
 745 void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
 746                    uint32_t *eax, uint32_t *ebx,
 747                    uint32_t *ecx, uint32_t *edx);
 748
 749 static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
 750 {
 751     return (dr7 >> (index * 2)) & 3;
 752 }
 753
 754 static inline int hw_breakpoint_type(unsigned long dr7, int index)
 755 {
 756     return (dr7 >> (DR7_TYPE_SHIFT + (index * 2))) & 3;
 757 }
 758
 759 static inline int hw_breakpoint_len(unsigned long dr7, int index)
 760 {
 761     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 2))) & 3);
 762     return (len == 2) ? 8 : len + 1;
 763 }
 764
 765 void hw_breakpoint_insert(CPUX86State *env, int index);
 766 void hw_breakpoint_remove(CPUX86State *env, int index);
 767 int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
 768
 769 /* will be suppressed */
 770 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
 771 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
 772 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
 773
 774 /* hw/apic.c */
 775 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
 776 uint64_t cpu_get_apic_base(CPUX86State *env);
 777 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
 778 #ifndef NO_CPU_IO_DEFS
 779 uint8_t cpu_get_apic_tpr(CPUX86State *env);
 780 #endif
 781
 782 /* hw/pc.c */
 783 void cpu_smm_update(CPUX86State *env);
 784 uint64_t cpu_get_tsc(CPUX86State *env);
 785
 786 /* used to debug */
 787 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 788 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 789
 790 #ifdef USE_KQEMU
 791 static inline int cpu_get_time_fast(void)
 792 {
 793     int low, high;
 794     asm volatile("rdtsc" : "=a" (low), "=d" (high));
 795     return low;
 796 }
 797 #endif
 798
 799 #define TARGET_PAGE_BITS 12
 800
 801 #define CPUState CPUX86State
 802 #define cpu_init cpu_x86_init
 803 #define cpu_exec cpu_x86_exec
 804 #define cpu_gen_code cpu_x86_gen_code
 805 #define cpu_signal_handler cpu_x86_signal_handler
 806 #define cpu_list x86_cpu_list
 807
 808 #define CPU_SAVE_VERSION 7
 809
 810 /* MMU modes definitions */
 811 #define MMU_MODE0_SUFFIX _kernel
 812 #define MMU_MODE1_SUFFIX _user
 813 #define MMU_USER_IDX 1
 814 static inline int cpu_mmu_index (CPUState *env)
 815 {
 816     return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
 817 }
 818
 819 /* translate.c */
 820 void optimize_flags_init(void);
 821
 822 typedef struct CCTable {
 823     int (*compute_all)(void); /* return all the flags */
 824     int (*compute_c)(void);  /* return the C flag */
 825 } CCTable;
 826
 827 #if defined(CONFIG_USER_ONLY)
 828 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 829 {
 830     if (newsp)
 831         env->regs[R_ESP] = newsp;
 832     env->regs[R_EAX] = 0;
 833 }
 834 #endif
 835
 836 #include "cpu-all.h"
 837 #include "exec-all.h"
 838
 839 #include "svm.h"
 840
 841 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 842 {
 843     env->eip = tb->pc - tb->cs_base;
 844 }
 845
 846 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 847                                         target_ulong *cs_base, int *flags)
 848 {
 849     *cs_base = env->segs[R_CS].base;
 850     *pc = *cs_base + env->eip;
 851     *flags = env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
 852 }
 853
 854 #endif /* CPU_I386_H */