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Add vs{l,r} instructions
[qemu/mini2440.git] / target-ppc / op_helper.c
blob55c9c5653872189c793facc6d9ec7c8c4b9d87cf
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <string.h>
21 #include "exec.h"
22 #include "host-utils.h"
23 #include "helper.h"
24
25 #include "helper_regs.h"
26
27 //#define DEBUG_OP
28 //#define DEBUG_EXCEPTIONS
29 //#define DEBUG_SOFTWARE_TLB
30
31 /*****************************************************************************/
32 /* Exceptions processing helpers */
33
34 void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
35 {
36 #if 0
37 printf("Raise exception %3x code : %d\n", exception, error_code);
38 #endif
39 env->exception_index = exception;
40 env->error_code = error_code;
41 cpu_loop_exit();
42 }
43
44 void helper_raise_exception (uint32_t exception)
45 {
46 helper_raise_exception_err(exception, 0);
47 }
48
49 /*****************************************************************************/
50 /* Registers load and stores */
51 target_ulong helper_load_cr (void)
52 {
53 return (env->crf[0] << 28) |
54 (env->crf[1] << 24) |
55 (env->crf[2] << 20) |
56 (env->crf[3] << 16) |
57 (env->crf[4] << 12) |
58 (env->crf[5] << 8) |
59 (env->crf[6] << 4) |
60 (env->crf[7] << 0);
61 }
62
63 void helper_store_cr (target_ulong val, uint32_t mask)
64 {
65 int i, sh;
66
67 for (i = 0, sh = 7; i < 8; i++, sh--) {
68 if (mask & (1 << sh))
69 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
70 }
71 }
72
73 /*****************************************************************************/
74 /* SPR accesses */
75 void helper_load_dump_spr (uint32_t sprn)
76 {
77 if (loglevel != 0) {
78 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
79 sprn, sprn, env->spr[sprn]);
80 }
81 }
82
83 void helper_store_dump_spr (uint32_t sprn)
84 {
85 if (loglevel != 0) {
86 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
87 sprn, sprn, env->spr[sprn]);
88 }
89 }
90
91 target_ulong helper_load_tbl (void)
92 {
93 return cpu_ppc_load_tbl(env);
94 }
95
96 target_ulong helper_load_tbu (void)
97 {
98 return cpu_ppc_load_tbu(env);
99 }
100
101 target_ulong helper_load_atbl (void)
102 {
103 return cpu_ppc_load_atbl(env);
104 }
105
106 target_ulong helper_load_atbu (void)
107 {
108 return cpu_ppc_load_atbu(env);
109 }
110
111 target_ulong helper_load_601_rtcl (void)
112 {
113 return cpu_ppc601_load_rtcl(env);
114 }
115
116 target_ulong helper_load_601_rtcu (void)
117 {
118 return cpu_ppc601_load_rtcu(env);
119 }
120
121 #if !defined(CONFIG_USER_ONLY)
122 #if defined (TARGET_PPC64)
123 void helper_store_asr (target_ulong val)
124 {
125 ppc_store_asr(env, val);
126 }
127 #endif
128
129 void helper_store_sdr1 (target_ulong val)
130 {
131 ppc_store_sdr1(env, val);
132 }
133
134 void helper_store_tbl (target_ulong val)
135 {
136 cpu_ppc_store_tbl(env, val);
137 }
138
139 void helper_store_tbu (target_ulong val)
140 {
141 cpu_ppc_store_tbu(env, val);
142 }
143
144 void helper_store_atbl (target_ulong val)
145 {
146 cpu_ppc_store_atbl(env, val);
147 }
148
149 void helper_store_atbu (target_ulong val)
150 {
151 cpu_ppc_store_atbu(env, val);
152 }
153
154 void helper_store_601_rtcl (target_ulong val)
155 {
156 cpu_ppc601_store_rtcl(env, val);
157 }
158
159 void helper_store_601_rtcu (target_ulong val)
160 {
161 cpu_ppc601_store_rtcu(env, val);
162 }
163
164 target_ulong helper_load_decr (void)
165 {
166 return cpu_ppc_load_decr(env);
167 }
168
169 void helper_store_decr (target_ulong val)
170 {
171 cpu_ppc_store_decr(env, val);
172 }
173
174 void helper_store_hid0_601 (target_ulong val)
175 {
176 target_ulong hid0;
177
178 hid0 = env->spr[SPR_HID0];
179 if ((val ^ hid0) & 0x00000008) {
180 /* Change current endianness */
181 env->hflags &= ~(1 << MSR_LE);
182 env->hflags_nmsr &= ~(1 << MSR_LE);
183 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
184 env->hflags |= env->hflags_nmsr;
185 if (loglevel != 0) {
186 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
187 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
188 }
189 }
190 env->spr[SPR_HID0] = (uint32_t)val;
191 }
192
193 void helper_store_403_pbr (uint32_t num, target_ulong value)
194 {
195 if (likely(env->pb[num] != value)) {
196 env->pb[num] = value;
197 /* Should be optimized */
198 tlb_flush(env, 1);
199 }
200 }
201
202 target_ulong helper_load_40x_pit (void)
203 {
204 return load_40x_pit(env);
205 }
206
207 void helper_store_40x_pit (target_ulong val)
208 {
209 store_40x_pit(env, val);
210 }
211
212 void helper_store_40x_dbcr0 (target_ulong val)
213 {
214 store_40x_dbcr0(env, val);
215 }
216
217 void helper_store_40x_sler (target_ulong val)
218 {
219 store_40x_sler(env, val);
220 }
221
222 void helper_store_booke_tcr (target_ulong val)
223 {
224 store_booke_tcr(env, val);
225 }
226
227 void helper_store_booke_tsr (target_ulong val)
228 {
229 store_booke_tsr(env, val);
230 }
231
232 void helper_store_ibatu (uint32_t nr, target_ulong val)
233 {
234 ppc_store_ibatu(env, nr, val);
235 }
236
237 void helper_store_ibatl (uint32_t nr, target_ulong val)
238 {
239 ppc_store_ibatl(env, nr, val);
240 }
241
242 void helper_store_dbatu (uint32_t nr, target_ulong val)
243 {
244 ppc_store_dbatu(env, nr, val);
245 }
246
247 void helper_store_dbatl (uint32_t nr, target_ulong val)
248 {
249 ppc_store_dbatl(env, nr, val);
250 }
251
252 void helper_store_601_batl (uint32_t nr, target_ulong val)
253 {
254 ppc_store_ibatl_601(env, nr, val);
255 }
256
257 void helper_store_601_batu (uint32_t nr, target_ulong val)
258 {
259 ppc_store_ibatu_601(env, nr, val);
260 }
261 #endif
262
263 /*****************************************************************************/
264 /* Memory load and stores */
265
266 static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
267 {
268 #if defined(TARGET_PPC64)
269 if (!msr_sf)
270 return (uint32_t)(addr + arg);
271 else
272 #endif
273 return addr + arg;
274 }
275
276 void helper_lmw (target_ulong addr, uint32_t reg)
277 {
278 for (; reg < 32; reg++) {
279 if (msr_le)
280 env->gpr[reg] = bswap32(ldl(addr));
281 else
282 env->gpr[reg] = ldl(addr);
283 addr = addr_add(addr, 4);
284 }
285 }
286
287 void helper_stmw (target_ulong addr, uint32_t reg)
288 {
289 for (; reg < 32; reg++) {
290 if (msr_le)
291 stl(addr, bswap32((uint32_t)env->gpr[reg]));
292 else
293 stl(addr, (uint32_t)env->gpr[reg]);
294 addr = addr_add(addr, 4);
295 }
296 }
297
298 void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
299 {
300 int sh;
301 for (; nb > 3; nb -= 4) {
302 env->gpr[reg] = ldl(addr);
303 reg = (reg + 1) % 32;
304 addr = addr_add(addr, 4);
305 }
306 if (unlikely(nb > 0)) {
307 env->gpr[reg] = 0;
308 for (sh = 24; nb > 0; nb--, sh -= 8) {
309 env->gpr[reg] |= ldub(addr) << sh;
310 addr = addr_add(addr, 1);
311 }
312 }
313 }
314 /* PPC32 specification says we must generate an exception if
315 * rA is in the range of registers to be loaded.
316 * In an other hand, IBM says this is valid, but rA won't be loaded.
317 * For now, I'll follow the spec...
318 */
319 void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
320 {
321 if (likely(xer_bc != 0)) {
322 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
323 (reg < rb && (reg + xer_bc) > rb))) {
324 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
325 POWERPC_EXCP_INVAL |
326 POWERPC_EXCP_INVAL_LSWX);
327 } else {
328 helper_lsw(addr, xer_bc, reg);
329 }
330 }
331 }
332
333 void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
334 {
335 int sh;
336 for (; nb > 3; nb -= 4) {
337 stl(addr, env->gpr[reg]);
338 reg = (reg + 1) % 32;
339 addr = addr_add(addr, 4);
340 }
341 if (unlikely(nb > 0)) {
342 for (sh = 24; nb > 0; nb--, sh -= 8) {
343 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
344 addr = addr_add(addr, 1);
345 }
346 }
347 }
348
349 static void do_dcbz(target_ulong addr, int dcache_line_size)
350 {
351 addr &= ~(dcache_line_size - 1);
352 int i;
353 for (i = 0 ; i < dcache_line_size ; i += 4) {
354 stl(addr + i , 0);
355 }
356 if (env->reserve == addr)
357 env->reserve = (target_ulong)-1ULL;
358 }
359
360 void helper_dcbz(target_ulong addr)
361 {
362 do_dcbz(addr, env->dcache_line_size);
363 }
364
365 void helper_dcbz_970(target_ulong addr)
366 {
367 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
368 do_dcbz(addr, 32);
369 else
370 do_dcbz(addr, env->dcache_line_size);
371 }
372
373 void helper_icbi(target_ulong addr)
374 {
375 uint32_t tmp;
376
377 addr &= ~(env->dcache_line_size - 1);
378 /* Invalidate one cache line :
379 * PowerPC specification says this is to be treated like a load
380 * (not a fetch) by the MMU. To be sure it will be so,
381 * do the load "by hand".
382 */
383 tmp = ldl(addr);
384 tb_invalidate_page_range(addr, addr + env->icache_line_size);
385 }
386
387 // XXX: to be tested
388 target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
389 {
390 int i, c, d;
391 d = 24;
392 for (i = 0; i < xer_bc; i++) {
393 c = ldub(addr);
394 addr = addr_add(addr, 1);
395 /* ra (if not 0) and rb are never modified */
396 if (likely(reg != rb && (ra == 0 || reg != ra))) {
397 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
398 }
399 if (unlikely(c == xer_cmp))
400 break;
401 if (likely(d != 0)) {
402 d -= 8;
403 } else {
404 d = 24;
405 reg++;
406 reg = reg & 0x1F;
407 }
408 }
409 return i;
410 }
411
412 /*****************************************************************************/
413 /* Fixed point operations helpers */
414 #if defined(TARGET_PPC64)
415
416 /* multiply high word */
417 uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
418 {
419 uint64_t tl, th;
420
421 muls64(&tl, &th, arg1, arg2);
422 return th;
423 }
424
425 /* multiply high word unsigned */
426 uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
427 {
428 uint64_t tl, th;
429
430 mulu64(&tl, &th, arg1, arg2);
431 return th;
432 }
433
434 uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
435 {
436 int64_t th;
437 uint64_t tl;
438
439 muls64(&tl, (uint64_t *)&th, arg1, arg2);
440 /* If th != 0 && th != -1, then we had an overflow */
441 if (likely((uint64_t)(th + 1) <= 1)) {
442 env->xer &= ~(1 << XER_OV);
443 } else {
444 env->xer |= (1 << XER_OV) | (1 << XER_SO);
445 }
446 return (int64_t)tl;
447 }
448 #endif
449
450 target_ulong helper_cntlzw (target_ulong t)
451 {
452 return clz32(t);
453 }
454
455 #if defined(TARGET_PPC64)
456 target_ulong helper_cntlzd (target_ulong t)
457 {
458 return clz64(t);
459 }
460 #endif
461
462 /* shift right arithmetic helper */
463 target_ulong helper_sraw (target_ulong value, target_ulong shift)
464 {
465 int32_t ret;
466
467 if (likely(!(shift & 0x20))) {
468 if (likely((uint32_t)shift != 0)) {
469 shift &= 0x1f;
470 ret = (int32_t)value >> shift;
471 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
472 env->xer &= ~(1 << XER_CA);
473 } else {
474 env->xer |= (1 << XER_CA);
475 }
476 } else {
477 ret = (int32_t)value;
478 env->xer &= ~(1 << XER_CA);
479 }
480 } else {
481 ret = (int32_t)value >> 31;
482 if (ret) {
483 env->xer |= (1 << XER_CA);
484 } else {
485 env->xer &= ~(1 << XER_CA);
486 }
487 }
488 return (target_long)ret;
489 }
490
491 #if defined(TARGET_PPC64)
492 target_ulong helper_srad (target_ulong value, target_ulong shift)
493 {
494 int64_t ret;
495
496 if (likely(!(shift & 0x40))) {
497 if (likely((uint64_t)shift != 0)) {
498 shift &= 0x3f;
499 ret = (int64_t)value >> shift;
500 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
501 env->xer &= ~(1 << XER_CA);
502 } else {
503 env->xer |= (1 << XER_CA);
504 }
505 } else {
506 ret = (int64_t)value;
507 env->xer &= ~(1 << XER_CA);
508 }
509 } else {
510 ret = (int64_t)value >> 63;
511 if (ret) {
512 env->xer |= (1 << XER_CA);
513 } else {
514 env->xer &= ~(1 << XER_CA);
515 }
516 }
517 return ret;
518 }
519 #endif
520
521 target_ulong helper_popcntb (target_ulong val)
522 {
523 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
524 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
525 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
526 return val;
527 }
528
529 #if defined(TARGET_PPC64)
530 target_ulong helper_popcntb_64 (target_ulong val)
531 {
532 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
533 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
534 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
535 return val;
536 }
537 #endif
538
539 /*****************************************************************************/
540 /* Floating point operations helpers */
541 uint64_t helper_float32_to_float64(uint32_t arg)
542 {
543 CPU_FloatU f;
544 CPU_DoubleU d;
545 f.l = arg;
546 d.d = float32_to_float64(f.f, &env->fp_status);
547 return d.ll;
548 }
549
550 uint32_t helper_float64_to_float32(uint64_t arg)
551 {
552 CPU_FloatU f;
553 CPU_DoubleU d;
554 d.ll = arg;
555 f.f = float64_to_float32(d.d, &env->fp_status);
556 return f.l;
557 }
558
559 static always_inline int isden (float64 d)
560 {
561 CPU_DoubleU u;
562
563 u.d = d;
564
565 return ((u.ll >> 52) & 0x7FF) == 0;
566 }
567
568 uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
569 {
570 CPU_DoubleU farg;
571 int isneg;
572 int ret;
573 farg.ll = arg;
574 isneg = float64_is_neg(farg.d);
575 if (unlikely(float64_is_nan(farg.d))) {
576 if (float64_is_signaling_nan(farg.d)) {
577 /* Signaling NaN: flags are undefined */
578 ret = 0x00;
579 } else {
580 /* Quiet NaN */
581 ret = 0x11;
582 }
583 } else if (unlikely(float64_is_infinity(farg.d))) {
584 /* +/- infinity */
585 if (isneg)
586 ret = 0x09;
587 else
588 ret = 0x05;
589 } else {
590 if (float64_is_zero(farg.d)) {
591 /* +/- zero */
592 if (isneg)
593 ret = 0x12;
594 else
595 ret = 0x02;
596 } else {
597 if (isden(farg.d)) {
598 /* Denormalized numbers */
599 ret = 0x10;
600 } else {
601 /* Normalized numbers */
602 ret = 0x00;
603 }
604 if (isneg) {
605 ret |= 0x08;
606 } else {
607 ret |= 0x04;
608 }
609 }
610 }
611 if (set_fprf) {
612 /* We update FPSCR_FPRF */
613 env->fpscr &= ~(0x1F << FPSCR_FPRF);
614 env->fpscr |= ret << FPSCR_FPRF;
615 }
616 /* We just need fpcc to update Rc1 */
617 return ret & 0xF;
618 }
619
620 /* Floating-point invalid operations exception */
621 static always_inline uint64_t fload_invalid_op_excp (int op)
622 {
623 uint64_t ret = 0;
624 int ve;
625
626 ve = fpscr_ve;
627 switch (op) {
628 case POWERPC_EXCP_FP_VXSNAN:
629 env->fpscr |= 1 << FPSCR_VXSNAN;
630 break;
631 case POWERPC_EXCP_FP_VXSOFT:
632 env->fpscr |= 1 << FPSCR_VXSOFT;
633 break;
634 case POWERPC_EXCP_FP_VXISI:
635 /* Magnitude subtraction of infinities */
636 env->fpscr |= 1 << FPSCR_VXISI;
637 goto update_arith;
638 case POWERPC_EXCP_FP_VXIDI:
639 /* Division of infinity by infinity */
640 env->fpscr |= 1 << FPSCR_VXIDI;
641 goto update_arith;
642 case POWERPC_EXCP_FP_VXZDZ:
643 /* Division of zero by zero */
644 env->fpscr |= 1 << FPSCR_VXZDZ;
645 goto update_arith;
646 case POWERPC_EXCP_FP_VXIMZ:
647 /* Multiplication of zero by infinity */
648 env->fpscr |= 1 << FPSCR_VXIMZ;
649 goto update_arith;
650 case POWERPC_EXCP_FP_VXVC:
651 /* Ordered comparison of NaN */
652 env->fpscr |= 1 << FPSCR_VXVC;
653 env->fpscr &= ~(0xF << FPSCR_FPCC);
654 env->fpscr |= 0x11 << FPSCR_FPCC;
655 /* We must update the target FPR before raising the exception */
656 if (ve != 0) {
657 env->exception_index = POWERPC_EXCP_PROGRAM;
658 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
659 /* Update the floating-point enabled exception summary */
660 env->fpscr |= 1 << FPSCR_FEX;
661 /* Exception is differed */
662 ve = 0;
663 }
664 break;
665 case POWERPC_EXCP_FP_VXSQRT:
666 /* Square root of a negative number */
667 env->fpscr |= 1 << FPSCR_VXSQRT;
668 update_arith:
669 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
670 if (ve == 0) {
671 /* Set the result to quiet NaN */
672 ret = 0xFFF8000000000000ULL;
673 env->fpscr &= ~(0xF << FPSCR_FPCC);
674 env->fpscr |= 0x11 << FPSCR_FPCC;
675 }
676 break;
677 case POWERPC_EXCP_FP_VXCVI:
678 /* Invalid conversion */
679 env->fpscr |= 1 << FPSCR_VXCVI;
680 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
681 if (ve == 0) {
682 /* Set the result to quiet NaN */
683 ret = 0xFFF8000000000000ULL;
684 env->fpscr &= ~(0xF << FPSCR_FPCC);
685 env->fpscr |= 0x11 << FPSCR_FPCC;
686 }
687 break;
688 }
689 /* Update the floating-point invalid operation summary */
690 env->fpscr |= 1 << FPSCR_VX;
691 /* Update the floating-point exception summary */
692 env->fpscr |= 1 << FPSCR_FX;
693 if (ve != 0) {
694 /* Update the floating-point enabled exception summary */
695 env->fpscr |= 1 << FPSCR_FEX;
696 if (msr_fe0 != 0 || msr_fe1 != 0)
697 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
698 }
699 return ret;
700 }
701
702 static always_inline void float_zero_divide_excp (void)
703 {
704 env->fpscr |= 1 << FPSCR_ZX;
705 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
706 /* Update the floating-point exception summary */
707 env->fpscr |= 1 << FPSCR_FX;
708 if (fpscr_ze != 0) {
709 /* Update the floating-point enabled exception summary */
710 env->fpscr |= 1 << FPSCR_FEX;
711 if (msr_fe0 != 0 || msr_fe1 != 0) {
712 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
713 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
714 }
715 }
716 }
717
718 static always_inline void float_overflow_excp (void)
719 {
720 env->fpscr |= 1 << FPSCR_OX;
721 /* Update the floating-point exception summary */
722 env->fpscr |= 1 << FPSCR_FX;
723 if (fpscr_oe != 0) {
724 /* XXX: should adjust the result */
725 /* Update the floating-point enabled exception summary */
726 env->fpscr |= 1 << FPSCR_FEX;
727 /* We must update the target FPR before raising the exception */
728 env->exception_index = POWERPC_EXCP_PROGRAM;
729 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
730 } else {
731 env->fpscr |= 1 << FPSCR_XX;
732 env->fpscr |= 1 << FPSCR_FI;
733 }
734 }
735
736 static always_inline void float_underflow_excp (void)
737 {
738 env->fpscr |= 1 << FPSCR_UX;
739 /* Update the floating-point exception summary */
740 env->fpscr |= 1 << FPSCR_FX;
741 if (fpscr_ue != 0) {
742 /* XXX: should adjust the result */
743 /* Update the floating-point enabled exception summary */
744 env->fpscr |= 1 << FPSCR_FEX;
745 /* We must update the target FPR before raising the exception */
746 env->exception_index = POWERPC_EXCP_PROGRAM;
747 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
748 }
749 }
750
751 static always_inline void float_inexact_excp (void)
752 {
753 env->fpscr |= 1 << FPSCR_XX;
754 /* Update the floating-point exception summary */
755 env->fpscr |= 1 << FPSCR_FX;
756 if (fpscr_xe != 0) {
757 /* Update the floating-point enabled exception summary */
758 env->fpscr |= 1 << FPSCR_FEX;
759 /* We must update the target FPR before raising the exception */
760 env->exception_index = POWERPC_EXCP_PROGRAM;
761 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
762 }
763 }
764
765 static always_inline void fpscr_set_rounding_mode (void)
766 {
767 int rnd_type;
768
769 /* Set rounding mode */
770 switch (fpscr_rn) {
771 case 0:
772 /* Best approximation (round to nearest) */
773 rnd_type = float_round_nearest_even;
774 break;
775 case 1:
776 /* Smaller magnitude (round toward zero) */
777 rnd_type = float_round_to_zero;
778 break;
779 case 2:
780 /* Round toward +infinite */
781 rnd_type = float_round_up;
782 break;
783 default:
784 case 3:
785 /* Round toward -infinite */
786 rnd_type = float_round_down;
787 break;
788 }
789 set_float_rounding_mode(rnd_type, &env->fp_status);
790 }
791
792 void helper_fpscr_clrbit (uint32_t bit)
793 {
794 int prev;
795
796 prev = (env->fpscr >> bit) & 1;
797 env->fpscr &= ~(1 << bit);
798 if (prev == 1) {
799 switch (bit) {
800 case FPSCR_RN1:
801 case FPSCR_RN:
802 fpscr_set_rounding_mode();
803 break;
804 default:
805 break;
806 }
807 }
808 }
809
810 void helper_fpscr_setbit (uint32_t bit)
811 {
812 int prev;
813
814 prev = (env->fpscr >> bit) & 1;
815 env->fpscr |= 1 << bit;
816 if (prev == 0) {
817 switch (bit) {
818 case FPSCR_VX:
819 env->fpscr |= 1 << FPSCR_FX;
820 if (fpscr_ve)
821 goto raise_ve;
822 case FPSCR_OX:
823 env->fpscr |= 1 << FPSCR_FX;
824 if (fpscr_oe)
825 goto raise_oe;
826 break;
827 case FPSCR_UX:
828 env->fpscr |= 1 << FPSCR_FX;
829 if (fpscr_ue)
830 goto raise_ue;
831 break;
832 case FPSCR_ZX:
833 env->fpscr |= 1 << FPSCR_FX;
834 if (fpscr_ze)
835 goto raise_ze;
836 break;
837 case FPSCR_XX:
838 env->fpscr |= 1 << FPSCR_FX;
839 if (fpscr_xe)
840 goto raise_xe;
841 break;
842 case FPSCR_VXSNAN:
843 case FPSCR_VXISI:
844 case FPSCR_VXIDI:
845 case FPSCR_VXZDZ:
846 case FPSCR_VXIMZ:
847 case FPSCR_VXVC:
848 case FPSCR_VXSOFT:
849 case FPSCR_VXSQRT:
850 case FPSCR_VXCVI:
851 env->fpscr |= 1 << FPSCR_VX;
852 env->fpscr |= 1 << FPSCR_FX;
853 if (fpscr_ve != 0)
854 goto raise_ve;
855 break;
856 case FPSCR_VE:
857 if (fpscr_vx != 0) {
858 raise_ve:
859 env->error_code = POWERPC_EXCP_FP;
860 if (fpscr_vxsnan)
861 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
862 if (fpscr_vxisi)
863 env->error_code |= POWERPC_EXCP_FP_VXISI;
864 if (fpscr_vxidi)
865 env->error_code |= POWERPC_EXCP_FP_VXIDI;
866 if (fpscr_vxzdz)
867 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
868 if (fpscr_vximz)
869 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
870 if (fpscr_vxvc)
871 env->error_code |= POWERPC_EXCP_FP_VXVC;
872 if (fpscr_vxsoft)
873 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
874 if (fpscr_vxsqrt)
875 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
876 if (fpscr_vxcvi)
877 env->error_code |= POWERPC_EXCP_FP_VXCVI;
878 goto raise_excp;
879 }
880 break;
881 case FPSCR_OE:
882 if (fpscr_ox != 0) {
883 raise_oe:
884 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
885 goto raise_excp;
886 }
887 break;
888 case FPSCR_UE:
889 if (fpscr_ux != 0) {
890 raise_ue:
891 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
892 goto raise_excp;
893 }
894 break;
895 case FPSCR_ZE:
896 if (fpscr_zx != 0) {
897 raise_ze:
898 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
899 goto raise_excp;
900 }
901 break;
902 case FPSCR_XE:
903 if (fpscr_xx != 0) {
904 raise_xe:
905 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
906 goto raise_excp;
907 }
908 break;
909 case FPSCR_RN1:
910 case FPSCR_RN:
911 fpscr_set_rounding_mode();
912 break;
913 default:
914 break;
915 raise_excp:
916 /* Update the floating-point enabled exception summary */
917 env->fpscr |= 1 << FPSCR_FEX;
918 /* We have to update Rc1 before raising the exception */
919 env->exception_index = POWERPC_EXCP_PROGRAM;
920 break;
921 }
922 }
923 }
924
925 void helper_store_fpscr (uint64_t arg, uint32_t mask)
926 {
927 /*
928 * We use only the 32 LSB of the incoming fpr
929 */
930 uint32_t prev, new;
931 int i;
932
933 prev = env->fpscr;
934 new = (uint32_t)arg;
935 new &= ~0x60000000;
936 new |= prev & 0x60000000;
937 for (i = 0; i < 8; i++) {
938 if (mask & (1 << i)) {
939 env->fpscr &= ~(0xF << (4 * i));
940 env->fpscr |= new & (0xF << (4 * i));
941 }
942 }
943 /* Update VX and FEX */
944 if (fpscr_ix != 0)
945 env->fpscr |= 1 << FPSCR_VX;
946 else
947 env->fpscr &= ~(1 << FPSCR_VX);
948 if ((fpscr_ex & fpscr_eex) != 0) {
949 env->fpscr |= 1 << FPSCR_FEX;
950 env->exception_index = POWERPC_EXCP_PROGRAM;
951 /* XXX: we should compute it properly */
952 env->error_code = POWERPC_EXCP_FP;
953 }
954 else
955 env->fpscr &= ~(1 << FPSCR_FEX);
956 fpscr_set_rounding_mode();
957 }
958
959 void helper_float_check_status (void)
960 {
961 #ifdef CONFIG_SOFTFLOAT
962 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
963 (env->error_code & POWERPC_EXCP_FP)) {
964 /* Differred floating-point exception after target FPR update */
965 if (msr_fe0 != 0 || msr_fe1 != 0)
966 helper_raise_exception_err(env->exception_index, env->error_code);
967 } else {
968 int status = get_float_exception_flags(&env->fp_status);
969 if (status & float_flag_divbyzero) {
970 float_zero_divide_excp();
971 } else if (status & float_flag_overflow) {
972 float_overflow_excp();
973 } else if (status & float_flag_underflow) {
974 float_underflow_excp();
975 } else if (status & float_flag_inexact) {
976 float_inexact_excp();
977 }
978 }
979 #else
980 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
981 (env->error_code & POWERPC_EXCP_FP)) {
982 /* Differred floating-point exception after target FPR update */
983 if (msr_fe0 != 0 || msr_fe1 != 0)
984 helper_raise_exception_err(env->exception_index, env->error_code);
985 }
986 #endif
987 }
988
989 #ifdef CONFIG_SOFTFLOAT
990 void helper_reset_fpstatus (void)
991 {
992 set_float_exception_flags(0, &env->fp_status);
993 }
994 #endif
995
996 /* fadd - fadd. */
997 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
998 {
999 CPU_DoubleU farg1, farg2;
1000
1001 farg1.ll = arg1;
1002 farg2.ll = arg2;
1003 #if USE_PRECISE_EMULATION
1004 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1005 float64_is_signaling_nan(farg2.d))) {
1006 /* sNaN addition */
1007 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1008 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1009 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
1010 /* Magnitude subtraction of infinities */
1011 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1012 } else {
1013 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1014 }
1015 #else
1016 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1017 #endif
1018 return farg1.ll;
1019 }
1020
1021 /* fsub - fsub. */
1022 uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
1023 {
1024 CPU_DoubleU farg1, farg2;
1025
1026 farg1.ll = arg1;
1027 farg2.ll = arg2;
1028 #if USE_PRECISE_EMULATION
1029 {
1030 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1031 float64_is_signaling_nan(farg2.d))) {
1032 /* sNaN subtraction */
1033 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1034 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1035 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
1036 /* Magnitude subtraction of infinities */
1037 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1038 } else {
1039 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1040 }
1041 }
1042 #else
1043 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1044 #endif
1045 return farg1.ll;
1046 }
1047
1048 /* fmul - fmul. */
1049 uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
1050 {
1051 CPU_DoubleU farg1, farg2;
1052
1053 farg1.ll = arg1;
1054 farg2.ll = arg2;
1055 #if USE_PRECISE_EMULATION
1056 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1057 float64_is_signaling_nan(farg2.d))) {
1058 /* sNaN multiplication */
1059 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1060 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1061 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1062 /* Multiplication of zero by infinity */
1063 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1064 } else {
1065 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1066 }
1067 #else
1068 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1069 #endif
1070 return farg1.ll;
1071 }
1072
1073 /* fdiv - fdiv. */
1074 uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
1075 {
1076 CPU_DoubleU farg1, farg2;
1077
1078 farg1.ll = arg1;
1079 farg2.ll = arg2;
1080 #if USE_PRECISE_EMULATION
1081 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1082 float64_is_signaling_nan(farg2.d))) {
1083 /* sNaN division */
1084 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1085 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d))) {
1086 /* Division of infinity by infinity */
1087 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
1088 } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
1089 /* Division of zero by zero */
1090 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
1091 } else {
1092 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1093 }
1094 #else
1095 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1096 #endif
1097 return farg1.ll;
1098 }
1099
1100 /* fabs */
1101 uint64_t helper_fabs (uint64_t arg)
1102 {
1103 CPU_DoubleU farg;
1104
1105 farg.ll = arg;
1106 farg.d = float64_abs(farg.d);
1107 return farg.ll;
1108 }
1109
1110 /* fnabs */
1111 uint64_t helper_fnabs (uint64_t arg)
1112 {
1113 CPU_DoubleU farg;
1114
1115 farg.ll = arg;
1116 farg.d = float64_abs(farg.d);
1117 farg.d = float64_chs(farg.d);
1118 return farg.ll;
1119 }
1120
1121 /* fneg */
1122 uint64_t helper_fneg (uint64_t arg)
1123 {
1124 CPU_DoubleU farg;
1125
1126 farg.ll = arg;
1127 farg.d = float64_chs(farg.d);
1128 return farg.ll;
1129 }
1130
1131 /* fctiw - fctiw. */
1132 uint64_t helper_fctiw (uint64_t arg)
1133 {
1134 CPU_DoubleU farg;
1135 farg.ll = arg;
1136
1137 if (unlikely(float64_is_signaling_nan(farg.d))) {
1138 /* sNaN conversion */
1139 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1140 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1141 /* qNan / infinity conversion */
1142 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1143 } else {
1144 farg.ll = float64_to_int32(farg.d, &env->fp_status);
1145 #if USE_PRECISE_EMULATION
1146 /* XXX: higher bits are not supposed to be significant.
1147 * to make tests easier, return the same as a real PowerPC 750
1148 */
1149 farg.ll |= 0xFFF80000ULL << 32;
1150 #endif
1151 }
1152 return farg.ll;
1153 }
1154
1155 /* fctiwz - fctiwz. */
1156 uint64_t helper_fctiwz (uint64_t arg)
1157 {
1158 CPU_DoubleU farg;
1159 farg.ll = arg;
1160
1161 if (unlikely(float64_is_signaling_nan(farg.d))) {
1162 /* sNaN conversion */
1163 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1164 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1165 /* qNan / infinity conversion */
1166 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1167 } else {
1168 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
1169 #if USE_PRECISE_EMULATION
1170 /* XXX: higher bits are not supposed to be significant.
1171 * to make tests easier, return the same as a real PowerPC 750
1172 */
1173 farg.ll |= 0xFFF80000ULL << 32;
1174 #endif
1175 }
1176 return farg.ll;
1177 }
1178
1179 #if defined(TARGET_PPC64)
1180 /* fcfid - fcfid. */
1181 uint64_t helper_fcfid (uint64_t arg)
1182 {
1183 CPU_DoubleU farg;
1184 farg.d = int64_to_float64(arg, &env->fp_status);
1185 return farg.ll;
1186 }
1187
1188 /* fctid - fctid. */
1189 uint64_t helper_fctid (uint64_t arg)
1190 {
1191 CPU_DoubleU farg;
1192 farg.ll = arg;
1193
1194 if (unlikely(float64_is_signaling_nan(farg.d))) {
1195 /* sNaN conversion */
1196 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1197 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1198 /* qNan / infinity conversion */
1199 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1200 } else {
1201 farg.ll = float64_to_int64(farg.d, &env->fp_status);
1202 }
1203 return farg.ll;
1204 }
1205
1206 /* fctidz - fctidz. */
1207 uint64_t helper_fctidz (uint64_t arg)
1208 {
1209 CPU_DoubleU farg;
1210 farg.ll = arg;
1211
1212 if (unlikely(float64_is_signaling_nan(farg.d))) {
1213 /* sNaN conversion */
1214 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1215 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1216 /* qNan / infinity conversion */
1217 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1218 } else {
1219 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
1220 }
1221 return farg.ll;
1222 }
1223
1224 #endif
1225
1226 static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
1227 {
1228 CPU_DoubleU farg;
1229 farg.ll = arg;
1230
1231 if (unlikely(float64_is_signaling_nan(farg.d))) {
1232 /* sNaN round */
1233 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1234 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
1235 /* qNan / infinity round */
1236 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1237 } else {
1238 set_float_rounding_mode(rounding_mode, &env->fp_status);
1239 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
1240 /* Restore rounding mode from FPSCR */
1241 fpscr_set_rounding_mode();
1242 }
1243 return farg.ll;
1244 }
1245
1246 uint64_t helper_frin (uint64_t arg)
1247 {
1248 return do_fri(arg, float_round_nearest_even);
1249 }
1250
1251 uint64_t helper_friz (uint64_t arg)
1252 {
1253 return do_fri(arg, float_round_to_zero);
1254 }
1255
1256 uint64_t helper_frip (uint64_t arg)
1257 {
1258 return do_fri(arg, float_round_up);
1259 }
1260
1261 uint64_t helper_frim (uint64_t arg)
1262 {
1263 return do_fri(arg, float_round_down);
1264 }
1265
1266 /* fmadd - fmadd. */
1267 uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1268 {
1269 CPU_DoubleU farg1, farg2, farg3;
1270
1271 farg1.ll = arg1;
1272 farg2.ll = arg2;
1273 farg3.ll = arg3;
1274 #if USE_PRECISE_EMULATION
1275 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1276 float64_is_signaling_nan(farg2.d) ||
1277 float64_is_signaling_nan(farg3.d))) {
1278 /* sNaN operation */
1279 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1280 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1281 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1282 /* Multiplication of zero by infinity */
1283 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1284 } else {
1285 #ifdef FLOAT128
1286 /* This is the way the PowerPC specification defines it */
1287 float128 ft0_128, ft1_128;
1288
1289 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1290 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1291 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1292 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1293 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1294 /* Magnitude subtraction of infinities */
1295 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1296 } else {
1297 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1298 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1299 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1300 }
1301 #else
1302 /* This is OK on x86 hosts */
1303 farg1.d = (farg1.d * farg2.d) + farg3.d;
1304 #endif
1305 }
1306 #else
1307 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1308 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1309 #endif
1310 return farg1.ll;
1311 }
1312
1313 /* fmsub - fmsub. */
1314 uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1315 {
1316 CPU_DoubleU farg1, farg2, farg3;
1317
1318 farg1.ll = arg1;
1319 farg2.ll = arg2;
1320 farg3.ll = arg3;
1321 #if USE_PRECISE_EMULATION
1322 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1323 float64_is_signaling_nan(farg2.d) ||
1324 float64_is_signaling_nan(farg3.d))) {
1325 /* sNaN operation */
1326 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1327 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1328 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1329 /* Multiplication of zero by infinity */
1330 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1331 } else {
1332 #ifdef FLOAT128
1333 /* This is the way the PowerPC specification defines it */
1334 float128 ft0_128, ft1_128;
1335
1336 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1337 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1338 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1339 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1340 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1341 /* Magnitude subtraction of infinities */
1342 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1343 } else {
1344 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1345 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1346 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1347 }
1348 #else
1349 /* This is OK on x86 hosts */
1350 farg1.d = (farg1.d * farg2.d) - farg3.d;
1351 #endif
1352 }
1353 #else
1354 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1355 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1356 #endif
1357 return farg1.ll;
1358 }
1359
1360 /* fnmadd - fnmadd. */
1361 uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1362 {
1363 CPU_DoubleU farg1, farg2, farg3;
1364
1365 farg1.ll = arg1;
1366 farg2.ll = arg2;
1367 farg3.ll = arg3;
1368
1369 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1370 float64_is_signaling_nan(farg2.d) ||
1371 float64_is_signaling_nan(farg3.d))) {
1372 /* sNaN operation */
1373 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1374 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1375 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1376 /* Multiplication of zero by infinity */
1377 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1378 } else {
1379 #if USE_PRECISE_EMULATION
1380 #ifdef FLOAT128
1381 /* This is the way the PowerPC specification defines it */
1382 float128 ft0_128, ft1_128;
1383
1384 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1385 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1386 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1387 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1388 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1389 /* Magnitude subtraction of infinities */
1390 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1391 } else {
1392 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1393 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1394 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1395 }
1396 #else
1397 /* This is OK on x86 hosts */
1398 farg1.d = (farg1.d * farg2.d) + farg3.d;
1399 #endif
1400 #else
1401 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1402 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1403 #endif
1404 if (likely(!float64_is_nan(farg1.d)))
1405 farg1.d = float64_chs(farg1.d);
1406 }
1407 return farg1.ll;
1408 }
1409
1410 /* fnmsub - fnmsub. */
1411 uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1412 {
1413 CPU_DoubleU farg1, farg2, farg3;
1414
1415 farg1.ll = arg1;
1416 farg2.ll = arg2;
1417 farg3.ll = arg3;
1418
1419 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1420 float64_is_signaling_nan(farg2.d) ||
1421 float64_is_signaling_nan(farg3.d))) {
1422 /* sNaN operation */
1423 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1424 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1425 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1426 /* Multiplication of zero by infinity */
1427 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
1428 } else {
1429 #if USE_PRECISE_EMULATION
1430 #ifdef FLOAT128
1431 /* This is the way the PowerPC specification defines it */
1432 float128 ft0_128, ft1_128;
1433
1434 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1435 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
1436 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1437 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1438 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1439 /* Magnitude subtraction of infinities */
1440 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1441 } else {
1442 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1443 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1444 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1445 }
1446 #else
1447 /* This is OK on x86 hosts */
1448 farg1.d = (farg1.d * farg2.d) - farg3.d;
1449 #endif
1450 #else
1451 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1452 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1453 #endif
1454 if (likely(!float64_is_nan(farg1.d)))
1455 farg1.d = float64_chs(farg1.d);
1456 }
1457 return farg1.ll;
1458 }
1459
1460 /* frsp - frsp. */
1461 uint64_t helper_frsp (uint64_t arg)
1462 {
1463 CPU_DoubleU farg;
1464 float32 f32;
1465 farg.ll = arg;
1466
1467 #if USE_PRECISE_EMULATION
1468 if (unlikely(float64_is_signaling_nan(farg.d))) {
1469 /* sNaN square root */
1470 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1471 } else {
1472 f32 = float64_to_float32(farg.d, &env->fp_status);
1473 farg.d = float32_to_float64(f32, &env->fp_status);
1474 }
1475 #else
1476 f32 = float64_to_float32(farg.d, &env->fp_status);
1477 farg.d = float32_to_float64(f32, &env->fp_status);
1478 #endif
1479 return farg.ll;
1480 }
1481
1482 /* fsqrt - fsqrt. */
1483 uint64_t helper_fsqrt (uint64_t arg)
1484 {
1485 CPU_DoubleU farg;
1486 farg.ll = arg;
1487
1488 if (unlikely(float64_is_signaling_nan(farg.d))) {
1489 /* sNaN square root */
1490 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1491 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1492 /* Square root of a negative nonzero number */
1493 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1494 } else {
1495 farg.d = float64_sqrt(farg.d, &env->fp_status);
1496 }
1497 return farg.ll;
1498 }
1499
1500 /* fre - fre. */
1501 uint64_t helper_fre (uint64_t arg)
1502 {
1503 CPU_DoubleU fone, farg;
1504 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
1505 farg.ll = arg;
1506
1507 if (unlikely(float64_is_signaling_nan(farg.d))) {
1508 /* sNaN reciprocal */
1509 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1510 } else {
1511 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1512 }
1513 return farg.d;
1514 }
1515
1516 /* fres - fres. */
1517 uint64_t helper_fres (uint64_t arg)
1518 {
1519 CPU_DoubleU fone, farg;
1520 float32 f32;
1521 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
1522 farg.ll = arg;
1523
1524 if (unlikely(float64_is_signaling_nan(farg.d))) {
1525 /* sNaN reciprocal */
1526 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1527 } else {
1528 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1529 f32 = float64_to_float32(farg.d, &env->fp_status);
1530 farg.d = float32_to_float64(f32, &env->fp_status);
1531 }
1532 return farg.ll;
1533 }
1534
1535 /* frsqrte - frsqrte. */
1536 uint64_t helper_frsqrte (uint64_t arg)
1537 {
1538 CPU_DoubleU fone, farg;
1539 float32 f32;
1540 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
1541 farg.ll = arg;
1542
1543 if (unlikely(float64_is_signaling_nan(farg.d))) {
1544 /* sNaN reciprocal square root */
1545 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1546 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
1547 /* Reciprocal square root of a negative nonzero number */
1548 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1549 } else {
1550 farg.d = float64_sqrt(farg.d, &env->fp_status);
1551 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1552 f32 = float64_to_float32(farg.d, &env->fp_status);
1553 farg.d = float32_to_float64(f32, &env->fp_status);
1554 }
1555 return farg.ll;
1556 }
1557
1558 /* fsel - fsel. */
1559 uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1560 {
1561 CPU_DoubleU farg1;
1562
1563 farg1.ll = arg1;
1564
1565 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) && !float64_is_nan(farg1.d))
1566 return arg2;
1567 else
1568 return arg3;
1569 }
1570
1571 void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1572 {
1573 CPU_DoubleU farg1, farg2;
1574 uint32_t ret = 0;
1575 farg1.ll = arg1;
1576 farg2.ll = arg2;
1577
1578 if (unlikely(float64_is_nan(farg1.d) ||
1579 float64_is_nan(farg2.d))) {
1580 ret = 0x01UL;
1581 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1582 ret = 0x08UL;
1583 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1584 ret = 0x04UL;
1585 } else {
1586 ret = 0x02UL;
1587 }
1588
1589 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1590 env->fpscr |= ret << FPSCR_FPRF;
1591 env->crf[crfD] = ret;
1592 if (unlikely(ret == 0x01UL
1593 && (float64_is_signaling_nan(farg1.d) ||
1594 float64_is_signaling_nan(farg2.d)))) {
1595 /* sNaN comparison */
1596 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1597 }
1598 }
1599
1600 void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1601 {
1602 CPU_DoubleU farg1, farg2;
1603 uint32_t ret = 0;
1604 farg1.ll = arg1;
1605 farg2.ll = arg2;
1606
1607 if (unlikely(float64_is_nan(farg1.d) ||
1608 float64_is_nan(farg2.d))) {
1609 ret = 0x01UL;
1610 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1611 ret = 0x08UL;
1612 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1613 ret = 0x04UL;
1614 } else {
1615 ret = 0x02UL;
1616 }
1617
1618 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1619 env->fpscr |= ret << FPSCR_FPRF;
1620 env->crf[crfD] = ret;
1621 if (unlikely (ret == 0x01UL)) {
1622 if (float64_is_signaling_nan(farg1.d) ||
1623 float64_is_signaling_nan(farg2.d)) {
1624 /* sNaN comparison */
1625 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1626 POWERPC_EXCP_FP_VXVC);
1627 } else {
1628 /* qNaN comparison */
1629 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1630 }
1631 }
1632 }
1633
1634 #if !defined (CONFIG_USER_ONLY)
1635 void helper_store_msr (target_ulong val)
1636 {
1637 val = hreg_store_msr(env, val, 0);
1638 if (val != 0) {
1639 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1640 helper_raise_exception(val);
1641 }
1642 }
1643
1644 static always_inline void do_rfi (target_ulong nip, target_ulong msr,
1645 target_ulong msrm, int keep_msrh)
1646 {
1647 #if defined(TARGET_PPC64)
1648 if (msr & (1ULL << MSR_SF)) {
1649 nip = (uint64_t)nip;
1650 msr &= (uint64_t)msrm;
1651 } else {
1652 nip = (uint32_t)nip;
1653 msr = (uint32_t)(msr & msrm);
1654 if (keep_msrh)
1655 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1656 }
1657 #else
1658 nip = (uint32_t)nip;
1659 msr &= (uint32_t)msrm;
1660 #endif
1661 /* XXX: beware: this is false if VLE is supported */
1662 env->nip = nip & ~((target_ulong)0x00000003);
1663 hreg_store_msr(env, msr, 1);
1664 #if defined (DEBUG_OP)
1665 cpu_dump_rfi(env->nip, env->msr);
1666 #endif
1667 /* No need to raise an exception here,
1668 * as rfi is always the last insn of a TB
1669 */
1670 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1671 }
1672
1673 void helper_rfi (void)
1674 {
1675 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1676 ~((target_ulong)0xFFFF0000), 1);
1677 }
1678
1679 #if defined(TARGET_PPC64)
1680 void helper_rfid (void)
1681 {
1682 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1683 ~((target_ulong)0xFFFF0000), 0);
1684 }
1685
1686 void helper_hrfid (void)
1687 {
1688 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1689 ~((target_ulong)0xFFFF0000), 0);
1690 }
1691 #endif
1692 #endif
1693
1694 void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
1695 {
1696 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1697 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1698 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1699 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1700 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
1701 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1702 }
1703 }
1704
1705 #if defined(TARGET_PPC64)
1706 void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
1707 {
1708 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1709 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1710 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1711 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1712 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
1713 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1714 }
1715 #endif
1716
1717 /*****************************************************************************/
1718 /* PowerPC 601 specific instructions (POWER bridge) */
1719
1720 target_ulong helper_clcs (uint32_t arg)
1721 {
1722 switch (arg) {
1723 case 0x0CUL:
1724 /* Instruction cache line size */
1725 return env->icache_line_size;
1726 break;
1727 case 0x0DUL:
1728 /* Data cache line size */
1729 return env->dcache_line_size;
1730 break;
1731 case 0x0EUL:
1732 /* Minimum cache line size */
1733 return (env->icache_line_size < env->dcache_line_size) ?
1734 env->icache_line_size : env->dcache_line_size;
1735 break;
1736 case 0x0FUL:
1737 /* Maximum cache line size */
1738 return (env->icache_line_size > env->dcache_line_size) ?
1739 env->icache_line_size : env->dcache_line_size;
1740 break;
1741 default:
1742 /* Undefined */
1743 return 0;
1744 break;
1745 }
1746 }
1747
1748 target_ulong helper_div (target_ulong arg1, target_ulong arg2)
1749 {
1750 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1751
1752 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1753 (int32_t)arg2 == 0) {
1754 env->spr[SPR_MQ] = 0;
1755 return INT32_MIN;
1756 } else {
1757 env->spr[SPR_MQ] = tmp % arg2;
1758 return tmp / (int32_t)arg2;
1759 }
1760 }
1761
1762 target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
1763 {
1764 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
1765
1766 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1767 (int32_t)arg2 == 0) {
1768 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1769 env->spr[SPR_MQ] = 0;
1770 return INT32_MIN;
1771 } else {
1772 env->spr[SPR_MQ] = tmp % arg2;
1773 tmp /= (int32_t)arg2;
1774 if ((int32_t)tmp != tmp) {
1775 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1776 } else {
1777 env->xer &= ~(1 << XER_OV);
1778 }
1779 return tmp;
1780 }
1781 }
1782
1783 target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
1784 {
1785 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1786 (int32_t)arg2 == 0) {
1787 env->spr[SPR_MQ] = 0;
1788 return INT32_MIN;
1789 } else {
1790 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1791 return (int32_t)arg1 / (int32_t)arg2;
1792 }
1793 }
1794
1795 target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
1796 {
1797 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1798 (int32_t)arg2 == 0) {
1799 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1800 env->spr[SPR_MQ] = 0;
1801 return INT32_MIN;
1802 } else {
1803 env->xer &= ~(1 << XER_OV);
1804 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1805 return (int32_t)arg1 / (int32_t)arg2;
1806 }
1807 }
1808
1809 #if !defined (CONFIG_USER_ONLY)
1810 target_ulong helper_rac (target_ulong addr)
1811 {
1812 mmu_ctx_t ctx;
1813 int nb_BATs;
1814 target_ulong ret = 0;
1815
1816 /* We don't have to generate many instances of this instruction,
1817 * as rac is supervisor only.
1818 */
1819 /* XXX: FIX THIS: Pretend we have no BAT */
1820 nb_BATs = env->nb_BATs;
1821 env->nb_BATs = 0;
1822 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1823 ret = ctx.raddr;
1824 env->nb_BATs = nb_BATs;
1825 return ret;
1826 }
1827
1828 void helper_rfsvc (void)
1829 {
1830 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1831 }
1832 #endif
1833
1834 /*****************************************************************************/
1835 /* 602 specific instructions */
1836 /* mfrom is the most crazy instruction ever seen, imho ! */
1837 /* Real implementation uses a ROM table. Do the same */
1838 /* Extremly decomposed:
1839 * -arg / 256
1840 * return 256 * log10(10 + 1.0) + 0.5
1841 */
1842 #if !defined (CONFIG_USER_ONLY)
1843 target_ulong helper_602_mfrom (target_ulong arg)
1844 {
1845 if (likely(arg < 602)) {
1846 #include "mfrom_table.c"
1847 return mfrom_ROM_table[arg];
1848 } else {
1849 return 0;
1850 }
1851 }
1852 #endif
1853
1854 /*****************************************************************************/
1855 /* Embedded PowerPC specific helpers */
1856
1857 /* XXX: to be improved to check access rights when in user-mode */
1858 target_ulong helper_load_dcr (target_ulong dcrn)
1859 {
1860 target_ulong val = 0;
1861
1862 if (unlikely(env->dcr_env == NULL)) {
1863 if (loglevel != 0) {
1864 fprintf(logfile, "No DCR environment\n");
1865 }
1866 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1867 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1868 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
1869 if (loglevel != 0) {
1870 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
1871 }
1872 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1873 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1874 }
1875 return val;
1876 }
1877
1878 void helper_store_dcr (target_ulong dcrn, target_ulong val)
1879 {
1880 if (unlikely(env->dcr_env == NULL)) {
1881 if (loglevel != 0) {
1882 fprintf(logfile, "No DCR environment\n");
1883 }
1884 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1885 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1886 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
1887 if (loglevel != 0) {
1888 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
1889 }
1890 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1891 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1892 }
1893 }
1894
1895 #if !defined(CONFIG_USER_ONLY)
1896 void helper_40x_rfci (void)
1897 {
1898 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1899 ~((target_ulong)0xFFFF0000), 0);
1900 }
1901
1902 void helper_rfci (void)
1903 {
1904 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1905 ~((target_ulong)0x3FFF0000), 0);
1906 }
1907
1908 void helper_rfdi (void)
1909 {
1910 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1911 ~((target_ulong)0x3FFF0000), 0);
1912 }
1913
1914 void helper_rfmci (void)
1915 {
1916 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1917 ~((target_ulong)0x3FFF0000), 0);
1918 }
1919 #endif
1920
1921 /* 440 specific */
1922 target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
1923 {
1924 target_ulong mask;
1925 int i;
1926
1927 i = 1;
1928 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1929 if ((high & mask) == 0) {
1930 if (update_Rc) {
1931 env->crf[0] = 0x4;
1932 }
1933 goto done;
1934 }
1935 i++;
1936 }
1937 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1938 if ((low & mask) == 0) {
1939 if (update_Rc) {
1940 env->crf[0] = 0x8;
1941 }
1942 goto done;
1943 }
1944 i++;
1945 }
1946 if (update_Rc) {
1947 env->crf[0] = 0x2;
1948 }
1949 done:
1950 env->xer = (env->xer & ~0x7F) | i;
1951 if (update_Rc) {
1952 env->crf[0] |= xer_so;
1953 }
1954 return i;
1955 }
1956
1957 /*****************************************************************************/
1958 /* Altivec extension helpers */
1959 #if defined(WORDS_BIGENDIAN)
1960 #define HI_IDX 0
1961 #define LO_IDX 1
1962 #else
1963 #define HI_IDX 1
1964 #define LO_IDX 0
1965 #endif
1966
1967 #if defined(WORDS_BIGENDIAN)
1968 #define VECTOR_FOR_INORDER_I(index, element) \
1969 for (index = 0; index < ARRAY_SIZE(r->element); index++)
1970 #else
1971 #define VECTOR_FOR_INORDER_I(index, element) \
1972 for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
1973 #endif
1974
1975 /* Saturating arithmetic helpers. */
1976 #define SATCVT(from, to, from_type, to_type, min, max, use_min, use_max) \
1977 static always_inline to_type cvt##from##to (from_type x, int *sat) \
1978 { \
1979 to_type r; \
1980 if (use_min && x < min) { \
1981 r = min; \
1982 *sat = 1; \
1983 } else if (use_max && x > max) { \
1984 r = max; \
1985 *sat = 1; \
1986 } else { \
1987 r = x; \
1988 } \
1989 return r; \
1990 }
1991 SATCVT(sh, sb, int16_t, int8_t, INT8_MIN, INT8_MAX, 1, 1)
1992 SATCVT(sw, sh, int32_t, int16_t, INT16_MIN, INT16_MAX, 1, 1)
1993 SATCVT(sd, sw, int64_t, int32_t, INT32_MIN, INT32_MAX, 1, 1)
1994 SATCVT(uh, ub, uint16_t, uint8_t, 0, UINT8_MAX, 0, 1)
1995 SATCVT(uw, uh, uint32_t, uint16_t, 0, UINT16_MAX, 0, 1)
1996 SATCVT(ud, uw, uint64_t, uint32_t, 0, UINT32_MAX, 0, 1)
1997 SATCVT(sh, ub, int16_t, uint8_t, 0, UINT8_MAX, 1, 1)
1998 SATCVT(sw, uh, int32_t, uint16_t, 0, UINT16_MAX, 1, 1)
1999 SATCVT(sd, uw, int64_t, uint32_t, 0, UINT32_MAX, 1, 1)
2000 #undef SATCVT
2001
2002 #define LVE(name, access, swap, element) \
2003 void helper_##name (ppc_avr_t *r, target_ulong addr) \
2004 { \
2005 size_t n_elems = ARRAY_SIZE(r->element); \
2006 int adjust = HI_IDX*(n_elems-1); \
2007 int sh = sizeof(r->element[0]) >> 1; \
2008 int index = (addr & 0xf) >> sh; \
2009 if(msr_le) { \
2010 r->element[LO_IDX ? index : (adjust - index)] = swap(access(addr)); \
2011 } else { \
2012 r->element[LO_IDX ? index : (adjust - index)] = access(addr); \
2013 } \
2014 }
2015 #define I(x) (x)
2016 LVE(lvebx, ldub, I, u8)
2017 LVE(lvehx, lduw, bswap16, u16)
2018 LVE(lvewx, ldl, bswap32, u32)
2019 #undef I
2020 #undef LVE
2021
2022 void helper_lvsl (ppc_avr_t *r, target_ulong sh)
2023 {
2024 int i, j = (sh & 0xf);
2025
2026 VECTOR_FOR_INORDER_I (i, u8) {
2027 r->u8[i] = j++;
2028 }
2029 }
2030
2031 void helper_lvsr (ppc_avr_t *r, target_ulong sh)
2032 {
2033 int i, j = 0x10 - (sh & 0xf);
2034
2035 VECTOR_FOR_INORDER_I (i, u8) {
2036 r->u8[i] = j++;
2037 }
2038 }
2039
2040 #define STVE(name, access, swap, element) \
2041 void helper_##name (ppc_avr_t *r, target_ulong addr) \
2042 { \
2043 size_t n_elems = ARRAY_SIZE(r->element); \
2044 int adjust = HI_IDX*(n_elems-1); \
2045 int sh = sizeof(r->element[0]) >> 1; \
2046 int index = (addr & 0xf) >> sh; \
2047 if(msr_le) { \
2048 access(addr, swap(r->element[LO_IDX ? index : (adjust - index)])); \
2049 } else { \
2050 access(addr, r->element[LO_IDX ? index : (adjust - index)]); \
2051 } \
2052 }
2053 #define I(x) (x)
2054 STVE(stvebx, stb, I, u8)
2055 STVE(stvehx, stw, bswap16, u16)
2056 STVE(stvewx, stl, bswap32, u32)
2057 #undef I
2058 #undef LVE
2059
2060 void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2061 {
2062 int i;
2063 for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
2064 r->u32[i] = ~a->u32[i] < b->u32[i];
2065 }
2066 }
2067
2068 #define VARITH_DO(name, op, element) \
2069 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2070 { \
2071 int i; \
2072 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2073 r->element[i] = a->element[i] op b->element[i]; \
2074 } \
2075 }
2076 #define VARITH(suffix, element) \
2077 VARITH_DO(add##suffix, +, element) \
2078 VARITH_DO(sub##suffix, -, element)
2079 VARITH(ubm, u8)
2080 VARITH(uhm, u16)
2081 VARITH(uwm, u32)
2082 #undef VARITH_DO
2083 #undef VARITH
2084
2085 #define VAVG_DO(name, element, etype) \
2086 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2087 { \
2088 int i; \
2089 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2090 etype x = (etype)a->element[i] + (etype)b->element[i] + 1; \
2091 r->element[i] = x >> 1; \
2092 } \
2093 }
2094
2095 #define VAVG(type, signed_element, signed_type, unsigned_element, unsigned_type) \
2096 VAVG_DO(avgs##type, signed_element, signed_type) \
2097 VAVG_DO(avgu##type, unsigned_element, unsigned_type)
2098 VAVG(b, s8, int16_t, u8, uint16_t)
2099 VAVG(h, s16, int32_t, u16, uint32_t)
2100 VAVG(w, s32, int64_t, u32, uint64_t)
2101 #undef VAVG_DO
2102 #undef VAVG
2103
2104 #define VCMP_DO(suffix, compare, element, record) \
2105 void helper_vcmp##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2106 { \
2107 uint32_t ones = (uint32_t)-1; \
2108 uint32_t all = ones; \
2109 uint32_t none = 0; \
2110 int i; \
2111 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2112 uint32_t result = (a->element[i] compare b->element[i] ? ones : 0x0); \
2113 switch (sizeof (a->element[0])) { \
2114 case 4: r->u32[i] = result; break; \
2115 case 2: r->u16[i] = result; break; \
2116 case 1: r->u8[i] = result; break; \
2117 } \
2118 all &= result; \
2119 none |= result; \
2120 } \
2121 if (record) { \
2122 env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
2123 } \
2124 }
2125 #define VCMP(suffix, compare, element) \
2126 VCMP_DO(suffix, compare, element, 0) \
2127 VCMP_DO(suffix##_dot, compare, element, 1)
2128 VCMP(equb, ==, u8)
2129 VCMP(equh, ==, u16)
2130 VCMP(equw, ==, u32)
2131 VCMP(gtub, >, u8)
2132 VCMP(gtuh, >, u16)
2133 VCMP(gtuw, >, u32)
2134 VCMP(gtsb, >, s8)
2135 VCMP(gtsh, >, s16)
2136 VCMP(gtsw, >, s32)
2137 #undef VCMP_DO
2138 #undef VCMP
2139
2140 void helper_vmhaddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2141 {
2142 int sat = 0;
2143 int i;
2144
2145 for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
2146 int32_t prod = a->s16[i] * b->s16[i];
2147 int32_t t = (int32_t)c->s16[i] + (prod >> 15);
2148 r->s16[i] = cvtswsh (t, &sat);
2149 }
2150
2151 if (sat) {
2152 env->vscr |= (1 << VSCR_SAT);
2153 }
2154 }
2155
2156 void helper_vmhraddshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2157 {
2158 int sat = 0;
2159 int i;
2160
2161 for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
2162 int32_t prod = a->s16[i] * b->s16[i] + 0x00004000;
2163 int32_t t = (int32_t)c->s16[i] + (prod >> 15);
2164 r->s16[i] = cvtswsh (t, &sat);
2165 }
2166
2167 if (sat) {
2168 env->vscr |= (1 << VSCR_SAT);
2169 }
2170 }
2171
2172 #define VMINMAX_DO(name, compare, element) \
2173 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2174 { \
2175 int i; \
2176 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2177 if (a->element[i] compare b->element[i]) { \
2178 r->element[i] = b->element[i]; \
2179 } else { \
2180 r->element[i] = a->element[i]; \
2181 } \
2182 } \
2183 }
2184 #define VMINMAX(suffix, element) \
2185 VMINMAX_DO(min##suffix, >, element) \
2186 VMINMAX_DO(max##suffix, <, element)
2187 VMINMAX(sb, s8)
2188 VMINMAX(sh, s16)
2189 VMINMAX(sw, s32)
2190 VMINMAX(ub, u8)
2191 VMINMAX(uh, u16)
2192 VMINMAX(uw, u32)
2193 #undef VMINMAX_DO
2194 #undef VMINMAX
2195
2196 void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2197 {
2198 int i;
2199 for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
2200 int32_t prod = a->s16[i] * b->s16[i];
2201 r->s16[i] = (int16_t) (prod + c->s16[i]);
2202 }
2203 }
2204
2205 #define VMRG_DO(name, element, highp) \
2206 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2207 { \
2208 ppc_avr_t result; \
2209 int i; \
2210 size_t n_elems = ARRAY_SIZE(r->element); \
2211 for (i = 0; i < n_elems/2; i++) { \
2212 if (highp) { \
2213 result.element[i*2+HI_IDX] = a->element[i]; \
2214 result.element[i*2+LO_IDX] = b->element[i]; \
2215 } else { \
2216 result.element[n_elems - i*2 - (1+HI_IDX)] = b->element[n_elems - i - 1]; \
2217 result.element[n_elems - i*2 - (1+LO_IDX)] = a->element[n_elems - i - 1]; \
2218 } \
2219 } \
2220 *r = result; \
2221 }
2222 #if defined(WORDS_BIGENDIAN)
2223 #define MRGHI 0
2224 #define MRGLO 1
2225 #else
2226 #define MRGHI 1
2227 #define MRGLO 0
2228 #endif
2229 #define VMRG(suffix, element) \
2230 VMRG_DO(mrgl##suffix, element, MRGHI) \
2231 VMRG_DO(mrgh##suffix, element, MRGLO)
2232 VMRG(b, u8)
2233 VMRG(h, u16)
2234 VMRG(w, u32)
2235 #undef VMRG_DO
2236 #undef VMRG
2237 #undef MRGHI
2238 #undef MRGLO
2239
2240 void helper_vmsummbm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2241 {
2242 int32_t prod[16];
2243 int i;
2244
2245 for (i = 0; i < ARRAY_SIZE(r->s8); i++) {
2246 prod[i] = (int32_t)a->s8[i] * b->u8[i];
2247 }
2248
2249 VECTOR_FOR_INORDER_I(i, s32) {
2250 r->s32[i] = c->s32[i] + prod[4*i] + prod[4*i+1] + prod[4*i+2] + prod[4*i+3];
2251 }
2252 }
2253
2254 void helper_vmsumshm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2255 {
2256 int32_t prod[8];
2257 int i;
2258
2259 for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
2260 prod[i] = a->s16[i] * b->s16[i];
2261 }
2262
2263 VECTOR_FOR_INORDER_I(i, s32) {
2264 r->s32[i] = c->s32[i] + prod[2*i] + prod[2*i+1];
2265 }
2266 }
2267
2268 void helper_vmsumshs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2269 {
2270 int32_t prod[8];
2271 int i;
2272 int sat = 0;
2273
2274 for (i = 0; i < ARRAY_SIZE(r->s16); i++) {
2275 prod[i] = (int32_t)a->s16[i] * b->s16[i];
2276 }
2277
2278 VECTOR_FOR_INORDER_I (i, s32) {
2279 int64_t t = (int64_t)c->s32[i] + prod[2*i] + prod[2*i+1];
2280 r->u32[i] = cvtsdsw(t, &sat);
2281 }
2282
2283 if (sat) {
2284 env->vscr |= (1 << VSCR_SAT);
2285 }
2286 }
2287
2288 void helper_vmsumubm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2289 {
2290 uint16_t prod[16];
2291 int i;
2292
2293 for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
2294 prod[i] = a->u8[i] * b->u8[i];
2295 }
2296
2297 VECTOR_FOR_INORDER_I(i, u32) {
2298 r->u32[i] = c->u32[i] + prod[4*i] + prod[4*i+1] + prod[4*i+2] + prod[4*i+3];
2299 }
2300 }
2301
2302 void helper_vmsumuhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2303 {
2304 uint32_t prod[8];
2305 int i;
2306
2307 for (i = 0; i < ARRAY_SIZE(r->u16); i++) {
2308 prod[i] = a->u16[i] * b->u16[i];
2309 }
2310
2311 VECTOR_FOR_INORDER_I(i, u32) {
2312 r->u32[i] = c->u32[i] + prod[2*i] + prod[2*i+1];
2313 }
2314 }
2315
2316 void helper_vmsumuhs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2317 {
2318 uint32_t prod[8];
2319 int i;
2320 int sat = 0;
2321
2322 for (i = 0; i < ARRAY_SIZE(r->u16); i++) {
2323 prod[i] = a->u16[i] * b->u16[i];
2324 }
2325
2326 VECTOR_FOR_INORDER_I (i, s32) {
2327 uint64_t t = (uint64_t)c->u32[i] + prod[2*i] + prod[2*i+1];
2328 r->u32[i] = cvtuduw(t, &sat);
2329 }
2330
2331 if (sat) {
2332 env->vscr |= (1 << VSCR_SAT);
2333 }
2334 }
2335
2336 #define VMUL_DO(name, mul_element, prod_element, evenp) \
2337 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2338 { \
2339 int i; \
2340 VECTOR_FOR_INORDER_I(i, prod_element) { \
2341 if (evenp) { \
2342 r->prod_element[i] = a->mul_element[i*2+HI_IDX] * b->mul_element[i*2+HI_IDX]; \
2343 } else { \
2344 r->prod_element[i] = a->mul_element[i*2+LO_IDX] * b->mul_element[i*2+LO_IDX]; \
2345 } \
2346 } \
2347 }
2348 #define VMUL(suffix, mul_element, prod_element) \
2349 VMUL_DO(mule##suffix, mul_element, prod_element, 1) \
2350 VMUL_DO(mulo##suffix, mul_element, prod_element, 0)
2351 VMUL(sb, s8, s16)
2352 VMUL(sh, s16, s32)
2353 VMUL(ub, u8, u16)
2354 VMUL(uh, u16, u32)
2355 #undef VMUL_DO
2356 #undef VMUL
2357
2358 void helper_vperm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2359 {
2360 ppc_avr_t result;
2361 int i;
2362 VECTOR_FOR_INORDER_I (i, u8) {
2363 int s = c->u8[i] & 0x1f;
2364 #if defined(WORDS_BIGENDIAN)
2365 int index = s & 0xf;
2366 #else
2367 int index = 15 - (s & 0xf);
2368 #endif
2369 if (s & 0x10) {
2370 result.u8[i] = b->u8[index];
2371 } else {
2372 result.u8[i] = a->u8[index];
2373 }
2374 }
2375 *r = result;
2376 }
2377
2378 #if defined(WORDS_BIGENDIAN)
2379 #define PKBIG 1
2380 #else
2381 #define PKBIG 0
2382 #endif
2383 void helper_vpkpx (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2384 {
2385 int i, j;
2386 ppc_avr_t result;
2387 #if defined(WORDS_BIGENDIAN)
2388 const ppc_avr_t *x[2] = { a, b };
2389 #else
2390 const ppc_avr_t *x[2] = { b, a };
2391 #endif
2392
2393 VECTOR_FOR_INORDER_I (i, u64) {
2394 VECTOR_FOR_INORDER_I (j, u32){
2395 uint32_t e = x[i]->u32[j];
2396 result.u16[4*i+j] = (((e >> 9) & 0xfc00) |
2397 ((e >> 6) & 0x3e0) |
2398 ((e >> 3) & 0x1f));
2399 }
2400 }
2401 *r = result;
2402 }
2403
2404 #define VPK(suffix, from, to, cvt, dosat) \
2405 void helper_vpk##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2406 { \
2407 int i; \
2408 int sat = 0; \
2409 ppc_avr_t result; \
2410 ppc_avr_t *a0 = PKBIG ? a : b; \
2411 ppc_avr_t *a1 = PKBIG ? b : a; \
2412 VECTOR_FOR_INORDER_I (i, from) { \
2413 result.to[i] = cvt(a0->from[i], &sat); \
2414 result.to[i+ARRAY_SIZE(r->from)] = cvt(a1->from[i], &sat); \
2415 } \
2416 *r = result; \
2417 if (dosat && sat) { \
2418 env->vscr |= (1 << VSCR_SAT); \
2419 } \
2420 }
2421 #define I(x, y) (x)
2422 VPK(shss, s16, s8, cvtshsb, 1)
2423 VPK(shus, s16, u8, cvtshub, 1)
2424 VPK(swss, s32, s16, cvtswsh, 1)
2425 VPK(swus, s32, u16, cvtswuh, 1)
2426 VPK(uhus, u16, u8, cvtuhub, 1)
2427 VPK(uwus, u32, u16, cvtuwuh, 1)
2428 VPK(uhum, u16, u8, I, 0)
2429 VPK(uwum, u32, u16, I, 0)
2430 #undef I
2431 #undef VPK
2432 #undef PKBIG
2433
2434 #define VROTATE(suffix, element) \
2435 void helper_vrl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2436 { \
2437 int i; \
2438 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2439 unsigned int mask = ((1 << (3 + (sizeof (a->element[0]) >> 1))) - 1); \
2440 unsigned int shift = b->element[i] & mask; \
2441 r->element[i] = (a->element[i] << shift) | (a->element[i] >> (sizeof(a->element[0]) * 8 - shift)); \
2442 } \
2443 }
2444 VROTATE(b, u8)
2445 VROTATE(h, u16)
2446 VROTATE(w, u32)
2447 #undef VROTATE
2448
2449 void helper_vsel (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
2450 {
2451 r->u64[0] = (a->u64[0] & ~c->u64[0]) | (b->u64[0] & c->u64[0]);
2452 r->u64[1] = (a->u64[1] & ~c->u64[1]) | (b->u64[1] & c->u64[1]);
2453 }
2454
2455 #if defined(WORDS_BIGENDIAN)
2456 #define LEFT 0
2457 #define RIGHT 1
2458 #else
2459 #define LEFT 1
2460 #define RIGHT 0
2461 #endif
2462 /* The specification says that the results are undefined if all of the
2463 * shift counts are not identical. We check to make sure that they are
2464 * to conform to what real hardware appears to do. */
2465 #define VSHIFT(suffix, leftp) \
2466 void helper_vs##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2467 { \
2468 int shift = b->u8[LO_IDX*0x15] & 0x7; \
2469 int doit = 1; \
2470 int i; \
2471 for (i = 0; i < ARRAY_SIZE(r->u8); i++) { \
2472 doit = doit && ((b->u8[i] & 0x7) == shift); \
2473 } \
2474 if (doit) { \
2475 if (shift == 0) { \
2476 *r = *a; \
2477 } else if (leftp) { \
2478 uint64_t carry = a->u64[LO_IDX] >> (64 - shift); \
2479 r->u64[HI_IDX] = (a->u64[HI_IDX] << shift) | carry; \
2480 r->u64[LO_IDX] = a->u64[LO_IDX] << shift; \
2481 } else { \
2482 uint64_t carry = a->u64[HI_IDX] << (64 - shift); \
2483 r->u64[LO_IDX] = (a->u64[LO_IDX] >> shift) | carry; \
2484 r->u64[HI_IDX] = a->u64[HI_IDX] >> shift; \
2485 } \
2486 } \
2487 }
2488 VSHIFT(l, LEFT)
2489 VSHIFT(r, RIGHT)
2490 #undef VSHIFT
2491 #undef LEFT
2492 #undef RIGHT
2493
2494 #define VSL(suffix, element) \
2495 void helper_vsl##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2496 { \
2497 int i; \
2498 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2499 unsigned int mask = ((1 << (3 + (sizeof (a->element[0]) >> 1))) - 1); \
2500 unsigned int shift = b->element[i] & mask; \
2501 r->element[i] = a->element[i] << shift; \
2502 } \
2503 }
2504 VSL(b, u8)
2505 VSL(h, u16)
2506 VSL(w, u32)
2507 #undef VSL
2508
2509 void helper_vsldoi (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
2510 {
2511 int sh = shift & 0xf;
2512 int i;
2513 ppc_avr_t result;
2514
2515 #if defined(WORDS_BIGENDIAN)
2516 for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
2517 int index = sh + i;
2518 if (index > 0xf) {
2519 result.u8[i] = b->u8[index-0x10];
2520 } else {
2521 result.u8[i] = a->u8[index];
2522 }
2523 }
2524 #else
2525 for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
2526 int index = (16 - sh) + i;
2527 if (index > 0xf) {
2528 result.u8[i] = a->u8[index-0x10];
2529 } else {
2530 result.u8[i] = b->u8[index];
2531 }
2532 }
2533 #endif
2534 *r = result;
2535 }
2536
2537 void helper_vslo (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2538 {
2539 int sh = (b->u8[LO_IDX*0xf] >> 3) & 0xf;
2540
2541 #if defined (WORDS_BIGENDIAN)
2542 memmove (&r->u8[0], &a->u8[sh], 16-sh);
2543 memset (&r->u8[16-sh], 0, sh);
2544 #else
2545 memmove (&r->u8[sh], &a->u8[0], 16-sh);
2546 memset (&r->u8[0], 0, sh);
2547 #endif
2548 }
2549
2550 /* Experimental testing shows that hardware masks the immediate. */
2551 #define _SPLAT_MASKED(element) (splat & (ARRAY_SIZE(r->element) - 1))
2552 #if defined(WORDS_BIGENDIAN)
2553 #define SPLAT_ELEMENT(element) _SPLAT_MASKED(element)
2554 #else
2555 #define SPLAT_ELEMENT(element) (ARRAY_SIZE(r->element)-1 - _SPLAT_MASKED(element))
2556 #endif
2557 #define VSPLT(suffix, element) \
2558 void helper_vsplt##suffix (ppc_avr_t *r, ppc_avr_t *b, uint32_t splat) \
2559 { \
2560 uint32_t s = b->element[SPLAT_ELEMENT(element)]; \
2561 int i; \
2562 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2563 r->element[i] = s; \
2564 } \
2565 }
2566 VSPLT(b, u8)
2567 VSPLT(h, u16)
2568 VSPLT(w, u32)
2569 #undef VSPLT
2570 #undef SPLAT_ELEMENT
2571 #undef _SPLAT_MASKED
2572
2573 #define VSR(suffix, element) \
2574 void helper_vsr##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2575 { \
2576 int i; \
2577 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2578 unsigned int mask = ((1 << (3 + (sizeof (a->element[0]) >> 1))) - 1); \
2579 unsigned int shift = b->element[i] & mask; \
2580 r->element[i] = a->element[i] >> shift; \
2581 } \
2582 }
2583 VSR(ab, s8)
2584 VSR(ah, s16)
2585 VSR(aw, s32)
2586 VSR(b, u8)
2587 VSR(h, u16)
2588 VSR(w, u32)
2589 #undef VSR
2590
2591 void helper_vsro (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2592 {
2593 int sh = (b->u8[LO_IDX*0xf] >> 3) & 0xf;
2594
2595 #if defined (WORDS_BIGENDIAN)
2596 memmove (&r->u8[sh], &a->u8[0], 16-sh);
2597 memset (&r->u8[0], 0, sh);
2598 #else
2599 memmove (&r->u8[0], &a->u8[sh], 16-sh);
2600 memset (&r->u8[16-sh], 0, sh);
2601 #endif
2602 }
2603
2604 void helper_vsubcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2605 {
2606 int i;
2607 for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
2608 r->u32[i] = a->u32[i] >= b->u32[i];
2609 }
2610 }
2611
2612 void helper_vsumsws (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2613 {
2614 int64_t t;
2615 int i, upper;
2616 ppc_avr_t result;
2617 int sat = 0;
2618
2619 #if defined(WORDS_BIGENDIAN)
2620 upper = ARRAY_SIZE(r->s32)-1;
2621 #else
2622 upper = 0;
2623 #endif
2624 t = (int64_t)b->s32[upper];
2625 for (i = 0; i < ARRAY_SIZE(r->s32); i++) {
2626 t += a->s32[i];
2627 result.s32[i] = 0;
2628 }
2629 result.s32[upper] = cvtsdsw(t, &sat);
2630 *r = result;
2631
2632 if (sat) {
2633 env->vscr |= (1 << VSCR_SAT);
2634 }
2635 }
2636
2637 void helper_vsum2sws (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2638 {
2639 int i, j, upper;
2640 ppc_avr_t result;
2641 int sat = 0;
2642
2643 #if defined(WORDS_BIGENDIAN)
2644 upper = 1;
2645 #else
2646 upper = 0;
2647 #endif
2648 for (i = 0; i < ARRAY_SIZE(r->u64); i++) {
2649 int64_t t = (int64_t)b->s32[upper+i*2];
2650 result.u64[i] = 0;
2651 for (j = 0; j < ARRAY_SIZE(r->u64); j++) {
2652 t += a->s32[2*i+j];
2653 }
2654 result.s32[upper+i*2] = cvtsdsw(t, &sat);
2655 }
2656
2657 *r = result;
2658 if (sat) {
2659 env->vscr |= (1 << VSCR_SAT);
2660 }
2661 }
2662
2663 void helper_vsum4sbs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2664 {
2665 int i, j;
2666 int sat = 0;
2667
2668 for (i = 0; i < ARRAY_SIZE(r->s32); i++) {
2669 int64_t t = (int64_t)b->s32[i];
2670 for (j = 0; j < ARRAY_SIZE(r->s32); j++) {
2671 t += a->s8[4*i+j];
2672 }
2673 r->s32[i] = cvtsdsw(t, &sat);
2674 }
2675
2676 if (sat) {
2677 env->vscr |= (1 << VSCR_SAT);
2678 }
2679 }
2680
2681 void helper_vsum4shs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2682 {
2683 int sat = 0;
2684 int i;
2685
2686 for (i = 0; i < ARRAY_SIZE(r->s32); i++) {
2687 int64_t t = (int64_t)b->s32[i];
2688 t += a->s16[2*i] + a->s16[2*i+1];
2689 r->s32[i] = cvtsdsw(t, &sat);
2690 }
2691
2692 if (sat) {
2693 env->vscr |= (1 << VSCR_SAT);
2694 }
2695 }
2696
2697 void helper_vsum4ubs (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
2698 {
2699 int i, j;
2700 int sat = 0;
2701
2702 for (i = 0; i < ARRAY_SIZE(r->u32); i++) {
2703 uint64_t t = (uint64_t)b->u32[i];
2704 for (j = 0; j < ARRAY_SIZE(r->u32); j++) {
2705 t += a->u8[4*i+j];
2706 }
2707 r->u32[i] = cvtuduw(t, &sat);
2708 }
2709
2710 if (sat) {
2711 env->vscr |= (1 << VSCR_SAT);
2712 }
2713 }
2714
2715 #if defined(WORDS_BIGENDIAN)
2716 #define UPKHI 1
2717 #define UPKLO 0
2718 #else
2719 #define UPKHI 0
2720 #define UPKLO 1
2721 #endif
2722 #define VUPKPX(suffix, hi) \
2723 void helper_vupk##suffix (ppc_avr_t *r, ppc_avr_t *b) \
2724 { \
2725 int i; \
2726 ppc_avr_t result; \
2727 for (i = 0; i < ARRAY_SIZE(r->u32); i++) { \
2728 uint16_t e = b->u16[hi ? i : i+4]; \
2729 uint8_t a = (e >> 15) ? 0xff : 0; \
2730 uint8_t r = (e >> 10) & 0x1f; \
2731 uint8_t g = (e >> 5) & 0x1f; \
2732 uint8_t b = e & 0x1f; \
2733 result.u32[i] = (a << 24) | (r << 16) | (g << 8) | b; \
2734 } \
2735 *r = result; \
2736 }
2737 VUPKPX(lpx, UPKLO)
2738 VUPKPX(hpx, UPKHI)
2739 #undef VUPKPX
2740
2741 #define VUPK(suffix, unpacked, packee, hi) \
2742 void helper_vupk##suffix (ppc_avr_t *r, ppc_avr_t *b) \
2743 { \
2744 int i; \
2745 ppc_avr_t result; \
2746 if (hi) { \
2747 for (i = 0; i < ARRAY_SIZE(r->unpacked); i++) { \
2748 result.unpacked[i] = b->packee[i]; \
2749 } \
2750 } else { \
2751 for (i = ARRAY_SIZE(r->unpacked); i < ARRAY_SIZE(r->packee); i++) { \
2752 result.unpacked[i-ARRAY_SIZE(r->unpacked)] = b->packee[i]; \
2753 } \
2754 } \
2755 *r = result; \
2756 }
2757 VUPK(hsb, s16, s8, UPKHI)
2758 VUPK(hsh, s32, s16, UPKHI)
2759 VUPK(lsb, s16, s8, UPKLO)
2760 VUPK(lsh, s32, s16, UPKLO)
2761 #undef VUPK
2762 #undef UPKHI
2763 #undef UPKLO
2764
2765 #undef VECTOR_FOR_INORDER_I
2766 #undef HI_IDX
2767 #undef LO_IDX
2768
2769 /*****************************************************************************/
2770 /* SPE extension helpers */
2771 /* Use a table to make this quicker */
2772 static uint8_t hbrev[16] = {
2773 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2774 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2775 };
2776
2777 static always_inline uint8_t byte_reverse (uint8_t val)
2778 {
2779 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2780 }
2781
2782 static always_inline uint32_t word_reverse (uint32_t val)
2783 {
2784 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2785 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2786 }
2787
2788 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
2789 target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
2790 {
2791 uint32_t a, b, d, mask;
2792
2793 mask = UINT32_MAX >> (32 - MASKBITS);
2794 a = arg1 & mask;
2795 b = arg2 & mask;
2796 d = word_reverse(1 + word_reverse(a | ~b));
2797 return (arg1 & ~mask) | (d & b);
2798 }
2799
2800 uint32_t helper_cntlsw32 (uint32_t val)
2801 {
2802 if (val & 0x80000000)
2803 return clz32(~val);
2804 else
2805 return clz32(val);
2806 }
2807
2808 uint32_t helper_cntlzw32 (uint32_t val)
2809 {
2810 return clz32(val);
2811 }
2812
2813 /* Single-precision floating-point conversions */
2814 static always_inline uint32_t efscfsi (uint32_t val)
2815 {
2816 CPU_FloatU u;
2817
2818 u.f = int32_to_float32(val, &env->spe_status);
2819
2820 return u.l;
2821 }
2822
2823 static always_inline uint32_t efscfui (uint32_t val)
2824 {
2825 CPU_FloatU u;
2826
2827 u.f = uint32_to_float32(val, &env->spe_status);
2828
2829 return u.l;
2830 }
2831
2832 static always_inline int32_t efsctsi (uint32_t val)
2833 {
2834 CPU_FloatU u;
2835
2836 u.l = val;
2837 /* NaN are not treated the same way IEEE 754 does */
2838 if (unlikely(float32_is_nan(u.f)))
2839 return 0;
2840
2841 return float32_to_int32(u.f, &env->spe_status);
2842 }
2843
2844 static always_inline uint32_t efsctui (uint32_t val)
2845 {
2846 CPU_FloatU u;
2847
2848 u.l = val;
2849 /* NaN are not treated the same way IEEE 754 does */
2850 if (unlikely(float32_is_nan(u.f)))
2851 return 0;
2852
2853 return float32_to_uint32(u.f, &env->spe_status);
2854 }
2855
2856 static always_inline uint32_t efsctsiz (uint32_t val)
2857 {
2858 CPU_FloatU u;
2859
2860 u.l = val;
2861 /* NaN are not treated the same way IEEE 754 does */
2862 if (unlikely(float32_is_nan(u.f)))
2863 return 0;
2864
2865 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2866 }
2867
2868 static always_inline uint32_t efsctuiz (uint32_t val)
2869 {
2870 CPU_FloatU u;
2871
2872 u.l = val;
2873 /* NaN are not treated the same way IEEE 754 does */
2874 if (unlikely(float32_is_nan(u.f)))
2875 return 0;
2876
2877 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2878 }
2879
2880 static always_inline uint32_t efscfsf (uint32_t val)
2881 {
2882 CPU_FloatU u;
2883 float32 tmp;
2884
2885 u.f = int32_to_float32(val, &env->spe_status);
2886 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2887 u.f = float32_div(u.f, tmp, &env->spe_status);
2888
2889 return u.l;
2890 }
2891
2892 static always_inline uint32_t efscfuf (uint32_t val)
2893 {
2894 CPU_FloatU u;
2895 float32 tmp;
2896
2897 u.f = uint32_to_float32(val, &env->spe_status);
2898 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2899 u.f = float32_div(u.f, tmp, &env->spe_status);
2900
2901 return u.l;
2902 }
2903
2904 static always_inline uint32_t efsctsf (uint32_t val)
2905 {
2906 CPU_FloatU u;
2907 float32 tmp;
2908
2909 u.l = val;
2910 /* NaN are not treated the same way IEEE 754 does */
2911 if (unlikely(float32_is_nan(u.f)))
2912 return 0;
2913 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2914 u.f = float32_mul(u.f, tmp, &env->spe_status);
2915
2916 return float32_to_int32(u.f, &env->spe_status);
2917 }
2918
2919 static always_inline uint32_t efsctuf (uint32_t val)
2920 {
2921 CPU_FloatU u;
2922 float32 tmp;
2923
2924 u.l = val;
2925 /* NaN are not treated the same way IEEE 754 does */
2926 if (unlikely(float32_is_nan(u.f)))
2927 return 0;
2928 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2929 u.f = float32_mul(u.f, tmp, &env->spe_status);
2930
2931 return float32_to_uint32(u.f, &env->spe_status);
2932 }
2933
2934 #define HELPER_SPE_SINGLE_CONV(name) \
2935 uint32_t helper_e##name (uint32_t val) \
2936 { \
2937 return e##name(val); \
2938 }
2939 /* efscfsi */
2940 HELPER_SPE_SINGLE_CONV(fscfsi);
2941 /* efscfui */
2942 HELPER_SPE_SINGLE_CONV(fscfui);
2943 /* efscfuf */
2944 HELPER_SPE_SINGLE_CONV(fscfuf);
2945 /* efscfsf */
2946 HELPER_SPE_SINGLE_CONV(fscfsf);
2947 /* efsctsi */
2948 HELPER_SPE_SINGLE_CONV(fsctsi);
2949 /* efsctui */
2950 HELPER_SPE_SINGLE_CONV(fsctui);
2951 /* efsctsiz */
2952 HELPER_SPE_SINGLE_CONV(fsctsiz);
2953 /* efsctuiz */
2954 HELPER_SPE_SINGLE_CONV(fsctuiz);
2955 /* efsctsf */
2956 HELPER_SPE_SINGLE_CONV(fsctsf);
2957 /* efsctuf */
2958 HELPER_SPE_SINGLE_CONV(fsctuf);
2959
2960 #define HELPER_SPE_VECTOR_CONV(name) \
2961 uint64_t helper_ev##name (uint64_t val) \
2962 { \
2963 return ((uint64_t)e##name(val >> 32) << 32) | \
2964 (uint64_t)e##name(val); \
2965 }
2966 /* evfscfsi */
2967 HELPER_SPE_VECTOR_CONV(fscfsi);
2968 /* evfscfui */
2969 HELPER_SPE_VECTOR_CONV(fscfui);
2970 /* evfscfuf */
2971 HELPER_SPE_VECTOR_CONV(fscfuf);
2972 /* evfscfsf */
2973 HELPER_SPE_VECTOR_CONV(fscfsf);
2974 /* evfsctsi */
2975 HELPER_SPE_VECTOR_CONV(fsctsi);
2976 /* evfsctui */
2977 HELPER_SPE_VECTOR_CONV(fsctui);
2978 /* evfsctsiz */
2979 HELPER_SPE_VECTOR_CONV(fsctsiz);
2980 /* evfsctuiz */
2981 HELPER_SPE_VECTOR_CONV(fsctuiz);
2982 /* evfsctsf */
2983 HELPER_SPE_VECTOR_CONV(fsctsf);
2984 /* evfsctuf */
2985 HELPER_SPE_VECTOR_CONV(fsctuf);
2986
2987 /* Single-precision floating-point arithmetic */
2988 static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
2989 {
2990 CPU_FloatU u1, u2;
2991 u1.l = op1;
2992 u2.l = op2;
2993 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2994 return u1.l;
2995 }
2996
2997 static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
2998 {
2999 CPU_FloatU u1, u2;
3000 u1.l = op1;
3001 u2.l = op2;
3002 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
3003 return u1.l;
3004 }
3005
3006 static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
3007 {
3008 CPU_FloatU u1, u2;
3009 u1.l = op1;
3010 u2.l = op2;
3011 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
3012 return u1.l;
3013 }
3014
3015 static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
3016 {
3017 CPU_FloatU u1, u2;
3018 u1.l = op1;
3019 u2.l = op2;
3020 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
3021 return u1.l;
3022 }
3023
3024 #define HELPER_SPE_SINGLE_ARITH(name) \
3025 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
3026 { \
3027 return e##name(op1, op2); \
3028 }
3029 /* efsadd */
3030 HELPER_SPE_SINGLE_ARITH(fsadd);
3031 /* efssub */
3032 HELPER_SPE_SINGLE_ARITH(fssub);
3033 /* efsmul */
3034 HELPER_SPE_SINGLE_ARITH(fsmul);
3035 /* efsdiv */
3036 HELPER_SPE_SINGLE_ARITH(fsdiv);
3037
3038 #define HELPER_SPE_VECTOR_ARITH(name) \
3039 uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
3040 { \
3041 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
3042 (uint64_t)e##name(op1, op2); \
3043 }
3044 /* evfsadd */
3045 HELPER_SPE_VECTOR_ARITH(fsadd);
3046 /* evfssub */
3047 HELPER_SPE_VECTOR_ARITH(fssub);
3048 /* evfsmul */
3049 HELPER_SPE_VECTOR_ARITH(fsmul);
3050 /* evfsdiv */
3051 HELPER_SPE_VECTOR_ARITH(fsdiv);
3052
3053 /* Single-precision floating-point comparisons */
3054 static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
3055 {
3056 CPU_FloatU u1, u2;
3057 u1.l = op1;
3058 u2.l = op2;
3059 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
3060 }
3061
3062 static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
3063 {
3064 CPU_FloatU u1, u2;
3065 u1.l = op1;
3066 u2.l = op2;
3067 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
3068 }
3069
3070 static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
3071 {
3072 CPU_FloatU u1, u2;
3073 u1.l = op1;
3074 u2.l = op2;
3075 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
3076 }
3077
3078 static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
3079 {
3080 /* XXX: TODO: test special values (NaN, infinites, ...) */
3081 return efststlt(op1, op2);
3082 }
3083
3084 static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
3085 {
3086 /* XXX: TODO: test special values (NaN, infinites, ...) */
3087 return efststgt(op1, op2);
3088 }
3089
3090 static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
3091 {
3092 /* XXX: TODO: test special values (NaN, infinites, ...) */
3093 return efststeq(op1, op2);
3094 }
3095
3096 #define HELPER_SINGLE_SPE_CMP(name) \
3097 uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
3098 { \
3099 return e##name(op1, op2) << 2; \
3100 }
3101 /* efststlt */
3102 HELPER_SINGLE_SPE_CMP(fststlt);
3103 /* efststgt */
3104 HELPER_SINGLE_SPE_CMP(fststgt);
3105 /* efststeq */
3106 HELPER_SINGLE_SPE_CMP(fststeq);
3107 /* efscmplt */
3108 HELPER_SINGLE_SPE_CMP(fscmplt);
3109 /* efscmpgt */
3110 HELPER_SINGLE_SPE_CMP(fscmpgt);
3111 /* efscmpeq */
3112 HELPER_SINGLE_SPE_CMP(fscmpeq);
3113
3114 static always_inline uint32_t evcmp_merge (int t0, int t1)
3115 {
3116 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
3117 }
3118
3119 #define HELPER_VECTOR_SPE_CMP(name) \
3120 uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
3121 { \
3122 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
3123 }
3124 /* evfststlt */
3125 HELPER_VECTOR_SPE_CMP(fststlt);
3126 /* evfststgt */
3127 HELPER_VECTOR_SPE_CMP(fststgt);
3128 /* evfststeq */
3129 HELPER_VECTOR_SPE_CMP(fststeq);
3130 /* evfscmplt */
3131 HELPER_VECTOR_SPE_CMP(fscmplt);
3132 /* evfscmpgt */
3133 HELPER_VECTOR_SPE_CMP(fscmpgt);
3134 /* evfscmpeq */
3135 HELPER_VECTOR_SPE_CMP(fscmpeq);
3136
3137 /* Double-precision floating-point conversion */
3138 uint64_t helper_efdcfsi (uint32_t val)
3139 {
3140 CPU_DoubleU u;
3141
3142 u.d = int32_to_float64(val, &env->spe_status);
3143
3144 return u.ll;
3145 }
3146
3147 uint64_t helper_efdcfsid (uint64_t val)
3148 {
3149 CPU_DoubleU u;
3150
3151 u.d = int64_to_float64(val, &env->spe_status);
3152
3153 return u.ll;
3154 }
3155
3156 uint64_t helper_efdcfui (uint32_t val)
3157 {
3158 CPU_DoubleU u;
3159
3160 u.d = uint32_to_float64(val, &env->spe_status);
3161
3162 return u.ll;
3163 }
3164
3165 uint64_t helper_efdcfuid (uint64_t val)
3166 {
3167 CPU_DoubleU u;
3168
3169 u.d = uint64_to_float64(val, &env->spe_status);
3170
3171 return u.ll;
3172 }
3173
3174 uint32_t helper_efdctsi (uint64_t val)
3175 {
3176 CPU_DoubleU u;
3177
3178 u.ll = val;
3179 /* NaN are not treated the same way IEEE 754 does */
3180 if (unlikely(float64_is_nan(u.d)))
3181 return 0;
3182
3183 return float64_to_int32(u.d, &env->spe_status);
3184 }
3185
3186 uint32_t helper_efdctui (uint64_t val)
3187 {
3188 CPU_DoubleU u;
3189
3190 u.ll = val;
3191 /* NaN are not treated the same way IEEE 754 does */
3192 if (unlikely(float64_is_nan(u.d)))
3193 return 0;
3194
3195 return float64_to_uint32(u.d, &env->spe_status);
3196 }
3197
3198 uint32_t helper_efdctsiz (uint64_t val)
3199 {
3200 CPU_DoubleU u;
3201
3202 u.ll = val;
3203 /* NaN are not treated the same way IEEE 754 does */
3204 if (unlikely(float64_is_nan(u.d)))
3205 return 0;
3206
3207 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
3208 }
3209
3210 uint64_t helper_efdctsidz (uint64_t val)
3211 {
3212 CPU_DoubleU u;
3213
3214 u.ll = val;
3215 /* NaN are not treated the same way IEEE 754 does */
3216 if (unlikely(float64_is_nan(u.d)))
3217 return 0;
3218
3219 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
3220 }
3221
3222 uint32_t helper_efdctuiz (uint64_t val)
3223 {
3224 CPU_DoubleU u;
3225
3226 u.ll = val;
3227 /* NaN are not treated the same way IEEE 754 does */
3228 if (unlikely(float64_is_nan(u.d)))
3229 return 0;
3230
3231 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
3232 }
3233
3234 uint64_t helper_efdctuidz (uint64_t val)
3235 {
3236 CPU_DoubleU u;
3237
3238 u.ll = val;
3239 /* NaN are not treated the same way IEEE 754 does */
3240 if (unlikely(float64_is_nan(u.d)))
3241 return 0;
3242
3243 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
3244 }
3245
3246 uint64_t helper_efdcfsf (uint32_t val)
3247 {
3248 CPU_DoubleU u;
3249 float64 tmp;
3250
3251 u.d = int32_to_float64(val, &env->spe_status);
3252 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
3253 u.d = float64_div(u.d, tmp, &env->spe_status);
3254
3255 return u.ll;
3256 }
3257
3258 uint64_t helper_efdcfuf (uint32_t val)
3259 {
3260 CPU_DoubleU u;
3261 float64 tmp;
3262
3263 u.d = uint32_to_float64(val, &env->spe_status);
3264 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
3265 u.d = float64_div(u.d, tmp, &env->spe_status);
3266
3267 return u.ll;
3268 }
3269
3270 uint32_t helper_efdctsf (uint64_t val)
3271 {
3272 CPU_DoubleU u;
3273 float64 tmp;
3274
3275 u.ll = val;
3276 /* NaN are not treated the same way IEEE 754 does */
3277 if (unlikely(float64_is_nan(u.d)))
3278 return 0;
3279 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
3280 u.d = float64_mul(u.d, tmp, &env->spe_status);
3281
3282 return float64_to_int32(u.d, &env->spe_status);
3283 }
3284
3285 uint32_t helper_efdctuf (uint64_t val)
3286 {
3287 CPU_DoubleU u;
3288 float64 tmp;
3289
3290 u.ll = val;
3291 /* NaN are not treated the same way IEEE 754 does */
3292 if (unlikely(float64_is_nan(u.d)))
3293 return 0;
3294 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
3295 u.d = float64_mul(u.d, tmp, &env->spe_status);
3296
3297 return float64_to_uint32(u.d, &env->spe_status);
3298 }
3299
3300 uint32_t helper_efscfd (uint64_t val)
3301 {
3302 CPU_DoubleU u1;
3303 CPU_FloatU u2;
3304
3305 u1.ll = val;
3306 u2.f = float64_to_float32(u1.d, &env->spe_status);
3307
3308 return u2.l;
3309 }
3310
3311 uint64_t helper_efdcfs (uint32_t val)
3312 {
3313 CPU_DoubleU u2;
3314 CPU_FloatU u1;
3315
3316 u1.l = val;
3317 u2.d = float32_to_float64(u1.f, &env->spe_status);
3318
3319 return u2.ll;
3320 }
3321
3322 /* Double precision fixed-point arithmetic */
3323 uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
3324 {
3325 CPU_DoubleU u1, u2;
3326 u1.ll = op1;
3327 u2.ll = op2;
3328 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
3329 return u1.ll;
3330 }
3331
3332 uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
3333 {
3334 CPU_DoubleU u1, u2;
3335 u1.ll = op1;
3336 u2.ll = op2;
3337 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
3338 return u1.ll;
3339 }
3340
3341 uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
3342 {
3343 CPU_DoubleU u1, u2;
3344 u1.ll = op1;
3345 u2.ll = op2;
3346 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
3347 return u1.ll;
3348 }
3349
3350 uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
3351 {
3352 CPU_DoubleU u1, u2;
3353 u1.ll = op1;
3354 u2.ll = op2;
3355 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
3356 return u1.ll;
3357 }
3358
3359 /* Double precision floating point helpers */
3360 uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
3361 {
3362 CPU_DoubleU u1, u2;
3363 u1.ll = op1;
3364 u2.ll = op2;
3365 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
3366 }
3367
3368 uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
3369 {
3370 CPU_DoubleU u1, u2;
3371 u1.ll = op1;
3372 u2.ll = op2;
3373 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
3374 }
3375
3376 uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
3377 {
3378 CPU_DoubleU u1, u2;
3379 u1.ll = op1;
3380 u2.ll = op2;
3381 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
3382 }
3383
3384 uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
3385 {
3386 /* XXX: TODO: test special values (NaN, infinites, ...) */
3387 return helper_efdtstlt(op1, op2);
3388 }
3389
3390 uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
3391 {
3392 /* XXX: TODO: test special values (NaN, infinites, ...) */
3393 return helper_efdtstgt(op1, op2);
3394 }
3395
3396 uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
3397 {
3398 /* XXX: TODO: test special values (NaN, infinites, ...) */
3399 return helper_efdtsteq(op1, op2);
3400 }
3401
3402 /*****************************************************************************/
3403 /* Softmmu support */
3404 #if !defined (CONFIG_USER_ONLY)
3405
3406 #define MMUSUFFIX _mmu
3407
3408 #define SHIFT 0
3409 #include "softmmu_template.h"
3410
3411 #define SHIFT 1
3412 #include "softmmu_template.h"
3413
3414 #define SHIFT 2
3415 #include "softmmu_template.h"
3416
3417 #define SHIFT 3
3418 #include "softmmu_template.h"
3419
3420 /* try to fill the TLB and return an exception if error. If retaddr is
3421 NULL, it means that the function was called in C code (i.e. not
3422 from generated code or from helper.c) */
3423 /* XXX: fix it to restore all registers */
3424 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
3425 {
3426 TranslationBlock *tb;
3427 CPUState *saved_env;
3428 unsigned long pc;
3429 int ret;
3430
3431 /* XXX: hack to restore env in all cases, even if not called from
3432 generated code */
3433 saved_env = env;
3434 env = cpu_single_env;
3435 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
3436 if (unlikely(ret != 0)) {
3437 if (likely(retaddr)) {
3438 /* now we have a real cpu fault */
3439 pc = (unsigned long)retaddr;
3440 tb = tb_find_pc(pc);
3441 if (likely(tb)) {
3442 /* the PC is inside the translated code. It means that we have
3443 a virtual CPU fault */
3444 cpu_restore_state(tb, env, pc, NULL);
3445 }
3446 }
3447 helper_raise_exception_err(env->exception_index, env->error_code);
3448 }
3449 env = saved_env;
3450 }
3451
3452 /* Segment registers load and store */
3453 target_ulong helper_load_sr (target_ulong sr_num)
3454 {
3455 return env->sr[sr_num];
3456 }
3457
3458 void helper_store_sr (target_ulong sr_num, target_ulong val)
3459 {
3460 ppc_store_sr(env, sr_num, val);
3461 }
3462
3463 /* SLB management */
3464 #if defined(TARGET_PPC64)
3465 target_ulong helper_load_slb (target_ulong slb_nr)
3466 {
3467 return ppc_load_slb(env, slb_nr);
3468 }
3469
3470 void helper_store_slb (target_ulong slb_nr, target_ulong rs)
3471 {
3472 ppc_store_slb(env, slb_nr, rs);
3473 }
3474
3475 void helper_slbia (void)
3476 {
3477 ppc_slb_invalidate_all(env);
3478 }
3479
3480 void helper_slbie (target_ulong addr)
3481 {
3482 ppc_slb_invalidate_one(env, addr);
3483 }
3484
3485 #endif /* defined(TARGET_PPC64) */
3486
3487 /* TLB management */
3488 void helper_tlbia (void)
3489 {
3490 ppc_tlb_invalidate_all(env);
3491 }
3492
3493 void helper_tlbie (target_ulong addr)
3494 {
3495 ppc_tlb_invalidate_one(env, addr);
3496 }
3497
3498 /* Software driven TLBs management */
3499 /* PowerPC 602/603 software TLB load instructions helpers */
3500 static void do_6xx_tlb (target_ulong new_EPN, int is_code)
3501 {
3502 target_ulong RPN, CMP, EPN;
3503 int way;
3504
3505 RPN = env->spr[SPR_RPA];
3506 if (is_code) {
3507 CMP = env->spr[SPR_ICMP];
3508 EPN = env->spr[SPR_IMISS];
3509 } else {
3510 CMP = env->spr[SPR_DCMP];
3511 EPN = env->spr[SPR_DMISS];
3512 }
3513 way = (env->spr[SPR_SRR1] >> 17) & 1;
3514 #if defined (DEBUG_SOFTWARE_TLB)
3515 if (loglevel != 0) {
3516 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
3517 " PTE1 " ADDRX " way %d\n",
3518 __func__, new_EPN, EPN, CMP, RPN, way);
3519 }
3520 #endif
3521 /* Store this TLB */
3522 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
3523 way, is_code, CMP, RPN);
3524 }
3525
3526 void helper_6xx_tlbd (target_ulong EPN)
3527 {
3528 do_6xx_tlb(EPN, 0);
3529 }
3530
3531 void helper_6xx_tlbi (target_ulong EPN)
3532 {
3533 do_6xx_tlb(EPN, 1);
3534 }
3535
3536 /* PowerPC 74xx software TLB load instructions helpers */
3537 static void do_74xx_tlb (target_ulong new_EPN, int is_code)
3538 {
3539 target_ulong RPN, CMP, EPN;
3540 int way;
3541
3542 RPN = env->spr[SPR_PTELO];
3543 CMP = env->spr[SPR_PTEHI];
3544 EPN = env->spr[SPR_TLBMISS] & ~0x3;
3545 way = env->spr[SPR_TLBMISS] & 0x3;
3546 #if defined (DEBUG_SOFTWARE_TLB)
3547 if (loglevel != 0) {
3548 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
3549 " PTE1 " ADDRX " way %d\n",
3550 __func__, new_EPN, EPN, CMP, RPN, way);
3551 }
3552 #endif
3553 /* Store this TLB */
3554 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
3555 way, is_code, CMP, RPN);
3556 }
3557
3558 void helper_74xx_tlbd (target_ulong EPN)
3559 {
3560 do_74xx_tlb(EPN, 0);
3561 }
3562
3563 void helper_74xx_tlbi (target_ulong EPN)
3564 {
3565 do_74xx_tlb(EPN, 1);
3566 }
3567
3568 static always_inline target_ulong booke_tlb_to_page_size (int size)
3569 {
3570 return 1024 << (2 * size);
3571 }
3572
3573 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
3574 {
3575 int size;
3576
3577 switch (page_size) {
3578 case 0x00000400UL:
3579 size = 0x0;
3580 break;
3581 case 0x00001000UL:
3582 size = 0x1;
3583 break;
3584 case 0x00004000UL:
3585 size = 0x2;
3586 break;
3587 case 0x00010000UL:
3588 size = 0x3;
3589 break;
3590 case 0x00040000UL:
3591 size = 0x4;
3592 break;
3593 case 0x00100000UL:
3594 size = 0x5;
3595 break;
3596 case 0x00400000UL:
3597 size = 0x6;
3598 break;
3599 case 0x01000000UL:
3600 size = 0x7;
3601 break;
3602 case 0x04000000UL:
3603 size = 0x8;
3604 break;
3605 case 0x10000000UL:
3606 size = 0x9;
3607 break;
3608 case 0x40000000UL:
3609 size = 0xA;
3610 break;
3611 #if defined (TARGET_PPC64)
3612 case 0x000100000000ULL:
3613 size = 0xB;
3614 break;
3615 case 0x000400000000ULL:
3616 size = 0xC;
3617 break;
3618 case 0x001000000000ULL:
3619 size = 0xD;
3620 break;
3621 case 0x004000000000ULL:
3622 size = 0xE;
3623 break;
3624 case 0x010000000000ULL:
3625 size = 0xF;
3626 break;
3627 #endif
3628 default:
3629 size = -1;
3630 break;
3631 }
3632
3633 return size;
3634 }
3635
3636 /* Helpers for 4xx TLB management */
3637 target_ulong helper_4xx_tlbre_lo (target_ulong entry)
3638 {
3639 ppcemb_tlb_t *tlb;
3640 target_ulong ret;
3641 int size;
3642
3643 entry &= 0x3F;
3644 tlb = &env->tlb[entry].tlbe;
3645 ret = tlb->EPN;
3646 if (tlb->prot & PAGE_VALID)
3647 ret |= 0x400;
3648 size = booke_page_size_to_tlb(tlb->size);
3649 if (size < 0 || size > 0x7)
3650 size = 1;
3651 ret |= size << 7;
3652 env->spr[SPR_40x_PID] = tlb->PID;
3653 return ret;
3654 }
3655
3656 target_ulong helper_4xx_tlbre_hi (target_ulong entry)
3657 {
3658 ppcemb_tlb_t *tlb;
3659 target_ulong ret;
3660
3661 entry &= 0x3F;
3662 tlb = &env->tlb[entry].tlbe;
3663 ret = tlb->RPN;
3664 if (tlb->prot & PAGE_EXEC)
3665 ret |= 0x200;
3666 if (tlb->prot & PAGE_WRITE)
3667 ret |= 0x100;
3668 return ret;
3669 }
3670
3671 void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
3672 {
3673 ppcemb_tlb_t *tlb;
3674 target_ulong page, end;
3675
3676 #if defined (DEBUG_SOFTWARE_TLB)
3677 if (loglevel != 0) {
3678 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
3679 }
3680 #endif
3681 entry &= 0x3F;
3682 tlb = &env->tlb[entry].tlbe;
3683 /* Invalidate previous TLB (if it's valid) */
3684 if (tlb->prot & PAGE_VALID) {
3685 end = tlb->EPN + tlb->size;
3686 #if defined (DEBUG_SOFTWARE_TLB)
3687 if (loglevel != 0) {
3688 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
3689 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
3690 }
3691 #endif
3692 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
3693 tlb_flush_page(env, page);
3694 }
3695 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
3696 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
3697 * If this ever occurs, one should use the ppcemb target instead
3698 * of the ppc or ppc64 one
3699 */
3700 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
3701 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
3702 "are not supported (%d)\n",
3703 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
3704 }
3705 tlb->EPN = val & ~(tlb->size - 1);
3706 if (val & 0x40)
3707 tlb->prot |= PAGE_VALID;
3708 else
3709 tlb->prot &= ~PAGE_VALID;
3710 if (val & 0x20) {
3711 /* XXX: TO BE FIXED */
3712 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
3713 }
3714 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
3715 tlb->attr = val & 0xFF;
3716 #if defined (DEBUG_SOFTWARE_TLB)
3717 if (loglevel != 0) {
3718 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3719 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3720 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
3721 tlb->prot & PAGE_READ ? 'r' : '-',
3722 tlb->prot & PAGE_WRITE ? 'w' : '-',
3723 tlb->prot & PAGE_EXEC ? 'x' : '-',
3724 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3725 }
3726 #endif
3727 /* Invalidate new TLB (if valid) */
3728 if (tlb->prot & PAGE_VALID) {
3729 end = tlb->EPN + tlb->size;
3730 #if defined (DEBUG_SOFTWARE_TLB)
3731 if (loglevel != 0) {
3732 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
3733 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
3734 }
3735 #endif
3736 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
3737 tlb_flush_page(env, page);
3738 }
3739 }
3740
3741 void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
3742 {
3743 ppcemb_tlb_t *tlb;
3744
3745 #if defined (DEBUG_SOFTWARE_TLB)
3746 if (loglevel != 0) {
3747 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
3748 }
3749 #endif
3750 entry &= 0x3F;
3751 tlb = &env->tlb[entry].tlbe;
3752 tlb->RPN = val & 0xFFFFFC00;
3753 tlb->prot = PAGE_READ;
3754 if (val & 0x200)
3755 tlb->prot |= PAGE_EXEC;
3756 if (val & 0x100)
3757 tlb->prot |= PAGE_WRITE;
3758 #if defined (DEBUG_SOFTWARE_TLB)
3759 if (loglevel != 0) {
3760 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
3761 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
3762 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
3763 tlb->prot & PAGE_READ ? 'r' : '-',
3764 tlb->prot & PAGE_WRITE ? 'w' : '-',
3765 tlb->prot & PAGE_EXEC ? 'x' : '-',
3766 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3767 }
3768 #endif
3769 }
3770
3771 target_ulong helper_4xx_tlbsx (target_ulong address)
3772 {
3773 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
3774 }
3775
3776 /* PowerPC 440 TLB management */
3777 void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
3778 {
3779 ppcemb_tlb_t *tlb;
3780 target_ulong EPN, RPN, size;
3781 int do_flush_tlbs;
3782
3783 #if defined (DEBUG_SOFTWARE_TLB)
3784 if (loglevel != 0) {
3785 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
3786 __func__, word, (int)entry, value);
3787 }
3788 #endif
3789 do_flush_tlbs = 0;
3790 entry &= 0x3F;
3791 tlb = &env->tlb[entry].tlbe;
3792 switch (word) {
3793 default:
3794 /* Just here to please gcc */
3795 case 0:
3796 EPN = value & 0xFFFFFC00;
3797 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
3798 do_flush_tlbs = 1;
3799 tlb->EPN = EPN;
3800 size = booke_tlb_to_page_size((value >> 4) & 0xF);
3801 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3802 do_flush_tlbs = 1;
3803 tlb->size = size;
3804 tlb->attr &= ~0x1;
3805 tlb->attr |= (value >> 8) & 1;
3806 if (value & 0x200) {
3807 tlb->prot |= PAGE_VALID;
3808 } else {
3809 if (tlb->prot & PAGE_VALID) {
3810 tlb->prot &= ~PAGE_VALID;
3811 do_flush_tlbs = 1;
3812 }
3813 }
3814 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3815 if (do_flush_tlbs)
3816 tlb_flush(env, 1);
3817 break;
3818 case 1:
3819 RPN = value & 0xFFFFFC0F;
3820 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3821 tlb_flush(env, 1);
3822 tlb->RPN = RPN;
3823 break;
3824 case 2:
3825 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
3826 tlb->prot = tlb->prot & PAGE_VALID;
3827 if (value & 0x1)
3828 tlb->prot |= PAGE_READ << 4;
3829 if (value & 0x2)
3830 tlb->prot |= PAGE_WRITE << 4;
3831 if (value & 0x4)
3832 tlb->prot |= PAGE_EXEC << 4;
3833 if (value & 0x8)
3834 tlb->prot |= PAGE_READ;
3835 if (value & 0x10)
3836 tlb->prot |= PAGE_WRITE;
3837 if (value & 0x20)
3838 tlb->prot |= PAGE_EXEC;
3839 break;
3840 }
3841 }
3842
3843 target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
3844 {
3845 ppcemb_tlb_t *tlb;
3846 target_ulong ret;
3847 int size;
3848
3849 entry &= 0x3F;
3850 tlb = &env->tlb[entry].tlbe;
3851 switch (word) {
3852 default:
3853 /* Just here to please gcc */
3854 case 0:
3855 ret = tlb->EPN;
3856 size = booke_page_size_to_tlb(tlb->size);
3857 if (size < 0 || size > 0xF)
3858 size = 1;
3859 ret |= size << 4;
3860 if (tlb->attr & 0x1)
3861 ret |= 0x100;
3862 if (tlb->prot & PAGE_VALID)
3863 ret |= 0x200;
3864 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3865 env->spr[SPR_440_MMUCR] |= tlb->PID;
3866 break;
3867 case 1:
3868 ret = tlb->RPN;
3869 break;
3870 case 2:
3871 ret = tlb->attr & ~0x1;
3872 if (tlb->prot & (PAGE_READ << 4))
3873 ret |= 0x1;
3874 if (tlb->prot & (PAGE_WRITE << 4))
3875 ret |= 0x2;
3876 if (tlb->prot & (PAGE_EXEC << 4))
3877 ret |= 0x4;
3878 if (tlb->prot & PAGE_READ)
3879 ret |= 0x8;
3880 if (tlb->prot & PAGE_WRITE)
3881 ret |= 0x10;
3882 if (tlb->prot & PAGE_EXEC)
3883 ret |= 0x20;
3884 break;
3885 }
3886 return ret;
3887 }
3888
3889 target_ulong helper_440_tlbsx (target_ulong address)
3890 {
3891 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3892 }
3893
3894 #endif /* !CONFIG_USER_ONLY */
Samsung s3c2440 and arm920t support for the mini2440 dev board