cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_DEFS_H
  21 #define CPU_DEFS_H
  22
  23 #include "config.h"
  24 #include <setjmp.h>
  25 #include <inttypes.h>
  26 #include "osdep.h"
  27
  28 #ifndef TARGET_LONG_BITS
  29 #error TARGET_LONG_BITS must be defined before including this header
  30 #endif
  31
  32 #ifndef TARGET_PHYS_ADDR_BITS
  33 #if TARGET_LONG_BITS >= HOST_LONG_BITS
  34 #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
  35 #else
  36 #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
  37 #endif
  38 #endif
  39
  40 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
  41
  42 /* target_ulong is the type of a virtual address */
  43 #if TARGET_LONG_SIZE == 4
  44 typedef int32_t target_long;
  45 typedef uint32_t target_ulong;
  46 #define TARGET_FMT_lx "%08x"
  47 #define TARGET_FMT_ld "%d"
  48 #elif TARGET_LONG_SIZE == 8
  49 typedef int64_t target_long;
  50 typedef uint64_t target_ulong;
  51 #define TARGET_FMT_lx "%016" PRIx64
  52 #define TARGET_FMT_ld "%" PRId64
  53 #else
  54 #error TARGET_LONG_SIZE undefined
  55 #endif
  56
  57 /* target_phys_addr_t is the type of a physical address (its size can
  58    be different from 'target_ulong'). We have sizeof(target_phys_addr)
  59    = max(sizeof(unsigned long),
  60    sizeof(size_of_target_physical_address)) because we must pass a
  61    host pointer to memory operations in some cases */
  62
  63 #if TARGET_PHYS_ADDR_BITS == 32
  64 typedef uint32_t target_phys_addr_t;
  65 #elif TARGET_PHYS_ADDR_BITS == 64
  66 typedef uint64_t target_phys_addr_t;
  67 #else
  68 #error TARGET_PHYS_ADDR_BITS undefined
  69 #endif
  70
  71 /* address in the RAM (different from a physical address) */
  72 typedef unsigned long ram_addr_t;
  73
  74 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
  75
  76 #define EXCP_INTERRUPT  0x10000 /* async interruption */
  77 #define EXCP_HLT        0x10001 /* hlt instruction reached */
  78 #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
  79 #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
  80 #define MAX_BREAKPOINTS 32
  81 #define MAX_WATCHPOINTS 32
  82
  83 #define TB_JMP_CACHE_BITS 12
  84 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
  85
  86 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
  87    addresses on the same page.  The top bits are the same.  This allows
  88    TLB invalidation to quickly clear a subset of the hash table.  */
  89 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
  90 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
  91 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
  92 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
  93
  94 #define CPU_TLB_BITS 8
  95 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
  96
  97 typedef struct CPUTLBEntry {
  98     /* bit 31 to TARGET_PAGE_BITS : virtual address
  99        bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
 100                                               zone number
 101        bit 3                      : indicates that the entry is invalid
 102        bit 2..0                   : zero
 103     */
 104     target_ulong addr_read;
 105     target_ulong addr_write;
 106     target_ulong addr_code;
 107     /* addend to virtual address to get physical address */
 108     target_phys_addr_t addend;
 109 } CPUTLBEntry;
 110
 111 /* Alpha has 4 different running levels */
 112 #if defined(TARGET_ALPHA)
 113 #define NB_MMU_MODES 4
 114 #elif defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
 115 #define NB_MMU_MODES 3
 116 #else
 117 #define NB_MMU_MODES 2
 118 #endif
 119
 120 #define CPU_COMMON                                                      \
 121     struct TranslationBlock *current_tb; /* currently executing TB  */  \
 122     /* soft mmu support */                                              \
 123     /* in order to avoid passing too many arguments to the memory       \
 124        write helpers, we store some rarely used information in the CPU  \
 125        context) */                                                      \
 126     unsigned long mem_write_pc; /* host pc at which the memory was      \
 127                                    written */                           \
 128     target_ulong mem_write_vaddr; /* target virtual addr at which the   \
 129                                      memory was written */              \
 130     /* 0 = kernel, 1 = user */                                          \
 131     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
 132     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
 133                                                                         \
 134     /* from this point: preserved by CPU reset */                       \
 135     /* ice debug support */                                             \
 136     target_ulong breakpoints[MAX_BREAKPOINTS];                          \
 137     int nb_breakpoints;                                                 \
 138     int singlestep_enabled;                                             \
 139                                                                         \
 140     struct {                                                            \
 141         target_ulong vaddr;                                             \
 142         int is_ram;                                                     \
 143     } watchpoint[MAX_WATCHPOINTS];                                      \
 144     int nb_watchpoints;                                                 \
 145     int watchpoint_hit;                                                 \
 146                                                                         \
 147     void *next_cpu; /* next CPU sharing TB cache */                     \
 148     int cpu_index; /* CPU index (informative) */                        \
 149     /* user data */                                                     \
 150     void *opaque;
 151
 152 #endif