hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "qemu-timer.h"
  23
  24 //#define DEBUG_APIC
  25 //#define DEBUG_IOAPIC
  26
  27 /* APIC Local Vector Table */
  28 #define APIC_LVT_TIMER   0
  29 #define APIC_LVT_THERMAL 1
  30 #define APIC_LVT_PERFORM 2
  31 #define APIC_LVT_LINT0   3
  32 #define APIC_LVT_LINT1   4
  33 #define APIC_LVT_ERROR   5
  34 #define APIC_LVT_NB      6
  35
  36 /* APIC delivery modes */
  37 #define APIC_DM_FIXED   0
  38 #define APIC_DM_LOWPRI  1
  39 #define APIC_DM_SMI     2
  40 #define APIC_DM_NMI     4
  41 #define APIC_DM_INIT    5
  42 #define APIC_DM_SIPI    6
  43 #define APIC_DM_EXTINT  7
  44
  45 /* APIC destination mode */
  46 #define APIC_DESTMODE_FLAT      0xf
  47 #define APIC_DESTMODE_CLUSTER   1
  48
  49 #define APIC_TRIGGER_EDGE  0
  50 #define APIC_TRIGGER_LEVEL 1
  51
  52 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  53 #define APIC_LVT_MASKED                 (1<<16)
  54 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  55 #define APIC_LVT_REMOTE_IRR             (1<<14)
  56 #define APIC_INPUT_POLARITY             (1<<13)
  57 #define APIC_SEND_PENDING               (1<<12)
  58
  59 #define IOAPIC_NUM_PINS                 0x18
  60
  61 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  62
  63 #define APIC_SV_ENABLE (1 << 8)
  64
  65 #define MAX_APICS 255
  66 #define MAX_APIC_WORDS 8
  67
  68 typedef struct APICState {
  69     CPUState *cpu_env;
  70     uint32_t apicbase;
  71     uint8_t id;
  72     uint8_t arb_id;
  73     uint8_t tpr;
  74     uint32_t spurious_vec;
  75     uint8_t log_dest;
  76     uint8_t dest_mode;
  77     uint32_t isr[8];  /* in service register */
  78     uint32_t tmr[8];  /* trigger mode register */
  79     uint32_t irr[8]; /* interrupt request register */
  80     uint32_t lvt[APIC_LVT_NB];
  81     uint32_t esr; /* error register */
  82     uint32_t icr[2];
  83
  84     uint32_t divide_conf;
  85     int count_shift;
  86     uint32_t initial_count;
  87     int64_t initial_count_load_time, next_time;
  88     QEMUTimer *timer;
  89 } APICState;
  90
  91 struct IOAPICState {
  92     uint8_t id;
  93     uint8_t ioregsel;
  94
  95     uint32_t irr;
  96     uint64_t ioredtbl[IOAPIC_NUM_PINS];
  97 };
  98
  99 static int apic_io_memory;
 100 static APICState *local_apics[MAX_APICS + 1];
 101 static int last_apic_id = 0;
 102
 103 static void apic_init_ipi(APICState *s);
 104 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 105 static void apic_update_irq(APICState *s);
 106
 107 /* Find first bit starting from msb. Return 0 if value = 0 */
 108 static int fls_bit(uint32_t value)
 109 {
 110     unsigned int ret = 0;
 111
 112 #if defined(HOST_I386)
 113     __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
 114     return ret;
 115 #else
 116     if (value > 0xffff)
 117         value >>= 16, ret = 16;
 118     if (value > 0xff)
 119         value >>= 8, ret += 8;
 120     if (value > 0xf)
 121         value >>= 4, ret += 4;
 122     if (value > 0x3)
 123         value >>= 2, ret += 2;
 124     return ret + (value >> 1);
 125 #endif
 126 }
 127
 128 /* Find first bit starting from lsb. Return 0 if value = 0 */
 129 static int ffs_bit(uint32_t value)
 130 {
 131     unsigned int ret = 0;
 132
 133 #if defined(HOST_I386)
 134     __asm__ __volatile__ ("bsf %1, %0\n" : "+r" (ret) : "rm" (value));
 135     return ret;
 136 #else
 137     if (!value)
 138         return 0;
 139     if (!(value & 0xffff))
 140         value >>= 16, ret = 16;
 141     if (!(value & 0xff))
 142         value >>= 8, ret += 8;
 143     if (!(value & 0xf))
 144         value >>= 4, ret += 4;
 145     if (!(value & 0x3))
 146         value >>= 2, ret += 2;
 147     if (!(value & 0x1))
 148         ret++;
 149     return ret;
 150 #endif
 151 }
 152
 153 static inline void set_bit(uint32_t *tab, int index)
 154 {
 155     int i, mask;
 156     i = index >> 5;
 157     mask = 1 << (index & 0x1f);
 158     tab[i] |= mask;
 159 }
 160
 161 static inline void reset_bit(uint32_t *tab, int index)
 162 {
 163     int i, mask;
 164     i = index >> 5;
 165     mask = 1 << (index & 0x1f);
 166     tab[i] &= ~mask;
 167 }
 168
 169 void apic_local_deliver(CPUState *env, int vector)
 170 {
 171     APICState *s = env->apic_state;
 172     uint32_t lvt = s->lvt[vector];
 173     int trigger_mode;
 174
 175     if (lvt & APIC_LVT_MASKED)
 176         return;
 177
 178     switch ((lvt >> 8) & 7) {
 179     case APIC_DM_SMI:
 180         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 181         break;
 182
 183     case APIC_DM_NMI:
 184         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 185         break;
 186
 187     case APIC_DM_EXTINT:
 188         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 189         break;
 190
 191     case APIC_DM_FIXED:
 192         trigger_mode = APIC_TRIGGER_EDGE;
 193         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 194             (lvt & APIC_LVT_LEVEL_TRIGGER))
 195             trigger_mode = APIC_TRIGGER_LEVEL;
 196         apic_set_irq(s, lvt & 0xff, trigger_mode);
 197     }
 198 }
 199
 200 #define foreach_apic(apic, deliver_bitmask, code) \
 201 {\
 202     int __i, __j, __mask;\
 203     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 204         __mask = deliver_bitmask[__i];\
 205         if (__mask) {\
 206             for(__j = 0; __j < 32; __j++) {\
 207                 if (__mask & (1 << __j)) {\
 208                     apic = local_apics[__i * 32 + __j];\
 209                     if (apic) {\
 210                         code;\
 211                     }\
 212                 }\
 213             }\
 214         }\
 215     }\
 216 }
 217
 218 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 219                              uint8_t delivery_mode,
 220                              uint8_t vector_num, uint8_t polarity,
 221                              uint8_t trigger_mode)
 222 {
 223     APICState *apic_iter;
 224
 225     switch (delivery_mode) {
 226         case APIC_DM_LOWPRI:
 227             /* XXX: search for focus processor, arbitration */
 228             {
 229                 int i, d;
 230                 d = -1;
 231                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 232                     if (deliver_bitmask[i]) {
 233                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 234                         break;
 235                     }
 236                 }
 237                 if (d >= 0) {
 238                     apic_iter = local_apics[d];
 239                     if (apic_iter) {
 240                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 241                     }
 242                 }
 243             }
 244             return;
 245
 246         case APIC_DM_FIXED:
 247             break;
 248
 249         case APIC_DM_SMI:
 250             foreach_apic(apic_iter, deliver_bitmask,
 251                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 252             return;
 253
 254         case APIC_DM_NMI:
 255             foreach_apic(apic_iter, deliver_bitmask,
 256                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 257             return;
 258
 259         case APIC_DM_INIT:
 260             /* normal INIT IPI sent to processors */
 261             foreach_apic(apic_iter, deliver_bitmask,
 262                          apic_init_ipi(apic_iter) );
 263             return;
 264
 265         case APIC_DM_EXTINT:
 266             /* handled in I/O APIC code */
 267             break;
 268
 269         default:
 270             return;
 271     }
 272
 273     foreach_apic(apic_iter, deliver_bitmask,
 274                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 275 }
 276
 277 void cpu_set_apic_base(CPUState *env, uint64_t val)
 278 {
 279     APICState *s = env->apic_state;
 280 #ifdef DEBUG_APIC
 281     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 282 #endif
 283     s->apicbase = (val & 0xfffff000) |
 284         (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 285     /* if disabled, cannot be enabled again */
 286     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 287         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 288         env->cpuid_features &= ~CPUID_APIC;
 289         s->spurious_vec &= ~APIC_SV_ENABLE;
 290     }
 291 }
 292
 293 uint64_t cpu_get_apic_base(CPUState *env)
 294 {
 295     APICState *s = env->apic_state;
 296 #ifdef DEBUG_APIC
 297     printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
 298 #endif
 299     return s->apicbase;
 300 }
 301
 302 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 303 {
 304     APICState *s = env->apic_state;
 305     s->tpr = (val & 0x0f) << 4;
 306     apic_update_irq(s);
 307 }
 308
 309 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 310 {
 311     APICState *s = env->apic_state;
 312     return s->tpr >> 4;
 313 }
 314
 315 /* return -1 if no bit is set */
 316 static int get_highest_priority_int(uint32_t *tab)
 317 {
 318     int i;
 319     for(i = 7; i >= 0; i--) {
 320         if (tab[i] != 0) {
 321             return i * 32 + fls_bit(tab[i]);
 322         }
 323     }
 324     return -1;
 325 }
 326
 327 static int apic_get_ppr(APICState *s)
 328 {
 329     int tpr, isrv, ppr;
 330
 331     tpr = (s->tpr >> 4);
 332     isrv = get_highest_priority_int(s->isr);
 333     if (isrv < 0)
 334         isrv = 0;
 335     isrv >>= 4;
 336     if (tpr >= isrv)
 337         ppr = s->tpr;
 338     else
 339         ppr = isrv << 4;
 340     return ppr;
 341 }
 342
 343 static int apic_get_arb_pri(APICState *s)
 344 {
 345     /* XXX: arbitration */
 346     return 0;
 347 }
 348
 349 /* signal the CPU if an irq is pending */
 350 static void apic_update_irq(APICState *s)
 351 {
 352     int irrv, ppr;
 353     if (!(s->spurious_vec & APIC_SV_ENABLE))
 354         return;
 355     irrv = get_highest_priority_int(s->irr);
 356     if (irrv < 0)
 357         return;
 358     ppr = apic_get_ppr(s);
 359     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 360         return;
 361     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 362 }
 363
 364 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 365 {
 366     set_bit(s->irr, vector_num);
 367     if (trigger_mode)
 368         set_bit(s->tmr, vector_num);
 369     else
 370         reset_bit(s->tmr, vector_num);
 371     apic_update_irq(s);
 372 }
 373
 374 static void apic_eoi(APICState *s)
 375 {
 376     int isrv;
 377     isrv = get_highest_priority_int(s->isr);
 378     if (isrv < 0)
 379         return;
 380     reset_bit(s->isr, isrv);
 381     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 382             set the remote IRR bit for level triggered interrupts. */
 383     apic_update_irq(s);
 384 }
 385
 386 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 387                                       uint8_t dest, uint8_t dest_mode)
 388 {
 389     APICState *apic_iter;
 390     int i;
 391
 392     if (dest_mode == 0) {
 393         if (dest == 0xff) {
 394             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 395         } else {
 396             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 397             set_bit(deliver_bitmask, dest);
 398         }
 399     } else {
 400         /* XXX: cluster mode */
 401         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 402         for(i = 0; i < MAX_APICS; i++) {
 403             apic_iter = local_apics[i];
 404             if (apic_iter) {
 405                 if (apic_iter->dest_mode == 0xf) {
 406                     if (dest & apic_iter->log_dest)
 407                         set_bit(deliver_bitmask, i);
 408                 } else if (apic_iter->dest_mode == 0x0) {
 409                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 410                         (dest & apic_iter->log_dest & 0x0f)) {
 411                         set_bit(deliver_bitmask, i);
 412                     }
 413                 }
 414             }
 415         }
 416     }
 417 }
 418
 419
 420 static void apic_init_ipi(APICState *s)
 421 {
 422     int i;
 423
 424     s->tpr = 0;
 425     s->spurious_vec = 0xff;
 426     s->log_dest = 0;
 427     s->dest_mode = 0xf;
 428     memset(s->isr, 0, sizeof(s->isr));
 429     memset(s->tmr, 0, sizeof(s->tmr));
 430     memset(s->irr, 0, sizeof(s->irr));
 431     for(i = 0; i < APIC_LVT_NB; i++)
 432         s->lvt[i] = 1 << 16; /* mask LVT */
 433     s->esr = 0;
 434     memset(s->icr, 0, sizeof(s->icr));
 435     s->divide_conf = 0;
 436     s->count_shift = 0;
 437     s->initial_count = 0;
 438     s->initial_count_load_time = 0;
 439     s->next_time = 0;
 440 }
 441
 442 /* send a SIPI message to the CPU to start it */
 443 static void apic_startup(APICState *s, int vector_num)
 444 {
 445     CPUState *env = s->cpu_env;
 446     if (!env->halted)
 447         return;
 448     env->eip = 0;
 449     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
 450                            0xffff, 0);
 451     env->halted = 0;
 452 }
 453
 454 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 455                          uint8_t delivery_mode, uint8_t vector_num,
 456                          uint8_t polarity, uint8_t trigger_mode)
 457 {
 458     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 459     int dest_shorthand = (s->icr[0] >> 18) & 3;
 460     APICState *apic_iter;
 461
 462     switch (dest_shorthand) {
 463     case 0:
 464         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 465         break;
 466     case 1:
 467         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 468         set_bit(deliver_bitmask, s->id);
 469         break;
 470     case 2:
 471         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 472         break;
 473     case 3:
 474         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 475         reset_bit(deliver_bitmask, s->id);
 476         break;
 477     }
 478
 479     switch (delivery_mode) {
 480         case APIC_DM_INIT:
 481             {
 482                 int trig_mode = (s->icr[0] >> 15) & 1;
 483                 int level = (s->icr[0] >> 14) & 1;
 484                 if (level == 0 && trig_mode == 1) {
 485                     foreach_apic(apic_iter, deliver_bitmask,
 486                                  apic_iter->arb_id = apic_iter->id );
 487                     return;
 488                 }
 489             }
 490             break;
 491
 492         case APIC_DM_SIPI:
 493             foreach_apic(apic_iter, deliver_bitmask,
 494                          apic_startup(apic_iter, vector_num) );
 495             return;
 496     }
 497
 498     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 499                      trigger_mode);
 500 }
 501
 502 int apic_get_interrupt(CPUState *env)
 503 {
 504     APICState *s = env->apic_state;
 505     int intno;
 506
 507     /* if the APIC is installed or enabled, we let the 8259 handle the
 508        IRQs */
 509     if (!s)
 510         return -1;
 511     if (!(s->spurious_vec & APIC_SV_ENABLE))
 512         return -1;
 513
 514     /* XXX: spurious IRQ handling */
 515     intno = get_highest_priority_int(s->irr);
 516     if (intno < 0)
 517         return -1;
 518     if (s->tpr && intno <= s->tpr)
 519         return s->spurious_vec & 0xff;
 520     reset_bit(s->irr, intno);
 521     set_bit(s->isr, intno);
 522     apic_update_irq(s);
 523     return intno;
 524 }
 525
 526 int apic_accept_pic_intr(CPUState *env)
 527 {
 528     APICState *s = env->apic_state;
 529     uint32_t lvt0;
 530
 531     if (!s)
 532         return -1;
 533
 534     lvt0 = s->lvt[APIC_LVT_LINT0];
 535
 536     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 537         (lvt0 & APIC_LVT_MASKED) == 0)
 538         return 1;
 539
 540     return 0;
 541 }
 542
 543 static uint32_t apic_get_current_count(APICState *s)
 544 {
 545     int64_t d;
 546     uint32_t val;
 547     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 548         s->count_shift;
 549     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 550         /* periodic */
 551         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 552     } else {
 553         if (d >= s->initial_count)
 554             val = 0;
 555         else
 556             val = s->initial_count - d;
 557     }
 558     return val;
 559 }
 560
 561 static void apic_timer_update(APICState *s, int64_t current_time)
 562 {
 563     int64_t next_time, d;
 564
 565     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 566         d = (current_time - s->initial_count_load_time) >>
 567             s->count_shift;
 568         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 569             if (!s->initial_count)
 570                 goto no_timer;
 571             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 572         } else {
 573             if (d >= s->initial_count)
 574                 goto no_timer;
 575             d = (uint64_t)s->initial_count + 1;
 576         }
 577         next_time = s->initial_count_load_time + (d << s->count_shift);
 578         qemu_mod_timer(s->timer, next_time);
 579         s->next_time = next_time;
 580     } else {
 581     no_timer:
 582         qemu_del_timer(s->timer);
 583     }
 584 }
 585
 586 static void apic_timer(void *opaque)
 587 {
 588     APICState *s = opaque;
 589
 590     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 591     apic_timer_update(s, s->next_time);
 592 }
 593
 594 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 595 {
 596     return 0;
 597 }
 598
 599 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 600 {
 601     return 0;
 602 }
 603
 604 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 605 {
 606 }
 607
 608 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 609 {
 610 }
 611
 612 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 613 {
 614     CPUState *env;
 615     APICState *s;
 616     uint32_t val;
 617     int index;
 618
 619     env = cpu_single_env;
 620     if (!env)
 621         return 0;
 622     s = env->apic_state;
 623
 624     index = (addr >> 4) & 0xff;
 625     switch(index) {
 626     case 0x02: /* id */
 627         val = s->id << 24;
 628         break;
 629     case 0x03: /* version */
 630         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 631         break;
 632     case 0x08:
 633         val = s->tpr;
 634         break;
 635     case 0x09:
 636         val = apic_get_arb_pri(s);
 637         break;
 638     case 0x0a:
 639         /* ppr */
 640         val = apic_get_ppr(s);
 641         break;
 642     case 0x0b:
 643         val = 0;
 644         break;
 645     case 0x0d:
 646         val = s->log_dest << 24;
 647         break;
 648     case 0x0e:
 649         val = s->dest_mode << 28;
 650         break;
 651     case 0x0f:
 652         val = s->spurious_vec;
 653         break;
 654     case 0x10 ... 0x17:
 655         val = s->isr[index & 7];
 656         break;
 657     case 0x18 ... 0x1f:
 658         val = s->tmr[index & 7];
 659         break;
 660     case 0x20 ... 0x27:
 661         val = s->irr[index & 7];
 662         break;
 663     case 0x28:
 664         val = s->esr;
 665         break;
 666     case 0x30:
 667     case 0x31:
 668         val = s->icr[index & 1];
 669         break;
 670     case 0x32 ... 0x37:
 671         val = s->lvt[index - 0x32];
 672         break;
 673     case 0x38:
 674         val = s->initial_count;
 675         break;
 676     case 0x39:
 677         val = apic_get_current_count(s);
 678         break;
 679     case 0x3e:
 680         val = s->divide_conf;
 681         break;
 682     default:
 683         s->esr |= ESR_ILLEGAL_ADDRESS;
 684         val = 0;
 685         break;
 686     }
 687 #ifdef DEBUG_APIC
 688     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 689 #endif
 690     return val;
 691 }
 692
 693 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 694 {
 695     CPUState *env;
 696     APICState *s;
 697     int index;
 698
 699     env = cpu_single_env;
 700     if (!env)
 701         return;
 702     s = env->apic_state;
 703
 704 #ifdef DEBUG_APIC
 705     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 706 #endif
 707
 708     index = (addr >> 4) & 0xff;
 709     switch(index) {
 710     case 0x02:
 711         s->id = (val >> 24);
 712         break;
 713     case 0x03:
 714         break;
 715     case 0x08:
 716         s->tpr = val;
 717         apic_update_irq(s);
 718         break;
 719     case 0x09:
 720     case 0x0a:
 721         break;
 722     case 0x0b: /* EOI */
 723         apic_eoi(s);
 724         break;
 725     case 0x0d:
 726         s->log_dest = val >> 24;
 727         break;
 728     case 0x0e:
 729         s->dest_mode = val >> 28;
 730         break;
 731     case 0x0f:
 732         s->spurious_vec = val & 0x1ff;
 733         apic_update_irq(s);
 734         break;
 735     case 0x10 ... 0x17:
 736     case 0x18 ... 0x1f:
 737     case 0x20 ... 0x27:
 738     case 0x28:
 739         break;
 740     case 0x30:
 741         s->icr[0] = val;
 742         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 743                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 744                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 745         break;
 746     case 0x31:
 747         s->icr[1] = val;
 748         break;
 749     case 0x32 ... 0x37:
 750         {
 751             int n = index - 0x32;
 752             s->lvt[n] = val;
 753             if (n == APIC_LVT_TIMER)
 754                 apic_timer_update(s, qemu_get_clock(vm_clock));
 755         }
 756         break;
 757     case 0x38:
 758         s->initial_count = val;
 759         s->initial_count_load_time = qemu_get_clock(vm_clock);
 760         apic_timer_update(s, s->initial_count_load_time);
 761         break;
 762     case 0x39:
 763         break;
 764     case 0x3e:
 765         {
 766             int v;
 767             s->divide_conf = val & 0xb;
 768             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 769             s->count_shift = (v + 1) & 7;
 770         }
 771         break;
 772     default:
 773         s->esr |= ESR_ILLEGAL_ADDRESS;
 774         break;
 775     }
 776 }
 777
 778 static void apic_save(QEMUFile *f, void *opaque)
 779 {
 780     APICState *s = opaque;
 781     int i;
 782
 783     qemu_put_be32s(f, &s->apicbase);
 784     qemu_put_8s(f, &s->id);
 785     qemu_put_8s(f, &s->arb_id);
 786     qemu_put_8s(f, &s->tpr);
 787     qemu_put_be32s(f, &s->spurious_vec);
 788     qemu_put_8s(f, &s->log_dest);
 789     qemu_put_8s(f, &s->dest_mode);
 790     for (i = 0; i < 8; i++) {
 791         qemu_put_be32s(f, &s->isr[i]);
 792         qemu_put_be32s(f, &s->tmr[i]);
 793         qemu_put_be32s(f, &s->irr[i]);
 794     }
 795     for (i = 0; i < APIC_LVT_NB; i++) {
 796         qemu_put_be32s(f, &s->lvt[i]);
 797     }
 798     qemu_put_be32s(f, &s->esr);
 799     qemu_put_be32s(f, &s->icr[0]);
 800     qemu_put_be32s(f, &s->icr[1]);
 801     qemu_put_be32s(f, &s->divide_conf);
 802     qemu_put_be32(f, s->count_shift);
 803     qemu_put_be32s(f, &s->initial_count);
 804     qemu_put_be64(f, s->initial_count_load_time);
 805     qemu_put_be64(f, s->next_time);
 806
 807     qemu_put_timer(f, s->timer);
 808 }
 809
 810 static int apic_load(QEMUFile *f, void *opaque, int version_id)
 811 {
 812     APICState *s = opaque;
 813     int i;
 814
 815     if (version_id > 2)
 816         return -EINVAL;
 817
 818     /* XXX: what if the base changes? (registered memory regions) */
 819     qemu_get_be32s(f, &s->apicbase);
 820     qemu_get_8s(f, &s->id);
 821     qemu_get_8s(f, &s->arb_id);
 822     qemu_get_8s(f, &s->tpr);
 823     qemu_get_be32s(f, &s->spurious_vec);
 824     qemu_get_8s(f, &s->log_dest);
 825     qemu_get_8s(f, &s->dest_mode);
 826     for (i = 0; i < 8; i++) {
 827         qemu_get_be32s(f, &s->isr[i]);
 828         qemu_get_be32s(f, &s->tmr[i]);
 829         qemu_get_be32s(f, &s->irr[i]);
 830     }
 831     for (i = 0; i < APIC_LVT_NB; i++) {
 832         qemu_get_be32s(f, &s->lvt[i]);
 833     }
 834     qemu_get_be32s(f, &s->esr);
 835     qemu_get_be32s(f, &s->icr[0]);
 836     qemu_get_be32s(f, &s->icr[1]);
 837     qemu_get_be32s(f, &s->divide_conf);
 838     s->count_shift=qemu_get_be32(f);
 839     qemu_get_be32s(f, &s->initial_count);
 840     s->initial_count_load_time=qemu_get_be64(f);
 841     s->next_time=qemu_get_be64(f);
 842
 843     if (version_id >= 2)
 844         qemu_get_timer(f, s->timer);
 845     return 0;
 846 }
 847
 848 static void apic_reset(void *opaque)
 849 {
 850     APICState *s = opaque;
 851     apic_init_ipi(s);
 852
 853     if (s->id == 0) {
 854         /*
 855          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 856          * time typically by BIOS, so PIC interrupt can be delivered to the
 857          * processor when local APIC is enabled.
 858          */
 859         s->lvt[APIC_LVT_LINT0] = 0x700;
 860     }
 861 }
 862
 863 static CPUReadMemoryFunc *apic_mem_read[3] = {
 864     apic_mem_readb,
 865     apic_mem_readw,
 866     apic_mem_readl,
 867 };
 868
 869 static CPUWriteMemoryFunc *apic_mem_write[3] = {
 870     apic_mem_writeb,
 871     apic_mem_writew,
 872     apic_mem_writel,
 873 };
 874
 875 int apic_init(CPUState *env)
 876 {
 877     APICState *s;
 878
 879     if (last_apic_id >= MAX_APICS)
 880         return -1;
 881     s = qemu_mallocz(sizeof(APICState));
 882     if (!s)
 883         return -1;
 884     env->apic_state = s;
 885     s->id = last_apic_id++;
 886     env->cpuid_apic_id = s->id;
 887     s->cpu_env = env;
 888     s->apicbase = 0xfee00000 |
 889         (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
 890
 891     apic_reset(s);
 892
 893     /* XXX: mapping more APICs at the same memory location */
 894     if (apic_io_memory == 0) {
 895         /* NOTE: the APIC is directly connected to the CPU - it is not
 896            on the global memory bus. */
 897         apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
 898                                                 apic_mem_write, NULL);
 899         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
 900                                      apic_io_memory);
 901     }
 902     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
 903
 904     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
 905     qemu_register_reset(apic_reset, s);
 906
 907     local_apics[s->id] = s;
 908     return 0;
 909 }
 910
 911 static void ioapic_service(IOAPICState *s)
 912 {
 913     uint8_t i;
 914     uint8_t trig_mode;
 915     uint8_t vector;
 916     uint8_t delivery_mode;
 917     uint32_t mask;
 918     uint64_t entry;
 919     uint8_t dest;
 920     uint8_t dest_mode;
 921     uint8_t polarity;
 922     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 923
 924     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 925         mask = 1 << i;
 926         if (s->irr & mask) {
 927             entry = s->ioredtbl[i];
 928             if (!(entry & APIC_LVT_MASKED)) {
 929                 trig_mode = ((entry >> 15) & 1);
 930                 dest = entry >> 56;
 931                 dest_mode = (entry >> 11) & 1;
 932                 delivery_mode = (entry >> 8) & 7;
 933                 polarity = (entry >> 13) & 1;
 934                 if (trig_mode == APIC_TRIGGER_EDGE)
 935                     s->irr &= ~mask;
 936                 if (delivery_mode == APIC_DM_EXTINT)
 937                     vector = pic_read_irq(isa_pic);
 938                 else
 939                     vector = entry & 0xff;
 940
 941                 apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 942                 apic_bus_deliver(deliver_bitmask, delivery_mode,
 943                                  vector, polarity, trig_mode);
 944             }
 945         }
 946     }
 947 }
 948
 949 void ioapic_set_irq(void *opaque, int vector, int level)
 950 {
 951     IOAPICState *s = opaque;
 952
 953     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 954         uint32_t mask = 1 << vector;
 955         uint64_t entry = s->ioredtbl[vector];
 956
 957         if ((entry >> 15) & 1) {
 958             /* level triggered */
 959             if (level) {
 960                 s->irr |= mask;
 961                 ioapic_service(s);
 962             } else {
 963                 s->irr &= ~mask;
 964             }
 965         } else {
 966             /* edge triggered */
 967             if (level) {
 968                 s->irr |= mask;
 969                 ioapic_service(s);
 970             }
 971         }
 972     }
 973 }
 974
 975 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
 976 {
 977     IOAPICState *s = opaque;
 978     int index;
 979     uint32_t val = 0;
 980
 981     addr &= 0xff;
 982     if (addr == 0x00) {
 983         val = s->ioregsel;
 984     } else if (addr == 0x10) {
 985         switch (s->ioregsel) {
 986             case 0x00:
 987                 val = s->id << 24;
 988                 break;
 989             case 0x01:
 990                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
 991                 break;
 992             case 0x02:
 993                 val = 0;
 994                 break;
 995             default:
 996                 index = (s->ioregsel - 0x10) >> 1;
 997                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 998                     if (s->ioregsel & 1)
 999                         val = s->ioredtbl[index] >> 32;
1000                     else
1001                         val = s->ioredtbl[index] & 0xffffffff;
1002                 }
1003         }
1004 #ifdef DEBUG_IOAPIC
1005         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
1006 #endif
1007     }
1008     return val;
1009 }
1010
1011 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1012 {
1013     IOAPICState *s = opaque;
1014     int index;
1015
1016     addr &= 0xff;
1017     if (addr == 0x00)  {
1018         s->ioregsel = val;
1019         return;
1020     } else if (addr == 0x10) {
1021 #ifdef DEBUG_IOAPIC
1022         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
1023 #endif
1024         switch (s->ioregsel) {
1025             case 0x00:
1026                 s->id = (val >> 24) & 0xff;
1027                 return;
1028             case 0x01:
1029             case 0x02:
1030                 return;
1031             default:
1032                 index = (s->ioregsel - 0x10) >> 1;
1033                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
1034                     if (s->ioregsel & 1) {
1035                         s->ioredtbl[index] &= 0xffffffff;
1036                         s->ioredtbl[index] |= (uint64_t)val << 32;
1037                     } else {
1038                         s->ioredtbl[index] &= ~0xffffffffULL;
1039                         s->ioredtbl[index] |= val;
1040                     }
1041                     ioapic_service(s);
1042                 }
1043         }
1044     }
1045 }
1046
1047 static void ioapic_save(QEMUFile *f, void *opaque)
1048 {
1049     IOAPICState *s = opaque;
1050     int i;
1051
1052     qemu_put_8s(f, &s->id);
1053     qemu_put_8s(f, &s->ioregsel);
1054     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1055         qemu_put_be64s(f, &s->ioredtbl[i]);
1056     }
1057 }
1058
1059 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
1060 {
1061     IOAPICState *s = opaque;
1062     int i;
1063
1064     if (version_id != 1)
1065         return -EINVAL;
1066
1067     qemu_get_8s(f, &s->id);
1068     qemu_get_8s(f, &s->ioregsel);
1069     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
1070         qemu_get_be64s(f, &s->ioredtbl[i]);
1071     }
1072     return 0;
1073 }
1074
1075 static void ioapic_reset(void *opaque)
1076 {
1077     IOAPICState *s = opaque;
1078     int i;
1079
1080     memset(s, 0, sizeof(*s));
1081     for(i = 0; i < IOAPIC_NUM_PINS; i++)
1082         s->ioredtbl[i] = 1 << 16; /* mask LVT */
1083 }
1084
1085 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
1086     ioapic_mem_readl,
1087     ioapic_mem_readl,
1088     ioapic_mem_readl,
1089 };
1090
1091 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
1092     ioapic_mem_writel,
1093     ioapic_mem_writel,
1094     ioapic_mem_writel,
1095 };
1096
1097 IOAPICState *ioapic_init(void)
1098 {
1099     IOAPICState *s;
1100     int io_memory;
1101
1102     s = qemu_mallocz(sizeof(IOAPICState));
1103     if (!s)
1104         return NULL;
1105     ioapic_reset(s);
1106     s->id = last_apic_id++;
1107
1108     io_memory = cpu_register_io_memory(0, ioapic_mem_read,
1109                                        ioapic_mem_write, s);
1110     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
1111
1112     register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
1113     qemu_register_reset(ioapic_reset, s);
1114
1115     return s;
1116 }