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Unify IRQ handling.
[qemu/mini2440.git] / hw / pcnet.c
blobf2130d7b40c5c10db3a6da74819c44db933806cf
1 /*
2 * QEMU AMD PC-Net II (Am79C970A) emulation
3 *
4 * Copyright (c) 2004 Antony T Curtis
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 /* This software was written to be compatible with the specification:
26 * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
27 * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
28 */
29
30 /*
31 * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
32 * produced as NCR89C100. See
33 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34 * and
35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
36 */
37
38 /* TODO: remove little endian host assumptions */
39
40 #include "vl.h"
41
42 //#define PCNET_DEBUG
43 //#define PCNET_DEBUG_IO
44 //#define PCNET_DEBUG_BCR
45 //#define PCNET_DEBUG_CSR
46 //#define PCNET_DEBUG_RMD
47 //#define PCNET_DEBUG_TMD
48 //#define PCNET_DEBUG_MATCH
49
50
51 #define PCNET_IOPORT_SIZE 0x20
52 #define PCNET_PNPMMIO_SIZE 0x20
53
54
55 typedef struct PCNetState_st PCNetState;
56
57 struct PCNetState_st {
58 PCIDevice dev;
59 PCIDevice *pci_dev;
60 VLANClientState *vc;
61 NICInfo *nd;
62 QEMUTimer *poll_timer;
63 int mmio_index, rap, isr, lnkst;
64 uint32_t rdra, tdra;
65 uint8_t prom[16];
66 uint16_t csr[128];
67 uint16_t bcr[32];
68 uint64_t timer;
69 int xmit_pos, recv_pos;
70 uint8_t buffer[4096];
71 int tx_busy;
72 qemu_irq irq;
73 void (*phys_mem_read)(void *dma_opaque, target_phys_addr_t addr,
74 uint8_t *buf, int len, int do_bswap);
75 void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
76 uint8_t *buf, int len, int do_bswap);
77 void *dma_opaque;
78 };
79
80 struct qemu_ether_header {
81 uint8_t ether_dhost[6];
82 uint8_t ether_shost[6];
83 uint16_t ether_type;
84 };
85
86 /* BUS CONFIGURATION REGISTERS */
87 #define BCR_MSRDA 0
88 #define BCR_MSWRA 1
89 #define BCR_MC 2
90 #define BCR_LNKST 4
91 #define BCR_LED1 5
92 #define BCR_LED2 6
93 #define BCR_LED3 7
94 #define BCR_FDC 9
95 #define BCR_BSBC 18
96 #define BCR_EECAS 19
97 #define BCR_SWS 20
98 #define BCR_PLAT 22
99
100 #define BCR_DWIO(S) !!((S)->bcr[BCR_BSBC] & 0x0080)
101 #define BCR_SSIZE32(S) !!((S)->bcr[BCR_SWS ] & 0x0100)
102 #define BCR_SWSTYLE(S) ((S)->bcr[BCR_SWS ] & 0x00FF)
103
104 #define CSR_INIT(S) !!(((S)->csr[0])&0x0001)
105 #define CSR_STRT(S) !!(((S)->csr[0])&0x0002)
106 #define CSR_STOP(S) !!(((S)->csr[0])&0x0004)
107 #define CSR_TDMD(S) !!(((S)->csr[0])&0x0008)
108 #define CSR_TXON(S) !!(((S)->csr[0])&0x0010)
109 #define CSR_RXON(S) !!(((S)->csr[0])&0x0020)
110 #define CSR_INEA(S) !!(((S)->csr[0])&0x0040)
111 #define CSR_BSWP(S) !!(((S)->csr[3])&0x0004)
112 #define CSR_LAPPEN(S) !!(((S)->csr[3])&0x0020)
113 #define CSR_DXSUFLO(S) !!(((S)->csr[3])&0x0040)
114 #define CSR_ASTRP_RCV(S) !!(((S)->csr[4])&0x0800)
115 #define CSR_DPOLL(S) !!(((S)->csr[4])&0x1000)
116 #define CSR_SPND(S) !!(((S)->csr[5])&0x0001)
117 #define CSR_LTINTEN(S) !!(((S)->csr[5])&0x4000)
118 #define CSR_TOKINTD(S) !!(((S)->csr[5])&0x8000)
119 #define CSR_DRX(S) !!(((S)->csr[15])&0x0001)
120 #define CSR_DTX(S) !!(((S)->csr[15])&0x0002)
121 #define CSR_LOOP(S) !!(((S)->csr[15])&0x0004)
122 #define CSR_DRCVPA(S) !!(((S)->csr[15])&0x2000)
123 #define CSR_DRCVBC(S) !!(((S)->csr[15])&0x4000)
124 #define CSR_PROM(S) !!(((S)->csr[15])&0x8000)
125
126 #define CSR_CRBC(S) ((S)->csr[40])
127 #define CSR_CRST(S) ((S)->csr[41])
128 #define CSR_CXBC(S) ((S)->csr[42])
129 #define CSR_CXST(S) ((S)->csr[43])
130 #define CSR_NRBC(S) ((S)->csr[44])
131 #define CSR_NRST(S) ((S)->csr[45])
132 #define CSR_POLL(S) ((S)->csr[46])
133 #define CSR_PINT(S) ((S)->csr[47])
134 #define CSR_RCVRC(S) ((S)->csr[72])
135 #define CSR_XMTRC(S) ((S)->csr[74])
136 #define CSR_RCVRL(S) ((S)->csr[76])
137 #define CSR_XMTRL(S) ((S)->csr[78])
138 #define CSR_MISSC(S) ((S)->csr[112])
139
140 #define CSR_IADR(S) ((S)->csr[ 1] | ((S)->csr[ 2] << 16))
141 #define CSR_CRBA(S) ((S)->csr[18] | ((S)->csr[19] << 16))
142 #define CSR_CXBA(S) ((S)->csr[20] | ((S)->csr[21] << 16))
143 #define CSR_NRBA(S) ((S)->csr[22] | ((S)->csr[23] << 16))
144 #define CSR_BADR(S) ((S)->csr[24] | ((S)->csr[25] << 16))
145 #define CSR_NRDA(S) ((S)->csr[26] | ((S)->csr[27] << 16))
146 #define CSR_CRDA(S) ((S)->csr[28] | ((S)->csr[29] << 16))
147 #define CSR_BADX(S) ((S)->csr[30] | ((S)->csr[31] << 16))
148 #define CSR_NXDA(S) ((S)->csr[32] | ((S)->csr[33] << 16))
149 #define CSR_CXDA(S) ((S)->csr[34] | ((S)->csr[35] << 16))
150 #define CSR_NNRD(S) ((S)->csr[36] | ((S)->csr[37] << 16))
151 #define CSR_NNXD(S) ((S)->csr[38] | ((S)->csr[39] << 16))
152 #define CSR_PXDA(S) ((S)->csr[60] | ((S)->csr[61] << 16))
153 #define CSR_NXBA(S) ((S)->csr[64] | ((S)->csr[65] << 16))
154
155 #define PHYSADDR(S,A) \
156 (BCR_SSIZE32(S) ? (A) : (A) | ((0xff00 & (uint32_t)(s)->csr[2])<<16))
157
158 struct pcnet_initblk16 {
159 uint16_t mode;
160 uint16_t padr[3];
161 uint16_t ladrf[4];
162 uint32_t rdra;
163 uint32_t tdra;
164 };
165
166 struct pcnet_initblk32 {
167 uint16_t mode;
168 uint8_t rlen;
169 uint8_t tlen;
170 uint16_t padr[3];
171 uint16_t _res;
172 uint16_t ladrf[4];
173 uint32_t rdra;
174 uint32_t tdra;
175 };
176
177 struct pcnet_TMD {
178 uint32_t tbadr;
179 int16_t length;
180 int16_t status;
181 uint32_t misc;
182 uint32_t res;
183 };
184
185 #define TMDL_BCNT_MASK 0x0fff
186 #define TMDL_BCNT_SH 0
187 #define TMDL_ONES_MASK 0xf000
188 #define TMDL_ONES_SH 12
189
190 #define TMDS_BPE_MASK 0x0080
191 #define TMDS_BPE_SH 7
192 #define TMDS_ENP_MASK 0x0100
193 #define TMDS_ENP_SH 8
194 #define TMDS_STP_MASK 0x0200
195 #define TMDS_STP_SH 9
196 #define TMDS_DEF_MASK 0x0400
197 #define TMDS_DEF_SH 10
198 #define TMDS_ONE_MASK 0x0800
199 #define TMDS_ONE_SH 11
200 #define TMDS_LTINT_MASK 0x1000
201 #define TMDS_LTINT_SH 12
202 #define TMDS_NOFCS_MASK 0x2000
203 #define TMDS_NOFCS_SH 13
204 #define TMDS_ERR_MASK 0x4000
205 #define TMDS_ERR_SH 14
206 #define TMDS_OWN_MASK 0x8000
207 #define TMDS_OWN_SH 15
208
209 #define TMDM_TRC_MASK 0x0000000f
210 #define TMDM_TRC_SH 0
211 #define TMDM_TDR_MASK 0x03ff0000
212 #define TMDM_TDR_SH 16
213 #define TMDM_RTRY_MASK 0x04000000
214 #define TMDM_RTRY_SH 26
215 #define TMDM_LCAR_MASK 0x08000000
216 #define TMDM_LCAR_SH 27
217 #define TMDM_LCOL_MASK 0x10000000
218 #define TMDM_LCOL_SH 28
219 #define TMDM_EXDEF_MASK 0x20000000
220 #define TMDM_EXDEF_SH 29
221 #define TMDM_UFLO_MASK 0x40000000
222 #define TMDM_UFLO_SH 30
223 #define TMDM_BUFF_MASK 0x80000000
224 #define TMDM_BUFF_SH 31
225
226 struct pcnet_RMD {
227 uint32_t rbadr;
228 int16_t buf_length;
229 int16_t status;
230 uint32_t msg_length;
231 uint32_t res;
232 };
233
234 #define RMDL_BCNT_MASK 0x0fff
235 #define RMDL_BCNT_SH 0
236 #define RMDL_ONES_MASK 0xf000
237 #define RMDL_ONES_SH 12
238
239 #define RMDS_BAM_MASK 0x0010
240 #define RMDS_BAM_SH 4
241 #define RMDS_LFAM_MASK 0x0020
242 #define RMDS_LFAM_SH 5
243 #define RMDS_PAM_MASK 0x0040
244 #define RMDS_PAM_SH 6
245 #define RMDS_BPE_MASK 0x0080
246 #define RMDS_BPE_SH 7
247 #define RMDS_ENP_MASK 0x0100
248 #define RMDS_ENP_SH 8
249 #define RMDS_STP_MASK 0x0200
250 #define RMDS_STP_SH 9
251 #define RMDS_BUFF_MASK 0x0400
252 #define RMDS_BUFF_SH 10
253 #define RMDS_CRC_MASK 0x0800
254 #define RMDS_CRC_SH 11
255 #define RMDS_OFLO_MASK 0x1000
256 #define RMDS_OFLO_SH 12
257 #define RMDS_FRAM_MASK 0x2000
258 #define RMDS_FRAM_SH 13
259 #define RMDS_ERR_MASK 0x4000
260 #define RMDS_ERR_SH 14
261 #define RMDS_OWN_MASK 0x8000
262 #define RMDS_OWN_SH 15
263
264 #define RMDM_MCNT_MASK 0x00000fff
265 #define RMDM_MCNT_SH 0
266 #define RMDM_ZEROS_MASK 0x0000f000
267 #define RMDM_ZEROS_SH 12
268 #define RMDM_RPC_MASK 0x00ff0000
269 #define RMDM_RPC_SH 16
270 #define RMDM_RCC_MASK 0xff000000
271 #define RMDM_RCC_SH 24
272
273 #define SET_FIELD(regp, name, field, value) \
274 (*(regp) = (*(regp) & ~(name ## _ ## field ## _MASK)) \
275 | ((value) << name ## _ ## field ## _SH))
276
277 #define GET_FIELD(reg, name, field) \
278 (((reg) & name ## _ ## field ## _MASK) >> name ## _ ## field ## _SH)
279
280 #define PRINT_TMD(T) printf( \
281 "TMD0 : TBADR=0x%08x\n" \
282 "TMD1 : OWN=%d, ERR=%d, FCS=%d, LTI=%d, " \
283 "ONE=%d, DEF=%d, STP=%d, ENP=%d,\n" \
284 " BPE=%d, BCNT=%d\n" \
285 "TMD2 : BUF=%d, UFL=%d, EXD=%d, LCO=%d, " \
286 "LCA=%d, RTR=%d,\n" \
287 " TDR=%d, TRC=%d\n", \
288 (T)->tbadr, \
289 GET_FIELD((T)->status, TMDS, OWN), \
290 GET_FIELD((T)->status, TMDS, ERR), \
291 GET_FIELD((T)->status, TMDS, NOFCS), \
292 GET_FIELD((T)->status, TMDS, LTINT), \
293 GET_FIELD((T)->status, TMDS, ONE), \
294 GET_FIELD((T)->status, TMDS, DEF), \
295 GET_FIELD((T)->status, TMDS, STP), \
296 GET_FIELD((T)->status, TMDS, ENP), \
297 GET_FIELD((T)->status, TMDS, BPE), \
298 4096-GET_FIELD((T)->length, TMDL, BCNT), \
299 GET_FIELD((T)->misc, TMDM, BUFF), \
300 GET_FIELD((T)->misc, TMDM, UFLO), \
301 GET_FIELD((T)->misc, TMDM, EXDEF), \
302 GET_FIELD((T)->misc, TMDM, LCOL), \
303 GET_FIELD((T)->misc, TMDM, LCAR), \
304 GET_FIELD((T)->misc, TMDM, RTRY), \
305 GET_FIELD((T)->misc, TMDM, TDR), \
306 GET_FIELD((T)->misc, TMDM, TRC))
307
308 #define PRINT_RMD(R) printf( \
309 "RMD0 : RBADR=0x%08x\n" \
310 "RMD1 : OWN=%d, ERR=%d, FRAM=%d, OFLO=%d, " \
311 "CRC=%d, BUFF=%d, STP=%d, ENP=%d,\n " \
312 "BPE=%d, PAM=%d, LAFM=%d, BAM=%d, ONES=%d, BCNT=%d\n" \
313 "RMD2 : RCC=%d, RPC=%d, MCNT=%d, ZEROS=%d\n", \
314 (R)->rbadr, \
315 GET_FIELD((R)->status, RMDS, OWN), \
316 GET_FIELD((R)->status, RMDS, ERR), \
317 GET_FIELD((R)->status, RMDS, FRAM), \
318 GET_FIELD((R)->status, RMDS, OFLO), \
319 GET_FIELD((R)->status, RMDS, CRC), \
320 GET_FIELD((R)->status, RMDS, BUFF), \
321 GET_FIELD((R)->status, RMDS, STP), \
322 GET_FIELD((R)->status, RMDS, ENP), \
323 GET_FIELD((R)->status, RMDS, BPE), \
324 GET_FIELD((R)->status, RMDS, PAM), \
325 GET_FIELD((R)->status, RMDS, LFAM), \
326 GET_FIELD((R)->status, RMDS, BAM), \
327 GET_FIELD((R)->buf_length, RMDL, ONES), \
328 4096-GET_FIELD((R)->buf_length, RMDL, BCNT), \
329 GET_FIELD((R)->msg_length, RMDM, RCC), \
330 GET_FIELD((R)->msg_length, RMDM, RPC), \
331 GET_FIELD((R)->msg_length, RMDM, MCNT), \
332 GET_FIELD((R)->msg_length, RMDM, ZEROS))
333
334 static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd,
335 target_phys_addr_t addr)
336 {
337 if (!BCR_SSIZE32(s)) {
338 struct {
339 uint32_t tbadr;
340 int16_t length;
341 int16_t status;
342 } xda;
343 s->phys_mem_read(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
344 tmd->tbadr = le32_to_cpu(xda.tbadr) & 0xffffff;
345 tmd->length = le16_to_cpu(xda.length);
346 tmd->status = (le32_to_cpu(xda.tbadr) >> 16) & 0xff00;
347 tmd->misc = le16_to_cpu(xda.status) << 16;
348 tmd->res = 0;
349 } else {
350 s->phys_mem_read(s->dma_opaque, addr, (void *)tmd, sizeof(*tmd), 0);
351 le32_to_cpus(&tmd->tbadr);
352 le16_to_cpus(&tmd->length);
353 le16_to_cpus(&tmd->status);
354 le32_to_cpus(&tmd->misc);
355 le32_to_cpus(&tmd->res);
356 if (BCR_SWSTYLE(s) == 3) {
357 uint32_t tmp = tmd->tbadr;
358 tmd->tbadr = tmd->misc;
359 tmd->misc = tmp;
360 }
361 }
362 }
363
364 static inline void pcnet_tmd_store(PCNetState *s, const struct pcnet_TMD *tmd,
365 target_phys_addr_t addr)
366 {
367 if (!BCR_SSIZE32(s)) {
368 struct {
369 uint32_t tbadr;
370 int16_t length;
371 int16_t status;
372 } xda;
373 xda.tbadr = cpu_to_le32((tmd->tbadr & 0xffffff) |
374 ((tmd->status & 0xff00) << 16));
375 xda.length = cpu_to_le16(tmd->length);
376 xda.status = cpu_to_le16(tmd->misc >> 16);
377 s->phys_mem_write(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
378 } else {
379 struct {
380 uint32_t tbadr;
381 int16_t length;
382 int16_t status;
383 uint32_t misc;
384 uint32_t res;
385 } xda;
386 xda.tbadr = cpu_to_le32(tmd->tbadr);
387 xda.length = cpu_to_le16(tmd->length);
388 xda.status = cpu_to_le16(tmd->status);
389 xda.misc = cpu_to_le32(tmd->misc);
390 xda.res = cpu_to_le32(tmd->res);
391 if (BCR_SWSTYLE(s) == 3) {
392 uint32_t tmp = xda.tbadr;
393 xda.tbadr = xda.misc;
394 xda.misc = tmp;
395 }
396 s->phys_mem_write(s->dma_opaque, addr, (void *)&xda, sizeof(xda), 0);
397 }
398 }
399
400 static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd,
401 target_phys_addr_t addr)
402 {
403 if (!BCR_SSIZE32(s)) {
404 struct {
405 uint32_t rbadr;
406 int16_t buf_length;
407 int16_t msg_length;
408 } rda;
409 s->phys_mem_read(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
410 rmd->rbadr = le32_to_cpu(rda.rbadr) & 0xffffff;
411 rmd->buf_length = le16_to_cpu(rda.buf_length);
412 rmd->status = (le32_to_cpu(rda.rbadr) >> 16) & 0xff00;
413 rmd->msg_length = le16_to_cpu(rda.msg_length);
414 rmd->res = 0;
415 } else {
416 s->phys_mem_read(s->dma_opaque, addr, (void *)rmd, sizeof(*rmd), 0);
417 le32_to_cpus(&rmd->rbadr);
418 le16_to_cpus(&rmd->buf_length);
419 le16_to_cpus(&rmd->status);
420 le32_to_cpus(&rmd->msg_length);
421 le32_to_cpus(&rmd->res);
422 if (BCR_SWSTYLE(s) == 3) {
423 uint32_t tmp = rmd->rbadr;
424 rmd->rbadr = rmd->msg_length;
425 rmd->msg_length = tmp;
426 }
427 }
428 }
429
430 static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd,
431 target_phys_addr_t addr)
432 {
433 if (!BCR_SSIZE32(s)) {
434 struct {
435 uint32_t rbadr;
436 int16_t buf_length;
437 int16_t msg_length;
438 } rda;
439 rda.rbadr = cpu_to_le32((rmd->rbadr & 0xffffff) |
440 ((rmd->status & 0xff00) << 16));
441 rda.buf_length = cpu_to_le16(rmd->buf_length);
442 rda.msg_length = cpu_to_le16(rmd->msg_length);
443 s->phys_mem_write(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
444 } else {
445 struct {
446 uint32_t rbadr;
447 int16_t buf_length;
448 int16_t status;
449 uint32_t msg_length;
450 uint32_t res;
451 } rda;
452 rda.rbadr = cpu_to_le32(rmd->rbadr);
453 rda.buf_length = cpu_to_le16(rmd->buf_length);
454 rda.status = cpu_to_le16(rmd->status);
455 rda.msg_length = cpu_to_le32(rmd->msg_length);
456 rda.res = cpu_to_le32(rmd->res);
457 if (BCR_SWSTYLE(s) == 3) {
458 uint32_t tmp = rda.rbadr;
459 rda.rbadr = rda.msg_length;
460 rda.msg_length = tmp;
461 }
462 s->phys_mem_write(s->dma_opaque, addr, (void *)&rda, sizeof(rda), 0);
463 }
464 }
465
466
467 #define TMDLOAD(TMD,ADDR) pcnet_tmd_load(s,TMD,ADDR)
468
469 #define TMDSTORE(TMD,ADDR) pcnet_tmd_store(s,TMD,ADDR)
470
471 #define RMDLOAD(RMD,ADDR) pcnet_rmd_load(s,RMD,ADDR)
472
473 #define RMDSTORE(RMD,ADDR) pcnet_rmd_store(s,RMD,ADDR)
474
475 #if 1
476
477 #define CHECK_RMD(ADDR,RES) do { \
478 struct pcnet_RMD rmd; \
479 RMDLOAD(&rmd,(ADDR)); \
480 (RES) |= (GET_FIELD(rmd.buf_length, RMDL, ONES) != 15) \
481 || (GET_FIELD(rmd.msg_length, RMDM, ZEROS) != 0); \
482 } while (0)
483
484 #define CHECK_TMD(ADDR,RES) do { \
485 struct pcnet_TMD tmd; \
486 TMDLOAD(&tmd,(ADDR)); \
487 (RES) |= (GET_FIELD(tmd.length, TMDL, ONES) != 15); \
488 } while (0)
489
490 #else
491
492 #define CHECK_RMD(ADDR,RES) do { \
493 switch (BCR_SWSTYLE(s)) { \
494 case 0x00: \
495 do { \
496 uint16_t rda[4]; \
497 s->phys_mem_read(s->dma_opaque, (ADDR), \
498 (void *)&rda[0], sizeof(rda), 0); \
499 (RES) |= (rda[2] & 0xf000)!=0xf000; \
500 (RES) |= (rda[3] & 0xf000)!=0x0000; \
501 } while (0); \
502 break; \
503 case 0x01: \
504 case 0x02: \
505 do { \
506 uint32_t rda[4]; \
507 s->phys_mem_read(s->dma_opaque, (ADDR), \
508 (void *)&rda[0], sizeof(rda), 0); \
509 (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
510 (RES) |= (rda[2] & 0x0000f000L)!=0x00000000L; \
511 } while (0); \
512 break; \
513 case 0x03: \
514 do { \
515 uint32_t rda[4]; \
516 s->phys_mem_read(s->dma_opaque, (ADDR), \
517 (void *)&rda[0], sizeof(rda), 0); \
518 (RES) |= (rda[0] & 0x0000f000L)!=0x00000000L; \
519 (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
520 } while (0); \
521 break; \
522 } \
523 } while (0)
524
525 #define CHECK_TMD(ADDR,RES) do { \
526 switch (BCR_SWSTYLE(s)) { \
527 case 0x00: \
528 do { \
529 uint16_t xda[4]; \
530 s->phys_mem_read(s->dma_opaque, (ADDR), \
531 (void *)&xda[0], sizeof(xda), 0); \
532 (RES) |= (xda[2] & 0xf000)!=0xf000; \
533 } while (0); \
534 break; \
535 case 0x01: \
536 case 0x02: \
537 case 0x03: \
538 do { \
539 uint32_t xda[4]; \
540 s->phys_mem_read(s->dma_opaque, (ADDR), \
541 (void *)&xda[0], sizeof(xda), 0); \
542 (RES) |= (xda[1] & 0x0000f000L)!=0x0000f000L; \
543 } while (0); \
544 break; \
545 } \
546 } while (0)
547
548 #endif
549
550 #define PRINT_PKTHDR(BUF) do { \
551 struct qemu_ether_header *hdr = (void *)(BUF); \
552 printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, " \
553 "shost=%02x:%02x:%02x:%02x:%02x:%02x, " \
554 "type=0x%04x\n", \
555 hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], \
556 hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], \
557 hdr->ether_shost[0],hdr->ether_shost[1],hdr->ether_shost[2], \
558 hdr->ether_shost[3],hdr->ether_shost[4],hdr->ether_shost[5], \
559 be16_to_cpu(hdr->ether_type)); \
560 } while (0)
561
562 #define MULTICAST_FILTER_LEN 8
563
564 static inline uint32_t lnc_mchash(const uint8_t *ether_addr)
565 {
566 #define LNC_POLYNOMIAL 0xEDB88320UL
567 uint32_t crc = 0xFFFFFFFF;
568 int idx, bit;
569 uint8_t data;
570
571 for (idx = 0; idx < 6; idx++) {
572 for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++) {
573 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);
574 data >>= 1;
575 }
576 }
577 return crc;
578 #undef LNC_POLYNOMIAL
579 }
580
581 #define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
582
583 /* generated using the AUTODIN II polynomial
584 * x^32 + x^26 + x^23 + x^22 + x^16 +
585 * x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
586 */
587 static const uint32_t crctab[256] = {
588 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
589 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
590 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
591 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
592 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
593 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
594 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
595 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
596 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
597 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
598 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
599 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
600 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
601 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
602 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
603 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
604 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
605 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
606 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
607 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
608 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
609 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
610 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
611 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
612 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
613 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
614 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
615 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
616 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
617 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
618 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
619 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
620 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
621 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
622 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
623 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
624 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
625 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
626 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
627 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
628 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
629 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
630 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
631 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
632 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
633 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
634 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
635 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
636 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
637 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
638 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
639 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
640 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
641 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
642 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
643 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
644 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
645 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
646 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
647 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
648 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
649 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
650 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
651 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
652 };
653
654 static inline int padr_match(PCNetState *s, const uint8_t *buf, int size)
655 {
656 struct qemu_ether_header *hdr = (void *)buf;
657 uint8_t padr[6] = {
658 s->csr[12] & 0xff, s->csr[12] >> 8,
659 s->csr[13] & 0xff, s->csr[13] >> 8,
660 s->csr[14] & 0xff, s->csr[14] >> 8
661 };
662 int result = (!CSR_DRCVPA(s)) && !memcmp(hdr->ether_dhost, padr, 6);
663 #ifdef PCNET_DEBUG_MATCH
664 printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "
665 "padr=%02x:%02x:%02x:%02x:%02x:%02x\n",
666 hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2],
667 hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5],
668 padr[0],padr[1],padr[2],padr[3],padr[4],padr[5]);
669 printf("padr_match result=%d\n", result);
670 #endif
671 return result;
672 }
673
674 static inline int padr_bcast(PCNetState *s, const uint8_t *buf, int size)
675 {
676 static const uint8_t BCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
677 struct qemu_ether_header *hdr = (void *)buf;
678 int result = !CSR_DRCVBC(s) && !memcmp(hdr->ether_dhost, BCAST, 6);
679 #ifdef PCNET_DEBUG_MATCH
680 printf("padr_bcast result=%d\n", result);
681 #endif
682 return result;
683 }
684
685 static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size)
686 {
687 struct qemu_ether_header *hdr = (void *)buf;
688 if ((*(hdr->ether_dhost)&0x01) &&
689 ((uint64_t *)&s->csr[8])[0] != 0LL) {
690 uint8_t ladr[8] = {
691 s->csr[8] & 0xff, s->csr[8] >> 8,
692 s->csr[9] & 0xff, s->csr[9] >> 8,
693 s->csr[10] & 0xff, s->csr[10] >> 8,
694 s->csr[11] & 0xff, s->csr[11] >> 8
695 };
696 int index = lnc_mchash(hdr->ether_dhost) >> 26;
697 return !!(ladr[index >> 3] & (1 << (index & 7)));
698 }
699 return 0;
700 }
701
702 static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx)
703 {
704 while (idx < 1) idx += CSR_RCVRL(s);
705 return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
706 }
707
708 static inline int64_t pcnet_get_next_poll_time(PCNetState *s, int64_t current_time)
709 {
710 int64_t next_time = current_time +
711 muldiv64(65536 - (CSR_SPND(s) ? 0 : CSR_POLL(s)),
712 ticks_per_sec, 33000000L);
713 if (next_time <= current_time)
714 next_time = current_time + 1;
715 return next_time;
716 }
717
718 static void pcnet_poll(PCNetState *s);
719 static void pcnet_poll_timer(void *opaque);
720
721 static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap);
722 static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value);
723 static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val);
724 static uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap);
725
726 static void pcnet_s_reset(PCNetState *s)
727 {
728 #ifdef PCNET_DEBUG
729 printf("pcnet_s_reset\n");
730 #endif
731
732 s->lnkst = 0x40;
733 s->rdra = 0;
734 s->tdra = 0;
735 s->rap = 0;
736
737 s->bcr[BCR_BSBC] &= ~0x0080;
738
739 s->csr[0] = 0x0004;
740 s->csr[3] = 0x0000;
741 s->csr[4] = 0x0115;
742 s->csr[5] = 0x0000;
743 s->csr[6] = 0x0000;
744 s->csr[8] = 0;
745 s->csr[9] = 0;
746 s->csr[10] = 0;
747 s->csr[11] = 0;
748 s->csr[12] = le16_to_cpu(((uint16_t *)&s->prom[0])[0]);
749 s->csr[13] = le16_to_cpu(((uint16_t *)&s->prom[0])[1]);
750 s->csr[14] = le16_to_cpu(((uint16_t *)&s->prom[0])[2]);
751 s->csr[15] &= 0x21c4;
752 s->csr[72] = 1;
753 s->csr[74] = 1;
754 s->csr[76] = 1;
755 s->csr[78] = 1;
756 s->csr[80] = 0x1410;
757 s->csr[88] = 0x1003;
758 s->csr[89] = 0x0262;
759 s->csr[94] = 0x0000;
760 s->csr[100] = 0x0200;
761 s->csr[103] = 0x0105;
762 s->csr[103] = 0x0105;
763 s->csr[112] = 0x0000;
764 s->csr[114] = 0x0000;
765 s->csr[122] = 0x0000;
766 s->csr[124] = 0x0000;
767
768 s->tx_busy = 0;
769 }
770
771 static void pcnet_update_irq(PCNetState *s)
772 {
773 int isr = 0;
774 s->csr[0] &= ~0x0080;
775
776 #if 1
777 if (((s->csr[0] & ~s->csr[3]) & 0x5f00) ||
778 (((s->csr[4]>>1) & ~s->csr[4]) & 0x0115) ||
779 (((s->csr[5]>>1) & s->csr[5]) & 0x0048))
780 #else
781 if ((!(s->csr[3] & 0x4000) && !!(s->csr[0] & 0x4000)) /* BABL */ ||
782 (!(s->csr[3] & 0x1000) && !!(s->csr[0] & 0x1000)) /* MISS */ ||
783 (!(s->csr[3] & 0x0100) && !!(s->csr[0] & 0x0100)) /* IDON */ ||
784 (!(s->csr[3] & 0x0200) && !!(s->csr[0] & 0x0200)) /* TINT */ ||
785 (!(s->csr[3] & 0x0400) && !!(s->csr[0] & 0x0400)) /* RINT */ ||
786 (!(s->csr[3] & 0x0800) && !!(s->csr[0] & 0x0800)) /* MERR */ ||
787 (!(s->csr[4] & 0x0001) && !!(s->csr[4] & 0x0002)) /* JAB */ ||
788 (!(s->csr[4] & 0x0004) && !!(s->csr[4] & 0x0008)) /* TXSTRT */ ||
789 (!(s->csr[4] & 0x0010) && !!(s->csr[4] & 0x0020)) /* RCVO */ ||
790 (!(s->csr[4] & 0x0100) && !!(s->csr[4] & 0x0200)) /* MFCO */ ||
791 (!!(s->csr[5] & 0x0040) && !!(s->csr[5] & 0x0080)) /* EXDINT */ ||
792 (!!(s->csr[5] & 0x0008) && !!(s->csr[5] & 0x0010)) /* MPINT */)
793 #endif
794 {
795
796 isr = CSR_INEA(s);
797 s->csr[0] |= 0x0080;
798 }
799
800 if (!!(s->csr[4] & 0x0080) && CSR_INEA(s)) { /* UINT */
801 s->csr[4] &= ~0x0080;
802 s->csr[4] |= 0x0040;
803 s->csr[0] |= 0x0080;
804 isr = 1;
805 #ifdef PCNET_DEBUG
806 printf("pcnet user int\n");
807 #endif
808 }
809
810 #if 1
811 if (((s->csr[5]>>1) & s->csr[5]) & 0x0500)
812 #else
813 if ((!!(s->csr[5] & 0x0400) && !!(s->csr[5] & 0x0800)) /* SINT */ ||
814 (!!(s->csr[5] & 0x0100) && !!(s->csr[5] & 0x0200)) /* SLPINT */ )
815 #endif
816 {
817 isr = 1;
818 s->csr[0] |= 0x0080;
819 }
820
821 if (isr != s->isr) {
822 #ifdef PCNET_DEBUG
823 printf("pcnet: INTA=%d\n", isr);
824 #endif
825 }
826 qemu_set_irq(s->irq, isr);
827 s->isr = isr;
828 }
829
830 static void pcnet_init(PCNetState *s)
831 {
832 int rlen, tlen;
833 uint16_t padr[3], ladrf[4], mode;
834 uint32_t rdra, tdra;
835
836 #ifdef PCNET_DEBUG
837 printf("pcnet_init init_addr=0x%08x\n", PHYSADDR(s,CSR_IADR(s)));
838 #endif
839
840 if (BCR_SSIZE32(s)) {
841 struct pcnet_initblk32 initblk;
842 s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
843 (uint8_t *)&initblk, sizeof(initblk), 0);
844 mode = le16_to_cpu(initblk.mode);
845 rlen = initblk.rlen >> 4;
846 tlen = initblk.tlen >> 4;
847 ladrf[0] = le16_to_cpu(initblk.ladrf[0]);
848 ladrf[1] = le16_to_cpu(initblk.ladrf[1]);
849 ladrf[2] = le16_to_cpu(initblk.ladrf[2]);
850 ladrf[3] = le16_to_cpu(initblk.ladrf[3]);
851 padr[0] = le16_to_cpu(initblk.padr[0]);
852 padr[1] = le16_to_cpu(initblk.padr[1]);
853 padr[2] = le16_to_cpu(initblk.padr[2]);
854 rdra = le32_to_cpu(initblk.rdra);
855 tdra = le32_to_cpu(initblk.tdra);
856 } else {
857 struct pcnet_initblk16 initblk;
858 s->phys_mem_read(s->dma_opaque, PHYSADDR(s,CSR_IADR(s)),
859 (uint8_t *)&initblk, sizeof(initblk), 0);
860 mode = le16_to_cpu(initblk.mode);
861 ladrf[0] = le16_to_cpu(initblk.ladrf[0]);
862 ladrf[1] = le16_to_cpu(initblk.ladrf[1]);
863 ladrf[2] = le16_to_cpu(initblk.ladrf[2]);
864 ladrf[3] = le16_to_cpu(initblk.ladrf[3]);
865 padr[0] = le16_to_cpu(initblk.padr[0]);
866 padr[1] = le16_to_cpu(initblk.padr[1]);
867 padr[2] = le16_to_cpu(initblk.padr[2]);
868 rdra = le32_to_cpu(initblk.rdra);
869 tdra = le32_to_cpu(initblk.tdra);
870 rlen = rdra >> 29;
871 tlen = tdra >> 29;
872 rdra &= 0x00ffffff;
873 tdra &= 0x00ffffff;
874 }
875
876 #if defined(PCNET_DEBUG)
877 printf("rlen=%d tlen=%d\n", rlen, tlen);
878 #endif
879
880 CSR_RCVRL(s) = (rlen < 9) ? (1 << rlen) : 512;
881 CSR_XMTRL(s) = (tlen < 9) ? (1 << tlen) : 512;
882 s->csr[ 6] = (tlen << 12) | (rlen << 8);
883 s->csr[15] = mode;
884 s->csr[ 8] = ladrf[0];
885 s->csr[ 9] = ladrf[1];
886 s->csr[10] = ladrf[2];
887 s->csr[11] = ladrf[3];
888 s->csr[12] = padr[0];
889 s->csr[13] = padr[1];
890 s->csr[14] = padr[2];
891 s->rdra = PHYSADDR(s, rdra);
892 s->tdra = PHYSADDR(s, tdra);
893
894 CSR_RCVRC(s) = CSR_RCVRL(s);
895 CSR_XMTRC(s) = CSR_XMTRL(s);
896
897 #ifdef PCNET_DEBUG
898 printf("pcnet ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]\n",
899 BCR_SSIZE32(s),
900 s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s));
901 #endif
902
903 s->csr[0] |= 0x0101;
904 s->csr[0] &= ~0x0004; /* clear STOP bit */
905 }
906
907 static void pcnet_start(PCNetState *s)
908 {
909 #ifdef PCNET_DEBUG
910 printf("pcnet_start\n");
911 #endif
912
913 if (!CSR_DTX(s))
914 s->csr[0] |= 0x0010; /* set TXON */
915
916 if (!CSR_DRX(s))
917 s->csr[0] |= 0x0020; /* set RXON */
918
919 s->csr[0] &= ~0x0004; /* clear STOP bit */
920 s->csr[0] |= 0x0002;
921 }
922
923 static void pcnet_stop(PCNetState *s)
924 {
925 #ifdef PCNET_DEBUG
926 printf("pcnet_stop\n");
927 #endif
928 s->csr[0] &= ~0x7feb;
929 s->csr[0] |= 0x0014;
930 s->csr[4] &= ~0x02c2;
931 s->csr[5] &= ~0x0011;
932 pcnet_poll_timer(s);
933 }
934
935 static void pcnet_rdte_poll(PCNetState *s)
936 {
937 s->csr[28] = s->csr[29] = 0;
938 if (s->rdra) {
939 int bad = 0;
940 #if 1
941 target_phys_addr_t crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
942 target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
943 target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
944 #else
945 target_phys_addr_t crda = s->rdra +
946 (CSR_RCVRL(s) - CSR_RCVRC(s)) *
947 (BCR_SWSTYLE(s) ? 16 : 8 );
948 int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
949 target_phys_addr_t nrda = s->rdra +
950 (CSR_RCVRL(s) - nrdc) *
951 (BCR_SWSTYLE(s) ? 16 : 8 );
952 int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
953 target_phys_addr_t nnrd = s->rdra +
954 (CSR_RCVRL(s) - nnrc) *
955 (BCR_SWSTYLE(s) ? 16 : 8 );
956 #endif
957
958 CHECK_RMD(PHYSADDR(s,crda), bad);
959 if (!bad) {
960 CHECK_RMD(PHYSADDR(s,nrda), bad);
961 if (bad || (nrda == crda)) nrda = 0;
962 CHECK_RMD(PHYSADDR(s,nnrd), bad);
963 if (bad || (nnrd == crda)) nnrd = 0;
964
965 s->csr[28] = crda & 0xffff;
966 s->csr[29] = crda >> 16;
967 s->csr[26] = nrda & 0xffff;
968 s->csr[27] = nrda >> 16;
969 s->csr[36] = nnrd & 0xffff;
970 s->csr[37] = nnrd >> 16;
971 #ifdef PCNET_DEBUG
972 if (bad) {
973 printf("pcnet: BAD RMD RECORDS AFTER 0x%08x\n",
974 PHYSADDR(s,crda));
975 }
976 } else {
977 printf("pcnet: BAD RMD RDA=0x%08x\n", PHYSADDR(s,crda));
978 #endif
979 }
980 }
981
982 if (CSR_CRDA(s)) {
983 struct pcnet_RMD rmd;
984 RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));
985 CSR_CRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
986 CSR_CRST(s) = rmd.status;
987 #ifdef PCNET_DEBUG_RMD_X
988 printf("CRDA=0x%08x CRST=0x%04x RCVRC=%d RMDL=0x%04x RMDS=0x%04x RMDM=0x%08x\n",
989 PHYSADDR(s,CSR_CRDA(s)), CSR_CRST(s), CSR_RCVRC(s),
990 rmd.buf_length, rmd.status, rmd.msg_length);
991 PRINT_RMD(&rmd);
992 #endif
993 } else {
994 CSR_CRBC(s) = CSR_CRST(s) = 0;
995 }
996
997 if (CSR_NRDA(s)) {
998 struct pcnet_RMD rmd;
999 RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));
1000 CSR_NRBC(s) = GET_FIELD(rmd.buf_length, RMDL, BCNT);
1001 CSR_NRST(s) = rmd.status;
1002 } else {
1003 CSR_NRBC(s) = CSR_NRST(s) = 0;
1004 }
1005
1006 }
1007
1008 static int pcnet_tdte_poll(PCNetState *s)
1009 {
1010 s->csr[34] = s->csr[35] = 0;
1011 if (s->tdra) {
1012 target_phys_addr_t cxda = s->tdra +
1013 (CSR_XMTRL(s) - CSR_XMTRC(s)) *
1014 (BCR_SWSTYLE(s) ? 16 : 8);
1015 int bad = 0;
1016 CHECK_TMD(PHYSADDR(s, cxda),bad);
1017 if (!bad) {
1018 if (CSR_CXDA(s) != cxda) {
1019 s->csr[60] = s->csr[34];
1020 s->csr[61] = s->csr[35];
1021 s->csr[62] = CSR_CXBC(s);
1022 s->csr[63] = CSR_CXST(s);
1023 }
1024 s->csr[34] = cxda & 0xffff;
1025 s->csr[35] = cxda >> 16;
1026 #ifdef PCNET_DEBUG_X
1027 printf("pcnet: BAD TMD XDA=0x%08x\n", PHYSADDR(s,cxda));
1028 #endif
1029 }
1030 }
1031
1032 if (CSR_CXDA(s)) {
1033 struct pcnet_TMD tmd;
1034
1035 TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
1036
1037 CSR_CXBC(s) = GET_FIELD(tmd.length, TMDL, BCNT);
1038 CSR_CXST(s) = tmd.status;
1039 } else {
1040 CSR_CXBC(s) = CSR_CXST(s) = 0;
1041 }
1042
1043 return !!(CSR_CXST(s) & 0x8000);
1044 }
1045
1046 static int pcnet_can_receive(void *opaque)
1047 {
1048 PCNetState *s = opaque;
1049 if (CSR_STOP(s) || CSR_SPND(s))
1050 return 0;
1051
1052 if (s->recv_pos > 0)
1053 return 0;
1054
1055 return sizeof(s->buffer)-16;
1056 }
1057
1058 #define MIN_BUF_SIZE 60
1059
1060 static void pcnet_receive(void *opaque, const uint8_t *buf, int size)
1061 {
1062 PCNetState *s = opaque;
1063 int is_padr = 0, is_bcast = 0, is_ladr = 0;
1064 uint8_t buf1[60];
1065
1066 if (CSR_DRX(s) || CSR_STOP(s) || CSR_SPND(s) || !size)
1067 return;
1068
1069 #ifdef PCNET_DEBUG
1070 printf("pcnet_receive size=%d\n", size);
1071 #endif
1072
1073 /* if too small buffer, then expand it */
1074 if (size < MIN_BUF_SIZE) {
1075 memcpy(buf1, buf, size);
1076 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
1077 buf = buf1;
1078 size = MIN_BUF_SIZE;
1079 }
1080
1081 if (CSR_PROM(s)
1082 || (is_padr=padr_match(s, buf, size))
1083 || (is_bcast=padr_bcast(s, buf, size))
1084 || (is_ladr=ladr_match(s, buf, size))) {
1085
1086 pcnet_rdte_poll(s);
1087
1088 if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
1089 struct pcnet_RMD rmd;
1090 int rcvrc = CSR_RCVRC(s)-1,i;
1091 target_phys_addr_t nrda;
1092 for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
1093 if (rcvrc <= 1)
1094 rcvrc = CSR_RCVRL(s);
1095 nrda = s->rdra +
1096 (CSR_RCVRL(s) - rcvrc) *
1097 (BCR_SWSTYLE(s) ? 16 : 8 );
1098 RMDLOAD(&rmd, PHYSADDR(s,nrda));
1099 if (GET_FIELD(rmd.status, RMDS, OWN)) {
1100 #ifdef PCNET_DEBUG_RMD
1101 printf("pcnet - scan buffer: RCVRC=%d PREV_RCVRC=%d\n",
1102 rcvrc, CSR_RCVRC(s));
1103 #endif
1104 CSR_RCVRC(s) = rcvrc;
1105 pcnet_rdte_poll(s);
1106 break;
1107 }
1108 }
1109 }
1110
1111 if (!(CSR_CRST(s) & 0x8000)) {
1112 #ifdef PCNET_DEBUG_RMD
1113 printf("pcnet - no buffer: RCVRC=%d\n", CSR_RCVRC(s));
1114 #endif
1115 s->csr[0] |= 0x1000; /* Set MISS flag */
1116 CSR_MISSC(s)++;
1117 } else {
1118 uint8_t *src = &s->buffer[8];
1119 target_phys_addr_t crda = CSR_CRDA(s);
1120 struct pcnet_RMD rmd;
1121 int pktcount = 0;
1122
1123 memcpy(src, buf, size);
1124
1125 #if 1
1126 /* no need to compute the CRC */
1127 src[size] = 0;
1128 src[size + 1] = 0;
1129 src[size + 2] = 0;
1130 src[size + 3] = 0;
1131 size += 4;
1132 #else
1133 /* XXX: avoid CRC generation */
1134 if (!CSR_ASTRP_RCV(s)) {
1135 uint32_t fcs = ~0;
1136 uint8_t *p = src;
1137
1138 while (size < 46) {
1139 src[size++] = 0;
1140 }
1141
1142 while (p != &src[size]) {
1143 CRC(fcs, *p++);
1144 }
1145 ((uint32_t *)&src[size])[0] = htonl(fcs);
1146 size += 4; /* FCS at end of packet */
1147 } else size += 4;
1148 #endif
1149
1150 #ifdef PCNET_DEBUG_MATCH
1151 PRINT_PKTHDR(buf);
1152 #endif
1153
1154 RMDLOAD(&rmd, PHYSADDR(s,crda));
1155 /*if (!CSR_LAPPEN(s))*/
1156 SET_FIELD(&rmd.status, RMDS, STP, 1);
1157
1158 #define PCNET_RECV_STORE() do { \
1159 int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),size); \
1160 target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr); \
1161 s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
1162 src += count; size -= count; \
1163 SET_FIELD(&rmd.msg_length, RMDM, MCNT, count); \
1164 SET_FIELD(&rmd.status, RMDS, OWN, 0); \
1165 RMDSTORE(&rmd, PHYSADDR(s,crda)); \
1166 pktcount++; \
1167 } while (0)
1168
1169 PCNET_RECV_STORE();
1170 if ((size > 0) && CSR_NRDA(s)) {
1171 target_phys_addr_t nrda = CSR_NRDA(s);
1172 RMDLOAD(&rmd, PHYSADDR(s,nrda));
1173 if (GET_FIELD(rmd.status, RMDS, OWN)) {
1174 crda = nrda;
1175 PCNET_RECV_STORE();
1176 if ((size > 0) && (nrda=CSR_NNRD(s))) {
1177 RMDLOAD(&rmd, PHYSADDR(s,nrda));
1178 if (GET_FIELD(rmd.status, RMDS, OWN)) {
1179 crda = nrda;
1180 PCNET_RECV_STORE();
1181 }
1182 }
1183 }
1184 }
1185
1186 #undef PCNET_RECV_STORE
1187
1188 RMDLOAD(&rmd, PHYSADDR(s,crda));
1189 if (size == 0) {
1190 SET_FIELD(&rmd.status, RMDS, ENP, 1);
1191 SET_FIELD(&rmd.status, RMDS, PAM, !CSR_PROM(s) && is_padr);
1192 SET_FIELD(&rmd.status, RMDS, LFAM, !CSR_PROM(s) && is_ladr);
1193 SET_FIELD(&rmd.status, RMDS, BAM, !CSR_PROM(s) && is_bcast);
1194 } else {
1195 SET_FIELD(&rmd.status, RMDS, OFLO, 1);
1196 SET_FIELD(&rmd.status, RMDS, BUFF, 1);
1197 SET_FIELD(&rmd.status, RMDS, ERR, 1);
1198 }
1199 RMDSTORE(&rmd, PHYSADDR(s,crda));
1200 s->csr[0] |= 0x0400;
1201
1202 #ifdef PCNET_DEBUG
1203 printf("RCVRC=%d CRDA=0x%08x BLKS=%d\n",
1204 CSR_RCVRC(s), PHYSADDR(s,CSR_CRDA(s)), pktcount);
1205 #endif
1206 #ifdef PCNET_DEBUG_RMD
1207 PRINT_RMD(&rmd);
1208 #endif
1209
1210 while (pktcount--) {
1211 if (CSR_RCVRC(s) <= 1)
1212 CSR_RCVRC(s) = CSR_RCVRL(s);
1213 else
1214 CSR_RCVRC(s)--;
1215 }
1216
1217 pcnet_rdte_poll(s);
1218
1219 }
1220 }
1221
1222 pcnet_poll(s);
1223 pcnet_update_irq(s);
1224 }
1225
1226 static void pcnet_transmit(PCNetState *s)
1227 {
1228 target_phys_addr_t xmit_cxda = 0;
1229 int count = CSR_XMTRL(s)-1;
1230 s->xmit_pos = -1;
1231
1232 if (!CSR_TXON(s)) {
1233 s->csr[0] &= ~0x0008;
1234 return;
1235 }
1236
1237 s->tx_busy = 1;
1238
1239 txagain:
1240 if (pcnet_tdte_poll(s)) {
1241 struct pcnet_TMD tmd;
1242
1243 TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));
1244
1245 #ifdef PCNET_DEBUG_TMD
1246 printf(" TMDLOAD 0x%08x\n", PHYSADDR(s,CSR_CXDA(s)));
1247 PRINT_TMD(&tmd);
1248 #endif
1249 if (GET_FIELD(tmd.status, TMDS, STP)) {
1250 s->xmit_pos = 0;
1251 if (!GET_FIELD(tmd.status, TMDS, ENP)) {
1252 int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
1253 s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
1254 s->buffer, bcnt, CSR_BSWP(s));
1255 s->xmit_pos += bcnt;
1256 }
1257 xmit_cxda = PHYSADDR(s,CSR_CXDA(s));
1258 }
1259 if (GET_FIELD(tmd.status, TMDS, ENP) && (s->xmit_pos >= 0)) {
1260 int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
1261 s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
1262 s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
1263 s->xmit_pos += bcnt;
1264 #ifdef PCNET_DEBUG
1265 printf("pcnet_transmit size=%d\n", s->xmit_pos);
1266 #endif
1267 if (CSR_LOOP(s))
1268 pcnet_receive(s, s->buffer, s->xmit_pos);
1269 else
1270 qemu_send_packet(s->vc, s->buffer, s->xmit_pos);
1271
1272 s->csr[0] &= ~0x0008; /* clear TDMD */
1273 s->csr[4] |= 0x0004; /* set TXSTRT */
1274 s->xmit_pos = -1;
1275 }
1276
1277 SET_FIELD(&tmd.status, TMDS, OWN, 0);
1278 TMDSTORE(&tmd, PHYSADDR(s,CSR_CXDA(s)));
1279 if (!CSR_TOKINTD(s) || (CSR_LTINTEN(s) && GET_FIELD(tmd.status, TMDS, LTINT)))
1280 s->csr[0] |= 0x0200; /* set TINT */
1281
1282 if (CSR_XMTRC(s)<=1)
1283 CSR_XMTRC(s) = CSR_XMTRL(s);
1284 else
1285 CSR_XMTRC(s)--;
1286 if (count--)
1287 goto txagain;
1288
1289 } else
1290 if (s->xmit_pos >= 0) {
1291 struct pcnet_TMD tmd;
1292 TMDLOAD(&tmd, PHYSADDR(s,xmit_cxda));
1293 SET_FIELD(&tmd.misc, TMDM, BUFF, 1);
1294 SET_FIELD(&tmd.misc, TMDM, UFLO, 1);
1295 SET_FIELD(&tmd.status, TMDS, ERR, 1);
1296 SET_FIELD(&tmd.status, TMDS, OWN, 0);
1297 TMDSTORE(&tmd, PHYSADDR(s,xmit_cxda));
1298 s->csr[0] |= 0x0200; /* set TINT */
1299 if (!CSR_DXSUFLO(s)) {
1300 s->csr[0] &= ~0x0010;
1301 } else
1302 if (count--)
1303 goto txagain;
1304 }
1305
1306 s->tx_busy = 0;
1307 }
1308
1309 static void pcnet_poll(PCNetState *s)
1310 {
1311 if (CSR_RXON(s)) {
1312 pcnet_rdte_poll(s);
1313 }
1314
1315 if (CSR_TDMD(s) ||
1316 (CSR_TXON(s) && !CSR_DPOLL(s) && pcnet_tdte_poll(s)))
1317 {
1318 /* prevent recursion */
1319 if (s->tx_busy)
1320 return;
1321
1322 pcnet_transmit(s);
1323 }
1324 }
1325
1326 static void pcnet_poll_timer(void *opaque)
1327 {
1328 PCNetState *s = opaque;
1329
1330 qemu_del_timer(s->poll_timer);
1331
1332 if (CSR_TDMD(s)) {
1333 pcnet_transmit(s);
1334 }
1335
1336 pcnet_update_irq(s);
1337
1338 if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
1339 uint64_t now = qemu_get_clock(vm_clock) * 33;
1340 if (!s->timer || !now)
1341 s->timer = now;
1342 else {
1343 uint64_t t = now - s->timer + CSR_POLL(s);
1344 if (t > 0xffffLL) {
1345 pcnet_poll(s);
1346 CSR_POLL(s) = CSR_PINT(s);
1347 } else
1348 CSR_POLL(s) = t;
1349 }
1350 qemu_mod_timer(s->poll_timer,
1351 pcnet_get_next_poll_time(s,qemu_get_clock(vm_clock)));
1352 }
1353 }
1354
1355
1356 static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value)
1357 {
1358 uint16_t val = new_value;
1359 #ifdef PCNET_DEBUG_CSR
1360 printf("pcnet_csr_writew rap=%d val=0x%04x\n", rap, val);
1361 #endif
1362 switch (rap) {
1363 case 0:
1364 s->csr[0] &= ~(val & 0x7f00); /* Clear any interrupt flags */
1365
1366 s->csr[0] = (s->csr[0] & ~0x0040) | (val & 0x0048);
1367
1368 val = (val & 0x007f) | (s->csr[0] & 0x7f00);
1369
1370 /* IFF STOP, STRT and INIT are set, clear STRT and INIT */
1371 if ((val&7) == 7)
1372 val &= ~3;
1373
1374 if (!CSR_STOP(s) && (val & 4))
1375 pcnet_stop(s);
1376
1377 if (!CSR_INIT(s) && (val & 1))
1378 pcnet_init(s);
1379
1380 if (!CSR_STRT(s) && (val & 2))
1381 pcnet_start(s);
1382
1383 if (CSR_TDMD(s))
1384 pcnet_transmit(s);
1385
1386 return;
1387 case 1:
1388 case 2:
1389 case 8:
1390 case 9:
1391 case 10:
1392 case 11:
1393 case 12:
1394 case 13:
1395 case 14:
1396 case 15:
1397 case 18: /* CRBAL */
1398 case 19: /* CRBAU */
1399 case 20: /* CXBAL */
1400 case 21: /* CXBAU */
1401 case 22: /* NRBAU */
1402 case 23: /* NRBAU */
1403 case 24:
1404 case 25:
1405 case 26:
1406 case 27:
1407 case 28:
1408 case 29:
1409 case 30:
1410 case 31:
1411 case 32:
1412 case 33:
1413 case 34:
1414 case 35:
1415 case 36:
1416 case 37:
1417 case 38:
1418 case 39:
1419 case 40: /* CRBC */
1420 case 41:
1421 case 42: /* CXBC */
1422 case 43:
1423 case 44:
1424 case 45:
1425 case 46: /* POLL */
1426 case 47: /* POLLINT */
1427 case 72:
1428 case 74:
1429 case 76: /* RCVRL */
1430 case 78: /* XMTRL */
1431 case 112:
1432 if (CSR_STOP(s) || CSR_SPND(s))
1433 break;
1434 return;
1435 case 3:
1436 break;
1437 case 4:
1438 s->csr[4] &= ~(val & 0x026a);
1439 val &= ~0x026a; val |= s->csr[4] & 0x026a;
1440 break;
1441 case 5:
1442 s->csr[5] &= ~(val & 0x0a90);
1443 val &= ~0x0a90; val |= s->csr[5] & 0x0a90;
1444 break;
1445 case 16:
1446 pcnet_csr_writew(s,1,val);
1447 return;
1448 case 17:
1449 pcnet_csr_writew(s,2,val);
1450 return;
1451 case 58:
1452 pcnet_bcr_writew(s,BCR_SWS,val);
1453 break;
1454 default:
1455 return;
1456 }
1457 s->csr[rap] = val;
1458 }
1459
1460 static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap)
1461 {
1462 uint32_t val;
1463 switch (rap) {
1464 case 0:
1465 pcnet_update_irq(s);
1466 val = s->csr[0];
1467 val |= (val & 0x7800) ? 0x8000 : 0;
1468 break;
1469 case 16:
1470 return pcnet_csr_readw(s,1);
1471 case 17:
1472 return pcnet_csr_readw(s,2);
1473 case 58:
1474 return pcnet_bcr_readw(s,BCR_SWS);
1475 case 88:
1476 val = s->csr[89];
1477 val <<= 16;
1478 val |= s->csr[88];
1479 break;
1480 default:
1481 val = s->csr[rap];
1482 }
1483 #ifdef PCNET_DEBUG_CSR
1484 printf("pcnet_csr_readw rap=%d val=0x%04x\n", rap, val);
1485 #endif
1486 return val;
1487 }
1488
1489 static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val)
1490 {
1491 rap &= 127;
1492 #ifdef PCNET_DEBUG_BCR
1493 printf("pcnet_bcr_writew rap=%d val=0x%04x\n", rap, val);
1494 #endif
1495 switch (rap) {
1496 case BCR_SWS:
1497 if (!(CSR_STOP(s) || CSR_SPND(s)))
1498 return;
1499 val &= ~0x0300;
1500 switch (val & 0x00ff) {
1501 case 0:
1502 val |= 0x0200;
1503 break;
1504 case 1:
1505 val |= 0x0100;
1506 break;
1507 case 2:
1508 case 3:
1509 val |= 0x0300;
1510 break;
1511 default:
1512 printf("Bad SWSTYLE=0x%02x\n", val & 0xff);
1513 val = 0x0200;
1514 break;
1515 }
1516 #ifdef PCNET_DEBUG
1517 printf("BCR_SWS=0x%04x\n", val);
1518 #endif
1519 case BCR_LNKST:
1520 case BCR_LED1:
1521 case BCR_LED2:
1522 case BCR_LED3:
1523 case BCR_MC:
1524 case BCR_FDC:
1525 case BCR_BSBC:
1526 case BCR_EECAS:
1527 case BCR_PLAT:
1528 s->bcr[rap] = val;
1529 break;
1530 default:
1531 break;
1532 }
1533 }
1534
1535 static uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap)
1536 {
1537 uint32_t val;
1538 rap &= 127;
1539 switch (rap) {
1540 case BCR_LNKST:
1541 case BCR_LED1:
1542 case BCR_LED2:
1543 case BCR_LED3:
1544 val = s->bcr[rap] & ~0x8000;
1545 val |= (val & 0x017f & s->lnkst) ? 0x8000 : 0;
1546 break;
1547 default:
1548 val = rap < 32 ? s->bcr[rap] : 0;
1549 break;
1550 }
1551 #ifdef PCNET_DEBUG_BCR
1552 printf("pcnet_bcr_readw rap=%d val=0x%04x\n", rap, val);
1553 #endif
1554 return val;
1555 }
1556
1557 void pcnet_h_reset(void *opaque)
1558 {
1559 PCNetState *s = opaque;
1560 int i;
1561 uint16_t checksum;
1562
1563 /* Initialize the PROM */
1564
1565 memcpy(s->prom, s->nd->macaddr, 6);
1566 s->prom[12] = s->prom[13] = 0x00;
1567 s->prom[14] = s->prom[15] = 0x57;
1568
1569 for (i = 0,checksum = 0; i < 16; i++)
1570 checksum += s->prom[i];
1571 *(uint16_t *)&s->prom[12] = cpu_to_le16(checksum);
1572
1573
1574 s->bcr[BCR_MSRDA] = 0x0005;
1575 s->bcr[BCR_MSWRA] = 0x0005;
1576 s->bcr[BCR_MC ] = 0x0002;
1577 s->bcr[BCR_LNKST] = 0x00c0;
1578 s->bcr[BCR_LED1 ] = 0x0084;
1579 s->bcr[BCR_LED2 ] = 0x0088;
1580 s->bcr[BCR_LED3 ] = 0x0090;
1581 s->bcr[BCR_FDC ] = 0x0000;
1582 s->bcr[BCR_BSBC ] = 0x9001;
1583 s->bcr[BCR_EECAS] = 0x0002;
1584 s->bcr[BCR_SWS ] = 0x0200;
1585 s->bcr[BCR_PLAT ] = 0xff06;
1586
1587 pcnet_s_reset(s);
1588 }
1589
1590 static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
1591 {
1592 PCNetState *s = opaque;
1593 #ifdef PCNET_DEBUG
1594 printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
1595 #endif
1596 /* Check APROMWE bit to enable write access */
1597 if (pcnet_bcr_readw(s,2) & 0x80)
1598 s->prom[addr & 15] = val;
1599 }
1600
1601 static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
1602 {
1603 PCNetState *s = opaque;
1604 uint32_t val = s->prom[addr &= 15];
1605 #ifdef PCNET_DEBUG
1606 printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val);
1607 #endif
1608 return val;
1609 }
1610
1611 static void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
1612 {
1613 PCNetState *s = opaque;
1614 pcnet_poll_timer(s);
1615 #ifdef PCNET_DEBUG_IO
1616 printf("pcnet_ioport_writew addr=0x%08x val=0x%04x\n", addr, val);
1617 #endif
1618 if (!BCR_DWIO(s)) {
1619 switch (addr & 0x0f) {
1620 case 0x00: /* RDP */
1621 pcnet_csr_writew(s, s->rap, val);
1622 break;
1623 case 0x02:
1624 s->rap = val & 0x7f;
1625 break;
1626 case 0x06:
1627 pcnet_bcr_writew(s, s->rap, val);
1628 break;
1629 }
1630 }
1631 pcnet_update_irq(s);
1632 }
1633
1634 static uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr)
1635 {
1636 PCNetState *s = opaque;
1637 uint32_t val = -1;
1638 pcnet_poll_timer(s);
1639 if (!BCR_DWIO(s)) {
1640 switch (addr & 0x0f) {
1641 case 0x00: /* RDP */
1642 val = pcnet_csr_readw(s, s->rap);
1643 break;
1644 case 0x02:
1645 val = s->rap;
1646 break;
1647 case 0x04:
1648 pcnet_s_reset(s);
1649 val = 0;
1650 break;
1651 case 0x06:
1652 val = pcnet_bcr_readw(s, s->rap);
1653 break;
1654 }
1655 }
1656 pcnet_update_irq(s);
1657 #ifdef PCNET_DEBUG_IO
1658 printf("pcnet_ioport_readw addr=0x%08x val=0x%04x\n", addr, val & 0xffff);
1659 #endif
1660 return val;
1661 }
1662
1663 static void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
1664 {
1665 PCNetState *s = opaque;
1666 pcnet_poll_timer(s);
1667 #ifdef PCNET_DEBUG_IO
1668 printf("pcnet_ioport_writel addr=0x%08x val=0x%08x\n", addr, val);
1669 #endif
1670 if (BCR_DWIO(s)) {
1671 switch (addr & 0x0f) {
1672 case 0x00: /* RDP */
1673 pcnet_csr_writew(s, s->rap, val & 0xffff);
1674 break;
1675 case 0x04:
1676 s->rap = val & 0x7f;
1677 break;
1678 case 0x0c:
1679 pcnet_bcr_writew(s, s->rap, val & 0xffff);
1680 break;
1681 }
1682 } else
1683 if ((addr & 0x0f) == 0) {
1684 /* switch device to dword i/o mode */
1685 pcnet_bcr_writew(s, BCR_BSBC, pcnet_bcr_readw(s, BCR_BSBC) | 0x0080);
1686 #ifdef PCNET_DEBUG_IO
1687 printf("device switched into dword i/o mode\n");
1688 #endif
1689 }
1690 pcnet_update_irq(s);
1691 }
1692
1693 static uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr)
1694 {
1695 PCNetState *s = opaque;
1696 uint32_t val = -1;
1697 pcnet_poll_timer(s);
1698 if (BCR_DWIO(s)) {
1699 switch (addr & 0x0f) {
1700 case 0x00: /* RDP */
1701 val = pcnet_csr_readw(s, s->rap);
1702 break;
1703 case 0x04:
1704 val = s->rap;
1705 break;
1706 case 0x08:
1707 pcnet_s_reset(s);
1708 val = 0;
1709 break;
1710 case 0x0c:
1711 val = pcnet_bcr_readw(s, s->rap);
1712 break;
1713 }
1714 }
1715 pcnet_update_irq(s);
1716 #ifdef PCNET_DEBUG_IO
1717 printf("pcnet_ioport_readl addr=0x%08x val=0x%08x\n", addr, val);
1718 #endif
1719 return val;
1720 }
1721
1722 static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
1723 uint32_t addr, uint32_t size, int type)
1724 {
1725 PCNetState *d = (PCNetState *)pci_dev;
1726
1727 #ifdef PCNET_DEBUG_IO
1728 printf("pcnet_ioport_map addr=0x%04x size=0x%04x\n", addr, size);
1729 #endif
1730
1731 register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
1732 register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d);
1733
1734 register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d);
1735 register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d);
1736 register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d);
1737 register_ioport_read(addr + 0x10, 0x10, 4, pcnet_ioport_readl, d);
1738 }
1739
1740 static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1741 {
1742 PCNetState *d = opaque;
1743 #ifdef PCNET_DEBUG_IO
1744 printf("pcnet_mmio_writeb addr=0x%08x val=0x%02x\n", addr, val);
1745 #endif
1746 if (!(addr & 0x10))
1747 pcnet_aprom_writeb(d, addr & 0x0f, val);
1748 }
1749
1750 static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr)
1751 {
1752 PCNetState *d = opaque;
1753 uint32_t val = -1;
1754 if (!(addr & 0x10))
1755 val = pcnet_aprom_readb(d, addr & 0x0f);
1756 #ifdef PCNET_DEBUG_IO
1757 printf("pcnet_mmio_readb addr=0x%08x val=0x%02x\n", addr, val & 0xff);
1758 #endif
1759 return val;
1760 }
1761
1762 static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1763 {
1764 PCNetState *d = opaque;
1765 #ifdef PCNET_DEBUG_IO
1766 printf("pcnet_mmio_writew addr=0x%08x val=0x%04x\n", addr, val);
1767 #endif
1768 if (addr & 0x10)
1769 pcnet_ioport_writew(d, addr & 0x0f, val);
1770 else {
1771 addr &= 0x0f;
1772 pcnet_aprom_writeb(d, addr, val & 0xff);
1773 pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
1774 }
1775 }
1776
1777 static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr)
1778 {
1779 PCNetState *d = opaque;
1780 uint32_t val = -1;
1781 if (addr & 0x10)
1782 val = pcnet_ioport_readw(d, addr & 0x0f);
1783 else {
1784 addr &= 0x0f;
1785 val = pcnet_aprom_readb(d, addr+1);
1786 val <<= 8;
1787 val |= pcnet_aprom_readb(d, addr);
1788 }
1789 #ifdef PCNET_DEBUG_IO
1790 printf("pcnet_mmio_readw addr=0x%08x val = 0x%04x\n", addr, val & 0xffff);
1791 #endif
1792 return val;
1793 }
1794
1795 static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1796 {
1797 PCNetState *d = opaque;
1798 #ifdef PCNET_DEBUG_IO
1799 printf("pcnet_mmio_writel addr=0x%08x val=0x%08x\n", addr, val);
1800 #endif
1801 if (addr & 0x10)
1802 pcnet_ioport_writel(d, addr & 0x0f, val);
1803 else {
1804 addr &= 0x0f;
1805 pcnet_aprom_writeb(d, addr, val & 0xff);
1806 pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
1807 pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
1808 pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
1809 }
1810 }
1811
1812 static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr)
1813 {
1814 PCNetState *d = opaque;
1815 uint32_t val;
1816 if (addr & 0x10)
1817 val = pcnet_ioport_readl(d, addr & 0x0f);
1818 else {
1819 addr &= 0x0f;
1820 val = pcnet_aprom_readb(d, addr+3);
1821 val <<= 8;
1822 val |= pcnet_aprom_readb(d, addr+2);
1823 val <<= 8;
1824 val |= pcnet_aprom_readb(d, addr+1);
1825 val <<= 8;
1826 val |= pcnet_aprom_readb(d, addr);
1827 }
1828 #ifdef PCNET_DEBUG_IO
1829 printf("pcnet_mmio_readl addr=0x%08x val=0x%08x\n", addr, val);
1830 #endif
1831 return val;
1832 }
1833
1834
1835 static void pcnet_save(QEMUFile *f, void *opaque)
1836 {
1837 PCNetState *s = opaque;
1838 unsigned int i;
1839
1840 if (s->pci_dev)
1841 pci_device_save(s->pci_dev, f);
1842
1843 qemu_put_be32s(f, &s->rap);
1844 qemu_put_be32s(f, &s->isr);
1845 qemu_put_be32s(f, &s->lnkst);
1846 qemu_put_be32s(f, &s->rdra);
1847 qemu_put_be32s(f, &s->tdra);
1848 qemu_put_buffer(f, s->prom, 16);
1849 for (i = 0; i < 128; i++)
1850 qemu_put_be16s(f, &s->csr[i]);
1851 for (i = 0; i < 32; i++)
1852 qemu_put_be16s(f, &s->bcr[i]);
1853 qemu_put_be64s(f, &s->timer);
1854 qemu_put_be32s(f, &s->xmit_pos);
1855 qemu_put_be32s(f, &s->recv_pos);
1856 qemu_put_buffer(f, s->buffer, 4096);
1857 qemu_put_be32s(f, &s->tx_busy);
1858 qemu_put_timer(f, s->poll_timer);
1859 }
1860
1861 static int pcnet_load(QEMUFile *f, void *opaque, int version_id)
1862 {
1863 PCNetState *s = opaque;
1864 int i, ret;
1865
1866 if (version_id != 2)
1867 return -EINVAL;
1868
1869 if (s->pci_dev) {
1870 ret = pci_device_load(s->pci_dev, f);
1871 if (ret < 0)
1872 return ret;
1873 }
1874
1875 qemu_get_be32s(f, &s->rap);
1876 qemu_get_be32s(f, &s->isr);
1877 qemu_get_be32s(f, &s->lnkst);
1878 qemu_get_be32s(f, &s->rdra);
1879 qemu_get_be32s(f, &s->tdra);
1880 qemu_get_buffer(f, s->prom, 16);
1881 for (i = 0; i < 128; i++)
1882 qemu_get_be16s(f, &s->csr[i]);
1883 for (i = 0; i < 32; i++)
1884 qemu_get_be16s(f, &s->bcr[i]);
1885 qemu_get_be64s(f, &s->timer);
1886 qemu_get_be32s(f, &s->xmit_pos);
1887 qemu_get_be32s(f, &s->recv_pos);
1888 qemu_get_buffer(f, s->buffer, 4096);
1889 qemu_get_be32s(f, &s->tx_busy);
1890 qemu_get_timer(f, s->poll_timer);
1891
1892 return 0;
1893 }
1894
1895 static void pcnet_common_init(PCNetState *d, NICInfo *nd, const char *info_str)
1896 {
1897 d->poll_timer = qemu_new_timer(vm_clock, pcnet_poll_timer, d);
1898
1899 d->nd = nd;
1900
1901 d->vc = qemu_new_vlan_client(nd->vlan, pcnet_receive,
1902 pcnet_can_receive, d);
1903
1904 snprintf(d->vc->info_str, sizeof(d->vc->info_str),
1905 "pcnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
1906 d->nd->macaddr[0],
1907 d->nd->macaddr[1],
1908 d->nd->macaddr[2],
1909 d->nd->macaddr[3],
1910 d->nd->macaddr[4],
1911 d->nd->macaddr[5]);
1912
1913 pcnet_h_reset(d);
1914 register_savevm("pcnet", 0, 2, pcnet_save, pcnet_load, d);
1915 }
1916
1917 /* PCI interface */
1918
1919 static CPUWriteMemoryFunc *pcnet_mmio_write[] = {
1920 (CPUWriteMemoryFunc *)&pcnet_mmio_writeb,
1921 (CPUWriteMemoryFunc *)&pcnet_mmio_writew,
1922 (CPUWriteMemoryFunc *)&pcnet_mmio_writel
1923 };
1924
1925 static CPUReadMemoryFunc *pcnet_mmio_read[] = {
1926 (CPUReadMemoryFunc *)&pcnet_mmio_readb,
1927 (CPUReadMemoryFunc *)&pcnet_mmio_readw,
1928 (CPUReadMemoryFunc *)&pcnet_mmio_readl
1929 };
1930
1931 static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
1932 uint32_t addr, uint32_t size, int type)
1933 {
1934 PCNetState *d = (PCNetState *)pci_dev;
1935
1936 #ifdef PCNET_DEBUG_IO
1937 printf("pcnet_ioport_map addr=0x%08x 0x%08x\n", addr, size);
1938 #endif
1939
1940 cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->mmio_index);
1941 }
1942
1943 static void pci_physical_memory_write(void *dma_opaque, target_phys_addr_t addr,
1944 uint8_t *buf, int len, int do_bswap)
1945 {
1946 cpu_physical_memory_write(addr, buf, len);
1947 }
1948
1949 static void pci_physical_memory_read(void *dma_opaque, target_phys_addr_t addr,
1950 uint8_t *buf, int len, int do_bswap)
1951 {
1952 cpu_physical_memory_read(addr, buf, len);
1953 }
1954
1955 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
1956 {
1957 PCNetState *d;
1958 uint8_t *pci_conf;
1959
1960 #if 0
1961 printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n",
1962 sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
1963 #endif
1964
1965 d = (PCNetState *)pci_register_device(bus, "PCNet", sizeof(PCNetState),
1966 devfn, NULL, NULL);
1967
1968 pci_conf = d->dev.config;
1969
1970 *(uint16_t *)&pci_conf[0x00] = cpu_to_le16(0x1022);
1971 *(uint16_t *)&pci_conf[0x02] = cpu_to_le16(0x2000);
1972 *(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007);
1973 *(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
1974 pci_conf[0x08] = 0x10;
1975 pci_conf[0x09] = 0x00;
1976 pci_conf[0x0a] = 0x00; // ethernet network controller
1977 pci_conf[0x0b] = 0x02;
1978 pci_conf[0x0e] = 0x00; // header_type
1979
1980 *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
1981 *(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000);
1982
1983 pci_conf[0x3d] = 1; // interrupt pin 0
1984 pci_conf[0x3e] = 0x06;
1985 pci_conf[0x3f] = 0xff;
1986
1987 /* Handler for memory-mapped I/O */
1988 d->mmio_index =
1989 cpu_register_io_memory(0, pcnet_mmio_read, pcnet_mmio_write, d);
1990
1991 pci_register_io_region((PCIDevice *)d, 0, PCNET_IOPORT_SIZE,
1992 PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);
1993
1994 pci_register_io_region((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE,
1995 PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);
1996
1997 d->irq = d->dev.irq[0];
1998 d->phys_mem_read = pci_physical_memory_read;
1999 d->phys_mem_write = pci_physical_memory_write;
2000 d->pci_dev = &d->dev;
2001
2002 pcnet_common_init(d, nd, "pcnet");
2003 }
2004
2005 /* SPARC32 interface */
2006
2007 #if defined (TARGET_SPARC) && !defined(TARGET_SPARC64) // Avoid compile failure
2008
2009 static CPUReadMemoryFunc *lance_mem_read[3] = {
2010 (CPUReadMemoryFunc *)&pcnet_ioport_readw,
2011 (CPUReadMemoryFunc *)&pcnet_ioport_readw,
2012 (CPUReadMemoryFunc *)&pcnet_ioport_readw,
2013 };
2014
2015 static CPUWriteMemoryFunc *lance_mem_write[3] = {
2016 (CPUWriteMemoryFunc *)&pcnet_ioport_writew,
2017 (CPUWriteMemoryFunc *)&pcnet_ioport_writew,
2018 (CPUWriteMemoryFunc *)&pcnet_ioport_writew,
2019 };
2020
2021 void *lance_init(NICInfo *nd, uint32_t leaddr, void *dma_opaque, qemu_irq irq)
2022 {
2023 PCNetState *d;
2024 int lance_io_memory;
2025
2026 d = qemu_mallocz(sizeof(PCNetState));
2027 if (!d)
2028 return NULL;
2029
2030 lance_io_memory =
2031 cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);
2032
2033 d->dma_opaque = dma_opaque;
2034 cpu_register_physical_memory(leaddr, 4, lance_io_memory);
2035
2036 d->irq = irq;
2037 d->phys_mem_read = ledma_memory_read;
2038 d->phys_mem_write = ledma_memory_write;
2039
2040 pcnet_common_init(d, nd, "lance");
2041
2042 return d;
2043 }
2044 #endif /* TARGET_SPARC */
Samsung s3c2440 and arm920t support for the mini2440 dev board