hw/cs4231.c

   1 /*
   2  * QEMU Crystal CS4231 audio chip emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug CS4231 */
  27 //#define DEBUG_CS
  28
  29 /*
  30  * In addition to Crystal CS4231 there is a DMA controller on Sparc.
  31  */
  32 #define CS_MAXADDR 0x3f
  33 #define CS_REGS 16
  34 #define CS_DREGS 32
  35 #define CS_MAXDREG (CS_DREGS - 1)
  36
  37 typedef struct CSState {
  38     uint32_t regs[CS_REGS];
  39     uint8_t dregs[CS_DREGS];
  40     void *intctl;
  41 } CSState;
  42
  43 #define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
  44 #define CS_VER 0xa0
  45 #define CS_CDC_VER 0x8a
  46
  47 #ifdef DEBUG_CS
  48 #define DPRINTF(fmt, args...)                           \
  49     do { printf("CS: " fmt , ##args); } while (0)
  50 #else
  51 #define DPRINTF(fmt, args...)
  52 #endif
  53
  54 static void cs_reset(void *opaque)
  55 {
  56     CSState *s = opaque;
  57
  58     memset(s->regs, 0, CS_REGS * 4);
  59     memset(s->dregs, 0, CS_DREGS);
  60     s->dregs[12] = CS_CDC_VER;
  61     s->dregs[25] = CS_VER;
  62 }
  63
  64 static uint32_t cs_mem_readl(void *opaque, target_phys_addr_t addr)
  65 {
  66     CSState *s = opaque;
  67     uint32_t saddr, ret;
  68
  69     saddr = (addr & CS_MAXADDR) >> 2;
  70     switch (saddr) {
  71     case 1:
  72         switch (CS_RAP(s)) {
  73         case 3: // Write only
  74             ret = 0;
  75             break;
  76         default:
  77             ret = s->dregs[CS_RAP(s)];
  78             break;
  79         }
  80         DPRINTF("read dreg[%d]: 0x%8.8x\n", CS_RAP(s), ret);
  81         break;
  82     default:
  83         ret = s->regs[saddr];
  84         DPRINTF("read reg[%d]: 0x%8.8x\n", saddr, ret);
  85         break;
  86     }
  87     return ret;
  88 }
  89
  90 static void cs_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  91 {
  92     CSState *s = opaque;
  93     uint32_t saddr;
  94
  95     saddr = (addr & CS_MAXADDR) >> 2;
  96     DPRINTF("write reg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->regs[saddr], val);
  97     switch (saddr) {
  98     case 1:
  99         DPRINTF("write dreg[%d]: 0x%2.2x -> 0x%2.2x\n", CS_RAP(s), s->dregs[CS_RAP(s)], val);
 100         switch(CS_RAP(s)) {
 101         case 11:
 102         case 25: // Read only
 103             break;
 104         case 12:
 105             val &= 0x40;
 106             val |= CS_CDC_VER; // Codec version
 107             s->dregs[CS_RAP(s)] = val;
 108             break;
 109         default:
 110             s->dregs[CS_RAP(s)] = val;
 111             break;
 112         }
 113         break;
 114     case 2: // Read only
 115         break;
 116     case 4:
 117         if (val & 1)
 118             cs_reset(s);
 119         val &= 0x7f;
 120         s->regs[saddr] = val;
 121         break;
 122     default:
 123         s->regs[saddr] = val;
 124         break;
 125     }
 126 }
 127
 128 static CPUReadMemoryFunc *cs_mem_read[3] = {
 129     cs_mem_readl,
 130     cs_mem_readl,
 131     cs_mem_readl,
 132 };
 133
 134 static CPUWriteMemoryFunc *cs_mem_write[3] = {
 135     cs_mem_writel,
 136     cs_mem_writel,
 137     cs_mem_writel,
 138 };
 139
 140 static void cs_save(QEMUFile *f, void *opaque)
 141 {
 142     CSState *s = opaque;
 143     unsigned int i;
 144
 145     for (i = 0; i < CS_REGS; i++)
 146         qemu_put_be32s(f, &s->regs[i]);
 147
 148     qemu_put_buffer(f, s->dregs, CS_DREGS);
 149 }
 150
 151 static int cs_load(QEMUFile *f, void *opaque, int version_id)
 152 {
 153     CSState *s = opaque;
 154     unsigned int i;
 155
 156     if (version_id > 1)
 157         return -EINVAL;
 158
 159     for (i = 0; i < CS_REGS; i++)
 160         qemu_get_be32s(f, &s->regs[i]);
 161
 162     qemu_get_buffer(f, s->dregs, CS_DREGS);
 163     return 0;
 164 }
 165
 166 void cs_init(target_phys_addr_t base, int irq, void *intctl)
 167 {
 168     int cs_io_memory;
 169     CSState *s;
 170
 171     s = qemu_mallocz(sizeof(CSState));
 172     if (!s)
 173         return;
 174
 175     cs_io_memory = cpu_register_io_memory(0, cs_mem_read, cs_mem_write, s);
 176     cpu_register_physical_memory(base, CS_MAXADDR, cs_io_memory);
 177     register_savevm("cs4231", base, 1, cs_save, cs_load, s);
 178     qemu_register_reset(cs_reset, s);
 179     cs_reset(s);
 180 }