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Improve ColdFire CPU selection.
[qemu/mini2440.git] / target-sparc / translate.c
blob8dbe3370fe8f589137a3821d3c071f44a4cc8749
1 /*
2 SPARC translation
3
4 Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 Copyright (C) 2003-2005 Fabrice Bellard
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 /*
23 TODO-list:
24
25 Rest of V9 instructions, VIS instructions
26 NPC/PC static optimisations (use JUMP_TB when possible)
27 Optimize synthetic instructions
28 128-bit float
29 */
30
31 #include <stdarg.h>
32 #include <stdlib.h>
33 #include <stdio.h>
34 #include <string.h>
35 #include <inttypes.h>
36
37 #include "cpu.h"
38 #include "exec-all.h"
39 #include "disas.h"
40
41 #define DEBUG_DISAS
42
43 #define DYNAMIC_PC 1 /* dynamic pc value */
44 #define JUMP_PC 2 /* dynamic pc value which takes only two values
45 according to jump_pc[T2] */
46
47 typedef struct DisasContext {
48 target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
49 target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
50 target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
51 int is_br;
52 int mem_idx;
53 int fpu_enabled;
54 struct TranslationBlock *tb;
55 } DisasContext;
56
57 struct sparc_def_t {
58 const unsigned char *name;
59 target_ulong iu_version;
60 uint32_t fpu_version;
61 uint32_t mmu_version;
62 };
63
64 static uint16_t *gen_opc_ptr;
65 static uint32_t *gen_opparam_ptr;
66 extern FILE *logfile;
67 extern int loglevel;
68
69 enum {
70 #define DEF(s,n,copy_size) INDEX_op_ ## s,
71 #include "opc.h"
72 #undef DEF
73 NB_OPS
74 };
75
76 #include "gen-op.h"
77
78 // This function uses non-native bit order
79 #define GET_FIELD(X, FROM, TO) \
80 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
81
82 // This function uses the order in the manuals, i.e. bit 0 is 2^0
83 #define GET_FIELD_SP(X, FROM, TO) \
84 GET_FIELD(X, 31 - (TO), 31 - (FROM))
85
86 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
87 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
88
89 #ifdef TARGET_SPARC64
90 #define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
91 #else
92 #define DFPREG(r) (r & 0x1e)
93 #endif
94
95 #ifdef USE_DIRECT_JUMP
96 #define TBPARAM(x)
97 #else
98 #define TBPARAM(x) (long)(x)
99 #endif
100
101 static int sign_extend(int x, int len)
102 {
103 len = 32 - len;
104 return (x << len) >> len;
105 }
106
107 #define IS_IMM (insn & (1<<13))
108
109 static void disas_sparc_insn(DisasContext * dc);
110
111 static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
112 {
113 gen_op_movl_g0_T0,
114 gen_op_movl_g1_T0,
115 gen_op_movl_g2_T0,
116 gen_op_movl_g3_T0,
117 gen_op_movl_g4_T0,
118 gen_op_movl_g5_T0,
119 gen_op_movl_g6_T0,
120 gen_op_movl_g7_T0,
121 gen_op_movl_o0_T0,
122 gen_op_movl_o1_T0,
123 gen_op_movl_o2_T0,
124 gen_op_movl_o3_T0,
125 gen_op_movl_o4_T0,
126 gen_op_movl_o5_T0,
127 gen_op_movl_o6_T0,
128 gen_op_movl_o7_T0,
129 gen_op_movl_l0_T0,
130 gen_op_movl_l1_T0,
131 gen_op_movl_l2_T0,
132 gen_op_movl_l3_T0,
133 gen_op_movl_l4_T0,
134 gen_op_movl_l5_T0,
135 gen_op_movl_l6_T0,
136 gen_op_movl_l7_T0,
137 gen_op_movl_i0_T0,
138 gen_op_movl_i1_T0,
139 gen_op_movl_i2_T0,
140 gen_op_movl_i3_T0,
141 gen_op_movl_i4_T0,
142 gen_op_movl_i5_T0,
143 gen_op_movl_i6_T0,
144 gen_op_movl_i7_T0,
145 },
146 {
147 gen_op_movl_g0_T1,
148 gen_op_movl_g1_T1,
149 gen_op_movl_g2_T1,
150 gen_op_movl_g3_T1,
151 gen_op_movl_g4_T1,
152 gen_op_movl_g5_T1,
153 gen_op_movl_g6_T1,
154 gen_op_movl_g7_T1,
155 gen_op_movl_o0_T1,
156 gen_op_movl_o1_T1,
157 gen_op_movl_o2_T1,
158 gen_op_movl_o3_T1,
159 gen_op_movl_o4_T1,
160 gen_op_movl_o5_T1,
161 gen_op_movl_o6_T1,
162 gen_op_movl_o7_T1,
163 gen_op_movl_l0_T1,
164 gen_op_movl_l1_T1,
165 gen_op_movl_l2_T1,
166 gen_op_movl_l3_T1,
167 gen_op_movl_l4_T1,
168 gen_op_movl_l5_T1,
169 gen_op_movl_l6_T1,
170 gen_op_movl_l7_T1,
171 gen_op_movl_i0_T1,
172 gen_op_movl_i1_T1,
173 gen_op_movl_i2_T1,
174 gen_op_movl_i3_T1,
175 gen_op_movl_i4_T1,
176 gen_op_movl_i5_T1,
177 gen_op_movl_i6_T1,
178 gen_op_movl_i7_T1,
179 }
180 };
181
182 static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
183 {
184 gen_op_movl_T0_g0,
185 gen_op_movl_T0_g1,
186 gen_op_movl_T0_g2,
187 gen_op_movl_T0_g3,
188 gen_op_movl_T0_g4,
189 gen_op_movl_T0_g5,
190 gen_op_movl_T0_g6,
191 gen_op_movl_T0_g7,
192 gen_op_movl_T0_o0,
193 gen_op_movl_T0_o1,
194 gen_op_movl_T0_o2,
195 gen_op_movl_T0_o3,
196 gen_op_movl_T0_o4,
197 gen_op_movl_T0_o5,
198 gen_op_movl_T0_o6,
199 gen_op_movl_T0_o7,
200 gen_op_movl_T0_l0,
201 gen_op_movl_T0_l1,
202 gen_op_movl_T0_l2,
203 gen_op_movl_T0_l3,
204 gen_op_movl_T0_l4,
205 gen_op_movl_T0_l5,
206 gen_op_movl_T0_l6,
207 gen_op_movl_T0_l7,
208 gen_op_movl_T0_i0,
209 gen_op_movl_T0_i1,
210 gen_op_movl_T0_i2,
211 gen_op_movl_T0_i3,
212 gen_op_movl_T0_i4,
213 gen_op_movl_T0_i5,
214 gen_op_movl_T0_i6,
215 gen_op_movl_T0_i7,
216 },
217 {
218 gen_op_movl_T1_g0,
219 gen_op_movl_T1_g1,
220 gen_op_movl_T1_g2,
221 gen_op_movl_T1_g3,
222 gen_op_movl_T1_g4,
223 gen_op_movl_T1_g5,
224 gen_op_movl_T1_g6,
225 gen_op_movl_T1_g7,
226 gen_op_movl_T1_o0,
227 gen_op_movl_T1_o1,
228 gen_op_movl_T1_o2,
229 gen_op_movl_T1_o3,
230 gen_op_movl_T1_o4,
231 gen_op_movl_T1_o5,
232 gen_op_movl_T1_o6,
233 gen_op_movl_T1_o7,
234 gen_op_movl_T1_l0,
235 gen_op_movl_T1_l1,
236 gen_op_movl_T1_l2,
237 gen_op_movl_T1_l3,
238 gen_op_movl_T1_l4,
239 gen_op_movl_T1_l5,
240 gen_op_movl_T1_l6,
241 gen_op_movl_T1_l7,
242 gen_op_movl_T1_i0,
243 gen_op_movl_T1_i1,
244 gen_op_movl_T1_i2,
245 gen_op_movl_T1_i3,
246 gen_op_movl_T1_i4,
247 gen_op_movl_T1_i5,
248 gen_op_movl_T1_i6,
249 gen_op_movl_T1_i7,
250 },
251 {
252 gen_op_movl_T2_g0,
253 gen_op_movl_T2_g1,
254 gen_op_movl_T2_g2,
255 gen_op_movl_T2_g3,
256 gen_op_movl_T2_g4,
257 gen_op_movl_T2_g5,
258 gen_op_movl_T2_g6,
259 gen_op_movl_T2_g7,
260 gen_op_movl_T2_o0,
261 gen_op_movl_T2_o1,
262 gen_op_movl_T2_o2,
263 gen_op_movl_T2_o3,
264 gen_op_movl_T2_o4,
265 gen_op_movl_T2_o5,
266 gen_op_movl_T2_o6,
267 gen_op_movl_T2_o7,
268 gen_op_movl_T2_l0,
269 gen_op_movl_T2_l1,
270 gen_op_movl_T2_l2,
271 gen_op_movl_T2_l3,
272 gen_op_movl_T2_l4,
273 gen_op_movl_T2_l5,
274 gen_op_movl_T2_l6,
275 gen_op_movl_T2_l7,
276 gen_op_movl_T2_i0,
277 gen_op_movl_T2_i1,
278 gen_op_movl_T2_i2,
279 gen_op_movl_T2_i3,
280 gen_op_movl_T2_i4,
281 gen_op_movl_T2_i5,
282 gen_op_movl_T2_i6,
283 gen_op_movl_T2_i7,
284 }
285 };
286
287 static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
288 gen_op_movl_T0_im,
289 gen_op_movl_T1_im,
290 gen_op_movl_T2_im
291 };
292
293 // Sign extending version
294 static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
295 gen_op_movl_T0_sim,
296 gen_op_movl_T1_sim,
297 gen_op_movl_T2_sim
298 };
299
300 #ifdef TARGET_SPARC64
301 #define GEN32(func, NAME) \
302 static GenOpFunc * const NAME ## _table [64] = { \
303 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
304 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
305 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
306 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
307 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
308 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
309 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
310 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
311 NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
312 NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
313 NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
314 NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
315 }; \
316 static inline void func(int n) \
317 { \
318 NAME ## _table[n](); \
319 }
320 #else
321 #define GEN32(func, NAME) \
322 static GenOpFunc *const NAME ## _table [32] = { \
323 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
324 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
325 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
326 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
327 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
328 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
329 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
330 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
331 }; \
332 static inline void func(int n) \
333 { \
334 NAME ## _table[n](); \
335 }
336 #endif
337
338 /* floating point registers moves */
339 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
340 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
341 GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
342 GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
343
344 GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
345 GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
346 GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
347 GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
348
349 #ifdef TARGET_SPARC64
350 // 'a' versions allowed to user depending on asi
351 #if defined(CONFIG_USER_ONLY)
352 #define supervisor(dc) 0
353 #define hypervisor(dc) 0
354 #define gen_op_ldst(name) gen_op_##name##_raw()
355 #define OP_LD_TABLE(width) \
356 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
357 { \
358 int asi, offset; \
359 \
360 if (IS_IMM) { \
361 offset = GET_FIELD(insn, 25, 31); \
362 if (is_ld) \
363 gen_op_ld_asi_reg(offset, size, sign); \
364 else \
365 gen_op_st_asi_reg(offset, size, sign); \
366 return; \
367 } \
368 asi = GET_FIELD(insn, 19, 26); \
369 switch (asi) { \
370 case 0x80: /* Primary address space */ \
371 gen_op_##width##_raw(); \
372 break; \
373 case 0x82: /* Primary address space, non-faulting load */ \
374 gen_op_##width##_raw(); \
375 break; \
376 default: \
377 break; \
378 } \
379 }
380
381 #else
382 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
383 #define OP_LD_TABLE(width) \
384 static GenOpFunc * const gen_op_##width[] = { \
385 &gen_op_##width##_user, \
386 &gen_op_##width##_kernel, \
387 }; \
388 \
389 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
390 { \
391 int asi, offset; \
392 \
393 if (IS_IMM) { \
394 offset = GET_FIELD(insn, 25, 31); \
395 if (is_ld) \
396 gen_op_ld_asi_reg(offset, size, sign); \
397 else \
398 gen_op_st_asi_reg(offset, size, sign); \
399 return; \
400 } \
401 asi = GET_FIELD(insn, 19, 26); \
402 if (is_ld) \
403 gen_op_ld_asi(asi, size, sign); \
404 else \
405 gen_op_st_asi(asi, size, sign); \
406 }
407
408 #define supervisor(dc) (dc->mem_idx == 1)
409 #define hypervisor(dc) (dc->mem_idx == 2)
410 #endif
411 #else
412 #if defined(CONFIG_USER_ONLY)
413 #define gen_op_ldst(name) gen_op_##name##_raw()
414 #define OP_LD_TABLE(width)
415 #define supervisor(dc) 0
416 #else
417 #define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
418 #define OP_LD_TABLE(width) \
419 static GenOpFunc * const gen_op_##width[] = { \
420 &gen_op_##width##_user, \
421 &gen_op_##width##_kernel, \
422 }; \
423 \
424 static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
425 { \
426 int asi; \
427 \
428 asi = GET_FIELD(insn, 19, 26); \
429 switch (asi) { \
430 case 10: /* User data access */ \
431 gen_op_##width##_user(); \
432 break; \
433 case 11: /* Supervisor data access */ \
434 gen_op_##width##_kernel(); \
435 break; \
436 case 0x20 ... 0x2f: /* MMU passthrough */ \
437 if (is_ld) \
438 gen_op_ld_asi(asi, size, sign); \
439 else \
440 gen_op_st_asi(asi, size, sign); \
441 break; \
442 default: \
443 if (is_ld) \
444 gen_op_ld_asi(asi, size, sign); \
445 else \
446 gen_op_st_asi(asi, size, sign); \
447 break; \
448 } \
449 }
450
451 #define supervisor(dc) (dc->mem_idx == 1)
452 #endif
453 #endif
454
455 OP_LD_TABLE(ld);
456 OP_LD_TABLE(st);
457 OP_LD_TABLE(ldub);
458 OP_LD_TABLE(lduh);
459 OP_LD_TABLE(ldsb);
460 OP_LD_TABLE(ldsh);
461 OP_LD_TABLE(stb);
462 OP_LD_TABLE(sth);
463 OP_LD_TABLE(std);
464 OP_LD_TABLE(ldstub);
465 OP_LD_TABLE(swap);
466 OP_LD_TABLE(ldd);
467 OP_LD_TABLE(stf);
468 OP_LD_TABLE(stdf);
469 OP_LD_TABLE(ldf);
470 OP_LD_TABLE(lddf);
471
472 #ifdef TARGET_SPARC64
473 OP_LD_TABLE(ldsw);
474 OP_LD_TABLE(ldx);
475 OP_LD_TABLE(stx);
476 OP_LD_TABLE(cas);
477 OP_LD_TABLE(casx);
478 #endif
479
480 static inline void gen_movl_imm_TN(int reg, uint32_t imm)
481 {
482 gen_op_movl_TN_im[reg](imm);
483 }
484
485 static inline void gen_movl_imm_T1(uint32_t val)
486 {
487 gen_movl_imm_TN(1, val);
488 }
489
490 static inline void gen_movl_imm_T0(uint32_t val)
491 {
492 gen_movl_imm_TN(0, val);
493 }
494
495 static inline void gen_movl_simm_TN(int reg, int32_t imm)
496 {
497 gen_op_movl_TN_sim[reg](imm);
498 }
499
500 static inline void gen_movl_simm_T1(int32_t val)
501 {
502 gen_movl_simm_TN(1, val);
503 }
504
505 static inline void gen_movl_simm_T0(int32_t val)
506 {
507 gen_movl_simm_TN(0, val);
508 }
509
510 static inline void gen_movl_reg_TN(int reg, int t)
511 {
512 if (reg)
513 gen_op_movl_reg_TN[t][reg] ();
514 else
515 gen_movl_imm_TN(t, 0);
516 }
517
518 static inline void gen_movl_reg_T0(int reg)
519 {
520 gen_movl_reg_TN(reg, 0);
521 }
522
523 static inline void gen_movl_reg_T1(int reg)
524 {
525 gen_movl_reg_TN(reg, 1);
526 }
527
528 static inline void gen_movl_reg_T2(int reg)
529 {
530 gen_movl_reg_TN(reg, 2);
531 }
532
533 static inline void gen_movl_TN_reg(int reg, int t)
534 {
535 if (reg)
536 gen_op_movl_TN_reg[t][reg] ();
537 }
538
539 static inline void gen_movl_T0_reg(int reg)
540 {
541 gen_movl_TN_reg(reg, 0);
542 }
543
544 static inline void gen_movl_T1_reg(int reg)
545 {
546 gen_movl_TN_reg(reg, 1);
547 }
548
549 static inline void gen_jmp_im(target_ulong pc)
550 {
551 #ifdef TARGET_SPARC64
552 if (pc == (uint32_t)pc) {
553 gen_op_jmp_im(pc);
554 } else {
555 gen_op_jmp_im64(pc >> 32, pc);
556 }
557 #else
558 gen_op_jmp_im(pc);
559 #endif
560 }
561
562 static inline void gen_movl_npc_im(target_ulong npc)
563 {
564 #ifdef TARGET_SPARC64
565 if (npc == (uint32_t)npc) {
566 gen_op_movl_npc_im(npc);
567 } else {
568 gen_op_movq_npc_im64(npc >> 32, npc);
569 }
570 #else
571 gen_op_movl_npc_im(npc);
572 #endif
573 }
574
575 static inline void gen_goto_tb(DisasContext *s, int tb_num,
576 target_ulong pc, target_ulong npc)
577 {
578 TranslationBlock *tb;
579
580 tb = s->tb;
581 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
582 (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
583 /* jump to same page: we can use a direct jump */
584 if (tb_num == 0)
585 gen_op_goto_tb0(TBPARAM(tb));
586 else
587 gen_op_goto_tb1(TBPARAM(tb));
588 gen_jmp_im(pc);
589 gen_movl_npc_im(npc);
590 gen_op_movl_T0_im((long)tb + tb_num);
591 gen_op_exit_tb();
592 } else {
593 /* jump to another page: currently not optimized */
594 gen_jmp_im(pc);
595 gen_movl_npc_im(npc);
596 gen_op_movl_T0_0();
597 gen_op_exit_tb();
598 }
599 }
600
601 static inline void gen_branch2(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
602 {
603 int l1;
604
605 l1 = gen_new_label();
606
607 gen_op_jz_T2_label(l1);
608
609 gen_goto_tb(dc, 0, pc1, pc1 + 4);
610
611 gen_set_label(l1);
612 gen_goto_tb(dc, 1, pc2, pc2 + 4);
613 }
614
615 static inline void gen_branch_a(DisasContext *dc, long tb, target_ulong pc1, target_ulong pc2)
616 {
617 int l1;
618
619 l1 = gen_new_label();
620
621 gen_op_jz_T2_label(l1);
622
623 gen_goto_tb(dc, 0, pc2, pc1);
624
625 gen_set_label(l1);
626 gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
627 }
628
629 static inline void gen_branch(DisasContext *dc, long tb, target_ulong pc, target_ulong npc)
630 {
631 gen_goto_tb(dc, 0, pc, npc);
632 }
633
634 static inline void gen_generic_branch(DisasContext *dc, target_ulong npc1, target_ulong npc2)
635 {
636 int l1, l2;
637
638 l1 = gen_new_label();
639 l2 = gen_new_label();
640 gen_op_jz_T2_label(l1);
641
642 gen_movl_npc_im(npc1);
643 gen_op_jmp_label(l2);
644
645 gen_set_label(l1);
646 gen_movl_npc_im(npc2);
647 gen_set_label(l2);
648 }
649
650 /* call this function before using T2 as it may have been set for a jump */
651 static inline void flush_T2(DisasContext * dc)
652 {
653 if (dc->npc == JUMP_PC) {
654 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
655 dc->npc = DYNAMIC_PC;
656 }
657 }
658
659 static inline void save_npc(DisasContext * dc)
660 {
661 if (dc->npc == JUMP_PC) {
662 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
663 dc->npc = DYNAMIC_PC;
664 } else if (dc->npc != DYNAMIC_PC) {
665 gen_movl_npc_im(dc->npc);
666 }
667 }
668
669 static inline void save_state(DisasContext * dc)
670 {
671 gen_jmp_im(dc->pc);
672 save_npc(dc);
673 }
674
675 static inline void gen_mov_pc_npc(DisasContext * dc)
676 {
677 if (dc->npc == JUMP_PC) {
678 gen_generic_branch(dc, dc->jump_pc[0], dc->jump_pc[1]);
679 gen_op_mov_pc_npc();
680 dc->pc = DYNAMIC_PC;
681 } else if (dc->npc == DYNAMIC_PC) {
682 gen_op_mov_pc_npc();
683 dc->pc = DYNAMIC_PC;
684 } else {
685 dc->pc = dc->npc;
686 }
687 }
688
689 static GenOpFunc * const gen_cond[2][16] = {
690 {
691 gen_op_eval_bn,
692 gen_op_eval_be,
693 gen_op_eval_ble,
694 gen_op_eval_bl,
695 gen_op_eval_bleu,
696 gen_op_eval_bcs,
697 gen_op_eval_bneg,
698 gen_op_eval_bvs,
699 gen_op_eval_ba,
700 gen_op_eval_bne,
701 gen_op_eval_bg,
702 gen_op_eval_bge,
703 gen_op_eval_bgu,
704 gen_op_eval_bcc,
705 gen_op_eval_bpos,
706 gen_op_eval_bvc,
707 },
708 {
709 #ifdef TARGET_SPARC64
710 gen_op_eval_bn,
711 gen_op_eval_xbe,
712 gen_op_eval_xble,
713 gen_op_eval_xbl,
714 gen_op_eval_xbleu,
715 gen_op_eval_xbcs,
716 gen_op_eval_xbneg,
717 gen_op_eval_xbvs,
718 gen_op_eval_ba,
719 gen_op_eval_xbne,
720 gen_op_eval_xbg,
721 gen_op_eval_xbge,
722 gen_op_eval_xbgu,
723 gen_op_eval_xbcc,
724 gen_op_eval_xbpos,
725 gen_op_eval_xbvc,
726 #endif
727 },
728 };
729
730 static GenOpFunc * const gen_fcond[4][16] = {
731 {
732 gen_op_eval_bn,
733 gen_op_eval_fbne,
734 gen_op_eval_fblg,
735 gen_op_eval_fbul,
736 gen_op_eval_fbl,
737 gen_op_eval_fbug,
738 gen_op_eval_fbg,
739 gen_op_eval_fbu,
740 gen_op_eval_ba,
741 gen_op_eval_fbe,
742 gen_op_eval_fbue,
743 gen_op_eval_fbge,
744 gen_op_eval_fbuge,
745 gen_op_eval_fble,
746 gen_op_eval_fbule,
747 gen_op_eval_fbo,
748 },
749 #ifdef TARGET_SPARC64
750 {
751 gen_op_eval_bn,
752 gen_op_eval_fbne_fcc1,
753 gen_op_eval_fblg_fcc1,
754 gen_op_eval_fbul_fcc1,
755 gen_op_eval_fbl_fcc1,
756 gen_op_eval_fbug_fcc1,
757 gen_op_eval_fbg_fcc1,
758 gen_op_eval_fbu_fcc1,
759 gen_op_eval_ba,
760 gen_op_eval_fbe_fcc1,
761 gen_op_eval_fbue_fcc1,
762 gen_op_eval_fbge_fcc1,
763 gen_op_eval_fbuge_fcc1,
764 gen_op_eval_fble_fcc1,
765 gen_op_eval_fbule_fcc1,
766 gen_op_eval_fbo_fcc1,
767 },
768 {
769 gen_op_eval_bn,
770 gen_op_eval_fbne_fcc2,
771 gen_op_eval_fblg_fcc2,
772 gen_op_eval_fbul_fcc2,
773 gen_op_eval_fbl_fcc2,
774 gen_op_eval_fbug_fcc2,
775 gen_op_eval_fbg_fcc2,
776 gen_op_eval_fbu_fcc2,
777 gen_op_eval_ba,
778 gen_op_eval_fbe_fcc2,
779 gen_op_eval_fbue_fcc2,
780 gen_op_eval_fbge_fcc2,
781 gen_op_eval_fbuge_fcc2,
782 gen_op_eval_fble_fcc2,
783 gen_op_eval_fbule_fcc2,
784 gen_op_eval_fbo_fcc2,
785 },
786 {
787 gen_op_eval_bn,
788 gen_op_eval_fbne_fcc3,
789 gen_op_eval_fblg_fcc3,
790 gen_op_eval_fbul_fcc3,
791 gen_op_eval_fbl_fcc3,
792 gen_op_eval_fbug_fcc3,
793 gen_op_eval_fbg_fcc3,
794 gen_op_eval_fbu_fcc3,
795 gen_op_eval_ba,
796 gen_op_eval_fbe_fcc3,
797 gen_op_eval_fbue_fcc3,
798 gen_op_eval_fbge_fcc3,
799 gen_op_eval_fbuge_fcc3,
800 gen_op_eval_fble_fcc3,
801 gen_op_eval_fbule_fcc3,
802 gen_op_eval_fbo_fcc3,
803 },
804 #else
805 {}, {}, {},
806 #endif
807 };
808
809 #ifdef TARGET_SPARC64
810 static void gen_cond_reg(int cond)
811 {
812 switch (cond) {
813 case 0x1:
814 gen_op_eval_brz();
815 break;
816 case 0x2:
817 gen_op_eval_brlez();
818 break;
819 case 0x3:
820 gen_op_eval_brlz();
821 break;
822 case 0x5:
823 gen_op_eval_brnz();
824 break;
825 case 0x6:
826 gen_op_eval_brgz();
827 break;
828 default:
829 case 0x7:
830 gen_op_eval_brgez();
831 break;
832 }
833 }
834 #endif
835
836 /* XXX: potentially incorrect if dynamic npc */
837 static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
838 {
839 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
840 target_ulong target = dc->pc + offset;
841
842 if (cond == 0x0) {
843 /* unconditional not taken */
844 if (a) {
845 dc->pc = dc->npc + 4;
846 dc->npc = dc->pc + 4;
847 } else {
848 dc->pc = dc->npc;
849 dc->npc = dc->pc + 4;
850 }
851 } else if (cond == 0x8) {
852 /* unconditional taken */
853 if (a) {
854 dc->pc = target;
855 dc->npc = dc->pc + 4;
856 } else {
857 dc->pc = dc->npc;
858 dc->npc = target;
859 }
860 } else {
861 flush_T2(dc);
862 gen_cond[cc][cond]();
863 if (a) {
864 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
865 dc->is_br = 1;
866 } else {
867 dc->pc = dc->npc;
868 dc->jump_pc[0] = target;
869 dc->jump_pc[1] = dc->npc + 4;
870 dc->npc = JUMP_PC;
871 }
872 }
873 }
874
875 /* XXX: potentially incorrect if dynamic npc */
876 static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
877 {
878 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
879 target_ulong target = dc->pc + offset;
880
881 if (cond == 0x0) {
882 /* unconditional not taken */
883 if (a) {
884 dc->pc = dc->npc + 4;
885 dc->npc = dc->pc + 4;
886 } else {
887 dc->pc = dc->npc;
888 dc->npc = dc->pc + 4;
889 }
890 } else if (cond == 0x8) {
891 /* unconditional taken */
892 if (a) {
893 dc->pc = target;
894 dc->npc = dc->pc + 4;
895 } else {
896 dc->pc = dc->npc;
897 dc->npc = target;
898 }
899 } else {
900 flush_T2(dc);
901 gen_fcond[cc][cond]();
902 if (a) {
903 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
904 dc->is_br = 1;
905 } else {
906 dc->pc = dc->npc;
907 dc->jump_pc[0] = target;
908 dc->jump_pc[1] = dc->npc + 4;
909 dc->npc = JUMP_PC;
910 }
911 }
912 }
913
914 #ifdef TARGET_SPARC64
915 /* XXX: potentially incorrect if dynamic npc */
916 static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
917 {
918 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
919 target_ulong target = dc->pc + offset;
920
921 flush_T2(dc);
922 gen_cond_reg(cond);
923 if (a) {
924 gen_branch_a(dc, (long)dc->tb, target, dc->npc);
925 dc->is_br = 1;
926 } else {
927 dc->pc = dc->npc;
928 dc->jump_pc[0] = target;
929 dc->jump_pc[1] = dc->npc + 4;
930 dc->npc = JUMP_PC;
931 }
932 }
933
934 static GenOpFunc * const gen_fcmps[4] = {
935 gen_op_fcmps,
936 gen_op_fcmps_fcc1,
937 gen_op_fcmps_fcc2,
938 gen_op_fcmps_fcc3,
939 };
940
941 static GenOpFunc * const gen_fcmpd[4] = {
942 gen_op_fcmpd,
943 gen_op_fcmpd_fcc1,
944 gen_op_fcmpd_fcc2,
945 gen_op_fcmpd_fcc3,
946 };
947
948 static GenOpFunc * const gen_fcmpes[4] = {
949 gen_op_fcmpes,
950 gen_op_fcmpes_fcc1,
951 gen_op_fcmpes_fcc2,
952 gen_op_fcmpes_fcc3,
953 };
954
955 static GenOpFunc * const gen_fcmped[4] = {
956 gen_op_fcmped,
957 gen_op_fcmped_fcc1,
958 gen_op_fcmped_fcc2,
959 gen_op_fcmped_fcc3,
960 };
961
962 #endif
963
964 static int gen_trap_ifnofpu(DisasContext * dc)
965 {
966 #if !defined(CONFIG_USER_ONLY)
967 if (!dc->fpu_enabled) {
968 save_state(dc);
969 gen_op_exception(TT_NFPU_INSN);
970 dc->is_br = 1;
971 return 1;
972 }
973 #endif
974 return 0;
975 }
976
977 /* before an instruction, dc->pc must be static */
978 static void disas_sparc_insn(DisasContext * dc)
979 {
980 unsigned int insn, opc, rs1, rs2, rd;
981
982 insn = ldl_code(dc->pc);
983 opc = GET_FIELD(insn, 0, 1);
984
985 rd = GET_FIELD(insn, 2, 6);
986 switch (opc) {
987 case 0: /* branches/sethi */
988 {
989 unsigned int xop = GET_FIELD(insn, 7, 9);
990 int32_t target;
991 switch (xop) {
992 #ifdef TARGET_SPARC64
993 case 0x1: /* V9 BPcc */
994 {
995 int cc;
996
997 target = GET_FIELD_SP(insn, 0, 18);
998 target = sign_extend(target, 18);
999 target <<= 2;
1000 cc = GET_FIELD_SP(insn, 20, 21);
1001 if (cc == 0)
1002 do_branch(dc, target, insn, 0);
1003 else if (cc == 2)
1004 do_branch(dc, target, insn, 1);
1005 else
1006 goto illegal_insn;
1007 goto jmp_insn;
1008 }
1009 case 0x3: /* V9 BPr */
1010 {
1011 target = GET_FIELD_SP(insn, 0, 13) |
1012 (GET_FIELD_SP(insn, 20, 21) << 14);
1013 target = sign_extend(target, 16);
1014 target <<= 2;
1015 rs1 = GET_FIELD(insn, 13, 17);
1016 gen_movl_reg_T0(rs1);
1017 do_branch_reg(dc, target, insn);
1018 goto jmp_insn;
1019 }
1020 case 0x5: /* V9 FBPcc */
1021 {
1022 int cc = GET_FIELD_SP(insn, 20, 21);
1023 if (gen_trap_ifnofpu(dc))
1024 goto jmp_insn;
1025 target = GET_FIELD_SP(insn, 0, 18);
1026 target = sign_extend(target, 19);
1027 target <<= 2;
1028 do_fbranch(dc, target, insn, cc);
1029 goto jmp_insn;
1030 }
1031 #else
1032 case 0x7: /* CBN+x */
1033 {
1034 goto ncp_insn;
1035 }
1036 #endif
1037 case 0x2: /* BN+x */
1038 {
1039 target = GET_FIELD(insn, 10, 31);
1040 target = sign_extend(target, 22);
1041 target <<= 2;
1042 do_branch(dc, target, insn, 0);
1043 goto jmp_insn;
1044 }
1045 case 0x6: /* FBN+x */
1046 {
1047 if (gen_trap_ifnofpu(dc))
1048 goto jmp_insn;
1049 target = GET_FIELD(insn, 10, 31);
1050 target = sign_extend(target, 22);
1051 target <<= 2;
1052 do_fbranch(dc, target, insn, 0);
1053 goto jmp_insn;
1054 }
1055 case 0x4: /* SETHI */
1056 #define OPTIM
1057 #if defined(OPTIM)
1058 if (rd) { // nop
1059 #endif
1060 uint32_t value = GET_FIELD(insn, 10, 31);
1061 gen_movl_imm_T0(value << 10);
1062 gen_movl_T0_reg(rd);
1063 #if defined(OPTIM)
1064 }
1065 #endif
1066 break;
1067 case 0x0: /* UNIMPL */
1068 default:
1069 goto illegal_insn;
1070 }
1071 break;
1072 }
1073 break;
1074 case 1:
1075 /*CALL*/ {
1076 target_long target = GET_FIELDs(insn, 2, 31) << 2;
1077
1078 #ifdef TARGET_SPARC64
1079 if (dc->pc == (uint32_t)dc->pc) {
1080 gen_op_movl_T0_im(dc->pc);
1081 } else {
1082 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1083 }
1084 #else
1085 gen_op_movl_T0_im(dc->pc);
1086 #endif
1087 gen_movl_T0_reg(15);
1088 target += dc->pc;
1089 gen_mov_pc_npc(dc);
1090 dc->npc = target;
1091 }
1092 goto jmp_insn;
1093 case 2: /* FPU & Logical Operations */
1094 {
1095 unsigned int xop = GET_FIELD(insn, 7, 12);
1096 if (xop == 0x3a) { /* generate trap */
1097 int cond;
1098
1099 rs1 = GET_FIELD(insn, 13, 17);
1100 gen_movl_reg_T0(rs1);
1101 if (IS_IMM) {
1102 rs2 = GET_FIELD(insn, 25, 31);
1103 #if defined(OPTIM)
1104 if (rs2 != 0) {
1105 #endif
1106 gen_movl_simm_T1(rs2);
1107 gen_op_add_T1_T0();
1108 #if defined(OPTIM)
1109 }
1110 #endif
1111 } else {
1112 rs2 = GET_FIELD(insn, 27, 31);
1113 #if defined(OPTIM)
1114 if (rs2 != 0) {
1115 #endif
1116 gen_movl_reg_T1(rs2);
1117 gen_op_add_T1_T0();
1118 #if defined(OPTIM)
1119 }
1120 #endif
1121 }
1122 cond = GET_FIELD(insn, 3, 6);
1123 if (cond == 0x8) {
1124 save_state(dc);
1125 gen_op_trap_T0();
1126 } else if (cond != 0) {
1127 #ifdef TARGET_SPARC64
1128 /* V9 icc/xcc */
1129 int cc = GET_FIELD_SP(insn, 11, 12);
1130 flush_T2(dc);
1131 save_state(dc);
1132 if (cc == 0)
1133 gen_cond[0][cond]();
1134 else if (cc == 2)
1135 gen_cond[1][cond]();
1136 else
1137 goto illegal_insn;
1138 #else
1139 flush_T2(dc);
1140 save_state(dc);
1141 gen_cond[0][cond]();
1142 #endif
1143 gen_op_trapcc_T0();
1144 }
1145 gen_op_next_insn();
1146 gen_op_movl_T0_0();
1147 gen_op_exit_tb();
1148 dc->is_br = 1;
1149 goto jmp_insn;
1150 } else if (xop == 0x28) {
1151 rs1 = GET_FIELD(insn, 13, 17);
1152 switch(rs1) {
1153 case 0: /* rdy */
1154 #ifndef TARGET_SPARC64
1155 case 0x01 ... 0x0e: /* undefined in the SPARCv8
1156 manual, rdy on the microSPARC
1157 II */
1158 case 0x0f: /* stbar in the SPARCv8 manual,
1159 rdy on the microSPARC II */
1160 case 0x10 ... 0x1f: /* implementation-dependent in the
1161 SPARCv8 manual, rdy on the
1162 microSPARC II */
1163 #endif
1164 gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1165 gen_movl_T0_reg(rd);
1166 break;
1167 #ifdef TARGET_SPARC64
1168 case 0x2: /* V9 rdccr */
1169 gen_op_rdccr();
1170 gen_movl_T0_reg(rd);
1171 break;
1172 case 0x3: /* V9 rdasi */
1173 gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1174 gen_movl_T0_reg(rd);
1175 break;
1176 case 0x4: /* V9 rdtick */
1177 gen_op_rdtick();
1178 gen_movl_T0_reg(rd);
1179 break;
1180 case 0x5: /* V9 rdpc */
1181 if (dc->pc == (uint32_t)dc->pc) {
1182 gen_op_movl_T0_im(dc->pc);
1183 } else {
1184 gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1185 }
1186 gen_movl_T0_reg(rd);
1187 break;
1188 case 0x6: /* V9 rdfprs */
1189 gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1190 gen_movl_T0_reg(rd);
1191 break;
1192 case 0xf: /* V9 membar */
1193 break; /* no effect */
1194 case 0x13: /* Graphics Status */
1195 if (gen_trap_ifnofpu(dc))
1196 goto jmp_insn;
1197 gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1198 gen_movl_T0_reg(rd);
1199 break;
1200 case 0x17: /* Tick compare */
1201 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1202 gen_movl_T0_reg(rd);
1203 break;
1204 case 0x18: /* System tick */
1205 gen_op_rdstick();
1206 gen_movl_T0_reg(rd);
1207 break;
1208 case 0x19: /* System tick compare */
1209 gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1210 gen_movl_T0_reg(rd);
1211 break;
1212 case 0x10: /* Performance Control */
1213 case 0x11: /* Performance Instrumentation Counter */
1214 case 0x12: /* Dispatch Control */
1215 case 0x14: /* Softint set, WO */
1216 case 0x15: /* Softint clear, WO */
1217 case 0x16: /* Softint write */
1218 #endif
1219 default:
1220 goto illegal_insn;
1221 }
1222 #if !defined(CONFIG_USER_ONLY)
1223 } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
1224 #ifndef TARGET_SPARC64
1225 if (!supervisor(dc))
1226 goto priv_insn;
1227 gen_op_rdpsr();
1228 #else
1229 if (!hypervisor(dc))
1230 goto priv_insn;
1231 rs1 = GET_FIELD(insn, 13, 17);
1232 switch (rs1) {
1233 case 0: // hpstate
1234 // gen_op_rdhpstate();
1235 break;
1236 case 1: // htstate
1237 // gen_op_rdhtstate();
1238 break;
1239 case 3: // hintp
1240 gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1241 break;
1242 case 5: // htba
1243 gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1244 break;
1245 case 6: // hver
1246 gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1247 break;
1248 case 31: // hstick_cmpr
1249 gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1250 break;
1251 default:
1252 goto illegal_insn;
1253 }
1254 #endif
1255 gen_movl_T0_reg(rd);
1256 break;
1257 } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1258 if (!supervisor(dc))
1259 goto priv_insn;
1260 #ifdef TARGET_SPARC64
1261 rs1 = GET_FIELD(insn, 13, 17);
1262 switch (rs1) {
1263 case 0: // tpc
1264 gen_op_rdtpc();
1265 break;
1266 case 1: // tnpc
1267 gen_op_rdtnpc();
1268 break;
1269 case 2: // tstate
1270 gen_op_rdtstate();
1271 break;
1272 case 3: // tt
1273 gen_op_rdtt();
1274 break;
1275 case 4: // tick
1276 gen_op_rdtick();
1277 break;
1278 case 5: // tba
1279 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1280 break;
1281 case 6: // pstate
1282 gen_op_rdpstate();
1283 break;
1284 case 7: // tl
1285 gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1286 break;
1287 case 8: // pil
1288 gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1289 break;
1290 case 9: // cwp
1291 gen_op_rdcwp();
1292 break;
1293 case 10: // cansave
1294 gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1295 break;
1296 case 11: // canrestore
1297 gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1298 break;
1299 case 12: // cleanwin
1300 gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1301 break;
1302 case 13: // otherwin
1303 gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1304 break;
1305 case 14: // wstate
1306 gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1307 break;
1308 case 16: // UA2005 gl
1309 gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1310 break;
1311 case 26: // UA2005 strand status
1312 if (!hypervisor(dc))
1313 goto priv_insn;
1314 gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1315 break;
1316 case 31: // ver
1317 gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1318 break;
1319 case 15: // fq
1320 default:
1321 goto illegal_insn;
1322 }
1323 #else
1324 gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1325 #endif
1326 gen_movl_T0_reg(rd);
1327 break;
1328 } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1329 #ifdef TARGET_SPARC64
1330 gen_op_flushw();
1331 #else
1332 if (!supervisor(dc))
1333 goto priv_insn;
1334 gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1335 gen_movl_T0_reg(rd);
1336 #endif
1337 break;
1338 #endif
1339 } else if (xop == 0x34) { /* FPU Operations */
1340 if (gen_trap_ifnofpu(dc))
1341 goto jmp_insn;
1342 gen_op_clear_ieee_excp_and_FTT();
1343 rs1 = GET_FIELD(insn, 13, 17);
1344 rs2 = GET_FIELD(insn, 27, 31);
1345 xop = GET_FIELD(insn, 18, 26);
1346 switch (xop) {
1347 case 0x1: /* fmovs */
1348 gen_op_load_fpr_FT0(rs2);
1349 gen_op_store_FT0_fpr(rd);
1350 break;
1351 case 0x5: /* fnegs */
1352 gen_op_load_fpr_FT1(rs2);
1353 gen_op_fnegs();
1354 gen_op_store_FT0_fpr(rd);
1355 break;
1356 case 0x9: /* fabss */
1357 gen_op_load_fpr_FT1(rs2);
1358 gen_op_fabss();
1359 gen_op_store_FT0_fpr(rd);
1360 break;
1361 case 0x29: /* fsqrts */
1362 gen_op_load_fpr_FT1(rs2);
1363 gen_op_fsqrts();
1364 gen_op_store_FT0_fpr(rd);
1365 break;
1366 case 0x2a: /* fsqrtd */
1367 gen_op_load_fpr_DT1(DFPREG(rs2));
1368 gen_op_fsqrtd();
1369 gen_op_store_DT0_fpr(DFPREG(rd));
1370 break;
1371 case 0x2b: /* fsqrtq */
1372 goto nfpu_insn;
1373 case 0x41:
1374 gen_op_load_fpr_FT0(rs1);
1375 gen_op_load_fpr_FT1(rs2);
1376 gen_op_fadds();
1377 gen_op_store_FT0_fpr(rd);
1378 break;
1379 case 0x42:
1380 gen_op_load_fpr_DT0(DFPREG(rs1));
1381 gen_op_load_fpr_DT1(DFPREG(rs2));
1382 gen_op_faddd();
1383 gen_op_store_DT0_fpr(DFPREG(rd));
1384 break;
1385 case 0x43: /* faddq */
1386 goto nfpu_insn;
1387 case 0x45:
1388 gen_op_load_fpr_FT0(rs1);
1389 gen_op_load_fpr_FT1(rs2);
1390 gen_op_fsubs();
1391 gen_op_store_FT0_fpr(rd);
1392 break;
1393 case 0x46:
1394 gen_op_load_fpr_DT0(DFPREG(rs1));
1395 gen_op_load_fpr_DT1(DFPREG(rs2));
1396 gen_op_fsubd();
1397 gen_op_store_DT0_fpr(DFPREG(rd));
1398 break;
1399 case 0x47: /* fsubq */
1400 goto nfpu_insn;
1401 case 0x49:
1402 gen_op_load_fpr_FT0(rs1);
1403 gen_op_load_fpr_FT1(rs2);
1404 gen_op_fmuls();
1405 gen_op_store_FT0_fpr(rd);
1406 break;
1407 case 0x4a:
1408 gen_op_load_fpr_DT0(DFPREG(rs1));
1409 gen_op_load_fpr_DT1(DFPREG(rs2));
1410 gen_op_fmuld();
1411 gen_op_store_DT0_fpr(rd);
1412 break;
1413 case 0x4b: /* fmulq */
1414 goto nfpu_insn;
1415 case 0x4d:
1416 gen_op_load_fpr_FT0(rs1);
1417 gen_op_load_fpr_FT1(rs2);
1418 gen_op_fdivs();
1419 gen_op_store_FT0_fpr(rd);
1420 break;
1421 case 0x4e:
1422 gen_op_load_fpr_DT0(DFPREG(rs1));
1423 gen_op_load_fpr_DT1(DFPREG(rs2));
1424 gen_op_fdivd();
1425 gen_op_store_DT0_fpr(DFPREG(rd));
1426 break;
1427 case 0x4f: /* fdivq */
1428 goto nfpu_insn;
1429 case 0x69:
1430 gen_op_load_fpr_FT0(rs1);
1431 gen_op_load_fpr_FT1(rs2);
1432 gen_op_fsmuld();
1433 gen_op_store_DT0_fpr(DFPREG(rd));
1434 break;
1435 case 0x6e: /* fdmulq */
1436 goto nfpu_insn;
1437 case 0xc4:
1438 gen_op_load_fpr_FT1(rs2);
1439 gen_op_fitos();
1440 gen_op_store_FT0_fpr(rd);
1441 break;
1442 case 0xc6:
1443 gen_op_load_fpr_DT1(DFPREG(rs2));
1444 gen_op_fdtos();
1445 gen_op_store_FT0_fpr(rd);
1446 break;
1447 case 0xc7: /* fqtos */
1448 goto nfpu_insn;
1449 case 0xc8:
1450 gen_op_load_fpr_FT1(rs2);
1451 gen_op_fitod();
1452 gen_op_store_DT0_fpr(DFPREG(rd));
1453 break;
1454 case 0xc9:
1455 gen_op_load_fpr_FT1(rs2);
1456 gen_op_fstod();
1457 gen_op_store_DT0_fpr(DFPREG(rd));
1458 break;
1459 case 0xcb: /* fqtod */
1460 goto nfpu_insn;
1461 case 0xcc: /* fitoq */
1462 goto nfpu_insn;
1463 case 0xcd: /* fstoq */
1464 goto nfpu_insn;
1465 case 0xce: /* fdtoq */
1466 goto nfpu_insn;
1467 case 0xd1:
1468 gen_op_load_fpr_FT1(rs2);
1469 gen_op_fstoi();
1470 gen_op_store_FT0_fpr(rd);
1471 break;
1472 case 0xd2:
1473 gen_op_load_fpr_DT1(rs2);
1474 gen_op_fdtoi();
1475 gen_op_store_FT0_fpr(rd);
1476 break;
1477 case 0xd3: /* fqtoi */
1478 goto nfpu_insn;
1479 #ifdef TARGET_SPARC64
1480 case 0x2: /* V9 fmovd */
1481 gen_op_load_fpr_DT0(DFPREG(rs2));
1482 gen_op_store_DT0_fpr(DFPREG(rd));
1483 break;
1484 case 0x6: /* V9 fnegd */
1485 gen_op_load_fpr_DT1(DFPREG(rs2));
1486 gen_op_fnegd();
1487 gen_op_store_DT0_fpr(DFPREG(rd));
1488 break;
1489 case 0xa: /* V9 fabsd */
1490 gen_op_load_fpr_DT1(DFPREG(rs2));
1491 gen_op_fabsd();
1492 gen_op_store_DT0_fpr(DFPREG(rd));
1493 break;
1494 case 0x81: /* V9 fstox */
1495 gen_op_load_fpr_FT1(rs2);
1496 gen_op_fstox();
1497 gen_op_store_DT0_fpr(DFPREG(rd));
1498 break;
1499 case 0x82: /* V9 fdtox */
1500 gen_op_load_fpr_DT1(DFPREG(rs2));
1501 gen_op_fdtox();
1502 gen_op_store_DT0_fpr(DFPREG(rd));
1503 break;
1504 case 0x84: /* V9 fxtos */
1505 gen_op_load_fpr_DT1(DFPREG(rs2));
1506 gen_op_fxtos();
1507 gen_op_store_FT0_fpr(rd);
1508 break;
1509 case 0x88: /* V9 fxtod */
1510 gen_op_load_fpr_DT1(DFPREG(rs2));
1511 gen_op_fxtod();
1512 gen_op_store_DT0_fpr(DFPREG(rd));
1513 break;
1514 case 0x3: /* V9 fmovq */
1515 case 0x7: /* V9 fnegq */
1516 case 0xb: /* V9 fabsq */
1517 case 0x83: /* V9 fqtox */
1518 case 0x8c: /* V9 fxtoq */
1519 goto nfpu_insn;
1520 #endif
1521 default:
1522 goto illegal_insn;
1523 }
1524 } else if (xop == 0x35) { /* FPU Operations */
1525 #ifdef TARGET_SPARC64
1526 int cond;
1527 #endif
1528 if (gen_trap_ifnofpu(dc))
1529 goto jmp_insn;
1530 gen_op_clear_ieee_excp_and_FTT();
1531 rs1 = GET_FIELD(insn, 13, 17);
1532 rs2 = GET_FIELD(insn, 27, 31);
1533 xop = GET_FIELD(insn, 18, 26);
1534 #ifdef TARGET_SPARC64
1535 if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1536 cond = GET_FIELD_SP(insn, 14, 17);
1537 gen_op_load_fpr_FT0(rd);
1538 gen_op_load_fpr_FT1(rs2);
1539 rs1 = GET_FIELD(insn, 13, 17);
1540 gen_movl_reg_T0(rs1);
1541 flush_T2(dc);
1542 gen_cond_reg(cond);
1543 gen_op_fmovs_cc();
1544 gen_op_store_FT0_fpr(rd);
1545 break;
1546 } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1547 cond = GET_FIELD_SP(insn, 14, 17);
1548 gen_op_load_fpr_DT0(rd);
1549 gen_op_load_fpr_DT1(rs2);
1550 flush_T2(dc);
1551 rs1 = GET_FIELD(insn, 13, 17);
1552 gen_movl_reg_T0(rs1);
1553 gen_cond_reg(cond);
1554 gen_op_fmovs_cc();
1555 gen_op_store_DT0_fpr(rd);
1556 break;
1557 } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1558 goto nfpu_insn;
1559 }
1560 #endif
1561 switch (xop) {
1562 #ifdef TARGET_SPARC64
1563 case 0x001: /* V9 fmovscc %fcc0 */
1564 cond = GET_FIELD_SP(insn, 14, 17);
1565 gen_op_load_fpr_FT0(rd);
1566 gen_op_load_fpr_FT1(rs2);
1567 flush_T2(dc);
1568 gen_fcond[0][cond]();
1569 gen_op_fmovs_cc();
1570 gen_op_store_FT0_fpr(rd);
1571 break;
1572 case 0x002: /* V9 fmovdcc %fcc0 */
1573 cond = GET_FIELD_SP(insn, 14, 17);
1574 gen_op_load_fpr_DT0(rd);
1575 gen_op_load_fpr_DT1(rs2);
1576 flush_T2(dc);
1577 gen_fcond[0][cond]();
1578 gen_op_fmovd_cc();
1579 gen_op_store_DT0_fpr(rd);
1580 break;
1581 case 0x003: /* V9 fmovqcc %fcc0 */
1582 goto nfpu_insn;
1583 case 0x041: /* V9 fmovscc %fcc1 */
1584 cond = GET_FIELD_SP(insn, 14, 17);
1585 gen_op_load_fpr_FT0(rd);
1586 gen_op_load_fpr_FT1(rs2);
1587 flush_T2(dc);
1588 gen_fcond[1][cond]();
1589 gen_op_fmovs_cc();
1590 gen_op_store_FT0_fpr(rd);
1591 break;
1592 case 0x042: /* V9 fmovdcc %fcc1 */
1593 cond = GET_FIELD_SP(insn, 14, 17);
1594 gen_op_load_fpr_DT0(rd);
1595 gen_op_load_fpr_DT1(rs2);
1596 flush_T2(dc);
1597 gen_fcond[1][cond]();
1598 gen_op_fmovd_cc();
1599 gen_op_store_DT0_fpr(rd);
1600 break;
1601 case 0x043: /* V9 fmovqcc %fcc1 */
1602 goto nfpu_insn;
1603 case 0x081: /* V9 fmovscc %fcc2 */
1604 cond = GET_FIELD_SP(insn, 14, 17);
1605 gen_op_load_fpr_FT0(rd);
1606 gen_op_load_fpr_FT1(rs2);
1607 flush_T2(dc);
1608 gen_fcond[2][cond]();
1609 gen_op_fmovs_cc();
1610 gen_op_store_FT0_fpr(rd);
1611 break;
1612 case 0x082: /* V9 fmovdcc %fcc2 */
1613 cond = GET_FIELD_SP(insn, 14, 17);
1614 gen_op_load_fpr_DT0(rd);
1615 gen_op_load_fpr_DT1(rs2);
1616 flush_T2(dc);
1617 gen_fcond[2][cond]();
1618 gen_op_fmovd_cc();
1619 gen_op_store_DT0_fpr(rd);
1620 break;
1621 case 0x083: /* V9 fmovqcc %fcc2 */
1622 goto nfpu_insn;
1623 case 0x0c1: /* V9 fmovscc %fcc3 */
1624 cond = GET_FIELD_SP(insn, 14, 17);
1625 gen_op_load_fpr_FT0(rd);
1626 gen_op_load_fpr_FT1(rs2);
1627 flush_T2(dc);
1628 gen_fcond[3][cond]();
1629 gen_op_fmovs_cc();
1630 gen_op_store_FT0_fpr(rd);
1631 break;
1632 case 0x0c2: /* V9 fmovdcc %fcc3 */
1633 cond = GET_FIELD_SP(insn, 14, 17);
1634 gen_op_load_fpr_DT0(rd);
1635 gen_op_load_fpr_DT1(rs2);
1636 flush_T2(dc);
1637 gen_fcond[3][cond]();
1638 gen_op_fmovd_cc();
1639 gen_op_store_DT0_fpr(rd);
1640 break;
1641 case 0x0c3: /* V9 fmovqcc %fcc3 */
1642 goto nfpu_insn;
1643 case 0x101: /* V9 fmovscc %icc */
1644 cond = GET_FIELD_SP(insn, 14, 17);
1645 gen_op_load_fpr_FT0(rd);
1646 gen_op_load_fpr_FT1(rs2);
1647 flush_T2(dc);
1648 gen_cond[0][cond]();
1649 gen_op_fmovs_cc();
1650 gen_op_store_FT0_fpr(rd);
1651 break;
1652 case 0x102: /* V9 fmovdcc %icc */
1653 cond = GET_FIELD_SP(insn, 14, 17);
1654 gen_op_load_fpr_DT0(rd);
1655 gen_op_load_fpr_DT1(rs2);
1656 flush_T2(dc);
1657 gen_cond[0][cond]();
1658 gen_op_fmovd_cc();
1659 gen_op_store_DT0_fpr(rd);
1660 break;
1661 case 0x103: /* V9 fmovqcc %icc */
1662 goto nfpu_insn;
1663 case 0x181: /* V9 fmovscc %xcc */
1664 cond = GET_FIELD_SP(insn, 14, 17);
1665 gen_op_load_fpr_FT0(rd);
1666 gen_op_load_fpr_FT1(rs2);
1667 flush_T2(dc);
1668 gen_cond[1][cond]();
1669 gen_op_fmovs_cc();
1670 gen_op_store_FT0_fpr(rd);
1671 break;
1672 case 0x182: /* V9 fmovdcc %xcc */
1673 cond = GET_FIELD_SP(insn, 14, 17);
1674 gen_op_load_fpr_DT0(rd);
1675 gen_op_load_fpr_DT1(rs2);
1676 flush_T2(dc);
1677 gen_cond[1][cond]();
1678 gen_op_fmovd_cc();
1679 gen_op_store_DT0_fpr(rd);
1680 break;
1681 case 0x183: /* V9 fmovqcc %xcc */
1682 goto nfpu_insn;
1683 #endif
1684 case 0x51: /* V9 %fcc */
1685 gen_op_load_fpr_FT0(rs1);
1686 gen_op_load_fpr_FT1(rs2);
1687 #ifdef TARGET_SPARC64
1688 gen_fcmps[rd & 3]();
1689 #else
1690 gen_op_fcmps();
1691 #endif
1692 break;
1693 case 0x52: /* V9 %fcc */
1694 gen_op_load_fpr_DT0(DFPREG(rs1));
1695 gen_op_load_fpr_DT1(DFPREG(rs2));
1696 #ifdef TARGET_SPARC64
1697 gen_fcmpd[rd & 3]();
1698 #else
1699 gen_op_fcmpd();
1700 #endif
1701 break;
1702 case 0x53: /* fcmpq */
1703 goto nfpu_insn;
1704 case 0x55: /* fcmpes, V9 %fcc */
1705 gen_op_load_fpr_FT0(rs1);
1706 gen_op_load_fpr_FT1(rs2);
1707 #ifdef TARGET_SPARC64
1708 gen_fcmpes[rd & 3]();
1709 #else
1710 gen_op_fcmpes();
1711 #endif
1712 break;
1713 case 0x56: /* fcmped, V9 %fcc */
1714 gen_op_load_fpr_DT0(DFPREG(rs1));
1715 gen_op_load_fpr_DT1(DFPREG(rs2));
1716 #ifdef TARGET_SPARC64
1717 gen_fcmped[rd & 3]();
1718 #else
1719 gen_op_fcmped();
1720 #endif
1721 break;
1722 case 0x57: /* fcmpeq */
1723 goto nfpu_insn;
1724 default:
1725 goto illegal_insn;
1726 }
1727 #if defined(OPTIM)
1728 } else if (xop == 0x2) {
1729 // clr/mov shortcut
1730
1731 rs1 = GET_FIELD(insn, 13, 17);
1732 if (rs1 == 0) {
1733 // or %g0, x, y -> mov T1, x; mov y, T1
1734 if (IS_IMM) { /* immediate */
1735 rs2 = GET_FIELDs(insn, 19, 31);
1736 gen_movl_simm_T1(rs2);
1737 } else { /* register */
1738 rs2 = GET_FIELD(insn, 27, 31);
1739 gen_movl_reg_T1(rs2);
1740 }
1741 gen_movl_T1_reg(rd);
1742 } else {
1743 gen_movl_reg_T0(rs1);
1744 if (IS_IMM) { /* immediate */
1745 // or x, #0, y -> mov T1, x; mov y, T1
1746 rs2 = GET_FIELDs(insn, 19, 31);
1747 if (rs2 != 0) {
1748 gen_movl_simm_T1(rs2);
1749 gen_op_or_T1_T0();
1750 }
1751 } else { /* register */
1752 // or x, %g0, y -> mov T1, x; mov y, T1
1753 rs2 = GET_FIELD(insn, 27, 31);
1754 if (rs2 != 0) {
1755 gen_movl_reg_T1(rs2);
1756 gen_op_or_T1_T0();
1757 }
1758 }
1759 gen_movl_T0_reg(rd);
1760 }
1761 #endif
1762 #ifdef TARGET_SPARC64
1763 } else if (xop == 0x25) { /* sll, V9 sllx */
1764 rs1 = GET_FIELD(insn, 13, 17);
1765 gen_movl_reg_T0(rs1);
1766 if (IS_IMM) { /* immediate */
1767 rs2 = GET_FIELDs(insn, 20, 31);
1768 gen_movl_simm_T1(rs2);
1769 } else { /* register */
1770 rs2 = GET_FIELD(insn, 27, 31);
1771 gen_movl_reg_T1(rs2);
1772 }
1773 if (insn & (1 << 12))
1774 gen_op_sllx();
1775 else
1776 gen_op_sll();
1777 gen_movl_T0_reg(rd);
1778 } else if (xop == 0x26) { /* srl, V9 srlx */
1779 rs1 = GET_FIELD(insn, 13, 17);
1780 gen_movl_reg_T0(rs1);
1781 if (IS_IMM) { /* immediate */
1782 rs2 = GET_FIELDs(insn, 20, 31);
1783 gen_movl_simm_T1(rs2);
1784 } else { /* register */
1785 rs2 = GET_FIELD(insn, 27, 31);
1786 gen_movl_reg_T1(rs2);
1787 }
1788 if (insn & (1 << 12))
1789 gen_op_srlx();
1790 else
1791 gen_op_srl();
1792 gen_movl_T0_reg(rd);
1793 } else if (xop == 0x27) { /* sra, V9 srax */
1794 rs1 = GET_FIELD(insn, 13, 17);
1795 gen_movl_reg_T0(rs1);
1796 if (IS_IMM) { /* immediate */
1797 rs2 = GET_FIELDs(insn, 20, 31);
1798 gen_movl_simm_T1(rs2);
1799 } else { /* register */
1800 rs2 = GET_FIELD(insn, 27, 31);
1801 gen_movl_reg_T1(rs2);
1802 }
1803 if (insn & (1 << 12))
1804 gen_op_srax();
1805 else
1806 gen_op_sra();
1807 gen_movl_T0_reg(rd);
1808 #endif
1809 } else if (xop < 0x36) {
1810 rs1 = GET_FIELD(insn, 13, 17);
1811 gen_movl_reg_T0(rs1);
1812 if (IS_IMM) { /* immediate */
1813 rs2 = GET_FIELDs(insn, 19, 31);
1814 gen_movl_simm_T1(rs2);
1815 } else { /* register */
1816 rs2 = GET_FIELD(insn, 27, 31);
1817 gen_movl_reg_T1(rs2);
1818 }
1819 if (xop < 0x20) {
1820 switch (xop & ~0x10) {
1821 case 0x0:
1822 if (xop & 0x10)
1823 gen_op_add_T1_T0_cc();
1824 else
1825 gen_op_add_T1_T0();
1826 break;
1827 case 0x1:
1828 gen_op_and_T1_T0();
1829 if (xop & 0x10)
1830 gen_op_logic_T0_cc();
1831 break;
1832 case 0x2:
1833 gen_op_or_T1_T0();
1834 if (xop & 0x10)
1835 gen_op_logic_T0_cc();
1836 break;
1837 case 0x3:
1838 gen_op_xor_T1_T0();
1839 if (xop & 0x10)
1840 gen_op_logic_T0_cc();
1841 break;
1842 case 0x4:
1843 if (xop & 0x10)
1844 gen_op_sub_T1_T0_cc();
1845 else
1846 gen_op_sub_T1_T0();
1847 break;
1848 case 0x5:
1849 gen_op_andn_T1_T0();
1850 if (xop & 0x10)
1851 gen_op_logic_T0_cc();
1852 break;
1853 case 0x6:
1854 gen_op_orn_T1_T0();
1855 if (xop & 0x10)
1856 gen_op_logic_T0_cc();
1857 break;
1858 case 0x7:
1859 gen_op_xnor_T1_T0();
1860 if (xop & 0x10)
1861 gen_op_logic_T0_cc();
1862 break;
1863 case 0x8:
1864 if (xop & 0x10)
1865 gen_op_addx_T1_T0_cc();
1866 else
1867 gen_op_addx_T1_T0();
1868 break;
1869 #ifdef TARGET_SPARC64
1870 case 0x9: /* V9 mulx */
1871 gen_op_mulx_T1_T0();
1872 break;
1873 #endif
1874 case 0xa:
1875 gen_op_umul_T1_T0();
1876 if (xop & 0x10)
1877 gen_op_logic_T0_cc();
1878 break;
1879 case 0xb:
1880 gen_op_smul_T1_T0();
1881 if (xop & 0x10)
1882 gen_op_logic_T0_cc();
1883 break;
1884 case 0xc:
1885 if (xop & 0x10)
1886 gen_op_subx_T1_T0_cc();
1887 else
1888 gen_op_subx_T1_T0();
1889 break;
1890 #ifdef TARGET_SPARC64
1891 case 0xd: /* V9 udivx */
1892 gen_op_udivx_T1_T0();
1893 break;
1894 #endif
1895 case 0xe:
1896 gen_op_udiv_T1_T0();
1897 if (xop & 0x10)
1898 gen_op_div_cc();
1899 break;
1900 case 0xf:
1901 gen_op_sdiv_T1_T0();
1902 if (xop & 0x10)
1903 gen_op_div_cc();
1904 break;
1905 default:
1906 goto illegal_insn;
1907 }
1908 gen_movl_T0_reg(rd);
1909 } else {
1910 switch (xop) {
1911 case 0x20: /* taddcc */
1912 gen_op_tadd_T1_T0_cc();
1913 gen_movl_T0_reg(rd);
1914 break;
1915 case 0x21: /* tsubcc */
1916 gen_op_tsub_T1_T0_cc();
1917 gen_movl_T0_reg(rd);
1918 break;
1919 case 0x22: /* taddcctv */
1920 gen_op_tadd_T1_T0_ccTV();
1921 gen_movl_T0_reg(rd);
1922 break;
1923 case 0x23: /* tsubcctv */
1924 gen_op_tsub_T1_T0_ccTV();
1925 gen_movl_T0_reg(rd);
1926 break;
1927 case 0x24: /* mulscc */
1928 gen_op_mulscc_T1_T0();
1929 gen_movl_T0_reg(rd);
1930 break;
1931 #ifndef TARGET_SPARC64
1932 case 0x25: /* sll */
1933 gen_op_sll();
1934 gen_movl_T0_reg(rd);
1935 break;
1936 case 0x26: /* srl */
1937 gen_op_srl();
1938 gen_movl_T0_reg(rd);
1939 break;
1940 case 0x27: /* sra */
1941 gen_op_sra();
1942 gen_movl_T0_reg(rd);
1943 break;
1944 #endif
1945 case 0x30:
1946 {
1947 switch(rd) {
1948 case 0: /* wry */
1949 gen_op_xor_T1_T0();
1950 gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
1951 break;
1952 #ifndef TARGET_SPARC64
1953 case 0x01 ... 0x0f: /* undefined in the
1954 SPARCv8 manual, nop
1955 on the microSPARC
1956 II */
1957 case 0x10 ... 0x1f: /* implementation-dependent
1958 in the SPARCv8
1959 manual, nop on the
1960 microSPARC II */
1961 break;
1962 #else
1963 case 0x2: /* V9 wrccr */
1964 gen_op_wrccr();
1965 break;
1966 case 0x3: /* V9 wrasi */
1967 gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1968 break;
1969 case 0x6: /* V9 wrfprs */
1970 gen_op_xor_T1_T0();
1971 gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1972 save_state(dc);
1973 gen_op_next_insn();
1974 gen_op_movl_T0_0();
1975 gen_op_exit_tb();
1976 dc->is_br = 1;
1977 break;
1978 case 0xf: /* V9 sir, nop if user */
1979 #if !defined(CONFIG_USER_ONLY)
1980 if (supervisor(dc))
1981 gen_op_sir();
1982 #endif
1983 break;
1984 case 0x13: /* Graphics Status */
1985 if (gen_trap_ifnofpu(dc))
1986 goto jmp_insn;
1987 gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
1988 break;
1989 case 0x17: /* Tick compare */
1990 #if !defined(CONFIG_USER_ONLY)
1991 if (!supervisor(dc))
1992 goto illegal_insn;
1993 #endif
1994 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
1995 gen_op_wrtick_cmpr();
1996 break;
1997 case 0x18: /* System tick */
1998 #if !defined(CONFIG_USER_ONLY)
1999 if (!supervisor(dc))
2000 goto illegal_insn;
2001 #endif
2002 gen_op_wrstick();
2003 break;
2004 case 0x19: /* System tick compare */
2005 #if !defined(CONFIG_USER_ONLY)
2006 if (!supervisor(dc))
2007 goto illegal_insn;
2008 #endif
2009 gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2010 gen_op_wrstick_cmpr();
2011 break;
2012
2013 case 0x10: /* Performance Control */
2014 case 0x11: /* Performance Instrumentation Counter */
2015 case 0x12: /* Dispatch Control */
2016 case 0x14: /* Softint set */
2017 case 0x15: /* Softint clear */
2018 case 0x16: /* Softint write */
2019 #endif
2020 default:
2021 goto illegal_insn;
2022 }
2023 }
2024 break;
2025 #if !defined(CONFIG_USER_ONLY)
2026 case 0x31: /* wrpsr, V9 saved, restored */
2027 {
2028 if (!supervisor(dc))
2029 goto priv_insn;
2030 #ifdef TARGET_SPARC64
2031 switch (rd) {
2032 case 0:
2033 gen_op_saved();
2034 break;
2035 case 1:
2036 gen_op_restored();
2037 break;
2038 case 2: /* UA2005 allclean */
2039 case 3: /* UA2005 otherw */
2040 case 4: /* UA2005 normalw */
2041 case 5: /* UA2005 invalw */
2042 // XXX
2043 default:
2044 goto illegal_insn;
2045 }
2046 #else
2047 gen_op_xor_T1_T0();
2048 gen_op_wrpsr();
2049 save_state(dc);
2050 gen_op_next_insn();
2051 gen_op_movl_T0_0();
2052 gen_op_exit_tb();
2053 dc->is_br = 1;
2054 #endif
2055 }
2056 break;
2057 case 0x32: /* wrwim, V9 wrpr */
2058 {
2059 if (!supervisor(dc))
2060 goto priv_insn;
2061 gen_op_xor_T1_T0();
2062 #ifdef TARGET_SPARC64
2063 switch (rd) {
2064 case 0: // tpc
2065 gen_op_wrtpc();
2066 break;
2067 case 1: // tnpc
2068 gen_op_wrtnpc();
2069 break;
2070 case 2: // tstate
2071 gen_op_wrtstate();
2072 break;
2073 case 3: // tt
2074 gen_op_wrtt();
2075 break;
2076 case 4: // tick
2077 gen_op_wrtick();
2078 break;
2079 case 5: // tba
2080 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2081 break;
2082 case 6: // pstate
2083 gen_op_wrpstate();
2084 save_state(dc);
2085 gen_op_next_insn();
2086 gen_op_movl_T0_0();
2087 gen_op_exit_tb();
2088 dc->is_br = 1;
2089 break;
2090 case 7: // tl
2091 gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2092 break;
2093 case 8: // pil
2094 gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2095 break;
2096 case 9: // cwp
2097 gen_op_wrcwp();
2098 break;
2099 case 10: // cansave
2100 gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2101 break;
2102 case 11: // canrestore
2103 gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2104 break;
2105 case 12: // cleanwin
2106 gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2107 break;
2108 case 13: // otherwin
2109 gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2110 break;
2111 case 14: // wstate
2112 gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2113 break;
2114 case 16: // UA2005 gl
2115 gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2116 break;
2117 case 26: // UA2005 strand status
2118 if (!hypervisor(dc))
2119 goto priv_insn;
2120 gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2121 break;
2122 default:
2123 goto illegal_insn;
2124 }
2125 #else
2126 gen_op_wrwim();
2127 #endif
2128 }
2129 break;
2130 case 0x33: /* wrtbr, UA2005 wrhpr */
2131 {
2132 #ifndef TARGET_SPARC64
2133 if (!supervisor(dc))
2134 goto priv_insn;
2135 gen_op_xor_T1_T0();
2136 gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2137 #else
2138 if (!hypervisor(dc))
2139 goto priv_insn;
2140 gen_op_xor_T1_T0();
2141 switch (rd) {
2142 case 0: // hpstate
2143 // XXX gen_op_wrhpstate();
2144 save_state(dc);
2145 gen_op_next_insn();
2146 gen_op_movl_T0_0();
2147 gen_op_exit_tb();
2148 dc->is_br = 1;
2149 break;
2150 case 1: // htstate
2151 // XXX gen_op_wrhtstate();
2152 break;
2153 case 3: // hintp
2154 gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2155 break;
2156 case 5: // htba
2157 gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2158 break;
2159 case 31: // hstick_cmpr
2160 gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2161 gen_op_wrhstick_cmpr();
2162 break;
2163 case 6: // hver readonly
2164 default:
2165 goto illegal_insn;
2166 }
2167 #endif
2168 }
2169 break;
2170 #endif
2171 #ifdef TARGET_SPARC64
2172 case 0x2c: /* V9 movcc */
2173 {
2174 int cc = GET_FIELD_SP(insn, 11, 12);
2175 int cond = GET_FIELD_SP(insn, 14, 17);
2176 if (IS_IMM) { /* immediate */
2177 rs2 = GET_FIELD_SPs(insn, 0, 10);
2178 gen_movl_simm_T1(rs2);
2179 }
2180 else {
2181 rs2 = GET_FIELD_SP(insn, 0, 4);
2182 gen_movl_reg_T1(rs2);
2183 }
2184 gen_movl_reg_T0(rd);
2185 flush_T2(dc);
2186 if (insn & (1 << 18)) {
2187 if (cc == 0)
2188 gen_cond[0][cond]();
2189 else if (cc == 2)
2190 gen_cond[1][cond]();
2191 else
2192 goto illegal_insn;
2193 } else {
2194 gen_fcond[cc][cond]();
2195 }
2196 gen_op_mov_cc();
2197 gen_movl_T0_reg(rd);
2198 break;
2199 }
2200 case 0x2d: /* V9 sdivx */
2201 gen_op_sdivx_T1_T0();
2202 gen_movl_T0_reg(rd);
2203 break;
2204 case 0x2e: /* V9 popc */
2205 {
2206 if (IS_IMM) { /* immediate */
2207 rs2 = GET_FIELD_SPs(insn, 0, 12);
2208 gen_movl_simm_T1(rs2);
2209 // XXX optimize: popc(constant)
2210 }
2211 else {
2212 rs2 = GET_FIELD_SP(insn, 0, 4);
2213 gen_movl_reg_T1(rs2);
2214 }
2215 gen_op_popc();
2216 gen_movl_T0_reg(rd);
2217 }
2218 case 0x2f: /* V9 movr */
2219 {
2220 int cond = GET_FIELD_SP(insn, 10, 12);
2221 rs1 = GET_FIELD(insn, 13, 17);
2222 flush_T2(dc);
2223 gen_movl_reg_T0(rs1);
2224 gen_cond_reg(cond);
2225 if (IS_IMM) { /* immediate */
2226 rs2 = GET_FIELD_SPs(insn, 0, 10);
2227 gen_movl_simm_T1(rs2);
2228 }
2229 else {
2230 rs2 = GET_FIELD_SP(insn, 0, 4);
2231 gen_movl_reg_T1(rs2);
2232 }
2233 gen_movl_reg_T0(rd);
2234 gen_op_mov_cc();
2235 gen_movl_T0_reg(rd);
2236 break;
2237 }
2238 #endif
2239 default:
2240 goto illegal_insn;
2241 }
2242 }
2243 } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2244 #ifdef TARGET_SPARC64
2245 int opf = GET_FIELD_SP(insn, 5, 13);
2246 rs1 = GET_FIELD(insn, 13, 17);
2247 rs2 = GET_FIELD(insn, 27, 31);
2248 if (gen_trap_ifnofpu(dc))
2249 goto jmp_insn;
2250
2251 switch (opf) {
2252 case 0x000: /* VIS I edge8cc */
2253 case 0x001: /* VIS II edge8n */
2254 case 0x002: /* VIS I edge8lcc */
2255 case 0x003: /* VIS II edge8ln */
2256 case 0x004: /* VIS I edge16cc */
2257 case 0x005: /* VIS II edge16n */
2258 case 0x006: /* VIS I edge16lcc */
2259 case 0x007: /* VIS II edge16ln */
2260 case 0x008: /* VIS I edge32cc */
2261 case 0x009: /* VIS II edge32n */
2262 case 0x00a: /* VIS I edge32lcc */
2263 case 0x00b: /* VIS II edge32ln */
2264 // XXX
2265 goto illegal_insn;
2266 case 0x010: /* VIS I array8 */
2267 gen_movl_reg_T0(rs1);
2268 gen_movl_reg_T1(rs2);
2269 gen_op_array8();
2270 gen_movl_T0_reg(rd);
2271 break;
2272 case 0x012: /* VIS I array16 */
2273 gen_movl_reg_T0(rs1);
2274 gen_movl_reg_T1(rs2);
2275 gen_op_array16();
2276 gen_movl_T0_reg(rd);
2277 break;
2278 case 0x014: /* VIS I array32 */
2279 gen_movl_reg_T0(rs1);
2280 gen_movl_reg_T1(rs2);
2281 gen_op_array32();
2282 gen_movl_T0_reg(rd);
2283 break;
2284 case 0x018: /* VIS I alignaddr */
2285 gen_movl_reg_T0(rs1);
2286 gen_movl_reg_T1(rs2);
2287 gen_op_alignaddr();
2288 gen_movl_T0_reg(rd);
2289 break;
2290 case 0x019: /* VIS II bmask */
2291 case 0x01a: /* VIS I alignaddrl */
2292 // XXX
2293 goto illegal_insn;
2294 case 0x020: /* VIS I fcmple16 */
2295 gen_op_load_fpr_DT0(rs1);
2296 gen_op_load_fpr_DT1(rs2);
2297 gen_op_fcmple16();
2298 gen_op_store_DT0_fpr(rd);
2299 break;
2300 case 0x022: /* VIS I fcmpne16 */
2301 gen_op_load_fpr_DT0(rs1);
2302 gen_op_load_fpr_DT1(rs2);
2303 gen_op_fcmpne16();
2304 gen_op_store_DT0_fpr(rd);
2305 break;
2306 case 0x024: /* VIS I fcmple32 */
2307 gen_op_load_fpr_DT0(rs1);
2308 gen_op_load_fpr_DT1(rs2);
2309 gen_op_fcmple32();
2310 gen_op_store_DT0_fpr(rd);
2311 break;
2312 case 0x026: /* VIS I fcmpne32 */
2313 gen_op_load_fpr_DT0(rs1);
2314 gen_op_load_fpr_DT1(rs2);
2315 gen_op_fcmpne32();
2316 gen_op_store_DT0_fpr(rd);
2317 break;
2318 case 0x028: /* VIS I fcmpgt16 */
2319 gen_op_load_fpr_DT0(rs1);
2320 gen_op_load_fpr_DT1(rs2);
2321 gen_op_fcmpgt16();
2322 gen_op_store_DT0_fpr(rd);
2323 break;
2324 case 0x02a: /* VIS I fcmpeq16 */
2325 gen_op_load_fpr_DT0(rs1);
2326 gen_op_load_fpr_DT1(rs2);
2327 gen_op_fcmpeq16();
2328 gen_op_store_DT0_fpr(rd);
2329 break;
2330 case 0x02c: /* VIS I fcmpgt32 */
2331 gen_op_load_fpr_DT0(rs1);
2332 gen_op_load_fpr_DT1(rs2);
2333 gen_op_fcmpgt32();
2334 gen_op_store_DT0_fpr(rd);
2335 break;
2336 case 0x02e: /* VIS I fcmpeq32 */
2337 gen_op_load_fpr_DT0(rs1);
2338 gen_op_load_fpr_DT1(rs2);
2339 gen_op_fcmpeq32();
2340 gen_op_store_DT0_fpr(rd);
2341 break;
2342 case 0x031: /* VIS I fmul8x16 */
2343 gen_op_load_fpr_DT0(rs1);
2344 gen_op_load_fpr_DT1(rs2);
2345 gen_op_fmul8x16();
2346 gen_op_store_DT0_fpr(rd);
2347 break;
2348 case 0x033: /* VIS I fmul8x16au */
2349 gen_op_load_fpr_DT0(rs1);
2350 gen_op_load_fpr_DT1(rs2);
2351 gen_op_fmul8x16au();
2352 gen_op_store_DT0_fpr(rd);
2353 break;
2354 case 0x035: /* VIS I fmul8x16al */
2355 gen_op_load_fpr_DT0(rs1);
2356 gen_op_load_fpr_DT1(rs2);
2357 gen_op_fmul8x16al();
2358 gen_op_store_DT0_fpr(rd);
2359 break;
2360 case 0x036: /* VIS I fmul8sux16 */
2361 gen_op_load_fpr_DT0(rs1);
2362 gen_op_load_fpr_DT1(rs2);
2363 gen_op_fmul8sux16();
2364 gen_op_store_DT0_fpr(rd);
2365 break;
2366 case 0x037: /* VIS I fmul8ulx16 */
2367 gen_op_load_fpr_DT0(rs1);
2368 gen_op_load_fpr_DT1(rs2);
2369 gen_op_fmul8ulx16();
2370 gen_op_store_DT0_fpr(rd);
2371 break;
2372 case 0x038: /* VIS I fmuld8sux16 */
2373 gen_op_load_fpr_DT0(rs1);
2374 gen_op_load_fpr_DT1(rs2);
2375 gen_op_fmuld8sux16();
2376 gen_op_store_DT0_fpr(rd);
2377 break;
2378 case 0x039: /* VIS I fmuld8ulx16 */
2379 gen_op_load_fpr_DT0(rs1);
2380 gen_op_load_fpr_DT1(rs2);
2381 gen_op_fmuld8ulx16();
2382 gen_op_store_DT0_fpr(rd);
2383 break;
2384 case 0x03a: /* VIS I fpack32 */
2385 case 0x03b: /* VIS I fpack16 */
2386 case 0x03d: /* VIS I fpackfix */
2387 case 0x03e: /* VIS I pdist */
2388 // XXX
2389 goto illegal_insn;
2390 case 0x048: /* VIS I faligndata */
2391 gen_op_load_fpr_DT0(rs1);
2392 gen_op_load_fpr_DT1(rs2);
2393 gen_op_faligndata();
2394 gen_op_store_DT0_fpr(rd);
2395 break;
2396 case 0x04b: /* VIS I fpmerge */
2397 gen_op_load_fpr_DT0(rs1);
2398 gen_op_load_fpr_DT1(rs2);
2399 gen_op_fpmerge();
2400 gen_op_store_DT0_fpr(rd);
2401 break;
2402 case 0x04c: /* VIS II bshuffle */
2403 // XXX
2404 goto illegal_insn;
2405 case 0x04d: /* VIS I fexpand */
2406 gen_op_load_fpr_DT0(rs1);
2407 gen_op_load_fpr_DT1(rs2);
2408 gen_op_fexpand();
2409 gen_op_store_DT0_fpr(rd);
2410 break;
2411 case 0x050: /* VIS I fpadd16 */
2412 gen_op_load_fpr_DT0(rs1);
2413 gen_op_load_fpr_DT1(rs2);
2414 gen_op_fpadd16();
2415 gen_op_store_DT0_fpr(rd);
2416 break;
2417 case 0x051: /* VIS I fpadd16s */
2418 gen_op_load_fpr_FT0(rs1);
2419 gen_op_load_fpr_FT1(rs2);
2420 gen_op_fpadd16s();
2421 gen_op_store_FT0_fpr(rd);
2422 break;
2423 case 0x052: /* VIS I fpadd32 */
2424 gen_op_load_fpr_DT0(rs1);
2425 gen_op_load_fpr_DT1(rs2);
2426 gen_op_fpadd32();
2427 gen_op_store_DT0_fpr(rd);
2428 break;
2429 case 0x053: /* VIS I fpadd32s */
2430 gen_op_load_fpr_FT0(rs1);
2431 gen_op_load_fpr_FT1(rs2);
2432 gen_op_fpadd32s();
2433 gen_op_store_FT0_fpr(rd);
2434 break;
2435 case 0x054: /* VIS I fpsub16 */
2436 gen_op_load_fpr_DT0(rs1);
2437 gen_op_load_fpr_DT1(rs2);
2438 gen_op_fpsub16();
2439 gen_op_store_DT0_fpr(rd);
2440 break;
2441 case 0x055: /* VIS I fpsub16s */
2442 gen_op_load_fpr_FT0(rs1);
2443 gen_op_load_fpr_FT1(rs2);
2444 gen_op_fpsub16s();
2445 gen_op_store_FT0_fpr(rd);
2446 break;
2447 case 0x056: /* VIS I fpsub32 */
2448 gen_op_load_fpr_DT0(rs1);
2449 gen_op_load_fpr_DT1(rs2);
2450 gen_op_fpadd32();
2451 gen_op_store_DT0_fpr(rd);
2452 break;
2453 case 0x057: /* VIS I fpsub32s */
2454 gen_op_load_fpr_FT0(rs1);
2455 gen_op_load_fpr_FT1(rs2);
2456 gen_op_fpsub32s();
2457 gen_op_store_FT0_fpr(rd);
2458 break;
2459 case 0x060: /* VIS I fzero */
2460 gen_op_movl_DT0_0();
2461 gen_op_store_DT0_fpr(rd);
2462 break;
2463 case 0x061: /* VIS I fzeros */
2464 gen_op_movl_FT0_0();
2465 gen_op_store_FT0_fpr(rd);
2466 break;
2467 case 0x062: /* VIS I fnor */
2468 gen_op_load_fpr_DT0(rs1);
2469 gen_op_load_fpr_DT1(rs2);
2470 gen_op_fnor();
2471 gen_op_store_DT0_fpr(rd);
2472 break;
2473 case 0x063: /* VIS I fnors */
2474 gen_op_load_fpr_FT0(rs1);
2475 gen_op_load_fpr_FT1(rs2);
2476 gen_op_fnors();
2477 gen_op_store_FT0_fpr(rd);
2478 break;
2479 case 0x064: /* VIS I fandnot2 */
2480 gen_op_load_fpr_DT1(rs1);
2481 gen_op_load_fpr_DT0(rs2);
2482 gen_op_fandnot();
2483 gen_op_store_DT0_fpr(rd);
2484 break;
2485 case 0x065: /* VIS I fandnot2s */
2486 gen_op_load_fpr_FT1(rs1);
2487 gen_op_load_fpr_FT0(rs2);
2488 gen_op_fandnots();
2489 gen_op_store_FT0_fpr(rd);
2490 break;
2491 case 0x066: /* VIS I fnot2 */
2492 gen_op_load_fpr_DT1(rs2);
2493 gen_op_fnot();
2494 gen_op_store_DT0_fpr(rd);
2495 break;
2496 case 0x067: /* VIS I fnot2s */
2497 gen_op_load_fpr_FT1(rs2);
2498 gen_op_fnot();
2499 gen_op_store_FT0_fpr(rd);
2500 break;
2501 case 0x068: /* VIS I fandnot1 */
2502 gen_op_load_fpr_DT0(rs1);
2503 gen_op_load_fpr_DT1(rs2);
2504 gen_op_fandnot();
2505 gen_op_store_DT0_fpr(rd);
2506 break;
2507 case 0x069: /* VIS I fandnot1s */
2508 gen_op_load_fpr_FT0(rs1);
2509 gen_op_load_fpr_FT1(rs2);
2510 gen_op_fandnots();
2511 gen_op_store_FT0_fpr(rd);
2512 break;
2513 case 0x06a: /* VIS I fnot1 */
2514 gen_op_load_fpr_DT1(rs1);
2515 gen_op_fnot();
2516 gen_op_store_DT0_fpr(rd);
2517 break;
2518 case 0x06b: /* VIS I fnot1s */
2519 gen_op_load_fpr_FT1(rs1);
2520 gen_op_fnot();
2521 gen_op_store_FT0_fpr(rd);
2522 break;
2523 case 0x06c: /* VIS I fxor */
2524 gen_op_load_fpr_DT0(rs1);
2525 gen_op_load_fpr_DT1(rs2);
2526 gen_op_fxor();
2527 gen_op_store_DT0_fpr(rd);
2528 break;
2529 case 0x06d: /* VIS I fxors */
2530 gen_op_load_fpr_FT0(rs1);
2531 gen_op_load_fpr_FT1(rs2);
2532 gen_op_fxors();
2533 gen_op_store_FT0_fpr(rd);
2534 break;
2535 case 0x06e: /* VIS I fnand */
2536 gen_op_load_fpr_DT0(rs1);
2537 gen_op_load_fpr_DT1(rs2);
2538 gen_op_fnand();
2539 gen_op_store_DT0_fpr(rd);
2540 break;
2541 case 0x06f: /* VIS I fnands */
2542 gen_op_load_fpr_FT0(rs1);
2543 gen_op_load_fpr_FT1(rs2);
2544 gen_op_fnands();
2545 gen_op_store_FT0_fpr(rd);
2546 break;
2547 case 0x070: /* VIS I fand */
2548 gen_op_load_fpr_DT0(rs1);
2549 gen_op_load_fpr_DT1(rs2);
2550 gen_op_fand();
2551 gen_op_store_DT0_fpr(rd);
2552 break;
2553 case 0x071: /* VIS I fands */
2554 gen_op_load_fpr_FT0(rs1);
2555 gen_op_load_fpr_FT1(rs2);
2556 gen_op_fands();
2557 gen_op_store_FT0_fpr(rd);
2558 break;
2559 case 0x072: /* VIS I fxnor */
2560 gen_op_load_fpr_DT0(rs1);
2561 gen_op_load_fpr_DT1(rs2);
2562 gen_op_fxnor();
2563 gen_op_store_DT0_fpr(rd);
2564 break;
2565 case 0x073: /* VIS I fxnors */
2566 gen_op_load_fpr_FT0(rs1);
2567 gen_op_load_fpr_FT1(rs2);
2568 gen_op_fxnors();
2569 gen_op_store_FT0_fpr(rd);
2570 break;
2571 case 0x074: /* VIS I fsrc1 */
2572 gen_op_load_fpr_DT0(rs1);
2573 gen_op_store_DT0_fpr(rd);
2574 break;
2575 case 0x075: /* VIS I fsrc1s */
2576 gen_op_load_fpr_FT0(rs1);
2577 gen_op_store_FT0_fpr(rd);
2578 break;
2579 case 0x076: /* VIS I fornot2 */
2580 gen_op_load_fpr_DT1(rs1);
2581 gen_op_load_fpr_DT0(rs2);
2582 gen_op_fornot();
2583 gen_op_store_DT0_fpr(rd);
2584 break;
2585 case 0x077: /* VIS I fornot2s */
2586 gen_op_load_fpr_FT1(rs1);
2587 gen_op_load_fpr_FT0(rs2);
2588 gen_op_fornots();
2589 gen_op_store_FT0_fpr(rd);
2590 break;
2591 case 0x078: /* VIS I fsrc2 */
2592 gen_op_load_fpr_DT0(rs2);
2593 gen_op_store_DT0_fpr(rd);
2594 break;
2595 case 0x079: /* VIS I fsrc2s */
2596 gen_op_load_fpr_FT0(rs2);
2597 gen_op_store_FT0_fpr(rd);
2598 break;
2599 case 0x07a: /* VIS I fornot1 */
2600 gen_op_load_fpr_DT0(rs1);
2601 gen_op_load_fpr_DT1(rs2);
2602 gen_op_fornot();
2603 gen_op_store_DT0_fpr(rd);
2604 break;
2605 case 0x07b: /* VIS I fornot1s */
2606 gen_op_load_fpr_FT0(rs1);
2607 gen_op_load_fpr_FT1(rs2);
2608 gen_op_fornots();
2609 gen_op_store_FT0_fpr(rd);
2610 break;
2611 case 0x07c: /* VIS I for */
2612 gen_op_load_fpr_DT0(rs1);
2613 gen_op_load_fpr_DT1(rs2);
2614 gen_op_for();
2615 gen_op_store_DT0_fpr(rd);
2616 break;
2617 case 0x07d: /* VIS I fors */
2618 gen_op_load_fpr_FT0(rs1);
2619 gen_op_load_fpr_FT1(rs2);
2620 gen_op_fors();
2621 gen_op_store_FT0_fpr(rd);
2622 break;
2623 case 0x07e: /* VIS I fone */
2624 gen_op_movl_DT0_1();
2625 gen_op_store_DT0_fpr(rd);
2626 break;
2627 case 0x07f: /* VIS I fones */
2628 gen_op_movl_FT0_1();
2629 gen_op_store_FT0_fpr(rd);
2630 break;
2631 case 0x080: /* VIS I shutdown */
2632 case 0x081: /* VIS II siam */
2633 // XXX
2634 goto illegal_insn;
2635 default:
2636 goto illegal_insn;
2637 }
2638 #else
2639 goto ncp_insn;
2640 #endif
2641 } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
2642 #ifdef TARGET_SPARC64
2643 goto illegal_insn;
2644 #else
2645 goto ncp_insn;
2646 #endif
2647 #ifdef TARGET_SPARC64
2648 } else if (xop == 0x39) { /* V9 return */
2649 rs1 = GET_FIELD(insn, 13, 17);
2650 gen_movl_reg_T0(rs1);
2651 if (IS_IMM) { /* immediate */
2652 rs2 = GET_FIELDs(insn, 19, 31);
2653 #if defined(OPTIM)
2654 if (rs2) {
2655 #endif
2656 gen_movl_simm_T1(rs2);
2657 gen_op_add_T1_T0();
2658 #if defined(OPTIM)
2659 }
2660 #endif
2661 } else { /* register */
2662 rs2 = GET_FIELD(insn, 27, 31);
2663 #if defined(OPTIM)
2664 if (rs2) {
2665 #endif
2666 gen_movl_reg_T1(rs2);
2667 gen_op_add_T1_T0();
2668 #if defined(OPTIM)
2669 }
2670 #endif
2671 }
2672 gen_op_restore();
2673 gen_mov_pc_npc(dc);
2674 gen_op_movl_npc_T0();
2675 dc->npc = DYNAMIC_PC;
2676 goto jmp_insn;
2677 #endif
2678 } else {
2679 rs1 = GET_FIELD(insn, 13, 17);
2680 gen_movl_reg_T0(rs1);
2681 if (IS_IMM) { /* immediate */
2682 rs2 = GET_FIELDs(insn, 19, 31);
2683 #if defined(OPTIM)
2684 if (rs2) {
2685 #endif
2686 gen_movl_simm_T1(rs2);
2687 gen_op_add_T1_T0();
2688 #if defined(OPTIM)
2689 }
2690 #endif
2691 } else { /* register */
2692 rs2 = GET_FIELD(insn, 27, 31);
2693 #if defined(OPTIM)
2694 if (rs2) {
2695 #endif
2696 gen_movl_reg_T1(rs2);
2697 gen_op_add_T1_T0();
2698 #if defined(OPTIM)
2699 }
2700 #endif
2701 }
2702 switch (xop) {
2703 case 0x38: /* jmpl */
2704 {
2705 if (rd != 0) {
2706 #ifdef TARGET_SPARC64
2707 if (dc->pc == (uint32_t)dc->pc) {
2708 gen_op_movl_T1_im(dc->pc);
2709 } else {
2710 gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2711 }
2712 #else
2713 gen_op_movl_T1_im(dc->pc);
2714 #endif
2715 gen_movl_T1_reg(rd);
2716 }
2717 gen_mov_pc_npc(dc);
2718 gen_op_movl_npc_T0();
2719 dc->npc = DYNAMIC_PC;
2720 }
2721 goto jmp_insn;
2722 #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2723 case 0x39: /* rett, V9 return */
2724 {
2725 if (!supervisor(dc))
2726 goto priv_insn;
2727 gen_mov_pc_npc(dc);
2728 gen_op_movl_npc_T0();
2729 dc->npc = DYNAMIC_PC;
2730 gen_op_rett();
2731 }
2732 goto jmp_insn;
2733 #endif
2734 case 0x3b: /* flush */
2735 gen_op_flush_T0();
2736 break;
2737 case 0x3c: /* save */
2738 save_state(dc);
2739 gen_op_save();
2740 gen_movl_T0_reg(rd);
2741 break;
2742 case 0x3d: /* restore */
2743 save_state(dc);
2744 gen_op_restore();
2745 gen_movl_T0_reg(rd);
2746 break;
2747 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
2748 case 0x3e: /* V9 done/retry */
2749 {
2750 switch (rd) {
2751 case 0:
2752 if (!supervisor(dc))
2753 goto priv_insn;
2754 dc->npc = DYNAMIC_PC;
2755 dc->pc = DYNAMIC_PC;
2756 gen_op_done();
2757 goto jmp_insn;
2758 case 1:
2759 if (!supervisor(dc))
2760 goto priv_insn;
2761 dc->npc = DYNAMIC_PC;
2762 dc->pc = DYNAMIC_PC;
2763 gen_op_retry();
2764 goto jmp_insn;
2765 default:
2766 goto illegal_insn;
2767 }
2768 }
2769 break;
2770 #endif
2771 default:
2772 goto illegal_insn;
2773 }
2774 }
2775 break;
2776 }
2777 break;
2778 case 3: /* load/store instructions */
2779 {
2780 unsigned int xop = GET_FIELD(insn, 7, 12);
2781 rs1 = GET_FIELD(insn, 13, 17);
2782 save_state(dc);
2783 gen_movl_reg_T0(rs1);
2784 if (IS_IMM) { /* immediate */
2785 rs2 = GET_FIELDs(insn, 19, 31);
2786 #if defined(OPTIM)
2787 if (rs2 != 0) {
2788 #endif
2789 gen_movl_simm_T1(rs2);
2790 gen_op_add_T1_T0();
2791 #if defined(OPTIM)
2792 }
2793 #endif
2794 } else { /* register */
2795 rs2 = GET_FIELD(insn, 27, 31);
2796 #if defined(OPTIM)
2797 if (rs2 != 0) {
2798 #endif
2799 gen_movl_reg_T1(rs2);
2800 gen_op_add_T1_T0();
2801 #if defined(OPTIM)
2802 }
2803 #endif
2804 }
2805 if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \
2806 (xop > 0x17 && xop <= 0x1d ) || \
2807 (xop > 0x2c && xop <= 0x33) || xop == 0x1f) {
2808 switch (xop) {
2809 case 0x0: /* load word */
2810 gen_op_ldst(ld);
2811 break;
2812 case 0x1: /* load unsigned byte */
2813 gen_op_ldst(ldub);
2814 break;
2815 case 0x2: /* load unsigned halfword */
2816 gen_op_ldst(lduh);
2817 break;
2818 case 0x3: /* load double word */
2819 if (rd & 1)
2820 goto illegal_insn;
2821 gen_op_ldst(ldd);
2822 gen_movl_T0_reg(rd + 1);
2823 break;
2824 case 0x9: /* load signed byte */
2825 gen_op_ldst(ldsb);
2826 break;
2827 case 0xa: /* load signed halfword */
2828 gen_op_ldst(ldsh);
2829 break;
2830 case 0xd: /* ldstub -- XXX: should be atomically */
2831 gen_op_ldst(ldstub);
2832 break;
2833 case 0x0f: /* swap register with memory. Also atomically */
2834 gen_movl_reg_T1(rd);
2835 gen_op_ldst(swap);
2836 break;
2837 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2838 case 0x10: /* load word alternate */
2839 #ifndef TARGET_SPARC64
2840 if (IS_IMM)
2841 goto illegal_insn;
2842 if (!supervisor(dc))
2843 goto priv_insn;
2844 #endif
2845 gen_op_lda(insn, 1, 4, 0);
2846 break;
2847 case 0x11: /* load unsigned byte alternate */
2848 #ifndef TARGET_SPARC64
2849 if (IS_IMM)
2850 goto illegal_insn;
2851 if (!supervisor(dc))
2852 goto priv_insn;
2853 #endif
2854 gen_op_lduba(insn, 1, 1, 0);
2855 break;
2856 case 0x12: /* load unsigned halfword alternate */
2857 #ifndef TARGET_SPARC64
2858 if (IS_IMM)
2859 goto illegal_insn;
2860 if (!supervisor(dc))
2861 goto priv_insn;
2862 #endif
2863 gen_op_lduha(insn, 1, 2, 0);
2864 break;
2865 case 0x13: /* load double word alternate */
2866 #ifndef TARGET_SPARC64
2867 if (IS_IMM)
2868 goto illegal_insn;
2869 if (!supervisor(dc))
2870 goto priv_insn;
2871 #endif
2872 if (rd & 1)
2873 goto illegal_insn;
2874 gen_op_ldda(insn, 1, 8, 0);
2875 gen_movl_T0_reg(rd + 1);
2876 break;
2877 case 0x19: /* load signed byte alternate */
2878 #ifndef TARGET_SPARC64
2879 if (IS_IMM)
2880 goto illegal_insn;
2881 if (!supervisor(dc))
2882 goto priv_insn;
2883 #endif
2884 gen_op_ldsba(insn, 1, 1, 1);
2885 break;
2886 case 0x1a: /* load signed halfword alternate */
2887 #ifndef TARGET_SPARC64
2888 if (IS_IMM)
2889 goto illegal_insn;
2890 if (!supervisor(dc))
2891 goto priv_insn;
2892 #endif
2893 gen_op_ldsha(insn, 1, 2 ,1);
2894 break;
2895 case 0x1d: /* ldstuba -- XXX: should be atomically */
2896 #ifndef TARGET_SPARC64
2897 if (IS_IMM)
2898 goto illegal_insn;
2899 if (!supervisor(dc))
2900 goto priv_insn;
2901 #endif
2902 gen_op_ldstuba(insn, 1, 1, 0);
2903 break;
2904 case 0x1f: /* swap reg with alt. memory. Also atomically */
2905 #ifndef TARGET_SPARC64
2906 if (IS_IMM)
2907 goto illegal_insn;
2908 if (!supervisor(dc))
2909 goto priv_insn;
2910 #endif
2911 gen_movl_reg_T1(rd);
2912 gen_op_swapa(insn, 1, 4, 0);
2913 break;
2914
2915 #ifndef TARGET_SPARC64
2916 case 0x30: /* ldc */
2917 case 0x31: /* ldcsr */
2918 case 0x33: /* lddc */
2919 goto ncp_insn;
2920 /* avoid warnings */
2921 (void) &gen_op_stfa;
2922 (void) &gen_op_stdfa;
2923 (void) &gen_op_ldfa;
2924 (void) &gen_op_lddfa;
2925 #else
2926 #if !defined(CONFIG_USER_ONLY)
2927 (void) &gen_op_cas;
2928 (void) &gen_op_casx;
2929 #endif
2930 #endif
2931 #endif
2932 #ifdef TARGET_SPARC64
2933 case 0x08: /* V9 ldsw */
2934 gen_op_ldst(ldsw);
2935 break;
2936 case 0x0b: /* V9 ldx */
2937 gen_op_ldst(ldx);
2938 break;
2939 case 0x18: /* V9 ldswa */
2940 gen_op_ldswa(insn, 1, 4, 1);
2941 break;
2942 case 0x1b: /* V9 ldxa */
2943 gen_op_ldxa(insn, 1, 8, 0);
2944 break;
2945 case 0x2d: /* V9 prefetch, no effect */
2946 goto skip_move;
2947 case 0x30: /* V9 ldfa */
2948 gen_op_ldfa(insn, 1, 8, 0); // XXX
2949 break;
2950 case 0x33: /* V9 lddfa */
2951 gen_op_lddfa(insn, 1, 8, 0); // XXX
2952
2953 break;
2954 case 0x3d: /* V9 prefetcha, no effect */
2955 goto skip_move;
2956 case 0x32: /* V9 ldqfa */
2957 goto nfpu_insn;
2958 #endif
2959 default:
2960 goto illegal_insn;
2961 }
2962 gen_movl_T1_reg(rd);
2963 #ifdef TARGET_SPARC64
2964 skip_move: ;
2965 #endif
2966 } else if (xop >= 0x20 && xop < 0x24) {
2967 if (gen_trap_ifnofpu(dc))
2968 goto jmp_insn;
2969 switch (xop) {
2970 case 0x20: /* load fpreg */
2971 gen_op_ldst(ldf);
2972 gen_op_store_FT0_fpr(rd);
2973 break;
2974 case 0x21: /* load fsr */
2975 gen_op_ldst(ldf);
2976 gen_op_ldfsr();
2977 break;
2978 case 0x22: /* load quad fpreg */
2979 goto nfpu_insn;
2980 case 0x23: /* load double fpreg */
2981 gen_op_ldst(lddf);
2982 gen_op_store_DT0_fpr(DFPREG(rd));
2983 break;
2984 default:
2985 goto illegal_insn;
2986 }
2987 } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
2988 xop == 0xe || xop == 0x1e) {
2989 gen_movl_reg_T1(rd);
2990 switch (xop) {
2991 case 0x4:
2992 gen_op_ldst(st);
2993 break;
2994 case 0x5:
2995 gen_op_ldst(stb);
2996 break;
2997 case 0x6:
2998 gen_op_ldst(sth);
2999 break;
3000 case 0x7:
3001 if (rd & 1)
3002 goto illegal_insn;
3003 flush_T2(dc);
3004 gen_movl_reg_T2(rd + 1);
3005 gen_op_ldst(std);
3006 break;
3007 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3008 case 0x14:
3009 #ifndef TARGET_SPARC64
3010 if (IS_IMM)
3011 goto illegal_insn;
3012 if (!supervisor(dc))
3013 goto priv_insn;
3014 #endif
3015 gen_op_sta(insn, 0, 4, 0);
3016 break;
3017 case 0x15:
3018 #ifndef TARGET_SPARC64
3019 if (IS_IMM)
3020 goto illegal_insn;
3021 if (!supervisor(dc))
3022 goto priv_insn;
3023 #endif
3024 gen_op_stba(insn, 0, 1, 0);
3025 break;
3026 case 0x16:
3027 #ifndef TARGET_SPARC64
3028 if (IS_IMM)
3029 goto illegal_insn;
3030 if (!supervisor(dc))
3031 goto priv_insn;
3032 #endif
3033 gen_op_stha(insn, 0, 2, 0);
3034 break;
3035 case 0x17:
3036 #ifndef TARGET_SPARC64
3037 if (IS_IMM)
3038 goto illegal_insn;
3039 if (!supervisor(dc))
3040 goto priv_insn;
3041 #endif
3042 if (rd & 1)
3043 goto illegal_insn;
3044 flush_T2(dc);
3045 gen_movl_reg_T2(rd + 1);
3046 gen_op_stda(insn, 0, 8, 0);
3047 break;
3048 #endif
3049 #ifdef TARGET_SPARC64
3050 case 0x0e: /* V9 stx */
3051 gen_op_ldst(stx);
3052 break;
3053 case 0x1e: /* V9 stxa */
3054 gen_op_stxa(insn, 0, 8, 0); // XXX
3055 break;
3056 #endif
3057 default:
3058 goto illegal_insn;
3059 }
3060 } else if (xop > 0x23 && xop < 0x28) {
3061 if (gen_trap_ifnofpu(dc))
3062 goto jmp_insn;
3063 switch (xop) {
3064 case 0x24:
3065 gen_op_load_fpr_FT0(rd);
3066 gen_op_ldst(stf);
3067 break;
3068 case 0x25: /* stfsr, V9 stxfsr */
3069 gen_op_stfsr();
3070 gen_op_ldst(stf);
3071 break;
3072 #if !defined(CONFIG_USER_ONLY)
3073 case 0x26: /* stdfq */
3074 if (!supervisor(dc))
3075 goto priv_insn;
3076 if (gen_trap_ifnofpu(dc))
3077 goto jmp_insn;
3078 goto nfq_insn;
3079 #endif
3080 case 0x27:
3081 gen_op_load_fpr_DT0(DFPREG(rd));
3082 gen_op_ldst(stdf);
3083 break;
3084 default:
3085 goto illegal_insn;
3086 }
3087 } else if (xop > 0x33 && xop < 0x3f) {
3088 switch (xop) {
3089 #ifdef TARGET_SPARC64
3090 case 0x34: /* V9 stfa */
3091 gen_op_stfa(insn, 0, 0, 0); // XXX
3092 break;
3093 case 0x37: /* V9 stdfa */
3094 gen_op_stdfa(insn, 0, 0, 0); // XXX
3095 break;
3096 case 0x3c: /* V9 casa */
3097 gen_op_casa(insn, 0, 4, 0); // XXX
3098 break;
3099 case 0x3e: /* V9 casxa */
3100 gen_op_casxa(insn, 0, 8, 0); // XXX
3101 break;
3102 case 0x36: /* V9 stqfa */
3103 goto nfpu_insn;
3104 #else
3105 case 0x34: /* stc */
3106 case 0x35: /* stcsr */
3107 case 0x36: /* stdcq */
3108 case 0x37: /* stdc */
3109 goto ncp_insn;
3110 #endif
3111 default:
3112 goto illegal_insn;
3113 }
3114 }
3115 else
3116 goto illegal_insn;
3117 }
3118 break;
3119 }
3120 /* default case for non jump instructions */
3121 if (dc->npc == DYNAMIC_PC) {
3122 dc->pc = DYNAMIC_PC;
3123 gen_op_next_insn();
3124 } else if (dc->npc == JUMP_PC) {
3125 /* we can do a static jump */
3126 gen_branch2(dc, (long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
3127 dc->is_br = 1;
3128 } else {
3129 dc->pc = dc->npc;
3130 dc->npc = dc->npc + 4;
3131 }
3132 jmp_insn:
3133 return;
3134 illegal_insn:
3135 save_state(dc);
3136 gen_op_exception(TT_ILL_INSN);
3137 dc->is_br = 1;
3138 return;
3139 #if !defined(CONFIG_USER_ONLY)
3140 priv_insn:
3141 save_state(dc);
3142 gen_op_exception(TT_PRIV_INSN);
3143 dc->is_br = 1;
3144 return;
3145 #endif
3146 nfpu_insn:
3147 save_state(dc);
3148 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3149 dc->is_br = 1;
3150 return;
3151 #if !defined(CONFIG_USER_ONLY)
3152 nfq_insn:
3153 save_state(dc);
3154 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3155 dc->is_br = 1;
3156 return;
3157 #endif
3158 #ifndef TARGET_SPARC64
3159 ncp_insn:
3160 save_state(dc);
3161 gen_op_exception(TT_NCP_INSN);
3162 dc->is_br = 1;
3163 return;
3164 #endif
3165 }
3166
3167 static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3168 int spc, CPUSPARCState *env)
3169 {
3170 target_ulong pc_start, last_pc;
3171 uint16_t *gen_opc_end;
3172 DisasContext dc1, *dc = &dc1;
3173 int j, lj = -1;
3174
3175 memset(dc, 0, sizeof(DisasContext));
3176 dc->tb = tb;
3177 pc_start = tb->pc;
3178 dc->pc = pc_start;
3179 last_pc = dc->pc;
3180 dc->npc = (target_ulong) tb->cs_base;
3181 #if defined(CONFIG_USER_ONLY)
3182 dc->mem_idx = 0;
3183 dc->fpu_enabled = 1;
3184 #else
3185 dc->mem_idx = ((env->psrs) != 0);
3186 #ifdef TARGET_SPARC64
3187 dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
3188 #else
3189 dc->fpu_enabled = ((env->psref) != 0);
3190 #endif
3191 #endif
3192 gen_opc_ptr = gen_opc_buf;
3193 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3194 gen_opparam_ptr = gen_opparam_buf;
3195 nb_gen_labels = 0;
3196
3197 do {
3198 if (env->nb_breakpoints > 0) {
3199 for(j = 0; j < env->nb_breakpoints; j++) {
3200 if (env->breakpoints[j] == dc->pc) {
3201 if (dc->pc != pc_start)
3202 save_state(dc);
3203 gen_op_debug();
3204 gen_op_movl_T0_0();
3205 gen_op_exit_tb();
3206 dc->is_br = 1;
3207 goto exit_gen_loop;
3208 }
3209 }
3210 }
3211 if (spc) {
3212 if (loglevel > 0)
3213 fprintf(logfile, "Search PC...\n");
3214 j = gen_opc_ptr - gen_opc_buf;
3215 if (lj < j) {
3216 lj++;
3217 while (lj < j)
3218 gen_opc_instr_start[lj++] = 0;
3219 gen_opc_pc[lj] = dc->pc;
3220 gen_opc_npc[lj] = dc->npc;
3221 gen_opc_instr_start[lj] = 1;
3222 }
3223 }
3224 last_pc = dc->pc;
3225 disas_sparc_insn(dc);
3226
3227 if (dc->is_br)
3228 break;
3229 /* if the next PC is different, we abort now */
3230 if (dc->pc != (last_pc + 4))
3231 break;
3232 /* if we reach a page boundary, we stop generation so that the
3233 PC of a TT_TFAULT exception is always in the right page */
3234 if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3235 break;
3236 /* if single step mode, we generate only one instruction and
3237 generate an exception */
3238 if (env->singlestep_enabled) {
3239 gen_jmp_im(dc->pc);
3240 gen_op_movl_T0_0();
3241 gen_op_exit_tb();
3242 break;
3243 }
3244 } while ((gen_opc_ptr < gen_opc_end) &&
3245 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
3246
3247 exit_gen_loop:
3248 if (!dc->is_br) {
3249 if (dc->pc != DYNAMIC_PC &&
3250 (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3251 /* static PC and NPC: we can use direct chaining */
3252 gen_branch(dc, (long)tb, dc->pc, dc->npc);
3253 } else {
3254 if (dc->pc != DYNAMIC_PC)
3255 gen_jmp_im(dc->pc);
3256 save_npc(dc);
3257 gen_op_movl_T0_0();
3258 gen_op_exit_tb();
3259 }
3260 }
3261 *gen_opc_ptr = INDEX_op_end;
3262 if (spc) {
3263 j = gen_opc_ptr - gen_opc_buf;
3264 lj++;
3265 while (lj <= j)
3266 gen_opc_instr_start[lj++] = 0;
3267 tb->size = 0;
3268 #if 0
3269 if (loglevel > 0) {
3270 page_dump(logfile);
3271 }
3272 #endif
3273 gen_opc_jump_pc[0] = dc->jump_pc[0];
3274 gen_opc_jump_pc[1] = dc->jump_pc[1];
3275 } else {
3276 tb->size = last_pc + 4 - pc_start;
3277 }
3278 #ifdef DEBUG_DISAS
3279 if (loglevel & CPU_LOG_TB_IN_ASM) {
3280 fprintf(logfile, "--------------\n");
3281 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3282 target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3283 fprintf(logfile, "\n");
3284 if (loglevel & CPU_LOG_TB_OP) {
3285 fprintf(logfile, "OP:\n");
3286 dump_ops(gen_opc_buf, gen_opparam_buf);
3287 fprintf(logfile, "\n");
3288 }
3289 }
3290 #endif
3291 return 0;
3292 }
3293
3294 int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
3295 {
3296 return gen_intermediate_code_internal(tb, 0, env);
3297 }
3298
3299 int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
3300 {
3301 return gen_intermediate_code_internal(tb, 1, env);
3302 }
3303
3304 extern int ram_size;
3305
3306 void cpu_reset(CPUSPARCState *env)
3307 {
3308 tlb_flush(env, 1);
3309 env->cwp = 0;
3310 env->wim = 1;
3311 env->regwptr = env->regbase + (env->cwp * 16);
3312 #if defined(CONFIG_USER_ONLY)
3313 env->user_mode_only = 1;
3314 #ifdef TARGET_SPARC64
3315 env->cleanwin = NWINDOWS - 1;
3316 env->cansave = NWINDOWS - 1;
3317 #endif
3318 #else
3319 env->psret = 0;
3320 env->psrs = 1;
3321 env->psrps = 1;
3322 #ifdef TARGET_SPARC64
3323 env->pstate = PS_PRIV;
3324 env->pc = 0x1fff0000000ULL;
3325 #else
3326 env->pc = 0xffd00000;
3327 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
3328 #endif
3329 env->npc = env->pc + 4;
3330 #endif
3331 }
3332
3333 CPUSPARCState *cpu_sparc_init(void)
3334 {
3335 CPUSPARCState *env;
3336
3337 env = qemu_mallocz(sizeof(CPUSPARCState));
3338 if (!env)
3339 return NULL;
3340 cpu_exec_init(env);
3341 cpu_reset(env);
3342 return (env);
3343 }
3344
3345 static const sparc_def_t sparc_defs[] = {
3346 #ifdef TARGET_SPARC64
3347 {
3348 .name = "TI UltraSparc II",
3349 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0 << 24)
3350 | (MAXTL << 8) | (NWINDOWS - 1)),
3351 .fpu_version = 0x00000000,
3352 .mmu_version = 0,
3353 },
3354 #else
3355 {
3356 .name = "Fujitsu MB86904",
3357 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3358 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3359 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
3360 },
3361 {
3362 .name = "Fujitsu MB86907",
3363 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3364 .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3365 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
3366 },
3367 {
3368 .name = "TI MicroSparc I",
3369 .iu_version = 0x41000000,
3370 .fpu_version = 4 << 17,
3371 .mmu_version = 0x41000000,
3372 },
3373 {
3374 .name = "TI SuperSparc II",
3375 .iu_version = 0x40000000,
3376 .fpu_version = 0 << 17,
3377 .mmu_version = 0x04000000,
3378 },
3379 {
3380 .name = "Ross RT620",
3381 .iu_version = 0x1e000000,
3382 .fpu_version = 1 << 17,
3383 .mmu_version = 0x17000000,
3384 },
3385 #endif
3386 };
3387
3388 int sparc_find_by_name(const unsigned char *name, const sparc_def_t **def)
3389 {
3390 int ret;
3391 unsigned int i;
3392
3393 ret = -1;
3394 *def = NULL;
3395 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3396 if (strcasecmp(name, sparc_defs[i].name) == 0) {
3397 *def = &sparc_defs[i];
3398 ret = 0;
3399 break;
3400 }
3401 }
3402
3403 return ret;
3404 }
3405
3406 void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3407 {
3408 unsigned int i;
3409
3410 for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3411 (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
3412 sparc_defs[i].name,
3413 sparc_defs[i].iu_version,
3414 sparc_defs[i].fpu_version,
3415 sparc_defs[i].mmu_version);
3416 }
3417 }
3418
3419 int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def)
3420 {
3421 env->version = def->iu_version;
3422 env->fsr = def->fpu_version;
3423 #if !defined(TARGET_SPARC64)
3424 env->mmuregs[0] = def->mmu_version;
3425 #endif
3426 return 0;
3427 }
3428
3429 #define GET_FLAG(a,b) ((env->psr & a)?b:'-')
3430
3431 void cpu_dump_state(CPUState *env, FILE *f,
3432 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
3433 int flags)
3434 {
3435 int i, x;
3436
3437 cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
3438 cpu_fprintf(f, "General Registers:\n");
3439 for (i = 0; i < 4; i++)
3440 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3441 cpu_fprintf(f, "\n");
3442 for (; i < 8; i++)
3443 cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3444 cpu_fprintf(f, "\nCurrent Register Window:\n");
3445 for (x = 0; x < 3; x++) {
3446 for (i = 0; i < 4; i++)
3447 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3448 (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
3449 env->regwptr[i + x * 8]);
3450 cpu_fprintf(f, "\n");
3451 for (; i < 8; i++)
3452 cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3453 (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
3454 env->regwptr[i + x * 8]);
3455 cpu_fprintf(f, "\n");
3456 }
3457 cpu_fprintf(f, "\nFloating Point Registers:\n");
3458 for (i = 0; i < 32; i++) {
3459 if ((i & 3) == 0)
3460 cpu_fprintf(f, "%%f%02d:", i);
3461 cpu_fprintf(f, " %016lf", env->fpr[i]);
3462 if ((i & 3) == 3)
3463 cpu_fprintf(f, "\n");
3464 }
3465 #ifdef TARGET_SPARC64
3466 cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
3467 env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
3468 cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3469 env->cansave, env->canrestore, env->otherwin, env->wstate,
3470 env->cleanwin, NWINDOWS - 1 - env->cwp);
3471 #else
3472 cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
3473 GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
3474 GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
3475 env->psrs?'S':'-', env->psrps?'P':'-',
3476 env->psret?'E':'-', env->wim);
3477 #endif
3478 cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
3479 }
3480
3481 #if defined(CONFIG_USER_ONLY)
3482 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3483 {
3484 return addr;
3485 }
3486
3487 #else
3488 extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
3489 int *access_index, target_ulong address, int rw,
3490 int is_user);
3491
3492 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3493 {
3494 target_phys_addr_t phys_addr;
3495 int prot, access_index;
3496
3497 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
3498 if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
3499 return -1;
3500 if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
3501 return -1;
3502 return phys_addr;
3503 }
3504 #endif
3505
3506 void helper_flush(target_ulong addr)
3507 {
3508 addr &= ~7;
3509 tb_invalidate_page_range(addr, addr + 8);
3510 }
Samsung s3c2440 and arm920t support for the mini2440 dev board