hw/sun4u.c

   1 /*
   2  * QEMU Sun4u System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25 #include "m48t59.h"
  26
  27 #define KERNEL_LOAD_ADDR     0x00404000
  28 #define CMDLINE_ADDR         0x003ff000
  29 #define INITRD_LOAD_ADDR     0x00300000
  30 #define PROM_SIZE_MAX        (512 * 1024)
  31 #define PROM_ADDR            0x1fff0000000ULL
  32 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  33 #define APB_MEM_BASE         0x1ff00000000ULL
  34 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  35 #define PROM_FILENAME        "openbios-sparc64"
  36 #define NVRAM_SIZE           0x2000
  37
  38 /* TSC handling */
  39
  40 uint64_t cpu_get_tsc()
  41 {
  42     return qemu_get_clock(vm_clock);
  43 }
  44
  45 int DMA_get_channel_mode (int nchan)
  46 {
  47     return 0;
  48 }
  49 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  50 {
  51     return 0;
  52 }
  53 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  54 {
  55     return 0;
  56 }
  57 void DMA_hold_DREQ (int nchan) {}
  58 void DMA_release_DREQ (int nchan) {}
  59 void DMA_schedule(int nchan) {}
  60 void DMA_run (void) {}
  61 void DMA_init (int high_page_enable) {}
  62 void DMA_register_channel (int nchan,
  63                            DMA_transfer_handler transfer_handler,
  64                            void *opaque)
  65 {
  66 }
  67
  68 /* NVRAM helpers */
  69 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
  70 {
  71     m48t59_write(nvram, addr, value);
  72 }
  73
  74 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
  75 {
  76     return m48t59_read(nvram, addr);
  77 }
  78
  79 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
  80 {
  81     m48t59_write(nvram, addr, value >> 8);
  82     m48t59_write(nvram, addr + 1, value & 0xFF);
  83 }
  84
  85 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
  86 {
  87     uint16_t tmp;
  88
  89     tmp = m48t59_read(nvram, addr) << 8;
  90     tmp |= m48t59_read(nvram, addr + 1);
  91
  92     return tmp;
  93 }
  94
  95 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
  96 {
  97     m48t59_write(nvram, addr, value >> 24);
  98     m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
  99     m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
 100     m48t59_write(nvram, addr + 3, value & 0xFF);
 101 }
 102
 103 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
 104 {
 105     uint32_t tmp;
 106
 107     tmp = m48t59_read(nvram, addr) << 24;
 108     tmp |= m48t59_read(nvram, addr + 1) << 16;
 109     tmp |= m48t59_read(nvram, addr + 2) << 8;
 110     tmp |= m48t59_read(nvram, addr + 3);
 111
 112     return tmp;
 113 }
 114
 115 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
 116                        const unsigned char *str, uint32_t max)
 117 {
 118     int i;
 119
 120     for (i = 0; i < max && str[i] != '\0'; i++) {
 121         m48t59_write(nvram, addr + i, str[i]);
 122     }
 123     m48t59_write(nvram, addr + max - 1, '\0');
 124 }
 125
 126 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
 127 {
 128     int i;
 129
 130     memset(dst, 0, max);
 131     for (i = 0; i < max; i++) {
 132         dst[i] = NVRAM_get_byte(nvram, addr + i);
 133         if (dst[i] == '\0')
 134             break;
 135     }
 136
 137     return i;
 138 }
 139
 140 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
 141 {
 142     uint16_t tmp;
 143     uint16_t pd, pd1, pd2;
 144
 145     tmp = prev >> 8;
 146     pd = prev ^ value;
 147     pd1 = pd & 0x000F;
 148     pd2 = ((pd >> 4) & 0x000F) ^ pd1;
 149     tmp ^= (pd1 << 3) | (pd1 << 8);
 150     tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
 151
 152     return tmp;
 153 }
 154
 155 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
 156 {
 157     uint32_t i;
 158     uint16_t crc = 0xFFFF;
 159     int odd;
 160
 161     odd = count & 1;
 162     count &= ~1;
 163     for (i = 0; i != count; i++) {
 164         crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
 165     }
 166     if (odd) {
 167         crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
 168     }
 169
 170     return crc;
 171 }
 172
 173 static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
 174                                 const unsigned char *str)
 175 {
 176     uint32_t len;
 177
 178     len = strlen(str) + 1;
 179     NVRAM_set_string(nvram, addr, str, len);
 180
 181     return addr + len;
 182 }
 183
 184 static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
 185                                     uint32_t end)
 186 {
 187     unsigned int i, sum;
 188
 189     // Length divided by 16
 190     m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
 191     m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
 192     // Checksum
 193     sum = m48t59_read(nvram, start);
 194     for (i = 0; i < 14; i++) {
 195         sum += m48t59_read(nvram, start + 2 + i);
 196         sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
 197     }
 198     m48t59_write(nvram, start + 1, sum & 0xff);
 199 }
 200
 201 extern int nographic;
 202
 203 int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 204                           const unsigned char *arch,
 205                           uint32_t RAM_size, int boot_device,
 206                           uint32_t kernel_image, uint32_t kernel_size,
 207                           const char *cmdline,
 208                           uint32_t initrd_image, uint32_t initrd_size,
 209                           uint32_t NVRAM_image,
 210                           int width, int height, int depth)
 211 {
 212     uint16_t crc;
 213     unsigned int i;
 214     uint32_t start, end;
 215
 216     /* Set parameters for Open Hack'Ware BIOS */
 217     NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
 218     NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
 219     NVRAM_set_word(nvram,   0x14, NVRAM_size);
 220     NVRAM_set_string(nvram, 0x20, arch, 16);
 221     NVRAM_set_byte(nvram,   0x2f, nographic & 0xff);
 222     NVRAM_set_lword(nvram,  0x30, RAM_size);
 223     NVRAM_set_byte(nvram,   0x34, boot_device);
 224     NVRAM_set_lword(nvram,  0x38, kernel_image);
 225     NVRAM_set_lword(nvram,  0x3C, kernel_size);
 226     if (cmdline) {
 227         /* XXX: put the cmdline in NVRAM too ? */
 228         strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
 229         NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
 230         NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
 231     } else {
 232         NVRAM_set_lword(nvram,  0x40, 0);
 233         NVRAM_set_lword(nvram,  0x44, 0);
 234     }
 235     NVRAM_set_lword(nvram,  0x48, initrd_image);
 236     NVRAM_set_lword(nvram,  0x4C, initrd_size);
 237     NVRAM_set_lword(nvram,  0x50, NVRAM_image);
 238
 239     NVRAM_set_word(nvram,   0x54, width);
 240     NVRAM_set_word(nvram,   0x56, height);
 241     NVRAM_set_word(nvram,   0x58, depth);
 242     crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
 243     NVRAM_set_word(nvram,  0xFC, crc);
 244
 245     // OpenBIOS nvram variables
 246     // Variable partition
 247     start = 252;
 248     m48t59_write(nvram, start, 0x70);
 249     NVRAM_set_string(nvram, start + 4, "system", 12);
 250
 251     end = start + 16;
 252     for (i = 0; i < nb_prom_envs; i++)
 253         end = nvram_set_var(nvram, end, prom_envs[i]);
 254
 255     m48t59_write(nvram, end++ , 0);
 256     end = start + ((end - start + 15) & ~15);
 257     nvram_finish_partition(nvram, start, end);
 258
 259     // free partition
 260     start = end;
 261     m48t59_write(nvram, start, 0x7f);
 262     NVRAM_set_string(nvram, start + 4, "free", 12);
 263
 264     end = 0x1fd0;
 265     nvram_finish_partition(nvram, start, end);
 266
 267     return 0;
 268 }
 269
 270 void pic_info()
 271 {
 272 }
 273
 274 void irq_info()
 275 {
 276 }
 277
 278 void qemu_system_powerdown(void)
 279 {
 280 }
 281
 282 static void main_cpu_reset(void *opaque)
 283 {
 284     CPUState *env = opaque;
 285
 286     cpu_reset(env);
 287     ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
 288     ptimer_run(env->tick, 0);
 289     ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
 290     ptimer_run(env->stick, 0);
 291     ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
 292     ptimer_run(env->hstick, 0);
 293 }
 294
 295 void tick_irq(void *opaque)
 296 {
 297     CPUState *env = opaque;
 298
 299     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 300 }
 301
 302 void stick_irq(void *opaque)
 303 {
 304     CPUState *env = opaque;
 305
 306     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 307 }
 308
 309 void hstick_irq(void *opaque)
 310 {
 311     CPUState *env = opaque;
 312
 313     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 314 }
 315
 316 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 317 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 318 static const int ide_irq[2] = { 14, 15 };
 319
 320 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 321 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 322
 323 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 324 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 325
 326 static fdctrl_t *floppy_controller;
 327
 328 /* Sun4u hardware initialisation */
 329 static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
 330              DisplayState *ds, const char **fd_filename, int snapshot,
 331              const char *kernel_filename, const char *kernel_cmdline,
 332              const char *initrd_filename, const char *cpu_model)
 333 {
 334     CPUState *env;
 335     char buf[1024];
 336     m48t59_t *nvram;
 337     int ret, linux_boot;
 338     unsigned int i;
 339     long prom_offset, initrd_size, kernel_size;
 340     PCIBus *pci_bus;
 341     const sparc_def_t *def;
 342     QEMUBH *bh;
 343
 344     linux_boot = (kernel_filename != NULL);
 345
 346     /* init CPUs */
 347     if (cpu_model == NULL)
 348         cpu_model = "TI UltraSparc II";
 349     sparc_find_by_name(cpu_model, &def);
 350     if (def == NULL) {
 351         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 352         exit(1);
 353     }
 354     env = cpu_init();
 355     cpu_sparc_register(env, def);
 356     bh = qemu_bh_new(tick_irq, env);
 357     env->tick = ptimer_init(bh);
 358     ptimer_set_period(env->tick, 1ULL);
 359
 360     bh = qemu_bh_new(stick_irq, env);
 361     env->stick = ptimer_init(bh);
 362     ptimer_set_period(env->stick, 1ULL);
 363
 364     bh = qemu_bh_new(hstick_irq, env);
 365     env->hstick = ptimer_init(bh);
 366     ptimer_set_period(env->hstick, 1ULL);
 367     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 368     qemu_register_reset(main_cpu_reset, env);
 369     main_cpu_reset(env);
 370
 371     /* allocate RAM */
 372     cpu_register_physical_memory(0, ram_size, 0);
 373
 374     prom_offset = ram_size + vga_ram_size;
 375     cpu_register_physical_memory(PROM_ADDR,
 376                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
 377                                  prom_offset | IO_MEM_ROM);
 378
 379     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
 380     ret = load_elf(buf, 0, NULL, NULL, NULL);
 381     if (ret < 0) {
 382         fprintf(stderr, "qemu: could not load prom '%s'\n",
 383                 buf);
 384         exit(1);
 385     }
 386
 387     kernel_size = 0;
 388     initrd_size = 0;
 389     if (linux_boot) {
 390         /* XXX: put correct offset */
 391         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 392         if (kernel_size < 0)
 393             kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 394         if (kernel_size < 0)
 395             kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
 396         if (kernel_size < 0) {
 397             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 398                     kernel_filename);
 399             exit(1);
 400         }
 401
 402         /* load initrd */
 403         if (initrd_filename) {
 404             initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
 405             if (initrd_size < 0) {
 406                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 407                         initrd_filename);
 408                 exit(1);
 409             }
 410         }
 411         if (initrd_size > 0) {
 412             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 413                 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
 414                     == 0x48647253) { // HdrS
 415                     stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 416                     stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
 417                     break;
 418                 }
 419             }
 420         }
 421     }
 422     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
 423     isa_mem_base = VGA_BASE;
 424     pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
 425
 426     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 427         if (serial_hds[i]) {
 428             serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
 429         }
 430     }
 431
 432     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 433         if (parallel_hds[i]) {
 434             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
 435         }
 436     }
 437
 438     for(i = 0; i < nb_nics; i++) {
 439         if (!nd_table[i].model)
 440             nd_table[i].model = "ne2k_pci";
 441         pci_nic_init(pci_bus, &nd_table[i], -1);
 442     }
 443
 444     pci_cmd646_ide_init(pci_bus, bs_table, 1);
 445     /* FIXME: wire up interrupts.  */
 446     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 447     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
 448     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 449     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
 450                          KERNEL_LOAD_ADDR, kernel_size,
 451                          kernel_cmdline,
 452                          INITRD_LOAD_ADDR, initrd_size,
 453                          /* XXX: need an option to load a NVRAM image */
 454                          0,
 455                          graphic_width, graphic_height, graphic_depth);
 456
 457 }
 458
 459 QEMUMachine sun4u_machine = {
 460     "sun4u",
 461     "Sun4u platform",
 462     sun4u_init,
 463 };