2 * Intel XScale PXA255/270 OS Timers.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Copyright (c) 2006 Thorsten Zitterell
7 * This code is licenced under the GPL.
24 #define OSCR 0x10 /* OS Timer Count */
33 #define OSSR 0x14 /* Timer status register */
35 #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
36 #define OMCR4 0xc0 /* OS Match Control registers */
46 #define PXA25X_FREQ 3686400 /* 3.6864 MHz */
47 #define PXA27X_FREQ 3250000 /* 3.25 MHz */
49 static int pxa2xx_timer4_freq
[8] = {
55 /* [5] is the "Externally supplied clock". Assign if necessary. */
59 struct pxa2xx_timer0_s
{
68 struct pxa2xx_timer4_s
{
69 struct pxa2xx_timer0_s tm
;
78 target_phys_addr_t base
;
83 struct pxa2xx_timer0_s timer
[4];
84 struct pxa2xx_timer4_s
*tm4
;
91 static void pxa2xx_timer_update(void *opaque
, uint64_t now_qemu
)
93 pxa2xx_timer_info
*s
= (pxa2xx_timer_info
*) opaque
;
99 muldiv64(now_qemu
- s
->lastload
, s
->freq
, ticks_per_sec
);
101 for (i
= 0; i
< 4; i
++) {
102 new_qemu
= now_qemu
+ muldiv64((uint32_t) (s
->timer
[i
].value
- now_vm
),
103 ticks_per_sec
, s
->freq
);
104 qemu_mod_timer(s
->timer
[i
].qtimer
, new_qemu
);
108 static void pxa2xx_timer_update4(void *opaque
, uint64_t now_qemu
, int n
)
110 pxa2xx_timer_info
*s
= (pxa2xx_timer_info
*) opaque
;
113 static const int counters
[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
116 if (s
->tm4
[n
].control
& (1 << 7))
119 counter
= counters
[n
];
121 if (!s
->tm4
[counter
].freq
) {
122 qemu_del_timer(s
->tm4
[n
].tm
.qtimer
);
126 now_vm
= s
->tm4
[counter
].clock
+ muldiv64(now_qemu
-
127 s
->tm4
[counter
].lastload
,
128 s
->tm4
[counter
].freq
, ticks_per_sec
);
130 new_qemu
= now_qemu
+ muldiv64((uint32_t) (s
->tm4
[n
].tm
.value
- now_vm
),
131 ticks_per_sec
, s
->tm4
[counter
].freq
);
132 qemu_mod_timer(s
->tm4
[n
].tm
.qtimer
, new_qemu
);
135 static uint32_t pxa2xx_timer_read(void *opaque
, target_phys_addr_t offset
)
137 pxa2xx_timer_info
*s
= (pxa2xx_timer_info
*) opaque
;
147 return s
->timer
[tm
].value
;
158 return s
->tm4
[tm
].tm
.value
;
160 return s
->clock
+ muldiv64(qemu_get_clock(vm_clock
) -
161 s
->lastload
, s
->freq
, ticks_per_sec
);
173 if ((tm
== 9 - 4 || tm
== 11 - 4) && (s
->tm4
[tm
].control
& (1 << 9))) {
174 if (s
->tm4
[tm
- 1].freq
)
175 s
->snapshot
= s
->tm4
[tm
- 1].clock
+ muldiv64(
176 qemu_get_clock(vm_clock
) -
177 s
->tm4
[tm
- 1].lastload
,
178 s
->tm4
[tm
- 1].freq
, ticks_per_sec
);
180 s
->snapshot
= s
->tm4
[tm
- 1].clock
;
183 if (!s
->tm4
[tm
].freq
)
184 return s
->tm4
[tm
].clock
;
185 return s
->tm4
[tm
].clock
+ muldiv64(qemu_get_clock(vm_clock
) -
186 s
->tm4
[tm
].lastload
, s
->tm4
[tm
].freq
, ticks_per_sec
);
188 return s
->irq_enabled
;
189 case OSSR
: /* Status register */
203 return s
->tm4
[tm
].control
;
208 cpu_abort(cpu_single_env
, "pxa2xx_timer_read: Bad offset "
209 REG_FMT
"\n", offset
);
215 static void pxa2xx_timer_write(void *opaque
, target_phys_addr_t offset
,
219 pxa2xx_timer_info
*s
= (pxa2xx_timer_info
*) opaque
;
228 s
->timer
[tm
].value
= value
;
229 pxa2xx_timer_update(s
, qemu_get_clock(vm_clock
));
241 s
->tm4
[tm
].tm
.value
= value
;
242 pxa2xx_timer_update4(s
, qemu_get_clock(vm_clock
), tm
);
245 s
->oldclock
= s
->clock
;
246 s
->lastload
= qemu_get_clock(vm_clock
);
248 pxa2xx_timer_update(s
, s
->lastload
);
260 s
->tm4
[tm
].oldclock
= s
->tm4
[tm
].clock
;
261 s
->tm4
[tm
].lastload
= qemu_get_clock(vm_clock
);
262 s
->tm4
[tm
].clock
= value
;
263 pxa2xx_timer_update4(s
, s
->tm4
[tm
].lastload
, tm
);
266 s
->irq_enabled
= value
& 0xfff;
268 case OSSR
: /* Status register */
270 for (i
= 0; i
< 4; i
++, value
>>= 1) {
271 if (s
->timer
[i
].level
&& (value
& 1)) {
272 s
->timer
[i
].level
= 0;
273 qemu_irq_lower(s
->timer
[i
].irq
);
277 for (i
= 0; i
< 8; i
++, value
>>= 1)
278 if (s
->tm4
[i
].tm
.level
&& (value
& 1))
279 s
->tm4
[i
].tm
.level
= 0;
280 if (!(s
->events
& 0xff0))
281 qemu_irq_lower(s
->tm4
->tm
.irq
);
284 case OWER
: /* XXX: Reset on OSMR3 match? */
293 s
->tm4
[tm
].control
= value
& 0x0ff;
294 /* XXX Stop if running (shouldn't happen) */
295 if ((value
& (1 << 7)) || tm
== 0)
296 s
->tm4
[tm
].freq
= pxa2xx_timer4_freq
[value
& 7];
299 pxa2xx_timer_update4(s
, qemu_get_clock(vm_clock
), tm
);
308 s
->tm4
[tm
].control
= value
& 0x3ff;
309 /* XXX Stop if running (shouldn't happen) */
310 if ((value
& (1 << 7)) || !(tm
& 1))
312 pxa2xx_timer4_freq
[(value
& (1 << 8)) ? 0 : (value
& 7)];
315 pxa2xx_timer_update4(s
, qemu_get_clock(vm_clock
), tm
);
320 cpu_abort(cpu_single_env
, "pxa2xx_timer_write: Bad offset "
321 REG_FMT
"\n", offset
);
325 static CPUReadMemoryFunc
*pxa2xx_timer_readfn
[] = {
331 static CPUWriteMemoryFunc
*pxa2xx_timer_writefn
[] = {
337 static void pxa2xx_timer_tick(void *opaque
)
339 struct pxa2xx_timer0_s
*t
= (struct pxa2xx_timer0_s
*) opaque
;
340 pxa2xx_timer_info
*i
= (pxa2xx_timer_info
*) t
->info
;
342 if (i
->irq_enabled
& (1 << t
->num
)) {
344 i
->events
|= 1 << t
->num
;
345 qemu_irq_raise(t
->irq
);
351 qemu_system_reset_request();
355 static void pxa2xx_timer_tick4(void *opaque
)
357 struct pxa2xx_timer4_s
*t
= (struct pxa2xx_timer4_s
*) opaque
;
358 pxa2xx_timer_info
*i
= (pxa2xx_timer_info
*) t
->tm
.info
;
360 pxa2xx_timer_tick(&t
->tm
);
361 if (t
->control
& (1 << 3))
363 if (t
->control
& (1 << 6))
364 pxa2xx_timer_update4(i
, qemu_get_clock(vm_clock
), t
->tm
.num
- 4);
367 static void pxa2xx_timer_save(QEMUFile
*f
, void *opaque
)
369 pxa2xx_timer_info
*s
= (pxa2xx_timer_info
*) opaque
;
372 qemu_put_be32s(f
, &s
->clock
);
373 qemu_put_be32s(f
, &s
->oldclock
);
374 qemu_put_be64s(f
, &s
->lastload
);
376 for (i
= 0; i
< 4; i
++) {
377 qemu_put_be32s(f
, &s
->timer
[i
].value
);
378 qemu_put_be32(f
, s
->timer
[i
].level
);
381 for (i
= 0; i
< 8; i
++) {
382 qemu_put_be32s(f
, &s
->tm4
[i
].tm
.value
);
383 qemu_put_be32(f
, s
->tm4
[i
].tm
.level
);
384 qemu_put_be32s(f
, &s
->tm4
[i
].oldclock
);
385 qemu_put_be32s(f
, &s
->tm4
[i
].clock
);
386 qemu_put_be64s(f
, &s
->tm4
[i
].lastload
);
387 qemu_put_be32s(f
, &s
->tm4
[i
].freq
);
388 qemu_put_be32s(f
, &s
->tm4
[i
].control
);
391 qemu_put_be32s(f
, &s
->events
);
392 qemu_put_be32s(f
, &s
->irq_enabled
);
393 qemu_put_be32s(f
, &s
->reset3
);
394 qemu_put_be32s(f
, &s
->snapshot
);
397 static int pxa2xx_timer_load(QEMUFile
*f
, void *opaque
, int version_id
)
399 pxa2xx_timer_info
*s
= (pxa2xx_timer_info
*) opaque
;
403 qemu_get_be32s(f
, &s
->clock
);
404 qemu_get_be32s(f
, &s
->oldclock
);
405 qemu_get_be64s(f
, &s
->lastload
);
407 now
= qemu_get_clock(vm_clock
);
408 for (i
= 0; i
< 4; i
++) {
409 qemu_get_be32s(f
, &s
->timer
[i
].value
);
410 s
->timer
[i
].level
= qemu_get_be32(f
);
412 pxa2xx_timer_update(s
, now
);
415 for (i
= 0; i
< 8; i
++) {
416 qemu_get_be32s(f
, &s
->tm4
[i
].tm
.value
);
417 s
->tm4
[i
].tm
.level
= qemu_get_be32(f
);
418 qemu_get_be32s(f
, &s
->tm4
[i
].oldclock
);
419 qemu_get_be32s(f
, &s
->tm4
[i
].clock
);
420 qemu_get_be64s(f
, &s
->tm4
[i
].lastload
);
421 qemu_get_be32s(f
, &s
->tm4
[i
].freq
);
422 qemu_get_be32s(f
, &s
->tm4
[i
].control
);
423 pxa2xx_timer_update4(s
, now
, i
);
426 qemu_get_be32s(f
, &s
->events
);
427 qemu_get_be32s(f
, &s
->irq_enabled
);
428 qemu_get_be32s(f
, &s
->reset3
);
429 qemu_get_be32s(f
, &s
->snapshot
);
434 static pxa2xx_timer_info
*pxa2xx_timer_init(target_phys_addr_t base
,
439 pxa2xx_timer_info
*s
;
441 s
= (pxa2xx_timer_info
*) qemu_mallocz(sizeof(pxa2xx_timer_info
));
446 s
->lastload
= qemu_get_clock(vm_clock
);
449 for (i
= 0; i
< 4; i
++) {
450 s
->timer
[i
].value
= 0;
451 s
->timer
[i
].irq
= irqs
[i
];
452 s
->timer
[i
].info
= s
;
454 s
->timer
[i
].level
= 0;
455 s
->timer
[i
].qtimer
= qemu_new_timer(vm_clock
,
456 pxa2xx_timer_tick
, &s
->timer
[i
]);
459 iomemtype
= cpu_register_io_memory(0, pxa2xx_timer_readfn
,
460 pxa2xx_timer_writefn
, s
);
461 cpu_register_physical_memory(base
, 0x00000fff, iomemtype
);
463 register_savevm("pxa2xx_timer", 0, 0,
464 pxa2xx_timer_save
, pxa2xx_timer_load
, s
);
469 void pxa25x_timer_init(target_phys_addr_t base
, qemu_irq
*irqs
)
471 pxa2xx_timer_info
*s
= pxa2xx_timer_init(base
, irqs
);
472 s
->freq
= PXA25X_FREQ
;
476 void pxa27x_timer_init(target_phys_addr_t base
,
477 qemu_irq
*irqs
, qemu_irq irq4
)
479 pxa2xx_timer_info
*s
= pxa2xx_timer_init(base
, irqs
);
481 s
->freq
= PXA27X_FREQ
;
482 s
->tm4
= (struct pxa2xx_timer4_s
*) qemu_mallocz(8 *
483 sizeof(struct pxa2xx_timer4_s
));
484 for (i
= 0; i
< 8; i
++) {
485 s
->tm4
[i
].tm
.value
= 0;
486 s
->tm4
[i
].tm
.irq
= irq4
;
487 s
->tm4
[i
].tm
.info
= s
;
488 s
->tm4
[i
].tm
.num
= i
+ 4;
489 s
->tm4
[i
].tm
.level
= 0;
491 s
->tm4
[i
].control
= 0x0;
492 s
->tm4
[i
].tm
.qtimer
= qemu_new_timer(vm_clock
,
493 pxa2xx_timer_tick4
, &s
->tm4
[i
]);