hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19 #include "vl.h"
  20
  21 //#define DEBUG
  22
  23 /* i82731AB (PIIX4) compatible power management function */
  24 #define PM_FREQ 3579545
  25
  26 #define ACPI_DBG_IO_ADDR  0xb044
  27
  28 typedef struct PIIX4PMState {
  29     PCIDevice dev;
  30     uint16_t pmsts;
  31     uint16_t pmen;
  32     uint16_t pmcntrl;
  33     uint8_t apmc;
  34     uint8_t apms;
  35     QEMUTimer *tmr_timer;
  36     int64_t tmr_overflow_time;
  37     i2c_bus *smbus;
  38     uint8_t smb_stat;
  39     uint8_t smb_ctl;
  40     uint8_t smb_cmd;
  41     uint8_t smb_addr;
  42     uint8_t smb_data0;
  43     uint8_t smb_data1;
  44     uint8_t smb_data[32];
  45     uint8_t smb_index;
  46 } PIIX4PMState;
  47
  48 #define RTC_EN (1 << 10)
  49 #define PWRBTN_EN (1 << 8)
  50 #define GBL_EN (1 << 5)
  51 #define TMROF_EN (1 << 0)
  52
  53 #define SCI_EN (1 << 0)
  54
  55 #define SUS_EN (1 << 13)
  56
  57 #define SMBHSTSTS 0x00
  58 #define SMBHSTCNT 0x02
  59 #define SMBHSTCMD 0x03
  60 #define SMBHSTADD 0x04
  61 #define SMBHSTDAT0 0x05
  62 #define SMBHSTDAT1 0x06
  63 #define SMBBLKDAT 0x07
  64
  65 static uint32_t get_pmtmr(PIIX4PMState *s)
  66 {
  67     uint32_t d;
  68     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  69     return d & 0xffffff;
  70 }
  71
  72 static int get_pmsts(PIIX4PMState *s)
  73 {
  74     int64_t d;
  75     int pmsts;
  76     pmsts = s->pmsts;
  77     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  78     if (d >= s->tmr_overflow_time)
  79         s->pmsts |= TMROF_EN;
  80     return pmsts;
  81 }
  82
  83 static void pm_update_sci(PIIX4PMState *s)
  84 {
  85     int sci_level, pmsts;
  86     int64_t expire_time;
  87
  88     pmsts = get_pmsts(s);
  89     sci_level = (((pmsts & s->pmen) &
  90                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
  91     qemu_set_irq(s->dev.irq[0], sci_level);
  92     /* schedule a timer interruption if needed */
  93     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
  94         expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
  95         qemu_mod_timer(s->tmr_timer, expire_time);
  96     } else {
  97         qemu_del_timer(s->tmr_timer);
  98     }
  99 }
 100
 101 static void pm_tmr_timer(void *opaque)
 102 {
 103     PIIX4PMState *s = opaque;
 104     pm_update_sci(s);
 105 }
 106
 107 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 108 {
 109     PIIX4PMState *s = opaque;
 110     addr &= 0x3f;
 111     switch(addr) {
 112     case 0x00:
 113         {
 114             int64_t d;
 115             int pmsts;
 116             pmsts = get_pmsts(s);
 117             if (pmsts & val & TMROF_EN) {
 118                 /* if TMRSTS is reset, then compute the new overflow time */
 119                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
 120                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 121             }
 122             s->pmsts &= ~val;
 123             pm_update_sci(s);
 124         }
 125         break;
 126     case 0x02:
 127         s->pmen = val;
 128         pm_update_sci(s);
 129         break;
 130     case 0x04:
 131         {
 132             int sus_typ;
 133             s->pmcntrl = val & ~(SUS_EN);
 134             if (val & SUS_EN) {
 135                 /* change suspend type */
 136                 sus_typ = (val >> 10) & 3;
 137                 switch(sus_typ) {
 138                 case 0: /* soft power off */
 139                     qemu_system_shutdown_request();
 140                     break;
 141                 default:
 142                     break;
 143                 }
 144             }
 145         }
 146         break;
 147     default:
 148         break;
 149     }
 150 #ifdef DEBUG
 151     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 152 #endif
 153 }
 154
 155 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 156 {
 157     PIIX4PMState *s = opaque;
 158     uint32_t val;
 159
 160     addr &= 0x3f;
 161     switch(addr) {
 162     case 0x00:
 163         val = get_pmsts(s);
 164         break;
 165     case 0x02:
 166         val = s->pmen;
 167         break;
 168     case 0x04:
 169         val = s->pmcntrl;
 170         break;
 171     default:
 172         val = 0;
 173         break;
 174     }
 175 #ifdef DEBUG
 176     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 177 #endif
 178     return val;
 179 }
 180
 181 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 182 {
 183     //    PIIX4PMState *s = opaque;
 184     addr &= 0x3f;
 185 #ifdef DEBUG
 186     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 187 #endif
 188 }
 189
 190 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 191 {
 192     PIIX4PMState *s = opaque;
 193     uint32_t val;
 194
 195     addr &= 0x3f;
 196     switch(addr) {
 197     case 0x08:
 198         val = get_pmtmr(s);
 199         break;
 200     default:
 201         val = 0;
 202         break;
 203     }
 204 #ifdef DEBUG
 205     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 206 #endif
 207     return val;
 208 }
 209
 210 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 211 {
 212     PIIX4PMState *s = opaque;
 213     addr &= 1;
 214 #ifdef DEBUG
 215     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 216 #endif
 217     if (addr == 0) {
 218         s->apmc = val;
 219         if (s->dev.config[0x5b] & (1 << 1)) {
 220             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 221         }
 222     } else {
 223         s->apms = val;
 224     }
 225 }
 226
 227 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 228 {
 229     PIIX4PMState *s = opaque;
 230     uint32_t val;
 231
 232     addr &= 1;
 233     if (addr == 0) {
 234         val = s->apmc;
 235     } else {
 236         val = s->apms;
 237     }
 238 #ifdef DEBUG
 239     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 240 #endif
 241     return val;
 242 }
 243
 244 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 245 {
 246 #if defined(DEBUG)
 247     printf("ACPI: DBG: 0x%08x\n", val);
 248 #endif
 249 }
 250
 251 static void smb_transaction(PIIX4PMState *s)
 252 {
 253     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 254     uint8_t read = s->smb_addr & 0x01;
 255     uint8_t cmd = s->smb_cmd;
 256     uint8_t addr = s->smb_addr >> 1;
 257     i2c_bus *bus = s->smbus;
 258
 259 #ifdef DEBUG
 260     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 261 #endif
 262     switch(prot) {
 263     case 0x0:
 264         smbus_quick_command(bus, addr, read);
 265         break;
 266     case 0x1:
 267         if (read) {
 268             s->smb_data0 = smbus_receive_byte(bus, addr);
 269         } else {
 270             smbus_send_byte(bus, addr, cmd);
 271         }
 272         break;
 273     case 0x2:
 274         if (read) {
 275             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 276         } else {
 277             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 278         }
 279         break;
 280     case 0x3:
 281         if (read) {
 282             uint16_t val;
 283             val = smbus_read_word(bus, addr, cmd);
 284             s->smb_data0 = val;
 285             s->smb_data1 = val >> 8;
 286         } else {
 287             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 288         }
 289         break;
 290     case 0x5:
 291         if (read) {
 292             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 293         } else {
 294             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 295         }
 296         break;
 297     default:
 298         goto error;
 299     }
 300     return;
 301
 302   error:
 303     s->smb_stat |= 0x04;
 304 }
 305
 306 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 307 {
 308     PIIX4PMState *s = opaque;
 309     addr &= 0x3f;
 310 #ifdef DEBUG
 311     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 312 #endif
 313     switch(addr) {
 314     case SMBHSTSTS:
 315         s->smb_stat = 0;
 316         s->smb_index = 0;
 317         break;
 318     case SMBHSTCNT:
 319         s->smb_ctl = val;
 320         if (val & 0x40)
 321             smb_transaction(s);
 322         break;
 323     case SMBHSTCMD:
 324         s->smb_cmd = val;
 325         break;
 326     case SMBHSTADD:
 327         s->smb_addr = val;
 328         break;
 329     case SMBHSTDAT0:
 330         s->smb_data0 = val;
 331         break;
 332     case SMBHSTDAT1:
 333         s->smb_data1 = val;
 334         break;
 335     case SMBBLKDAT:
 336         s->smb_data[s->smb_index++] = val;
 337         if (s->smb_index > 31)
 338             s->smb_index = 0;
 339         break;
 340     default:
 341         break;
 342     }
 343 }
 344
 345 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 346 {
 347     PIIX4PMState *s = opaque;
 348     uint32_t val;
 349
 350     addr &= 0x3f;
 351     switch(addr) {
 352     case SMBHSTSTS:
 353         val = s->smb_stat;
 354         break;
 355     case SMBHSTCNT:
 356         s->smb_index = 0;
 357         val = s->smb_ctl & 0x1f;
 358         break;
 359     case SMBHSTCMD:
 360         val = s->smb_cmd;
 361         break;
 362     case SMBHSTADD:
 363         val = s->smb_addr;
 364         break;
 365     case SMBHSTDAT0:
 366         val = s->smb_data0;
 367         break;
 368     case SMBHSTDAT1:
 369         val = s->smb_data1;
 370         break;
 371     case SMBBLKDAT:
 372         val = s->smb_data[s->smb_index++];
 373         if (s->smb_index > 31)
 374             s->smb_index = 0;
 375         break;
 376     default:
 377         val = 0;
 378         break;
 379     }
 380 #ifdef DEBUG
 381     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 382 #endif
 383     return val;
 384 }
 385
 386 static void pm_io_space_update(PIIX4PMState *s)
 387 {
 388     uint32_t pm_io_base;
 389
 390     if (s->dev.config[0x80] & 1) {
 391         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 392         pm_io_base &= 0xfffe;
 393
 394         /* XXX: need to improve memory and ioport allocation */
 395 #if defined(DEBUG)
 396         printf("PM: mapping to 0x%x\n", pm_io_base);
 397 #endif
 398         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 399         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 400         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 401         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 402     }
 403 }
 404
 405 static void pm_write_config(PCIDevice *d,
 406                             uint32_t address, uint32_t val, int len)
 407 {
 408     pci_default_write_config(d, address, val, len);
 409     if (address == 0x80)
 410         pm_io_space_update((PIIX4PMState *)d);
 411 }
 412
 413 static void pm_save(QEMUFile* f,void *opaque)
 414 {
 415     PIIX4PMState *s = opaque;
 416
 417     pci_device_save(&s->dev, f);
 418
 419     qemu_put_be16s(f, &s->pmsts);
 420     qemu_put_be16s(f, &s->pmen);
 421     qemu_put_be16s(f, &s->pmcntrl);
 422     qemu_put_8s(f, &s->apmc);
 423     qemu_put_8s(f, &s->apms);
 424     qemu_put_timer(f, s->tmr_timer);
 425     qemu_put_be64s(f, &s->tmr_overflow_time);
 426 }
 427
 428 static int pm_load(QEMUFile* f,void* opaque,int version_id)
 429 {
 430     PIIX4PMState *s = opaque;
 431     int ret;
 432
 433     if (version_id > 1)
 434         return -EINVAL;
 435
 436     ret = pci_device_load(&s->dev, f);
 437     if (ret < 0)
 438         return ret;
 439
 440     qemu_get_be16s(f, &s->pmsts);
 441     qemu_get_be16s(f, &s->pmen);
 442     qemu_get_be16s(f, &s->pmcntrl);
 443     qemu_get_8s(f, &s->apmc);
 444     qemu_get_8s(f, &s->apms);
 445     qemu_get_timer(f, s->tmr_timer);
 446     qemu_get_be64s(f, &s->tmr_overflow_time);
 447
 448     pm_io_space_update(s);
 449
 450     return 0;
 451 }
 452
 453 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
 454 {
 455     PIIX4PMState *s;
 456     uint8_t *pci_conf;
 457
 458     s = (PIIX4PMState *)pci_register_device(bus,
 459                                          "PM", sizeof(PIIX4PMState),
 460                                          devfn, NULL, pm_write_config);
 461     pci_conf = s->dev.config;
 462     pci_conf[0x00] = 0x86;
 463     pci_conf[0x01] = 0x80;
 464     pci_conf[0x02] = 0x13;
 465     pci_conf[0x03] = 0x71;
 466     pci_conf[0x08] = 0x00; // revision number
 467     pci_conf[0x09] = 0x00;
 468     pci_conf[0x0a] = 0x80; // other bridge device
 469     pci_conf[0x0b] = 0x06; // bridge device
 470     pci_conf[0x0e] = 0x00; // header_type
 471     pci_conf[0x3d] = 0x01; // interrupt pin 1
 472
 473     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 474
 475     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 476     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 477
 478     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 479
 480     /* XXX: which specification is used ? The i82731AB has different
 481        mappings */
 482     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 483     pci_conf[0x63] = 0x60;
 484     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 485         (serial_hds[1] != NULL ? 0x90 : 0);
 486
 487     pci_conf[0x90] = smb_io_base | 1;
 488     pci_conf[0x91] = smb_io_base >> 8;
 489     pci_conf[0xd2] = 0x09;
 490     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 491     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 492
 493     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 494
 495     register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
 496
 497     s->smbus = i2c_init_bus();
 498     return s->smbus;
 499 }