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ARM946 CPU support.
[qemu/mini2440.git] / hw / pxa2xx.c
blob9f4c46c68396ef7fcadd13c2456f8fc466e2cf8a
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licenced under the GPL.
8 */
9
10 # include "vl.h"
11
12 static struct {
13 target_phys_addr_t io_base;
14 int irqn;
15 } pxa255_serial[] = {
16 { 0x40100000, PXA2XX_PIC_FFUART },
17 { 0x40200000, PXA2XX_PIC_BTUART },
18 { 0x40700000, PXA2XX_PIC_STUART },
19 { 0x41600000, PXA25X_PIC_HWUART },
20 { 0, 0 }
21 }, pxa270_serial[] = {
22 { 0x40100000, PXA2XX_PIC_FFUART },
23 { 0x40200000, PXA2XX_PIC_BTUART },
24 { 0x40700000, PXA2XX_PIC_STUART },
25 { 0, 0 }
26 };
27
28 static struct {
29 target_phys_addr_t io_base;
30 int irqn;
31 } pxa250_ssp[] = {
32 { 0x41000000, PXA2XX_PIC_SSP },
33 { 0, 0 }
34 }, pxa255_ssp[] = {
35 { 0x41000000, PXA2XX_PIC_SSP },
36 { 0x41400000, PXA25X_PIC_NSSP },
37 { 0, 0 }
38 }, pxa26x_ssp[] = {
39 { 0x41000000, PXA2XX_PIC_SSP },
40 { 0x41400000, PXA25X_PIC_NSSP },
41 { 0x41500000, PXA26X_PIC_ASSP },
42 { 0, 0 }
43 }, pxa27x_ssp[] = {
44 { 0x41000000, PXA2XX_PIC_SSP },
45 { 0x41700000, PXA27X_PIC_SSP2 },
46 { 0x41900000, PXA2XX_PIC_SSP3 },
47 { 0, 0 }
48 };
49
50 #define PMCR 0x00 /* Power Manager Control register */
51 #define PSSR 0x04 /* Power Manager Sleep Status register */
52 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
53 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
54 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
55 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
56 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
57 #define PCFR 0x1c /* Power Manager General Configuration register */
58 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
59 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
60 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
61 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
62 #define RCSR 0x30 /* Reset Controller Status register */
63 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
64 #define PTSR 0x38 /* Power Manager Standby Configuration register */
65 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
66 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
67 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
68 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
69 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
70 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
71
72 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
73 {
74 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
75 addr -= s->pm_base;
76
77 switch (addr) {
78 case PMCR ... PCMD31:
79 if (addr & 3)
80 goto fail;
81
82 return s->pm_regs[addr >> 2];
83 default:
84 fail:
85 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
86 break;
87 }
88 return 0;
89 }
90
91 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
92 uint32_t value)
93 {
94 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
95 addr -= s->pm_base;
96
97 switch (addr) {
98 case PMCR:
99 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
100 s->pm_regs[addr >> 2] |= value & 0x15;
101 break;
102
103 case PSSR: /* Read-clean registers */
104 case RCSR:
105 case PKSR:
106 s->pm_regs[addr >> 2] &= ~value;
107 break;
108
109 default: /* Read-write registers */
110 if (addr >= PMCR && addr <= PCMD31 && !(addr & 3)) {
111 s->pm_regs[addr >> 2] = value;
112 break;
113 }
114
115 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
116 break;
117 }
118 }
119
120 static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
121 pxa2xx_pm_read,
122 pxa2xx_pm_read,
123 pxa2xx_pm_read,
124 };
125
126 static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
127 pxa2xx_pm_write,
128 pxa2xx_pm_write,
129 pxa2xx_pm_write,
130 };
131
132 #define CCCR 0x00 /* Core Clock Configuration register */
133 #define CKEN 0x04 /* Clock Enable register */
134 #define OSCC 0x08 /* Oscillator Configuration register */
135 #define CCSR 0x0c /* Core Clock Status register */
136
137 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
138 {
139 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
140 addr -= s->cm_base;
141
142 switch (addr) {
143 case CCCR:
144 case CKEN:
145 case OSCC:
146 return s->cm_regs[addr >> 2];
147
148 case CCSR:
149 return s->cm_regs[CCCR >> 2] | (3 << 28);
150
151 default:
152 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
153 break;
154 }
155 return 0;
156 }
157
158 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
159 uint32_t value)
160 {
161 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
162 addr -= s->cm_base;
163
164 switch (addr) {
165 case CCCR:
166 case CKEN:
167 s->cm_regs[addr >> 2] = value;
168 break;
169
170 case OSCC:
171 s->cm_regs[addr >> 2] &= ~0x6e;
172 s->cm_regs[addr >> 2] |= value & 0x6e;
173 break;
174
175 default:
176 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
177 break;
178 }
179 }
180
181 static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
182 pxa2xx_cm_read,
183 pxa2xx_cm_read,
184 pxa2xx_cm_read,
185 };
186
187 static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
188 pxa2xx_cm_write,
189 pxa2xx_cm_write,
190 pxa2xx_cm_write,
191 };
192
193 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
194 {
195 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
196
197 switch (reg) {
198 case 6: /* Clock Configuration register */
199 return s->clkcfg;
200
201 case 7: /* Power Mode register */
202 return 0;
203
204 default:
205 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
206 break;
207 }
208 return 0;
209 }
210
211 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
212 uint32_t value)
213 {
214 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
215 static const char *pwrmode[8] = {
216 "Normal", "Idle", "Deep-idle", "Standby",
217 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
218 };
219
220 switch (reg) {
221 case 6: /* Clock Configuration register */
222 s->clkcfg = value & 0xf;
223 if (value & 2)
224 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
225 break;
226
227 case 7: /* Power Mode register */
228 if (value & 8)
229 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
230 switch (value & 7) {
231 case 0:
232 /* Do nothing */
233 break;
234
235 case 1:
236 /* Idle */
237 if (!(s->cm_regs[CCCR] & (1 << 31))) { /* CPDIS */
238 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
239 break;
240 }
241 /* Fall through. */
242
243 case 2:
244 /* Deep-Idle */
245 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
246 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
247 goto message;
248
249 case 3:
250 s->env->uncached_cpsr =
251 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
252 s->env->cp15.c1_sys = 0;
253 s->env->cp15.c1_coproc = 0;
254 s->env->cp15.c2_base = 0;
255 s->env->cp15.c3 = 0;
256 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
257 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
258
259 /*
260 * The scratch-pad register is almost universally used
261 * for storing the return address on suspend. For the
262 * lack of a resuming bootloader, perform a jump
263 * directly to that address.
264 */
265 memset(s->env->regs, 0, 4 * 15);
266 s->env->regs[15] = s->pm_regs[PSPR >> 2];
267
268 #if 0
269 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
270 cpu_physical_memory_write(0, &buffer, 4);
271 buffer = s->pm_regs[PSPR >> 2];
272 cpu_physical_memory_write(8, &buffer, 4);
273 #endif
274
275 /* Suspend */
276 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
277
278 goto message;
279
280 default:
281 message:
282 printf("%s: machine entered %s mode\n", __FUNCTION__,
283 pwrmode[value & 7]);
284 }
285 break;
286
287 default:
288 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
289 break;
290 }
291 }
292
293 /* Performace Monitoring Registers */
294 #define CPPMNC 0 /* Performance Monitor Control register */
295 #define CPCCNT 1 /* Clock Counter register */
296 #define CPINTEN 4 /* Interrupt Enable register */
297 #define CPFLAG 5 /* Overflow Flag register */
298 #define CPEVTSEL 8 /* Event Selection register */
299
300 #define CPPMN0 0 /* Performance Count register 0 */
301 #define CPPMN1 1 /* Performance Count register 1 */
302 #define CPPMN2 2 /* Performance Count register 2 */
303 #define CPPMN3 3 /* Performance Count register 3 */
304
305 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
306 {
307 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
308
309 switch (reg) {
310 case CPPMNC:
311 return s->pmnc;
312 case CPCCNT:
313 if (s->pmnc & 1)
314 return qemu_get_clock(vm_clock);
315 else
316 return 0;
317 case CPINTEN:
318 case CPFLAG:
319 case CPEVTSEL:
320 return 0;
321
322 default:
323 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
324 break;
325 }
326 return 0;
327 }
328
329 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
330 uint32_t value)
331 {
332 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
333
334 switch (reg) {
335 case CPPMNC:
336 s->pmnc = value;
337 break;
338
339 case CPCCNT:
340 case CPINTEN:
341 case CPFLAG:
342 case CPEVTSEL:
343 break;
344
345 default:
346 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
347 break;
348 }
349 }
350
351 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
352 {
353 switch (crm) {
354 case 0:
355 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
356 case 1:
357 return pxa2xx_perf_read(opaque, op2, reg, crm);
358 case 2:
359 switch (reg) {
360 case CPPMN0:
361 case CPPMN1:
362 case CPPMN2:
363 case CPPMN3:
364 return 0;
365 }
366 /* Fall through */
367 default:
368 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
369 break;
370 }
371 return 0;
372 }
373
374 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
375 uint32_t value)
376 {
377 switch (crm) {
378 case 0:
379 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
380 break;
381 case 1:
382 pxa2xx_perf_write(opaque, op2, reg, crm, value);
383 break;
384 case 2:
385 switch (reg) {
386 case CPPMN0:
387 case CPPMN1:
388 case CPPMN2:
389 case CPPMN3:
390 return;
391 }
392 /* Fall through */
393 default:
394 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
395 break;
396 }
397 }
398
399 #define MDCNFG 0x00 /* SDRAM Configuration register */
400 #define MDREFR 0x04 /* SDRAM Refresh Control register */
401 #define MSC0 0x08 /* Static Memory Control register 0 */
402 #define MSC1 0x0c /* Static Memory Control register 1 */
403 #define MSC2 0x10 /* Static Memory Control register 2 */
404 #define MECR 0x14 /* Expansion Memory Bus Config register */
405 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
406 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
407 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
408 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
409 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
410 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
411 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
412 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
413 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
414 #define ARB_CNTL 0x48 /* Arbiter Control register */
415 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
416 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
417 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
418 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
419 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
420 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
421 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
422
423 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
424 {
425 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
426 addr -= s->mm_base;
427
428 switch (addr) {
429 case MDCNFG ... SA1110:
430 if ((addr & 3) == 0)
431 return s->mm_regs[addr >> 2];
432
433 default:
434 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
435 break;
436 }
437 return 0;
438 }
439
440 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
441 uint32_t value)
442 {
443 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
444 addr -= s->mm_base;
445
446 switch (addr) {
447 case MDCNFG ... SA1110:
448 if ((addr & 3) == 0) {
449 s->mm_regs[addr >> 2] = value;
450 break;
451 }
452
453 default:
454 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
455 break;
456 }
457 }
458
459 static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
460 pxa2xx_mm_read,
461 pxa2xx_mm_read,
462 pxa2xx_mm_read,
463 };
464
465 static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
466 pxa2xx_mm_write,
467 pxa2xx_mm_write,
468 pxa2xx_mm_write,
469 };
470
471 /* Synchronous Serial Ports */
472 struct pxa2xx_ssp_s {
473 target_phys_addr_t base;
474 qemu_irq irq;
475 int enable;
476
477 uint32_t sscr[2];
478 uint32_t sspsp;
479 uint32_t ssto;
480 uint32_t ssitr;
481 uint32_t sssr;
482 uint8_t sstsa;
483 uint8_t ssrsa;
484 uint8_t ssacd;
485
486 uint32_t rx_fifo[16];
487 int rx_level;
488 int rx_start;
489
490 uint32_t (*readfn)(void *opaque);
491 void (*writefn)(void *opaque, uint32_t value);
492 void *opaque;
493 };
494
495 #define SSCR0 0x00 /* SSP Control register 0 */
496 #define SSCR1 0x04 /* SSP Control register 1 */
497 #define SSSR 0x08 /* SSP Status register */
498 #define SSITR 0x0c /* SSP Interrupt Test register */
499 #define SSDR 0x10 /* SSP Data register */
500 #define SSTO 0x28 /* SSP Time-Out register */
501 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
502 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
503 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
504 #define SSTSS 0x38 /* SSP Time Slot Status register */
505 #define SSACD 0x3c /* SSP Audio Clock Divider register */
506
507 /* Bitfields for above registers */
508 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
509 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
510 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
511 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
512 #define SSCR0_SSE (1 << 7)
513 #define SSCR0_RIM (1 << 22)
514 #define SSCR0_TIM (1 << 23)
515 #define SSCR0_MOD (1 << 31)
516 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
517 #define SSCR1_RIE (1 << 0)
518 #define SSCR1_TIE (1 << 1)
519 #define SSCR1_LBM (1 << 2)
520 #define SSCR1_MWDS (1 << 5)
521 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
522 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
523 #define SSCR1_EFWR (1 << 14)
524 #define SSCR1_PINTE (1 << 18)
525 #define SSCR1_TINTE (1 << 19)
526 #define SSCR1_RSRE (1 << 20)
527 #define SSCR1_TSRE (1 << 21)
528 #define SSCR1_EBCEI (1 << 29)
529 #define SSITR_INT (7 << 5)
530 #define SSSR_TNF (1 << 2)
531 #define SSSR_RNE (1 << 3)
532 #define SSSR_TFS (1 << 5)
533 #define SSSR_RFS (1 << 6)
534 #define SSSR_ROR (1 << 7)
535 #define SSSR_PINT (1 << 18)
536 #define SSSR_TINT (1 << 19)
537 #define SSSR_EOC (1 << 20)
538 #define SSSR_TUR (1 << 21)
539 #define SSSR_BCE (1 << 23)
540 #define SSSR_RW 0x00bc0080
541
542 static void pxa2xx_ssp_int_update(struct pxa2xx_ssp_s *s)
543 {
544 int level = 0;
545
546 level |= s->ssitr & SSITR_INT;
547 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
548 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
549 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
550 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
551 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
552 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
553 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
554 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
555 qemu_set_irq(s->irq, !!level);
556 }
557
558 static void pxa2xx_ssp_fifo_update(struct pxa2xx_ssp_s *s)
559 {
560 s->sssr &= ~(0xf << 12); /* Clear RFL */
561 s->sssr &= ~(0xf << 8); /* Clear TFL */
562 s->sssr &= ~SSSR_TNF;
563 if (s->enable) {
564 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
565 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
566 s->sssr |= SSSR_RFS;
567 else
568 s->sssr &= ~SSSR_RFS;
569 if (0 <= SSCR1_TFT(s->sscr[1]))
570 s->sssr |= SSSR_TFS;
571 else
572 s->sssr &= ~SSSR_TFS;
573 if (s->rx_level)
574 s->sssr |= SSSR_RNE;
575 else
576 s->sssr &= ~SSSR_RNE;
577 s->sssr |= SSSR_TNF;
578 }
579
580 pxa2xx_ssp_int_update(s);
581 }
582
583 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
584 {
585 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
586 uint32_t retval;
587 addr -= s->base;
588
589 switch (addr) {
590 case SSCR0:
591 return s->sscr[0];
592 case SSCR1:
593 return s->sscr[1];
594 case SSPSP:
595 return s->sspsp;
596 case SSTO:
597 return s->ssto;
598 case SSITR:
599 return s->ssitr;
600 case SSSR:
601 return s->sssr | s->ssitr;
602 case SSDR:
603 if (!s->enable)
604 return 0xffffffff;
605 if (s->rx_level < 1) {
606 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
607 return 0xffffffff;
608 }
609 s->rx_level --;
610 retval = s->rx_fifo[s->rx_start ++];
611 s->rx_start &= 0xf;
612 pxa2xx_ssp_fifo_update(s);
613 return retval;
614 case SSTSA:
615 return s->sstsa;
616 case SSRSA:
617 return s->ssrsa;
618 case SSTSS:
619 return 0;
620 case SSACD:
621 return s->ssacd;
622 default:
623 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
624 break;
625 }
626 return 0;
627 }
628
629 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
630 uint32_t value)
631 {
632 struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
633 addr -= s->base;
634
635 switch (addr) {
636 case SSCR0:
637 s->sscr[0] = value & 0xc7ffffff;
638 s->enable = value & SSCR0_SSE;
639 if (value & SSCR0_MOD)
640 printf("%s: Attempt to use network mode\n", __FUNCTION__);
641 if (s->enable && SSCR0_DSS(value) < 4)
642 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
643 SSCR0_DSS(value));
644 if (!(value & SSCR0_SSE)) {
645 s->sssr = 0;
646 s->ssitr = 0;
647 s->rx_level = 0;
648 }
649 pxa2xx_ssp_fifo_update(s);
650 break;
651
652 case SSCR1:
653 s->sscr[1] = value;
654 if (value & (SSCR1_LBM | SSCR1_EFWR))
655 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
656 pxa2xx_ssp_fifo_update(s);
657 break;
658
659 case SSPSP:
660 s->sspsp = value;
661 break;
662
663 case SSTO:
664 s->ssto = value;
665 break;
666
667 case SSITR:
668 s->ssitr = value & SSITR_INT;
669 pxa2xx_ssp_int_update(s);
670 break;
671
672 case SSSR:
673 s->sssr &= ~(value & SSSR_RW);
674 pxa2xx_ssp_int_update(s);
675 break;
676
677 case SSDR:
678 if (SSCR0_UWIRE(s->sscr[0])) {
679 if (s->sscr[1] & SSCR1_MWDS)
680 value &= 0xffff;
681 else
682 value &= 0xff;
683 } else
684 /* Note how 32bits overflow does no harm here */
685 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
686
687 /* Data goes from here to the Tx FIFO and is shifted out from
688 * there directly to the slave, no need to buffer it.
689 */
690 if (s->enable) {
691 if (s->writefn)
692 s->writefn(s->opaque, value);
693
694 if (s->rx_level < 0x10) {
695 if (s->readfn)
696 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] =
697 s->readfn(s->opaque);
698 else
699 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = 0x0;
700 } else
701 s->sssr |= SSSR_ROR;
702 }
703 pxa2xx_ssp_fifo_update(s);
704 break;
705
706 case SSTSA:
707 s->sstsa = value;
708 break;
709
710 case SSRSA:
711 s->ssrsa = value;
712 break;
713
714 case SSACD:
715 s->ssacd = value;
716 break;
717
718 default:
719 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
720 break;
721 }
722 }
723
724 void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
725 uint32_t (*readfn)(void *opaque),
726 void (*writefn)(void *opaque, uint32_t value), void *opaque)
727 {
728 if (!port) {
729 printf("%s: no such SSP\n", __FUNCTION__);
730 exit(-1);
731 }
732
733 port->opaque = opaque;
734 port->readfn = readfn;
735 port->writefn = writefn;
736 }
737
738 static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
739 pxa2xx_ssp_read,
740 pxa2xx_ssp_read,
741 pxa2xx_ssp_read,
742 };
743
744 static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
745 pxa2xx_ssp_write,
746 pxa2xx_ssp_write,
747 pxa2xx_ssp_write,
748 };
749
750 /* Real-Time Clock */
751 #define RCNR 0x00 /* RTC Counter register */
752 #define RTAR 0x04 /* RTC Alarm register */
753 #define RTSR 0x08 /* RTC Status register */
754 #define RTTR 0x0c /* RTC Timer Trim register */
755 #define RDCR 0x10 /* RTC Day Counter register */
756 #define RYCR 0x14 /* RTC Year Counter register */
757 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
758 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
759 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
760 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
761 #define SWCR 0x28 /* RTC Stopwatch Counter register */
762 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
763 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
764 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
765 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
766
767 static inline void pxa2xx_rtc_int_update(struct pxa2xx_state_s *s)
768 {
769 qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
770 }
771
772 static void pxa2xx_rtc_hzupdate(struct pxa2xx_state_s *s)
773 {
774 int64_t rt = qemu_get_clock(rt_clock);
775 s->last_rcnr += ((rt - s->last_hz) << 15) /
776 (1000 * ((s->rttr & 0xffff) + 1));
777 s->last_rdcr += ((rt - s->last_hz) << 15) /
778 (1000 * ((s->rttr & 0xffff) + 1));
779 s->last_hz = rt;
780 }
781
782 static void pxa2xx_rtc_swupdate(struct pxa2xx_state_s *s)
783 {
784 int64_t rt = qemu_get_clock(rt_clock);
785 if (s->rtsr & (1 << 12))
786 s->last_swcr += (rt - s->last_sw) / 10;
787 s->last_sw = rt;
788 }
789
790 static void pxa2xx_rtc_piupdate(struct pxa2xx_state_s *s)
791 {
792 int64_t rt = qemu_get_clock(rt_clock);
793 if (s->rtsr & (1 << 15))
794 s->last_swcr += rt - s->last_pi;
795 s->last_pi = rt;
796 }
797
798 static inline void pxa2xx_rtc_alarm_update(struct pxa2xx_state_s *s,
799 uint32_t rtsr)
800 {
801 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
802 qemu_mod_timer(s->rtc_hz, s->last_hz +
803 (((s->rtar - s->last_rcnr) * 1000 *
804 ((s->rttr & 0xffff) + 1)) >> 15));
805 else
806 qemu_del_timer(s->rtc_hz);
807
808 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
809 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
810 (((s->rdar1 - s->last_rdcr) * 1000 *
811 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
812 else
813 qemu_del_timer(s->rtc_rdal1);
814
815 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
816 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
817 (((s->rdar2 - s->last_rdcr) * 1000 *
818 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
819 else
820 qemu_del_timer(s->rtc_rdal2);
821
822 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
823 qemu_mod_timer(s->rtc_swal1, s->last_sw +
824 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
825 else
826 qemu_del_timer(s->rtc_swal1);
827
828 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
829 qemu_mod_timer(s->rtc_swal2, s->last_sw +
830 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
831 else
832 qemu_del_timer(s->rtc_swal2);
833
834 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
835 qemu_mod_timer(s->rtc_pi, s->last_pi +
836 (s->piar & 0xffff) - s->last_rtcpicr);
837 else
838 qemu_del_timer(s->rtc_pi);
839 }
840
841 static inline void pxa2xx_rtc_hz_tick(void *opaque)
842 {
843 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
844 s->rtsr |= (1 << 0);
845 pxa2xx_rtc_alarm_update(s, s->rtsr);
846 pxa2xx_rtc_int_update(s);
847 }
848
849 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
850 {
851 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
852 s->rtsr |= (1 << 4);
853 pxa2xx_rtc_alarm_update(s, s->rtsr);
854 pxa2xx_rtc_int_update(s);
855 }
856
857 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
858 {
859 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
860 s->rtsr |= (1 << 6);
861 pxa2xx_rtc_alarm_update(s, s->rtsr);
862 pxa2xx_rtc_int_update(s);
863 }
864
865 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
866 {
867 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
868 s->rtsr |= (1 << 8);
869 pxa2xx_rtc_alarm_update(s, s->rtsr);
870 pxa2xx_rtc_int_update(s);
871 }
872
873 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
874 {
875 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
876 s->rtsr |= (1 << 10);
877 pxa2xx_rtc_alarm_update(s, s->rtsr);
878 pxa2xx_rtc_int_update(s);
879 }
880
881 static inline void pxa2xx_rtc_pi_tick(void *opaque)
882 {
883 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
884 s->rtsr |= (1 << 13);
885 pxa2xx_rtc_piupdate(s);
886 s->last_rtcpicr = 0;
887 pxa2xx_rtc_alarm_update(s, s->rtsr);
888 pxa2xx_rtc_int_update(s);
889 }
890
891 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
892 {
893 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
894 addr -= s->rtc_base;
895
896 switch (addr) {
897 case RTTR:
898 return s->rttr;
899 case RTSR:
900 return s->rtsr;
901 case RTAR:
902 return s->rtar;
903 case RDAR1:
904 return s->rdar1;
905 case RDAR2:
906 return s->rdar2;
907 case RYAR1:
908 return s->ryar1;
909 case RYAR2:
910 return s->ryar2;
911 case SWAR1:
912 return s->swar1;
913 case SWAR2:
914 return s->swar2;
915 case PIAR:
916 return s->piar;
917 case RCNR:
918 return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
919 (1000 * ((s->rttr & 0xffff) + 1));
920 case RDCR:
921 return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
922 (1000 * ((s->rttr & 0xffff) + 1));
923 case RYCR:
924 return s->last_rycr;
925 case SWCR:
926 if (s->rtsr & (1 << 12))
927 return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
928 else
929 return s->last_swcr;
930 default:
931 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
932 break;
933 }
934 return 0;
935 }
936
937 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
938 uint32_t value)
939 {
940 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
941 addr -= s->rtc_base;
942
943 switch (addr) {
944 case RTTR:
945 if (!(s->rttr & (1 << 31))) {
946 pxa2xx_rtc_hzupdate(s);
947 s->rttr = value;
948 pxa2xx_rtc_alarm_update(s, s->rtsr);
949 }
950 break;
951
952 case RTSR:
953 if ((s->rtsr ^ value) & (1 << 15))
954 pxa2xx_rtc_piupdate(s);
955
956 if ((s->rtsr ^ value) & (1 << 12))
957 pxa2xx_rtc_swupdate(s);
958
959 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
960 pxa2xx_rtc_alarm_update(s, value);
961
962 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
963 pxa2xx_rtc_int_update(s);
964 break;
965
966 case RTAR:
967 s->rtar = value;
968 pxa2xx_rtc_alarm_update(s, s->rtsr);
969 break;
970
971 case RDAR1:
972 s->rdar1 = value;
973 pxa2xx_rtc_alarm_update(s, s->rtsr);
974 break;
975
976 case RDAR2:
977 s->rdar2 = value;
978 pxa2xx_rtc_alarm_update(s, s->rtsr);
979 break;
980
981 case RYAR1:
982 s->ryar1 = value;
983 pxa2xx_rtc_alarm_update(s, s->rtsr);
984 break;
985
986 case RYAR2:
987 s->ryar2 = value;
988 pxa2xx_rtc_alarm_update(s, s->rtsr);
989 break;
990
991 case SWAR1:
992 pxa2xx_rtc_swupdate(s);
993 s->swar1 = value;
994 s->last_swcr = 0;
995 pxa2xx_rtc_alarm_update(s, s->rtsr);
996 break;
997
998 case SWAR2:
999 s->swar2 = value;
1000 pxa2xx_rtc_alarm_update(s, s->rtsr);
1001 break;
1002
1003 case PIAR:
1004 s->piar = value;
1005 pxa2xx_rtc_alarm_update(s, s->rtsr);
1006 break;
1007
1008 case RCNR:
1009 pxa2xx_rtc_hzupdate(s);
1010 s->last_rcnr = value;
1011 pxa2xx_rtc_alarm_update(s, s->rtsr);
1012 break;
1013
1014 case RDCR:
1015 pxa2xx_rtc_hzupdate(s);
1016 s->last_rdcr = value;
1017 pxa2xx_rtc_alarm_update(s, s->rtsr);
1018 break;
1019
1020 case RYCR:
1021 s->last_rycr = value;
1022 break;
1023
1024 case SWCR:
1025 pxa2xx_rtc_swupdate(s);
1026 s->last_swcr = value;
1027 pxa2xx_rtc_alarm_update(s, s->rtsr);
1028 break;
1029
1030 case RTCPICR:
1031 pxa2xx_rtc_piupdate(s);
1032 s->last_rtcpicr = value & 0xffff;
1033 pxa2xx_rtc_alarm_update(s, s->rtsr);
1034 break;
1035
1036 default:
1037 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1038 }
1039 }
1040
1041 static void pxa2xx_rtc_reset(struct pxa2xx_state_s *s)
1042 {
1043 struct tm *tm;
1044 time_t ti;
1045 int wom;
1046
1047 s->rttr = 0x7fff;
1048 s->rtsr = 0;
1049
1050 time(&ti);
1051 if (rtc_utc)
1052 tm = gmtime(&ti);
1053 else
1054 tm = localtime(&ti);
1055 wom = ((tm->tm_mday - 1) / 7) + 1;
1056
1057 s->last_rcnr = (uint32_t) ti;
1058 s->last_rdcr = (wom << 20) | ((tm->tm_wday + 1) << 17) |
1059 (tm->tm_hour << 12) | (tm->tm_min << 6) | tm->tm_sec;
1060 s->last_rycr = ((tm->tm_year + 1900) << 9) |
1061 ((tm->tm_mon + 1) << 5) | tm->tm_mday;
1062 s->last_swcr = (tm->tm_hour << 19) |
1063 (tm->tm_min << 13) | (tm->tm_sec << 7);
1064 s->last_rtcpicr = 0;
1065 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1066
1067 s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1068 s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1069 s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1070 s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1071 s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1072 s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1073 }
1074
1075 static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
1076 pxa2xx_rtc_read,
1077 pxa2xx_rtc_read,
1078 pxa2xx_rtc_read,
1079 };
1080
1081 static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
1082 pxa2xx_rtc_write,
1083 pxa2xx_rtc_write,
1084 pxa2xx_rtc_write,
1085 };
1086
1087 /* PXA Inter-IC Sound Controller */
1088 static void pxa2xx_i2s_reset(struct pxa2xx_i2s_s *i2s)
1089 {
1090 i2s->rx_len = 0;
1091 i2s->tx_len = 0;
1092 i2s->fifo_len = 0;
1093 i2s->clk = 0x1a;
1094 i2s->control[0] = 0x00;
1095 i2s->control[1] = 0x00;
1096 i2s->status = 0x00;
1097 i2s->mask = 0x00;
1098 }
1099
1100 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1101 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1102 #define SACR_DREC(val) (val & (1 << 3))
1103 #define SACR_DPRL(val) (val & (1 << 4))
1104
1105 static inline void pxa2xx_i2s_update(struct pxa2xx_i2s_s *i2s)
1106 {
1107 int rfs, tfs;
1108 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1109 !SACR_DREC(i2s->control[1]);
1110 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1111 i2s->enable && !SACR_DPRL(i2s->control[1]);
1112
1113 pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1114 pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1115
1116 i2s->status &= 0xe0;
1117 if (i2s->rx_len)
1118 i2s->status |= 1 << 1; /* RNE */
1119 if (i2s->enable)
1120 i2s->status |= 1 << 2; /* BSY */
1121 if (tfs)
1122 i2s->status |= 1 << 3; /* TFS */
1123 if (rfs)
1124 i2s->status |= 1 << 4; /* RFS */
1125 if (!(i2s->tx_len && i2s->enable))
1126 i2s->status |= i2s->fifo_len << 8; /* TFL */
1127 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1128
1129 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1130 }
1131
1132 #define SACR0 0x00 /* Serial Audio Global Control register */
1133 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1134 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1135 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1136 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1137 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1138 #define SADR 0x80 /* Serial Audio Data register */
1139
1140 static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1141 {
1142 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1143 addr -= s->base;
1144
1145 switch (addr) {
1146 case SACR0:
1147 return s->control[0];
1148 case SACR1:
1149 return s->control[1];
1150 case SASR0:
1151 return s->status;
1152 case SAIMR:
1153 return s->mask;
1154 case SAICR:
1155 return 0;
1156 case SADIV:
1157 return s->clk;
1158 case SADR:
1159 if (s->rx_len > 0) {
1160 s->rx_len --;
1161 pxa2xx_i2s_update(s);
1162 return s->codec_in(s->opaque);
1163 }
1164 return 0;
1165 default:
1166 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1167 break;
1168 }
1169 return 0;
1170 }
1171
1172 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1173 uint32_t value)
1174 {
1175 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1176 uint32_t *sample;
1177 addr -= s->base;
1178
1179 switch (addr) {
1180 case SACR0:
1181 if (value & (1 << 3)) /* RST */
1182 pxa2xx_i2s_reset(s);
1183 s->control[0] = value & 0xff3d;
1184 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1185 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1186 s->codec_out(s->opaque, *sample);
1187 s->status &= ~(1 << 7); /* I2SOFF */
1188 }
1189 if (value & (1 << 4)) /* EFWR */
1190 printf("%s: Attempt to use special function\n", __FUNCTION__);
1191 s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1192 pxa2xx_i2s_update(s);
1193 break;
1194 case SACR1:
1195 s->control[1] = value & 0x0039;
1196 if (value & (1 << 5)) /* ENLBF */
1197 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1198 if (value & (1 << 4)) /* DPRL */
1199 s->fifo_len = 0;
1200 pxa2xx_i2s_update(s);
1201 break;
1202 case SAIMR:
1203 s->mask = value & 0x0078;
1204 pxa2xx_i2s_update(s);
1205 break;
1206 case SAICR:
1207 s->status &= ~(value & (3 << 5));
1208 pxa2xx_i2s_update(s);
1209 break;
1210 case SADIV:
1211 s->clk = value & 0x007f;
1212 break;
1213 case SADR:
1214 if (s->tx_len && s->enable) {
1215 s->tx_len --;
1216 pxa2xx_i2s_update(s);
1217 s->codec_out(s->opaque, value);
1218 } else if (s->fifo_len < 16) {
1219 s->fifo[s->fifo_len ++] = value;
1220 pxa2xx_i2s_update(s);
1221 }
1222 break;
1223 default:
1224 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1225 }
1226 }
1227
1228 static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
1229 pxa2xx_i2s_read,
1230 pxa2xx_i2s_read,
1231 pxa2xx_i2s_read,
1232 };
1233
1234 static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
1235 pxa2xx_i2s_write,
1236 pxa2xx_i2s_write,
1237 pxa2xx_i2s_write,
1238 };
1239
1240 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1241 {
1242 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
1243 uint32_t *sample;
1244
1245 /* Signal FIFO errors */
1246 if (s->enable && s->tx_len)
1247 s->status |= 1 << 5; /* TUR */
1248 if (s->enable && s->rx_len)
1249 s->status |= 1 << 6; /* ROR */
1250
1251 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1252 * handle the cases where it makes a difference. */
1253 s->tx_len = tx - s->fifo_len;
1254 s->rx_len = rx;
1255 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1256 if (s->enable)
1257 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1258 s->codec_out(s->opaque, *sample);
1259 pxa2xx_i2s_update(s);
1260 }
1261
1262 static struct pxa2xx_i2s_s *pxa2xx_i2s_init(target_phys_addr_t base,
1263 qemu_irq irq, struct pxa2xx_dma_state_s *dma)
1264 {
1265 int iomemtype;
1266 struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
1267 qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
1268
1269 s->base = base;
1270 s->irq = irq;
1271 s->dma = dma;
1272 s->data_req = pxa2xx_i2s_data_req;
1273
1274 pxa2xx_i2s_reset(s);
1275
1276 iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
1277 pxa2xx_i2s_writefn, s);
1278 cpu_register_physical_memory(s->base & 0xfff00000, 0xfffff, iomemtype);
1279
1280 return s;
1281 }
1282
1283 /* PXA Fast Infra-red Communications Port */
1284 struct pxa2xx_fir_s {
1285 target_phys_addr_t base;
1286 qemu_irq irq;
1287 struct pxa2xx_dma_state_s *dma;
1288 int enable;
1289 CharDriverState *chr;
1290
1291 uint8_t control[3];
1292 uint8_t status[2];
1293
1294 int rx_len;
1295 int rx_start;
1296 uint8_t rx_fifo[64];
1297 };
1298
1299 static void pxa2xx_fir_reset(struct pxa2xx_fir_s *s)
1300 {
1301 s->control[0] = 0x00;
1302 s->control[1] = 0x00;
1303 s->control[2] = 0x00;
1304 s->status[0] = 0x00;
1305 s->status[1] = 0x00;
1306 s->enable = 0;
1307 }
1308
1309 static inline void pxa2xx_fir_update(struct pxa2xx_fir_s *s)
1310 {
1311 static const int tresh[4] = { 8, 16, 32, 0 };
1312 int intr = 0;
1313 if ((s->control[0] & (1 << 4)) && /* RXE */
1314 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1315 s->status[0] |= 1 << 4; /* RFS */
1316 else
1317 s->status[0] &= ~(1 << 4); /* RFS */
1318 if (s->control[0] & (1 << 3)) /* TXE */
1319 s->status[0] |= 1 << 3; /* TFS */
1320 else
1321 s->status[0] &= ~(1 << 3); /* TFS */
1322 if (s->rx_len)
1323 s->status[1] |= 1 << 2; /* RNE */
1324 else
1325 s->status[1] &= ~(1 << 2); /* RNE */
1326 if (s->control[0] & (1 << 4)) /* RXE */
1327 s->status[1] |= 1 << 0; /* RSY */
1328 else
1329 s->status[1] &= ~(1 << 0); /* RSY */
1330
1331 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1332 (s->status[0] & (1 << 4)); /* RFS */
1333 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1334 (s->status[0] & (1 << 3)); /* TFS */
1335 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1336 (s->status[0] & (1 << 6)); /* EOC */
1337 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1338 (s->status[0] & (1 << 1)); /* TUR */
1339 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1340
1341 pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1342 pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1343
1344 qemu_set_irq(s->irq, intr && s->enable);
1345 }
1346
1347 #define ICCR0 0x00 /* FICP Control register 0 */
1348 #define ICCR1 0x04 /* FICP Control register 1 */
1349 #define ICCR2 0x08 /* FICP Control register 2 */
1350 #define ICDR 0x0c /* FICP Data register */
1351 #define ICSR0 0x14 /* FICP Status register 0 */
1352 #define ICSR1 0x18 /* FICP Status register 1 */
1353 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1354
1355 static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1356 {
1357 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1358 uint8_t ret;
1359 addr -= s->base;
1360
1361 switch (addr) {
1362 case ICCR0:
1363 return s->control[0];
1364 case ICCR1:
1365 return s->control[1];
1366 case ICCR2:
1367 return s->control[2];
1368 case ICDR:
1369 s->status[0] &= ~0x01;
1370 s->status[1] &= ~0x72;
1371 if (s->rx_len) {
1372 s->rx_len --;
1373 ret = s->rx_fifo[s->rx_start ++];
1374 s->rx_start &= 63;
1375 pxa2xx_fir_update(s);
1376 return ret;
1377 }
1378 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1379 break;
1380 case ICSR0:
1381 return s->status[0];
1382 case ICSR1:
1383 return s->status[1] | (1 << 3); /* TNF */
1384 case ICFOR:
1385 return s->rx_len;
1386 default:
1387 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1388 break;
1389 }
1390 return 0;
1391 }
1392
1393 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1394 uint32_t value)
1395 {
1396 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1397 uint8_t ch;
1398 addr -= s->base;
1399
1400 switch (addr) {
1401 case ICCR0:
1402 s->control[0] = value;
1403 if (!(value & (1 << 4))) /* RXE */
1404 s->rx_len = s->rx_start = 0;
1405 if (!(value & (1 << 3))) /* TXE */
1406 /* Nop */;
1407 s->enable = value & 1; /* ITR */
1408 if (!s->enable)
1409 s->status[0] = 0;
1410 pxa2xx_fir_update(s);
1411 break;
1412 case ICCR1:
1413 s->control[1] = value;
1414 break;
1415 case ICCR2:
1416 s->control[2] = value & 0x3f;
1417 pxa2xx_fir_update(s);
1418 break;
1419 case ICDR:
1420 if (s->control[2] & (1 << 2)) /* TXP */
1421 ch = value;
1422 else
1423 ch = ~value;
1424 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1425 qemu_chr_write(s->chr, &ch, 1);
1426 break;
1427 case ICSR0:
1428 s->status[0] &= ~(value & 0x66);
1429 pxa2xx_fir_update(s);
1430 break;
1431 case ICFOR:
1432 break;
1433 default:
1434 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1435 }
1436 }
1437
1438 static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
1439 pxa2xx_fir_read,
1440 pxa2xx_fir_read,
1441 pxa2xx_fir_read,
1442 };
1443
1444 static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
1445 pxa2xx_fir_write,
1446 pxa2xx_fir_write,
1447 pxa2xx_fir_write,
1448 };
1449
1450 static int pxa2xx_fir_is_empty(void *opaque)
1451 {
1452 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1453 return (s->rx_len < 64);
1454 }
1455
1456 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1457 {
1458 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
1459 if (!(s->control[0] & (1 << 4))) /* RXE */
1460 return;
1461
1462 while (size --) {
1463 s->status[1] |= 1 << 4; /* EOF */
1464 if (s->rx_len >= 64) {
1465 s->status[1] |= 1 << 6; /* ROR */
1466 break;
1467 }
1468
1469 if (s->control[2] & (1 << 3)) /* RXP */
1470 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1471 else
1472 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1473 }
1474
1475 pxa2xx_fir_update(s);
1476 }
1477
1478 static void pxa2xx_fir_event(void *opaque, int event)
1479 {
1480 }
1481
1482 static struct pxa2xx_fir_s *pxa2xx_fir_init(target_phys_addr_t base,
1483 qemu_irq irq, struct pxa2xx_dma_state_s *dma,
1484 CharDriverState *chr)
1485 {
1486 int iomemtype;
1487 struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
1488 qemu_mallocz(sizeof(struct pxa2xx_fir_s));
1489
1490 s->base = base;
1491 s->irq = irq;
1492 s->dma = dma;
1493 s->chr = chr;
1494
1495 pxa2xx_fir_reset(s);
1496
1497 iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
1498 pxa2xx_fir_writefn, s);
1499 cpu_register_physical_memory(s->base, 0xfff, iomemtype);
1500
1501 if (chr)
1502 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
1503 pxa2xx_fir_rx, pxa2xx_fir_event, s);
1504
1505 return s;
1506 }
1507
1508 void pxa2xx_reset(int line, int level, void *opaque)
1509 {
1510 struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
1511 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
1512 cpu_reset(s->env);
1513 /* TODO: reset peripherals */
1514 }
1515 }
1516
1517 /* Initialise a PXA270 integrated chip (ARM based core). */
1518 struct pxa2xx_state_s *pxa270_init(DisplayState *ds, const char *revision)
1519 {
1520 struct pxa2xx_state_s *s;
1521 struct pxa2xx_ssp_s *ssp;
1522 int iomemtype, i;
1523 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
1524
1525 if (revision && strncmp(revision, "pxa27", 5)) {
1526 fprintf(stderr, "Machine requires a PXA27x processor.\n");
1527 exit(1);
1528 }
1529
1530 s->env = cpu_init();
1531 cpu_arm_set_model(s->env, revision ?: "pxa270");
1532
1533 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
1534
1535 s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
1536
1537 pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
1538 s->pic[PXA27X_PIC_OST_4_11], s->env);
1539
1540 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
1541
1542 s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
1543
1544 for (i = 0; pxa270_serial[i].io_base; i ++)
1545 if (serial_hds[i])
1546 serial_mm_init(pxa270_serial[i].io_base, 2,
1547 s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
1548 else
1549 break;
1550 if (serial_hds[i])
1551 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
1552 s->dma, serial_hds[i]);
1553
1554 if (ds)
1555 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
1556
1557 s->cm_base = 0x41300000;
1558 s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
1559 s->clkcfg = 0x00000009; /* Turbo mode active */
1560 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
1561 pxa2xx_cm_writefn, s);
1562 cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
1563
1564 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
1565
1566 s->mm_base = 0x48000000;
1567 s->mm_regs[MDMRS >> 2] = 0x00020002;
1568 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
1569 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
1570 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
1571 pxa2xx_mm_writefn, s);
1572 cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
1573
1574 for (i = 0; pxa27x_ssp[i].io_base; i ++);
1575 s->ssp = (struct pxa2xx_ssp_s **)
1576 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
1577 ssp = (struct pxa2xx_ssp_s *)
1578 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
1579 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
1580 s->ssp[i] = &ssp[i];
1581 ssp[i].base = pxa27x_ssp[i].io_base;
1582 ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
1583
1584 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
1585 pxa2xx_ssp_writefn, &ssp[i]);
1586 cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
1587 }
1588
1589 if (usb_enabled) {
1590 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
1591 }
1592
1593 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
1594 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
1595
1596 s->rtc_base = 0x40900000;
1597 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
1598 pxa2xx_rtc_writefn, s);
1599 cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
1600 pxa2xx_rtc_reset(s);
1601
1602 s->pm_base = 0x40f00000;
1603 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
1604 pxa2xx_pm_writefn, s);
1605 cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
1606
1607 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
1608
1609 /* GPIO1 resets the processor */
1610 /* The handler can be overriden by board-specific code */
1611 pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
1612 return s;
1613 }
1614
1615 /* Initialise a PXA255 integrated chip (ARM based core). */
1616 struct pxa2xx_state_s *pxa255_init(DisplayState *ds)
1617 {
1618 struct pxa2xx_state_s *s;
1619 struct pxa2xx_ssp_s *ssp;
1620 int iomemtype, i;
1621 s = (struct pxa2xx_state_s *) qemu_mallocz(sizeof(struct pxa2xx_state_s));
1622
1623 s->env = cpu_init();
1624 cpu_arm_set_model(s->env, "pxa255");
1625
1626 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
1627
1628 s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
1629
1630 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0], s->env);
1631
1632 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
1633
1634 s->mmc = pxa2xx_mmci_init(0x41100000, s->pic[PXA2XX_PIC_MMC], s->dma);
1635
1636 for (i = 0; pxa255_serial[i].io_base; i ++)
1637 if (serial_hds[i])
1638 serial_mm_init(pxa255_serial[i].io_base, 2,
1639 s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
1640 else
1641 break;
1642 if (serial_hds[i])
1643 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
1644 s->dma, serial_hds[i]);
1645
1646 if (ds)
1647 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
1648
1649 s->cm_base = 0x41300000;
1650 s->cm_regs[CCCR >> 4] = 0x02000210; /* 416.0 MHz */
1651 s->clkcfg = 0x00000009; /* Turbo mode active */
1652 iomemtype = cpu_register_io_memory(0, pxa2xx_cm_readfn,
1653 pxa2xx_cm_writefn, s);
1654 cpu_register_physical_memory(s->cm_base, 0xfff, iomemtype);
1655
1656 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
1657
1658 s->mm_base = 0x48000000;
1659 s->mm_regs[MDMRS >> 2] = 0x00020002;
1660 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
1661 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
1662 iomemtype = cpu_register_io_memory(0, pxa2xx_mm_readfn,
1663 pxa2xx_mm_writefn, s);
1664 cpu_register_physical_memory(s->mm_base, 0xfff, iomemtype);
1665
1666 for (i = 0; pxa255_ssp[i].io_base; i ++);
1667 s->ssp = (struct pxa2xx_ssp_s **)
1668 qemu_mallocz(sizeof(struct pxa2xx_ssp_s *) * i);
1669 ssp = (struct pxa2xx_ssp_s *)
1670 qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
1671 for (i = 0; pxa255_ssp[i].io_base; i ++) {
1672 s->ssp[i] = &ssp[i];
1673 ssp[i].base = pxa255_ssp[i].io_base;
1674 ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
1675
1676 iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
1677 pxa2xx_ssp_writefn, &ssp[i]);
1678 cpu_register_physical_memory(ssp[i].base, 0xfff, iomemtype);
1679 }
1680
1681 if (usb_enabled) {
1682 usb_ohci_init_pxa(0x4c000000, 3, -1, s->pic[PXA2XX_PIC_USBH1]);
1683 }
1684
1685 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
1686 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
1687
1688 s->rtc_base = 0x40900000;
1689 iomemtype = cpu_register_io_memory(0, pxa2xx_rtc_readfn,
1690 pxa2xx_rtc_writefn, s);
1691 cpu_register_physical_memory(s->rtc_base, 0xfff, iomemtype);
1692 pxa2xx_rtc_reset(s);
1693
1694 s->pm_base = 0x40f00000;
1695 iomemtype = cpu_register_io_memory(0, pxa2xx_pm_readfn,
1696 pxa2xx_pm_writefn, s);
1697 cpu_register_physical_memory(s->pm_base, 0xfff, iomemtype);
1698
1699 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
1700
1701 /* GPIO1 resets the processor */
1702 /* The handler can be overriden by board-specific code */
1703 pxa2xx_gpio_handler_set(s->gpio, 1, pxa2xx_reset, s);
1704 return s;
1705 }
Samsung s3c2440 and arm920t support for the mini2440 dev board