2 * internal execution defines for qemu
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
24 /* is_jmp field values */
25 #define DISAS_NEXT 0 /* next instruction can be analyzed */
26 #define DISAS_JUMP 1 /* only pc was modified dynamically */
27 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
28 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
30 struct TranslationBlock
;
32 /* XXX: make safe guess about sizes */
33 #define MAX_OP_PER_INSTR 32
34 /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
35 #define MAX_OPC_PARAM 10
36 #define OPC_BUF_SIZE 512
37 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
39 /* Maximum size a TCG op can expand to. This is complicated because a
40 single op may require several host instructions and regirster reloads.
41 For now take a wild guess at 128 bytes, which should allow at least
42 a couple of fixup instructions per argument. */
43 #define TCG_MAX_OP_SIZE 128
45 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
47 extern target_ulong gen_opc_pc
[OPC_BUF_SIZE
];
48 extern target_ulong gen_opc_npc
[OPC_BUF_SIZE
];
49 extern uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
50 extern uint8_t gen_opc_instr_start
[OPC_BUF_SIZE
];
51 extern target_ulong gen_opc_jump_pc
[2];
52 extern uint32_t gen_opc_hflags
[OPC_BUF_SIZE
];
54 typedef void (GenOpFunc
)(void);
55 typedef void (GenOpFunc1
)(long);
56 typedef void (GenOpFunc2
)(long, long);
57 typedef void (GenOpFunc3
)(long, long, long);
59 #if defined(TARGET_I386)
61 void optimize_flags_init(void);
68 int gen_intermediate_code(CPUState
*env
, struct TranslationBlock
*tb
);
69 int gen_intermediate_code_pc(CPUState
*env
, struct TranslationBlock
*tb
);
70 void gen_pc_load(CPUState
*env
, struct TranslationBlock
*tb
,
71 unsigned long searched_pc
, int pc_pos
, void *puc
);
73 unsigned long code_gen_max_block_size(void);
74 void cpu_gen_init(void);
75 int cpu_gen_code(CPUState
*env
, struct TranslationBlock
*tb
,
76 int *gen_code_size_ptr
);
77 int cpu_restore_state(struct TranslationBlock
*tb
,
78 CPUState
*env
, unsigned long searched_pc
,
80 int cpu_gen_code_copy(CPUState
*env
, struct TranslationBlock
*tb
,
81 int max_code_size
, int *gen_code_size_ptr
);
82 int cpu_restore_state_copy(struct TranslationBlock
*tb
,
83 CPUState
*env
, unsigned long searched_pc
,
85 void cpu_resume_from_signal(CPUState
*env1
, void *puc
);
86 void cpu_exec_init(CPUState
*env
);
87 int page_unprotect(target_ulong address
, unsigned long pc
, void *puc
);
88 void tb_invalidate_phys_page_range(target_phys_addr_t start
, target_phys_addr_t end
,
89 int is_cpu_write_access
);
90 void tb_invalidate_page_range(target_ulong start
, target_ulong end
);
91 void tlb_flush_page(CPUState
*env
, target_ulong addr
);
92 void tlb_flush(CPUState
*env
, int flush_global
);
93 int tlb_set_page_exec(CPUState
*env
, target_ulong vaddr
,
94 target_phys_addr_t paddr
, int prot
,
95 int mmu_idx
, int is_softmmu
);
96 static inline int tlb_set_page(CPUState
*env
, target_ulong vaddr
,
97 target_phys_addr_t paddr
, int prot
,
98 int mmu_idx
, int is_softmmu
)
100 if (prot
& PAGE_READ
)
102 return tlb_set_page_exec(env
, vaddr
, paddr
, prot
, mmu_idx
, is_softmmu
);
105 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
107 #define CODE_GEN_PHYS_HASH_BITS 15
108 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS)
110 /* maximum total translate dcode allocated */
112 /* NOTE: the translated code area cannot be too big because on some
113 archs the range of "fast" function calls is limited. Here is a
114 summary of the ranges:
116 i386 : signed 32 bits
119 sparc : signed 32 bits
120 alpha : signed 23 bits
123 #if defined(__alpha__)
124 #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024)
125 #elif defined(__ia64)
126 #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */
127 #elif defined(__powerpc__)
128 #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024)
130 /* XXX: make it dynamic on x86 */
131 #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024)
134 //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
136 /* estimated block size for TB allocation */
137 /* XXX: use a per code average code fragment size and modulate it
138 according to the host CPU */
139 #if defined(CONFIG_SOFTMMU)
140 #define CODE_GEN_AVG_BLOCK_SIZE 128
142 #define CODE_GEN_AVG_BLOCK_SIZE 64
145 #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
147 #if defined(__powerpc__) || defined(__x86_64__)
148 #define USE_DIRECT_JUMP
150 #if defined(__i386__) && !defined(_WIN32)
151 #define USE_DIRECT_JUMP
154 typedef struct TranslationBlock
{
155 target_ulong pc
; /* simulated PC corresponding to this block (EIP + CS base) */
156 target_ulong cs_base
; /* CS base for this block */
157 uint64_t flags
; /* flags defining in which context the code was generated */
158 uint16_t size
; /* size of target code for this block (1 <=
159 size <= TARGET_PAGE_SIZE) */
160 uint16_t cflags
; /* compile flags */
161 #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
162 #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
163 #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
164 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
166 uint8_t *tc_ptr
; /* pointer to the translated code */
167 /* next matching tb for physical address. */
168 struct TranslationBlock
*phys_hash_next
;
169 /* first and second physical page containing code. The lower bit
170 of the pointer tells the index in page_next[] */
171 struct TranslationBlock
*page_next
[2];
172 target_ulong page_addr
[2];
174 /* the following data are used to directly call another TB from
175 the code of this one. */
176 uint16_t tb_next_offset
[2]; /* offset of original jump target */
177 #ifdef USE_DIRECT_JUMP
178 uint16_t tb_jmp_offset
[4]; /* offset of jump instruction */
180 unsigned long tb_next
[2]; /* address of jump generated code */
182 /* list of TBs jumping to this one. This is a circular list using
183 the two least significant bits of the pointers to tell what is
184 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
186 struct TranslationBlock
*jmp_next
[2];
187 struct TranslationBlock
*jmp_first
;
190 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc
)
193 tmp
= pc
^ (pc
>> (TARGET_PAGE_BITS
- TB_JMP_PAGE_BITS
));
194 return (tmp
>> TB_JMP_PAGE_BITS
) & TB_JMP_PAGE_MASK
;
197 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc
)
200 tmp
= pc
^ (pc
>> (TARGET_PAGE_BITS
- TB_JMP_PAGE_BITS
));
201 return (((tmp
>> TB_JMP_PAGE_BITS
) & TB_JMP_PAGE_MASK
) |
202 (tmp
& TB_JMP_ADDR_MASK
));
205 static inline unsigned int tb_phys_hash_func(unsigned long pc
)
207 return pc
& (CODE_GEN_PHYS_HASH_SIZE
- 1);
210 TranslationBlock
*tb_alloc(target_ulong pc
);
211 void tb_flush(CPUState
*env
);
212 void tb_link_phys(TranslationBlock
*tb
,
213 target_ulong phys_pc
, target_ulong phys_page2
);
215 extern TranslationBlock
*tb_phys_hash
[CODE_GEN_PHYS_HASH_SIZE
];
217 extern uint8_t code_gen_buffer
[CODE_GEN_BUFFER_SIZE
];
218 extern uint8_t *code_gen_ptr
;
220 #if defined(USE_DIRECT_JUMP)
222 #if defined(__powerpc__)
223 static inline void tb_set_jmp_target1(unsigned long jmp_addr
, unsigned long addr
)
227 /* patch the branch destination */
228 ptr
= (uint32_t *)jmp_addr
;
230 val
= (val
& ~0x03fffffc) | ((addr
- jmp_addr
) & 0x03fffffc);
233 asm volatile ("dcbst 0,%0" : : "r"(ptr
) : "memory");
234 asm volatile ("sync" : : : "memory");
235 asm volatile ("icbi 0,%0" : : "r"(ptr
) : "memory");
236 asm volatile ("sync" : : : "memory");
237 asm volatile ("isync" : : : "memory");
239 #elif defined(__i386__) || defined(__x86_64__)
240 static inline void tb_set_jmp_target1(unsigned long jmp_addr
, unsigned long addr
)
242 /* patch the branch destination */
243 *(uint32_t *)jmp_addr
= addr
- (jmp_addr
+ 4);
244 /* no need to flush icache explicitely */
248 static inline void tb_set_jmp_target(TranslationBlock
*tb
,
249 int n
, unsigned long addr
)
251 unsigned long offset
;
253 offset
= tb
->tb_jmp_offset
[n
];
254 tb_set_jmp_target1((unsigned long)(tb
->tc_ptr
+ offset
), addr
);
255 offset
= tb
->tb_jmp_offset
[n
+ 2];
256 if (offset
!= 0xffff)
257 tb_set_jmp_target1((unsigned long)(tb
->tc_ptr
+ offset
), addr
);
262 /* set the jump target */
263 static inline void tb_set_jmp_target(TranslationBlock
*tb
,
264 int n
, unsigned long addr
)
266 tb
->tb_next
[n
] = addr
;
271 static inline void tb_add_jump(TranslationBlock
*tb
, int n
,
272 TranslationBlock
*tb_next
)
274 /* NOTE: this test is only needed for thread safety */
275 if (!tb
->jmp_next
[n
]) {
276 /* patch the native jump address */
277 tb_set_jmp_target(tb
, n
, (unsigned long)tb_next
->tc_ptr
);
279 /* add in TB jmp circular list */
280 tb
->jmp_next
[n
] = tb_next
->jmp_first
;
281 tb_next
->jmp_first
= (TranslationBlock
*)((long)(tb
) | (n
));
285 TranslationBlock
*tb_find_pc(unsigned long pc_ptr
);
288 #define offsetof(type, field) ((size_t) &((type *)0)->field)
292 #define ASM_DATA_SECTION ".section \".data\"\n"
293 #define ASM_PREVIOUS_SECTION ".section .text\n"
294 #elif defined(__APPLE__)
295 #define ASM_DATA_SECTION ".data\n"
296 #define ASM_PREVIOUS_SECTION ".text\n"
298 #define ASM_DATA_SECTION ".section \".data\"\n"
299 #define ASM_PREVIOUS_SECTION ".previous\n"
302 #define ASM_OP_LABEL_NAME(n, opname) \
303 ASM_NAME(__op_label) #n "." ASM_NAME(opname)
305 extern CPUWriteMemoryFunc
*io_mem_write
[IO_MEM_NB_ENTRIES
][4];
306 extern CPUReadMemoryFunc
*io_mem_read
[IO_MEM_NB_ENTRIES
][4];
307 extern void *io_mem_opaque
[IO_MEM_NB_ENTRIES
];
309 #if defined(__hppa__)
311 typedef int spinlock_t
[4];
313 #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }
315 static inline void resetlock (spinlock_t
*p
)
317 (*p
)[0] = (*p
)[1] = (*p
)[2] = (*p
)[3] = 1;
322 typedef int spinlock_t
;
324 #define SPIN_LOCK_UNLOCKED 0
326 static inline void resetlock (spinlock_t
*p
)
328 *p
= SPIN_LOCK_UNLOCKED
;
333 #if defined(__powerpc__)
334 static inline int testandset (int *p
)
337 __asm__
__volatile__ (
345 : "r" (p
), "r" (1), "r" (0)
349 #elif defined(__i386__)
350 static inline int testandset (int *p
)
352 long int readval
= 0;
354 __asm__
__volatile__ ("lock; cmpxchgl %2, %0"
355 : "+m" (*p
), "+a" (readval
)
360 #elif defined(__x86_64__)
361 static inline int testandset (int *p
)
363 long int readval
= 0;
365 __asm__
__volatile__ ("lock; cmpxchgl %2, %0"
366 : "+m" (*p
), "+a" (readval
)
371 #elif defined(__s390__)
372 static inline int testandset (int *p
)
376 __asm__
__volatile__ ("0: cs %0,%1,0(%2)\n"
379 : "r" (1), "a" (p
), "0" (*p
)
383 #elif defined(__alpha__)
384 static inline int testandset (int *p
)
389 __asm__
__volatile__ ("0: mov 1,%2\n"
396 : "=r" (ret
), "=m" (*p
), "=r" (one
)
400 #elif defined(__sparc__)
401 static inline int testandset (int *p
)
405 __asm__
__volatile__("ldstub [%1], %0"
410 return (ret
? 1 : 0);
412 #elif defined(__arm__)
413 static inline int testandset (int *spinlock
)
415 register unsigned int ret
;
416 __asm__
__volatile__("swp %0, %1, [%2]"
418 : "0"(1), "r"(spinlock
));
422 #elif defined(__mc68000)
423 static inline int testandset (int *p
)
426 __asm__
__volatile__("tas %1; sne %0"
432 #elif defined(__hppa__)
434 /* Because malloc only guarantees 8-byte alignment for malloc'd data,
435 and GCC only guarantees 8-byte alignment for stack locals, we can't
436 be assured of 16-byte alignment for atomic lock data even if we
437 specify "__attribute ((aligned(16)))" in the type declaration. So,
438 we use a struct containing an array of four ints for the atomic lock
439 type and dynamically select the 16-byte aligned int from the array
440 for the semaphore. */
441 #define __PA_LDCW_ALIGNMENT 16
442 static inline void *ldcw_align (void *p
) {
443 unsigned long a
= (unsigned long)p
;
444 a
= (a
+ __PA_LDCW_ALIGNMENT
- 1) & ~(__PA_LDCW_ALIGNMENT
- 1);
448 static inline int testandset (spinlock_t
*p
)
452 __asm__
__volatile__("ldcw 0(%1),%0"
459 #elif defined(__ia64)
461 #include <ia64intrin.h>
463 static inline int testandset (int *p
)
465 return __sync_lock_test_and_set (p
, 1);
467 #elif defined(__mips__)
468 static inline int testandset (int *p
)
472 __asm__
__volatile__ (
481 : "=r" (ret
), "+R" (*p
)
488 #error unimplemented CPU support
491 #if defined(CONFIG_USER_ONLY)
492 static inline void spin_lock(spinlock_t
*lock
)
494 while (testandset(lock
));
497 static inline void spin_unlock(spinlock_t
*lock
)
502 static inline int spin_trylock(spinlock_t
*lock
)
504 return !testandset(lock
);
507 static inline void spin_lock(spinlock_t
*lock
)
511 static inline void spin_unlock(spinlock_t
*lock
)
515 static inline int spin_trylock(spinlock_t
*lock
)
521 extern spinlock_t tb_lock
;
523 extern int tb_invalidated_flag
;
525 #if !defined(CONFIG_USER_ONLY)
527 void tlb_fill(target_ulong addr
, int is_write
, int mmu_idx
,
530 #define ACCESS_TYPE (NB_MMU_MODES + 1)
531 #define MEMSUFFIX _code
532 #define env cpu_single_env
535 #include "softmmu_header.h"
538 #include "softmmu_header.h"
541 #include "softmmu_header.h"
544 #include "softmmu_header.h"
552 #if defined(CONFIG_USER_ONLY)
553 static inline target_ulong
get_phys_addr_code(CPUState
*env
, target_ulong addr
)
558 /* NOTE: this function can trigger an exception */
559 /* NOTE2: the returned address is not exactly the physical address: it
560 is the offset relative to phys_ram_base */
561 static inline target_ulong
get_phys_addr_code(CPUState
*env
, target_ulong addr
)
563 int mmu_idx
, index
, pd
;
565 index
= (addr
>> TARGET_PAGE_BITS
) & (CPU_TLB_SIZE
- 1);
566 mmu_idx
= cpu_mmu_index(env
);
567 if (__builtin_expect(env
->tlb_table
[mmu_idx
][index
].addr_code
!=
568 (addr
& TARGET_PAGE_MASK
), 0)) {
571 pd
= env
->tlb_table
[mmu_idx
][index
].addr_code
& ~TARGET_PAGE_MASK
;
572 if (pd
> IO_MEM_ROM
&& !(pd
& IO_MEM_ROMD
)) {
573 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
574 do_unassigned_access(addr
, 0, 1, 0);
576 cpu_abort(env
, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx
"\n", addr
);
579 return addr
+ env
->tlb_table
[mmu_idx
][index
].addend
- (unsigned long)phys_ram_base
;
584 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
586 int kqemu_init(CPUState
*env
);
587 int kqemu_cpu_exec(CPUState
*env
);
588 void kqemu_flush_page(CPUState
*env
, target_ulong addr
);
589 void kqemu_flush(CPUState
*env
, int global
);
590 void kqemu_set_notdirty(CPUState
*env
, ram_addr_t ram_addr
);
591 void kqemu_modify_page(CPUState
*env
, ram_addr_t ram_addr
);
592 void kqemu_cpu_interrupt(CPUState
*env
);
593 void kqemu_record_dump(void);
595 static inline int kqemu_is_ok(CPUState
*env
)
597 return(env
->kqemu_enabled
&&
598 (env
->cr
[0] & CR0_PE_MASK
) &&
599 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
) &&
600 (env
->eflags
& IF_MASK
) &&
601 !(env
->eflags
& VM_MASK
) &&
602 (env
->kqemu_enabled
== 2 ||
603 ((env
->hflags
& HF_CPL_MASK
) == 3 &&
604 (env
->eflags
& IOPL_MASK
) != IOPL_MASK
)));