hw/pflash_cfi01.c

   1 /*
   2  *  CFI parallel flash with Intel command set emulation
   3  *
   4  *  Copyright (c) 2006 Thorsten Zitterell
   5  *  Copyright (c) 2005 Jocelyn Mayer
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 /*
  23  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  24  * Supported commands/modes are:
  25  * - flash read
  26  * - flash write
  27  * - flash ID read
  28  * - sector erase
  29  * - CFI queries
  30  *
  31  * It does not support timings
  32  * It does not support flash interleaving
  33  * It does not implement software data protection as found in many real chips
  34  * It does not implement erase suspend/resume commands
  35  * It does not implement multiple sectors erase
  36  *
  37  * It does not implement much more ...
  38  */
  39
  40 #include "hw.h"
  41 #include "flash.h"
  42 #include "block.h"
  43 #include "qemu-timer.h"
  44
  45 #define PFLASH_BUG(fmt, args...) \
  46 do { \
  47     printf("PFLASH: Possible BUG - " fmt, ##args); \
  48     exit(1); \
  49 } while(0)
  50
  51 /* #define PFLASH_DEBUG */
  52 #ifdef PFLASH_DEBUG
  53 #define DPRINTF(fmt, args...)                      \
  54 do {                                               \
  55         printf("PFLASH: " fmt , ##args);           \
  56 } while (0)
  57 #else
  58 #define DPRINTF(fmt, args...) do { } while (0)
  59 #endif
  60
  61 struct pflash_t {
  62     BlockDriverState *bs;
  63     target_ulong base;
  64     target_ulong sector_len;
  65     target_ulong total_len;
  66     int width;
  67     int wcycle; /* if 0, the flash is read normally */
  68     int bypass;
  69     int ro;
  70     uint8_t cmd;
  71     uint8_t status;
  72     uint16_t ident[4];
  73     uint8_t cfi_len;
  74     uint8_t cfi_table[0x52];
  75     target_ulong counter;
  76     QEMUTimer *timer;
  77     ram_addr_t off;
  78     int fl_mem;
  79     void *storage;
  80 };
  81
  82 static void pflash_timer (void *opaque)
  83 {
  84     pflash_t *pfl = opaque;
  85
  86     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
  87     /* Reset flash */
  88     pfl->status ^= 0x80;
  89     if (pfl->bypass) {
  90         pfl->wcycle = 2;
  91     } else {
  92         cpu_register_physical_memory(pfl->base, pfl->total_len,
  93                         pfl->off | IO_MEM_ROMD | pfl->fl_mem);
  94         pfl->wcycle = 0;
  95     }
  96     pfl->cmd = 0;
  97 }
  98
  99 static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
 100 {
 101     target_ulong boff;
 102     uint32_t ret;
 103     uint8_t *p;
 104
 105     ret = -1;
 106     offset -= pfl->base;
 107     boff = offset & 0xFF; /* why this here ?? */
 108
 109     if (pfl->width == 2)
 110         boff = boff >> 1;
 111     else if (pfl->width == 4)
 112         boff = boff >> 2;
 113
 114     DPRINTF("%s: reading offset " TARGET_FMT_lx " under cmd %02x\n",
 115             __func__, boff, pfl->cmd);
 116
 117     switch (pfl->cmd) {
 118     case 0x00:
 119         /* Flash area read */
 120         p = pfl->storage;
 121         switch (width) {
 122         case 1:
 123             ret = p[offset];
 124             DPRINTF("%s: data offset " TARGET_FMT_lx " %02x\n",
 125                     __func__, offset, ret);
 126             break;
 127         case 2:
 128 #if defined(TARGET_WORDS_BIGENDIAN)
 129             ret = p[offset] << 8;
 130             ret |= p[offset + 1];
 131 #else
 132             ret = p[offset];
 133             ret |= p[offset + 1] << 8;
 134 #endif
 135             DPRINTF("%s: data offset " TARGET_FMT_lx " %04x\n",
 136                     __func__, offset, ret);
 137             break;
 138         case 4:
 139 #if defined(TARGET_WORDS_BIGENDIAN)
 140             ret = p[offset] << 24;
 141             ret |= p[offset + 1] << 16;
 142             ret |= p[offset + 2] << 8;
 143             ret |= p[offset + 3];
 144 #else
 145             ret = p[offset];
 146             ret |= p[offset + 1] << 8;
 147             ret |= p[offset + 1] << 8;
 148             ret |= p[offset + 2] << 16;
 149             ret |= p[offset + 3] << 24;
 150 #endif
 151             DPRINTF("%s: data offset " TARGET_FMT_lx " %08x\n",
 152                     __func__, offset, ret);
 153             break;
 154         default:
 155             DPRINTF("BUG in %s\n", __func__);
 156         }
 157
 158         break;
 159     case 0x20: /* Block erase */
 160     case 0x50: /* Clear status register */
 161     case 0x60: /* Block /un)lock */
 162     case 0x70: /* Status Register */
 163     case 0xe8: /* Write block */
 164         /* Status register read */
 165         ret = pfl->status;
 166         DPRINTF("%s: status %x\n", __func__, ret);
 167         break;
 168     case 0x98: /* Query mode */
 169         if (boff > pfl->cfi_len)
 170             ret = 0;
 171         else
 172             ret = pfl->cfi_table[boff];
 173         break;
 174     default:
 175         /* This should never happen : reset state & treat it as a read */
 176         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 177         pfl->wcycle = 0;
 178         pfl->cmd = 0;
 179     }
 180     return ret;
 181 }
 182
 183 /* update flash content on disk */
 184 static void pflash_update(pflash_t *pfl, int offset,
 185                           int size)
 186 {
 187     int offset_end;
 188     if (pfl->bs) {
 189         offset_end = offset + size;
 190         /* round to sectors */
 191         offset = offset >> 9;
 192         offset_end = (offset_end + 511) >> 9;
 193         bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
 194                    offset_end - offset);
 195     }
 196 }
 197
 198 static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
 199                           int width)
 200 {
 201     target_ulong boff;
 202     uint8_t *p;
 203     uint8_t cmd;
 204
 205     cmd = value;
 206     offset -= pfl->base;
 207
 208     DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d wcycle 0x%x\n",
 209             __func__, offset, value, width, pfl->wcycle);
 210
 211     /* Set the device in I/O access mode */
 212     cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
 213     boff = offset & (pfl->sector_len - 1);
 214
 215     if (pfl->width == 2)
 216         boff = boff >> 1;
 217     else if (pfl->width == 4)
 218         boff = boff >> 2;
 219
 220     switch (pfl->wcycle) {
 221     case 0:
 222         /* read mode */
 223         switch (cmd) {
 224         case 0x00: /* ??? */
 225             goto reset_flash;
 226         case 0x20: /* Block erase */
 227             p = pfl->storage;
 228             offset &= ~(pfl->sector_len - 1);
 229
 230             DPRINTF("%s: block erase at " TARGET_FMT_lx " bytes "
 231                     TARGET_FMT_lx "\n",
 232                     __func__, offset, pfl->sector_len);
 233
 234             memset(p + offset, 0xff, pfl->sector_len);
 235             pflash_update(pfl, offset, pfl->sector_len);
 236             pfl->status |= 0x80; /* Ready! */
 237             break;
 238         case 0x50: /* Clear status bits */
 239             DPRINTF("%s: Clear status bits\n", __func__);
 240             pfl->status = 0x0;
 241             goto reset_flash;
 242         case 0x60: /* Block (un)lock */
 243             DPRINTF("%s: Block unlock\n", __func__);
 244             break;
 245         case 0x70: /* Status Register */
 246             DPRINTF("%s: Read status register\n", __func__);
 247             pfl->cmd = cmd;
 248             return;
 249         case 0x98: /* CFI query */
 250             DPRINTF("%s: CFI query\n", __func__);
 251             break;
 252         case 0xe8: /* Write to buffer */
 253             DPRINTF("%s: Write to buffer\n", __func__);
 254             pfl->status |= 0x80; /* Ready! */
 255             break;
 256         case 0xff: /* Read array mode */
 257             DPRINTF("%s: Read array mode\n", __func__);
 258             goto reset_flash;
 259         default:
 260             goto error_flash;
 261         }
 262         pfl->wcycle++;
 263         pfl->cmd = cmd;
 264         return;
 265     case 1:
 266         switch (pfl->cmd) {
 267         case 0x20: /* Block erase */
 268         case 0x28:
 269             if (cmd == 0xd0) { /* confirm */
 270                 pfl->wcycle = 1;
 271                 pfl->status |= 0x80;
 272             } else if (cmd == 0xff) { /* read array mode */
 273                 goto reset_flash;
 274             } else
 275                 goto error_flash;
 276
 277             break;
 278         case 0xe8:
 279             DPRINTF("%s: block write of %x bytes\n", __func__, cmd);
 280             pfl->counter = cmd;
 281             pfl->wcycle++;
 282             break;
 283         case 0x60:
 284             if (cmd == 0xd0) {
 285                 pfl->wcycle = 0;
 286                 pfl->status |= 0x80;
 287             } else if (cmd == 0x01) {
 288                 pfl->wcycle = 0;
 289                 pfl->status |= 0x80;
 290             } else if (cmd == 0xff) {
 291                 goto reset_flash;
 292             } else {
 293                 DPRINTF("%s: Unknown (un)locking command\n", __func__);
 294                 goto reset_flash;
 295             }
 296             break;
 297         case 0x98:
 298             if (cmd == 0xff) {
 299                 goto reset_flash;
 300             } else {
 301                 DPRINTF("%s: leaving query mode\n", __func__);
 302             }
 303             break;
 304         default:
 305             goto error_flash;
 306         }
 307         return;
 308     case 2:
 309         switch (pfl->cmd) {
 310         case 0xe8: /* Block write */
 311             p = pfl->storage;
 312             DPRINTF("%s: block write offset " TARGET_FMT_lx
 313                     " value %x counter " TARGET_FMT_lx "\n",
 314                     __func__, offset, value, pfl->counter);
 315             switch (width) {
 316             case 1:
 317                 p[offset] = value;
 318                 pflash_update(pfl, offset, 1);
 319                 break;
 320             case 2:
 321 #if defined(TARGET_WORDS_BIGENDIAN)
 322                 p[offset] = value >> 8;
 323                 p[offset + 1] = value;
 324 #else
 325                 p[offset] = value;
 326                 p[offset + 1] = value >> 8;
 327 #endif
 328                 pflash_update(pfl, offset, 2);
 329                 break;
 330             case 4:
 331 #if defined(TARGET_WORDS_BIGENDIAN)
 332                 p[offset] = value >> 24;
 333                 p[offset + 1] = value >> 16;
 334                 p[offset + 2] = value >> 8;
 335                 p[offset + 3] = value;
 336 #else
 337                 p[offset] = value;
 338                 p[offset + 1] = value >> 8;
 339                 p[offset + 2] = value >> 16;
 340                 p[offset + 3] = value >> 24;
 341 #endif
 342                 pflash_update(pfl, offset, 4);
 343                 break;
 344             }
 345
 346             pfl->status |= 0x80;
 347
 348             if (!pfl->counter) {
 349                 DPRINTF("%s: block write finished\n", __func__);
 350                 pfl->wcycle++;
 351             }
 352
 353             pfl->counter--;
 354             break;
 355         default:
 356             goto error_flash;
 357         }
 358         return;
 359     case 3: /* Confirm mode */
 360         switch (pfl->cmd) {
 361         case 0xe8: /* Block write */
 362             if (cmd == 0xd0) {
 363                 pfl->wcycle = 0;
 364                 pfl->status |= 0x80;
 365             } else {
 366                 DPRINTF("%s: unknown command for \"write block\"\n", __func__);
 367                 PFLASH_BUG("Write block confirm");
 368                 goto reset_flash;
 369             }
 370             break;
 371         default:
 372             goto error_flash;
 373         }
 374         return;
 375     default:
 376         /* Should never happen */
 377         DPRINTF("%s: invalid write state\n",  __func__);
 378         goto reset_flash;
 379     }
 380     return;
 381
 382  error_flash:
 383     printf("%s: Unimplemented flash cmd sequence "
 384            "(offset " TARGET_FMT_lx ", wcycle 0x%x cmd 0x%x value 0x%x)\n",
 385            __func__, offset, pfl->wcycle, pfl->cmd, value);
 386
 387  reset_flash:
 388     cpu_register_physical_memory(pfl->base, pfl->total_len,
 389                     pfl->off | IO_MEM_ROMD | pfl->fl_mem);
 390
 391     pfl->bypass = 0;
 392     pfl->wcycle = 0;
 393     pfl->cmd = 0;
 394     return;
 395 }
 396
 397
 398 static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
 399 {
 400     return pflash_read(opaque, addr, 1);
 401 }
 402
 403 static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
 404 {
 405     pflash_t *pfl = opaque;
 406
 407     return pflash_read(pfl, addr, 2);
 408 }
 409
 410 static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
 411 {
 412     pflash_t *pfl = opaque;
 413
 414     return pflash_read(pfl, addr, 4);
 415 }
 416
 417 static void pflash_writeb (void *opaque, target_phys_addr_t addr,
 418                            uint32_t value)
 419 {
 420     pflash_write(opaque, addr, value, 1);
 421 }
 422
 423 static void pflash_writew (void *opaque, target_phys_addr_t addr,
 424                            uint32_t value)
 425 {
 426     pflash_t *pfl = opaque;
 427
 428     pflash_write(pfl, addr, value, 2);
 429 }
 430
 431 static void pflash_writel (void *opaque, target_phys_addr_t addr,
 432                            uint32_t value)
 433 {
 434     pflash_t *pfl = opaque;
 435
 436     pflash_write(pfl, addr, value, 4);
 437 }
 438
 439 static CPUWriteMemoryFunc *pflash_write_ops[] = {
 440     &pflash_writeb,
 441     &pflash_writew,
 442     &pflash_writel,
 443 };
 444
 445 static CPUReadMemoryFunc *pflash_read_ops[] = {
 446     &pflash_readb,
 447     &pflash_readw,
 448     &pflash_readl,
 449 };
 450
 451 /* Count trailing zeroes of a 32 bits quantity */
 452 static int ctz32 (uint32_t n)
 453 {
 454     int ret;
 455
 456     ret = 0;
 457     if (!(n & 0xFFFF)) {
 458         ret += 16;
 459         n = n >> 16;
 460     }
 461     if (!(n & 0xFF)) {
 462         ret += 8;
 463         n = n >> 8;
 464     }
 465     if (!(n & 0xF)) {
 466         ret += 4;
 467         n = n >> 4;
 468     }
 469     if (!(n & 0x3)) {
 470         ret += 2;
 471         n = n >> 2;
 472     }
 473     if (!(n & 0x1)) {
 474         ret++;
 475         n = n >> 1;
 476     }
 477 #if 0 /* This is not necessary as n is never 0 */
 478     if (!n)
 479         ret++;
 480 #endif
 481
 482     return ret;
 483 }
 484
 485 pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
 486                                 BlockDriverState *bs, uint32_t sector_len,
 487                                 int nb_blocs, int width,
 488                                 uint16_t id0, uint16_t id1,
 489                                 uint16_t id2, uint16_t id3)
 490 {
 491     pflash_t *pfl;
 492     target_long total_len;
 493
 494     total_len = sector_len * nb_blocs;
 495
 496     /* XXX: to be fixed */
 497 #if 0
 498     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 499         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 500         return NULL;
 501 #endif
 502
 503     pfl = qemu_mallocz(sizeof(pflash_t));
 504
 505     if (pfl == NULL)
 506         return NULL;
 507     pfl->storage = phys_ram_base + off;
 508     pfl->fl_mem = cpu_register_io_memory(0,
 509                     pflash_read_ops, pflash_write_ops, pfl);
 510     pfl->off = off;
 511     cpu_register_physical_memory(base, total_len,
 512                     off | pfl->fl_mem | IO_MEM_ROMD);
 513
 514     pfl->bs = bs;
 515     if (pfl->bs) {
 516         /* read the initial flash content */
 517         bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
 518     }
 519 #if 0 /* XXX: there should be a bit to set up read-only,
 520        *      the same way the hardware does (with WP pin).
 521        */
 522     pfl->ro = 1;
 523 #else
 524     pfl->ro = 0;
 525 #endif
 526     pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
 527     pfl->base = base;
 528     pfl->sector_len = sector_len;
 529     pfl->total_len = total_len;
 530     pfl->width = width;
 531     pfl->wcycle = 0;
 532     pfl->cmd = 0;
 533     pfl->status = 0;
 534     pfl->ident[0] = id0;
 535     pfl->ident[1] = id1;
 536     pfl->ident[2] = id2;
 537     pfl->ident[3] = id3;
 538     /* Hardcoded CFI table */
 539     pfl->cfi_len = 0x52;
 540     /* Standard "QRY" string */
 541     pfl->cfi_table[0x10] = 'Q';
 542     pfl->cfi_table[0x11] = 'R';
 543     pfl->cfi_table[0x12] = 'Y';
 544     /* Command set (Intel) */
 545     pfl->cfi_table[0x13] = 0x01;
 546     pfl->cfi_table[0x14] = 0x00;
 547     /* Primary extended table address (none) */
 548     pfl->cfi_table[0x15] = 0x31;
 549     pfl->cfi_table[0x16] = 0x00;
 550     /* Alternate command set (none) */
 551     pfl->cfi_table[0x17] = 0x00;
 552     pfl->cfi_table[0x18] = 0x00;
 553     /* Alternate extended table (none) */
 554     pfl->cfi_table[0x19] = 0x00;
 555     pfl->cfi_table[0x1A] = 0x00;
 556     /* Vcc min */
 557     pfl->cfi_table[0x1B] = 0x45;
 558     /* Vcc max */
 559     pfl->cfi_table[0x1C] = 0x55;
 560     /* Vpp min (no Vpp pin) */
 561     pfl->cfi_table[0x1D] = 0x00;
 562     /* Vpp max (no Vpp pin) */
 563     pfl->cfi_table[0x1E] = 0x00;
 564     /* Reserved */
 565     pfl->cfi_table[0x1F] = 0x07;
 566     /* Timeout for min size buffer write */
 567     pfl->cfi_table[0x20] = 0x07;
 568     /* Typical timeout for block erase */
 569     pfl->cfi_table[0x21] = 0x0a;
 570     /* Typical timeout for full chip erase (4096 ms) */
 571     pfl->cfi_table[0x22] = 0x00;
 572     /* Reserved */
 573     pfl->cfi_table[0x23] = 0x04;
 574     /* Max timeout for buffer write */
 575     pfl->cfi_table[0x24] = 0x04;
 576     /* Max timeout for block erase */
 577     pfl->cfi_table[0x25] = 0x04;
 578     /* Max timeout for chip erase */
 579     pfl->cfi_table[0x26] = 0x00;
 580     /* Device size */
 581     pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
 582     /* Flash device interface (8 & 16 bits) */
 583     pfl->cfi_table[0x28] = 0x02;
 584     pfl->cfi_table[0x29] = 0x00;
 585     /* Max number of bytes in multi-bytes write */
 586     pfl->cfi_table[0x2A] = 0x04;
 587     pfl->cfi_table[0x2B] = 0x00;
 588     /* Number of erase block regions (uniform) */
 589     pfl->cfi_table[0x2C] = 0x01;
 590     /* Erase block region 1 */
 591     pfl->cfi_table[0x2D] = nb_blocs - 1;
 592     pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
 593     pfl->cfi_table[0x2F] = sector_len >> 8;
 594     pfl->cfi_table[0x30] = sector_len >> 16;
 595
 596     /* Extended */
 597     pfl->cfi_table[0x31] = 'P';
 598     pfl->cfi_table[0x32] = 'R';
 599     pfl->cfi_table[0x33] = 'I';
 600
 601     pfl->cfi_table[0x34] = '1';
 602     pfl->cfi_table[0x35] = '1';
 603
 604     pfl->cfi_table[0x36] = 0x00;
 605     pfl->cfi_table[0x37] = 0x00;
 606     pfl->cfi_table[0x38] = 0x00;
 607     pfl->cfi_table[0x39] = 0x00;
 608
 609     pfl->cfi_table[0x3a] = 0x00;
 610
 611     pfl->cfi_table[0x3b] = 0x00;
 612     pfl->cfi_table[0x3c] = 0x00;
 613
 614     return pfl;
 615 }