2 * Samsung S3C2410A RISC Microprocessor support (ARM920T based SoC).
4 * Copyright (c) 2007 OpenMoko, Inc.
5 * Author: Andrzej Zaborowski <andrew@openedhand.com>
7 * This code is licenced under the GNU GPL v2.
10 # define S3C_H "s3c.h"
12 # include "qemu-common.h"
16 /* Interrupt numbers */
17 # define S3C_PIC_EINT0 0
18 # define S3C_PIC_EINT1 1
19 # define S3C_PIC_EINT2 2
20 # define S3C_PIC_EINT3 3
21 # define S3C_PIC_EINT4 4
22 # define S3C_PIC_EINT8 5
23 # define S3C_PIC_WDT 9
24 # define S3C_PIC_TIMER0 10
25 # define S3C_PIC_TIMER1 11
26 # define S3C_PIC_TIMER2 12
27 # define S3C_PIC_TIMER3 13
28 # define S3C_PIC_TIMER4 14
29 # define S3C_PIC_UART2 15
30 # define S3C_PIC_LCD 16
31 # define S3C_PIC_DMA0 17
32 # define S3C_PIC_DMA1 18
33 # define S3C_PIC_DMA2 19
34 # define S3C_PIC_DMA3 20
35 # define S3C_PIC_SDI 21
36 # define S3C_PIC_SPI0 22
37 # define S3C_PIC_UART1 23
38 # define S3C_PIC_USBD 25
39 # define S3C_PIC_USBH 26
40 # define S3C_PIC_IIC 27
41 # define S3C_PIC_UART0 28
42 # define S3C_PIC_SPI1 29
43 # define S3C_PIC_RTC 30
44 # define S3C_PIC_ADC 31
45 /* "Sub source" interrupt numbers */
46 # define S3C_PICS_RXD0 32
47 # define S3C_PICS_TXD0 33
48 # define S3C_PICS_ERR0 34
49 # define S3C_PICS_RXD1 35
50 # define S3C_PICS_TXD1 36
51 # define S3C_PICS_ERR1 37
52 # define S3C_PICS_RXD2 38
53 # define S3C_PICS_TXD2 39
54 # define S3C_PICS_ERR2 40
55 # define S3C_PICS_TC 41
56 # define S3C_PICS_ADC 42
58 # define S3C_PIC_MAX 43
59 /* External interrupt numbers */
60 # define S3C_EINT(n) ((n >= 8) ? (6 << 5) | (n - 8) : (5 << 5) | n)
63 # define S3C_RQ_nXDREQ0 0x00
64 # define S3C_RQ_nXDREQ1 0x10
65 # define S3C_RQ_I2SSDO 0x20
66 # define S3C_RQ_UART2 0x30
67 # define S3C_RQ_UART0 0x01
68 # define S3C_RQ_UART1 0x11
69 # define S3C_RQ_I2SSDI0 0x21
70 # define S3C_RQ_SDI0 0x31
71 # define S3C_RQ_SDI1 0x02
72 # define S3C_RQ_I2SSDI1 0x12
73 # define S3C_RQ_SDI2 0x22
74 # define S3C_RQ_SPI1 0x32
75 # define S3C_RQ_TIMER0 0x03
76 # define S3C_RQ_SPI0 0x13
77 # define S3C_RQ_TIMER1 0x23
78 # define S3C_RQ_TIMER2 0x33
79 # define S3C_RQ_USB_EP1 0x04
80 # define S3C_RQ_USB_EP2 0x14
81 # define S3C_RQ_USB_EP3 0x24
82 # define S3C_RQ_USB_EP4 0x34
84 # define S3C_RQ_MAX 0x35
86 /* I/O port numbers */
87 # define S3C_GP(b, n) (((b) << 5) | n)
88 # define S3C_GPA(n) S3C_GP(0, n)
89 # define S3C_GPB(n) S3C_GP(1, n)
90 # define S3C_GPC(n) S3C_GP(2, n)
91 # define S3C_GPD(n) S3C_GP(3, n)
92 # define S3C_GPE(n) S3C_GP(4, n)
93 # define S3C_GPF(n) S3C_GP(5, n)
94 # define S3C_GPG(n) S3C_GP(6, n)
95 # define S3C_GPH(n) S3C_GP(7, n)
96 # define S3C_GP_MAX S3C_GP(8, 0)
98 # define S3C_RAM_BASE 0x30000000
99 # define S3C_SRAM_BASE 0x40000000
100 # define S3C_SRAM_SIZE 0x00001000
102 # define S3C_PCLK_FREQ 66500000 /* Hz */
103 # define S3C_XTAL_FREQ 32768 /* Hz */
106 struct s3c_pic_state_s
;
107 struct s3c_pic_state_s
*s3c_pic_init(target_phys_addr_t base
,
109 qemu_irq
*s3c_pic_get(struct s3c_pic_state_s
*s
);
111 struct s3c_dma_state_s
;
112 struct s3c_dma_state_s
*s3c_dma_init(target_phys_addr_t base
, qemu_irq
*pic
);
113 qemu_irq
*s3c_dma_get(struct s3c_dma_state_s
*s
);
115 /* GPIO TODO: remove this out, replace with qemu_irq or sumpthin */
116 typedef void (*gpio_handler_t
)(int line
, int level
, void *opaque
);
118 struct s3c_timers_state_s
;
119 struct s3c_timers_state_s
*s3c_timers_init(target_phys_addr_t base
,
120 qemu_irq
*pic
, qemu_irq
*dma
);
121 void s3c_timers_cmp_handler_set(void *opaque
, int line
,
122 gpio_handler_t handler
, void *cmp_opaque
);
124 struct s3c_uart_state_s
;
125 struct s3c_uart_state_s
*s3c_uart_init(target_phys_addr_t base
,
126 qemu_irq
*irqs
, qemu_irq
*dma
);
127 void s3c_uart_attach(struct s3c_uart_state_s
*s
, CharDriverState
*chr
);
129 struct s3c_adc_state_s
;
130 struct s3c_adc_state_s
*s3c_adc_init(target_phys_addr_t base
, qemu_irq irq
,
132 void s3c_adc_setscale(struct s3c_adc_state_s
*adc
, const int m
[]);
134 struct s3c_i2c_state_s
;
135 struct s3c_i2c_state_s
*s3c_i2c_init(target_phys_addr_t base
, qemu_irq irq
);
136 i2c_bus
*s3c_i2c_bus(struct s3c_i2c_state_s
*s
);
138 struct s3c_i2s_state_s
;
139 struct s3c_i2s_state_s
*s3c_i2s_init(target_phys_addr_t base
, qemu_irq
*dma
);
141 struct s3c_wdt_state_s
;
142 struct s3c_wdt_state_s
*s3c_wdt_init(target_phys_addr_t base
, qemu_irq irq
);
145 struct s3c_gpio_state_s
;
146 struct s3c_gpio_state_s
*s3c_gpio_init(target_phys_addr_t base
, qemu_irq
*pic
);
147 qemu_irq
*s3c_gpio_in_get(struct s3c_gpio_state_s
*s
);
148 void s3c_gpio_out_set(struct s3c_gpio_state_s
*s
, int line
, qemu_irq handler
);
149 void s3c_gpio_setpwrstat(struct s3c_gpio_state_s
*s
, int stat
);
150 void s3c_gpio_reset(struct s3c_gpio_state_s
*s
);
153 struct s3c_lcd_state_s
;
154 struct s3c_lcd_state_s
*s3c_lcd_init(target_phys_addr_t base
, DisplayState
*ds
,
156 void s3c_lcd_reset(struct s3c_lcd_state_s
*s
);
159 struct s3c_mmci_state_s
;
160 struct s3c_mmci_state_s
*s3c_mmci_init(target_phys_addr_t base
, uint16_t model
,
161 SDState
*mmc
, qemu_irq irq
, qemu_irq
*dma
);
162 void s3c_mmci_reset(struct s3c_mmci_state_s
*s
);
165 struct s3c_rtc_state_s
;
166 struct s3c_rtc_state_s
*s3c_rtc_init(target_phys_addr_t base
, qemu_irq irq
);
167 void s3c_rtc_reset(struct s3c_rtc_state_s
*s
);
170 struct s3c_udc_state_s
;
171 struct s3c_udc_state_s
*s3c_udc_init(target_phys_addr_t base
, qemu_irq irq
,
173 void s3c_udc_reset(struct s3c_udc_state_s
*s
);
176 struct s3c_spi_state_s
;
177 struct s3c_spi_state_s
*s3c_spi_init(target_phys_addr_t base
,
178 qemu_irq irq0
, qemu_irq drq0
, qemu_irq irq1
, qemu_irq drq1
,
179 struct s3c_gpio_state_s
*gpio
);
180 void s3c_spi_attach(struct s3c_spi_state_s
*s
, int ch
,
181 uint8_t (*txrx
)(void *opaque
, uint8_t value
),
182 uint8_t (*btxrx
)(void *opaque
, uint8_t value
), void *opaque
);
188 struct s3c_pic_state_s
*pic
;
189 struct s3c_dma_state_s
*dma
;
190 struct s3c_gpio_state_s
*io
;
191 struct s3c_lcd_state_s
*lcd
;
192 struct s3c_timers_state_s
*timers
;
193 struct s3c_uart_state_s
*uart
[3];
194 struct s3c_mmci_state_s
*mmci
;
195 struct s3c_adc_state_s
*adc
;
196 struct s3c_i2c_state_s
*i2c
;
197 struct s3c_i2s_state_s
*i2s
;
198 struct s3c_rtc_state_s
*rtc
;
199 struct s3c_spi_state_s
*spi
;
200 struct s3c_udc_state_s
*udc
;
201 struct s3c_wdt_state_s
*wdt
;
203 /* Memory controller */
204 target_phys_addr_t mc_base
;
205 uint32_t mc_regs
[13];
207 /* NAND Flash controller */
208 target_phys_addr_t nand_base
;
209 struct nand_flash_s
*nand
;
213 struct ecc_state_s nfecc
;
216 /* Clock & power management */
217 target_phys_addr_t clkpwr_base
;
218 uint32_t clkpwr_regs
[6];
222 struct s3c_state_s
*s3c2410_init(unsigned int sdram_size
, DisplayState
*ds
,
224 void s3c_nand_register(struct s3c_state_s
*s
, struct nand_flash_s
*chip
);
225 void s3c_nand_setwp(struct s3c_state_s
*s
, int wp
);
227 struct s3c_i2s_state_s
{ /* XXX move to .c */
228 target_phys_addr_t base
;
230 void (*data_req
)(void *, int, int);
241 void (*codec_out
)(void *, uint32_t);
242 uint32_t (*codec_in
)(void *);