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[qemu/mini2440.git] / hw / sun4m.c
blob734b576aaea6bc8558d2835061816c9ece25a0fc
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37
38 //#define DEBUG_IRQ
39
40 /*
41 * Sun4m architecture was used in the following machines:
42 *
43 * SPARCserver 6xxMP/xx
44 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
45 * SPARCclassic X (4/10)
46 * SPARCstation LX/ZX (4/30)
47 * SPARCstation Voyager
48 * SPARCstation 10/xx, SPARCserver 10/xx
49 * SPARCstation 5, SPARCserver 5
50 * SPARCstation 20/xx, SPARCserver 20
51 * SPARCstation 4
52 *
53 * Sun4d architecture was used in the following machines:
54 *
55 * SPARCcenter 2000
56 * SPARCserver 1000
57 *
58 * Sun4c architecture was used in the following machines:
59 * SPARCstation 1/1+, SPARCserver 1/1+
60 * SPARCstation SLC
61 * SPARCstation IPC
62 * SPARCstation ELC
63 * SPARCstation IPX
64 *
65 * See for example: http://www.sunhelp.org/faq/sunref1.html
66 */
67
68 #ifdef DEBUG_IRQ
69 #define DPRINTF(fmt, args...) \
70 do { printf("CPUIRQ: " fmt , ##args); } while (0)
71 #else
72 #define DPRINTF(fmt, args...)
73 #endif
74
75 #define KERNEL_LOAD_ADDR 0x00004000
76 #define CMDLINE_ADDR 0x007ff000
77 #define INITRD_LOAD_ADDR 0x00800000
78 #define PROM_SIZE_MAX (512 * 1024)
79 #define PROM_VADDR 0xffd00000
80 #define PROM_FILENAME "openbios-sparc32"
81
82 // Control plane, 8-bit and 24-bit planes
83 #define TCX_SIZE (9 * 1024 * 1024)
84
85 #define MAX_CPUS 16
86 #define MAX_PILS 16
87
88 struct hwdef {
89 target_phys_addr_t iommu_base, slavio_base;
90 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
91 target_phys_addr_t serial_base, fd_base;
92 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
93 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
94 target_phys_addr_t ecc_base;
95 uint32_t ecc_version;
96 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
97 long vram_size, nvram_size;
98 // IRQ numbers are not PIL ones, but master interrupt controller
99 // register bit numbers
100 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
101 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
102 int machine_id; // For NVRAM
103 uint32_t iommu_version;
104 uint32_t intbit_to_level[32];
105 uint64_t max_mem;
106 const char * const default_cpu_model;
107 };
108
109 #define MAX_IOUNITS 5
110
111 struct sun4d_hwdef {
112 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
113 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
114 target_phys_addr_t serial_base;
115 target_phys_addr_t espdma_base, esp_base;
116 target_phys_addr_t ledma_base, le_base;
117 target_phys_addr_t tcx_base;
118 target_phys_addr_t sbi_base;
119 unsigned long vram_size, nvram_size;
120 // IRQ numbers are not PIL ones, but SBI register bit numbers
121 int esp_irq, le_irq, clock_irq, clock1_irq;
122 int ser_irq, ms_kb_irq, me_irq;
123 int machine_id; // For NVRAM
124 uint32_t iounit_version;
125 uint64_t max_mem;
126 const char * const default_cpu_model;
127 };
128
129 int DMA_get_channel_mode (int nchan)
130 {
131 return 0;
132 }
133 int DMA_read_memory (int nchan, void *buf, int pos, int size)
134 {
135 return 0;
136 }
137 int DMA_write_memory (int nchan, void *buf, int pos, int size)
138 {
139 return 0;
140 }
141 void DMA_hold_DREQ (int nchan) {}
142 void DMA_release_DREQ (int nchan) {}
143 void DMA_schedule(int nchan) {}
144 void DMA_run (void) {}
145 void DMA_init (int high_page_enable) {}
146 void DMA_register_channel (int nchan,
147 DMA_transfer_handler transfer_handler,
148 void *opaque)
149 {
150 }
151
152 extern int nographic;
153
154 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
155 const char *boot_devices, ram_addr_t RAM_size,
156 uint32_t kernel_size,
157 int width, int height, int depth,
158 int machine_id, const char *arch)
159 {
160 unsigned int i;
161 uint32_t start, end;
162 uint8_t image[0x1ff0];
163 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
164 struct sparc_arch_cfg *sparc_header;
165 struct OpenBIOS_nvpart_v1 *part_header;
166
167 memset(image, '\0', sizeof(image));
168
169 // Try to match PPC NVRAM
170 strcpy(header->struct_ident, "QEMU_BIOS");
171 header->struct_version = cpu_to_be32(3); /* structure v3 */
172
173 header->nvram_size = cpu_to_be16(0x2000);
174 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
175 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
176 strcpy(header->arch, arch);
177 header->nb_cpus = smp_cpus & 0xff;
178 header->RAM0_base = 0;
179 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
180 strcpy(header->boot_devices, boot_devices);
181 header->nboot_devices = strlen(boot_devices) & 0xff;
182 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
183 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
184 if (cmdline) {
185 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
186 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
187 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
188 }
189 // XXX add initrd_image, initrd_size
190 header->width = cpu_to_be16(width);
191 header->height = cpu_to_be16(height);
192 header->depth = cpu_to_be16(depth);
193 if (nographic)
194 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
195
196 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
197
198 // Architecture specific header
199 start = sizeof(ohwcfg_v3_t);
200 sparc_header = (struct sparc_arch_cfg *)&image[start];
201 sparc_header->valid = 0;
202 start += sizeof(struct sparc_arch_cfg);
203
204 // OpenBIOS nvram variables
205 // Variable partition
206 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
207 part_header->signature = OPENBIOS_PART_SYSTEM;
208 strcpy(part_header->name, "system");
209
210 end = start + sizeof(struct OpenBIOS_nvpart_v1);
211 for (i = 0; i < nb_prom_envs; i++)
212 end = OpenBIOS_set_var(image, end, prom_envs[i]);
213
214 // End marker
215 image[end++] = '\0';
216
217 end = start + ((end - start + 15) & ~15);
218 OpenBIOS_finish_partition(part_header, end - start);
219
220 // free partition
221 start = end;
222 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
223 part_header->signature = OPENBIOS_PART_FREE;
224 strcpy(part_header->name, "free");
225
226 end = 0x1fd0;
227 OpenBIOS_finish_partition(part_header, end - start);
228
229 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
230
231 for (i = 0; i < sizeof(image); i++)
232 m48t59_write(nvram, i, image[i]);
233 }
234
235 static void *slavio_intctl;
236
237 void pic_info(void)
238 {
239 if (slavio_intctl)
240 slavio_pic_info(slavio_intctl);
241 }
242
243 void irq_info(void)
244 {
245 if (slavio_intctl)
246 slavio_irq_info(slavio_intctl);
247 }
248
249 void cpu_check_irqs(CPUState *env)
250 {
251 if (env->pil_in && (env->interrupt_index == 0 ||
252 (env->interrupt_index & ~15) == TT_EXTINT)) {
253 unsigned int i;
254
255 for (i = 15; i > 0; i--) {
256 if (env->pil_in & (1 << i)) {
257 int old_interrupt = env->interrupt_index;
258
259 env->interrupt_index = TT_EXTINT | i;
260 if (old_interrupt != env->interrupt_index) {
261 DPRINTF("Set CPU IRQ %d\n", i);
262 cpu_interrupt(env, CPU_INTERRUPT_HARD);
263 }
264 break;
265 }
266 }
267 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
268 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
269 env->interrupt_index = 0;
270 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
271 }
272 }
273
274 static void cpu_set_irq(void *opaque, int irq, int level)
275 {
276 CPUState *env = opaque;
277
278 if (level) {
279 DPRINTF("Raise CPU IRQ %d\n", irq);
280 env->halted = 0;
281 env->pil_in |= 1 << irq;
282 cpu_check_irqs(env);
283 } else {
284 DPRINTF("Lower CPU IRQ %d\n", irq);
285 env->pil_in &= ~(1 << irq);
286 cpu_check_irqs(env);
287 }
288 }
289
290 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
291 {
292 }
293
294 static void *slavio_misc;
295
296 void qemu_system_powerdown(void)
297 {
298 slavio_set_power_fail(slavio_misc, 1);
299 }
300
301 static void main_cpu_reset(void *opaque)
302 {
303 CPUState *env = opaque;
304
305 cpu_reset(env);
306 env->halted = 0;
307 }
308
309 static void secondary_cpu_reset(void *opaque)
310 {
311 CPUState *env = opaque;
312
313 cpu_reset(env);
314 env->halted = 1;
315 }
316
317 static unsigned long sun4m_load_kernel(const char *kernel_filename,
318 const char *initrd_filename,
319 ram_addr_t RAM_size)
320 {
321 int linux_boot;
322 unsigned int i;
323 long initrd_size, kernel_size;
324
325 linux_boot = (kernel_filename != NULL);
326
327 kernel_size = 0;
328 if (linux_boot) {
329 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
330 NULL);
331 if (kernel_size < 0)
332 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
333 RAM_size - KERNEL_LOAD_ADDR);
334 if (kernel_size < 0)
335 kernel_size = load_image_targphys(kernel_filename,
336 KERNEL_LOAD_ADDR,
337 RAM_size - KERNEL_LOAD_ADDR);
338 if (kernel_size < 0) {
339 fprintf(stderr, "qemu: could not load kernel '%s'\n",
340 kernel_filename);
341 exit(1);
342 }
343
344 /* load initrd */
345 initrd_size = 0;
346 if (initrd_filename) {
347 initrd_size = load_image_targphys(initrd_filename,
348 INITRD_LOAD_ADDR,
349 RAM_size - INITRD_LOAD_ADDR);
350 if (initrd_size < 0) {
351 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
352 initrd_filename);
353 exit(1);
354 }
355 }
356 if (initrd_size > 0) {
357 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
358 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
359 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
360 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
361 break;
362 }
363 }
364 }
365 }
366 return kernel_size;
367 }
368
369 static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
370 const char *boot_device,
371 DisplayState *ds, const char *kernel_filename,
372 const char *kernel_cmdline,
373 const char *initrd_filename, const char *cpu_model)
374
375 {
376 CPUState *env, *envs[MAX_CPUS];
377 unsigned int i;
378 void *iommu, *espdma, *ledma, *main_esp, *nvram;
379 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
380 *espdma_irq, *ledma_irq;
381 qemu_irq *esp_reset, *le_reset;
382 qemu_irq *fdc_tc;
383 unsigned long prom_offset, kernel_size;
384 int ret;
385 char buf[1024];
386 BlockDriverState *fd[MAX_FD];
387 int drive_index;
388
389 /* init CPUs */
390 if (!cpu_model)
391 cpu_model = hwdef->default_cpu_model;
392
393 for(i = 0; i < smp_cpus; i++) {
394 env = cpu_init(cpu_model);
395 if (!env) {
396 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
397 exit(1);
398 }
399 cpu_sparc_set_id(env, i);
400 envs[i] = env;
401 if (i == 0) {
402 qemu_register_reset(main_cpu_reset, env);
403 } else {
404 qemu_register_reset(secondary_cpu_reset, env);
405 env->halted = 1;
406 }
407 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
408 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
409 env->prom_addr = hwdef->slavio_base;
410 }
411
412 for (i = smp_cpus; i < MAX_CPUS; i++)
413 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
414
415
416 /* allocate RAM */
417 if ((uint64_t)RAM_size > hwdef->max_mem) {
418 fprintf(stderr,
419 "qemu: Too much memory for this machine: %d, maximum %d\n",
420 (unsigned int)(RAM_size / (1024 * 1024)),
421 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
422 exit(1);
423 }
424 cpu_register_physical_memory(0, RAM_size, 0);
425
426 /* load boot prom */
427 prom_offset = RAM_size + hwdef->vram_size;
428 cpu_register_physical_memory(hwdef->slavio_base,
429 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
430 TARGET_PAGE_MASK,
431 prom_offset | IO_MEM_ROM);
432
433 if (bios_name == NULL)
434 bios_name = PROM_FILENAME;
435 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
436 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
437 if (ret < 0 || ret > PROM_SIZE_MAX)
438 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
439 if (ret < 0 || ret > PROM_SIZE_MAX) {
440 fprintf(stderr, "qemu: could not load prom '%s'\n",
441 buf);
442 exit(1);
443 }
444 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
445
446 /* set up devices */
447 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
448 hwdef->intctl_base + 0x10000ULL,
449 &hwdef->intbit_to_level[0],
450 &slavio_irq, &slavio_cpu_irq,
451 cpu_irqs,
452 hwdef->clock_irq);
453
454 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
455 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
456
457 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
458 prom_offset | IO_MEM_ROM);
459 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
460 sizeof(idreg_data));
461 }
462
463 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
464 slavio_irq[hwdef->me_irq]);
465
466 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
467 iommu, &espdma_irq, &esp_reset);
468
469 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
470 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
471 &le_reset);
472
473 if (graphic_depth != 8 && graphic_depth != 24) {
474 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
475 exit (1);
476 }
477 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
478 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
479
480 if (nd_table[0].model == NULL
481 || strcmp(nd_table[0].model, "lance") == 0) {
482 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
483 } else if (strcmp(nd_table[0].model, "?") == 0) {
484 fprintf(stderr, "qemu: Supported NICs: lance\n");
485 exit (1);
486 } else {
487 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
488 exit (1);
489 }
490
491 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
492 hwdef->nvram_size, 8);
493
494 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
495 slavio_cpu_irq, smp_cpus);
496
497 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
498 nographic);
499 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
500 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
501 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
502 serial_hds[1], serial_hds[0]);
503
504 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
505 hwdef->aux1_base, hwdef->aux2_base,
506 slavio_irq[hwdef->me_irq], envs[0],
507 &fdc_tc);
508
509 if (hwdef->fd_base != (target_phys_addr_t)-1) {
510 /* there is zero or one floppy drive */
511 memset(fd, 0, sizeof(fd));
512 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
513 if (drive_index != -1)
514 fd[0] = drives_table[drive_index].bdrv;
515
516 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
517 fdc_tc);
518 }
519
520 if (drive_get_max_bus(IF_SCSI) > 0) {
521 fprintf(stderr, "qemu: too many SCSI bus\n");
522 exit(1);
523 }
524
525 main_esp = esp_init(hwdef->esp_base, 2,
526 espdma_memory_read, espdma_memory_write,
527 espdma, *espdma_irq, esp_reset);
528
529 for (i = 0; i < ESP_MAX_DEVS; i++) {
530 drive_index = drive_get_index(IF_SCSI, 0, i);
531 if (drive_index == -1)
532 continue;
533 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
534 }
535
536 if (hwdef->cs_base != (target_phys_addr_t)-1)
537 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
538
539 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
540 RAM_size);
541
542 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
543 boot_device, RAM_size, kernel_size, graphic_width,
544 graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
545
546 if (hwdef->ecc_base != (target_phys_addr_t)-1)
547 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
548 hwdef->ecc_version);
549 }
550
551 static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
552 const char *boot_device,
553 DisplayState *ds, const char *kernel_filename,
554 const char *kernel_cmdline,
555 const char *initrd_filename, const char *cpu_model)
556 {
557 CPUState *env;
558 unsigned int i;
559 void *iommu, *espdma, *ledma, *main_esp, *nvram;
560 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
561 qemu_irq *esp_reset, *le_reset;
562 qemu_irq *fdc_tc;
563 unsigned long prom_offset, kernel_size;
564 int ret;
565 char buf[1024];
566 BlockDriverState *fd[MAX_FD];
567 int drive_index;
568
569 /* init CPU */
570 if (!cpu_model)
571 cpu_model = hwdef->default_cpu_model;
572
573 env = cpu_init(cpu_model);
574 if (!env) {
575 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
576 exit(1);
577 }
578
579 cpu_sparc_set_id(env, 0);
580
581 qemu_register_reset(main_cpu_reset, env);
582 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
583 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
584 env->prom_addr = hwdef->slavio_base;
585
586 /* allocate RAM */
587 if ((uint64_t)RAM_size > hwdef->max_mem) {
588 fprintf(stderr,
589 "qemu: Too much memory for this machine: %d, maximum %d\n",
590 (unsigned int)(RAM_size / (1024 * 1024)),
591 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
592 exit(1);
593 }
594 cpu_register_physical_memory(0, RAM_size, 0);
595
596 /* load boot prom */
597 prom_offset = RAM_size + hwdef->vram_size;
598 cpu_register_physical_memory(hwdef->slavio_base,
599 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
600 TARGET_PAGE_MASK,
601 prom_offset | IO_MEM_ROM);
602
603 if (bios_name == NULL)
604 bios_name = PROM_FILENAME;
605 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
606 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
607 if (ret < 0 || ret > PROM_SIZE_MAX)
608 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
609 if (ret < 0 || ret > PROM_SIZE_MAX) {
610 fprintf(stderr, "qemu: could not load prom '%s'\n",
611 buf);
612 exit(1);
613 }
614 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
615
616 /* set up devices */
617 slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
618 &slavio_irq, cpu_irqs);
619
620 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
621 slavio_irq[hwdef->me_irq]);
622
623 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
624 iommu, &espdma_irq, &esp_reset);
625
626 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
627 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
628 &le_reset);
629
630 if (graphic_depth != 8 && graphic_depth != 24) {
631 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
632 exit (1);
633 }
634 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
635 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
636
637 if (nd_table[0].model == NULL
638 || strcmp(nd_table[0].model, "lance") == 0) {
639 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
640 } else if (strcmp(nd_table[0].model, "?") == 0) {
641 fprintf(stderr, "qemu: Supported NICs: lance\n");
642 exit (1);
643 } else {
644 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
645 exit (1);
646 }
647
648 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
649 hwdef->nvram_size, 2);
650
651 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
652 nographic);
653 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
654 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
655 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
656 serial_hds[1], serial_hds[0]);
657
658 slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
659 hwdef->aux1_base, hwdef->aux2_base,
660 slavio_irq[hwdef->me_irq], env, &fdc_tc);
661
662 if (hwdef->fd_base != (target_phys_addr_t)-1) {
663 /* there is zero or one floppy drive */
664 fd[1] = fd[0] = NULL;
665 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
666 if (drive_index != -1)
667 fd[0] = drives_table[drive_index].bdrv;
668
669 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
670 fdc_tc);
671 }
672
673 if (drive_get_max_bus(IF_SCSI) > 0) {
674 fprintf(stderr, "qemu: too many SCSI bus\n");
675 exit(1);
676 }
677
678 main_esp = esp_init(hwdef->esp_base, 2,
679 espdma_memory_read, espdma_memory_write,
680 espdma, *espdma_irq, esp_reset);
681
682 for (i = 0; i < ESP_MAX_DEVS; i++) {
683 drive_index = drive_get_index(IF_SCSI, 0, i);
684 if (drive_index == -1)
685 continue;
686 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
687 }
688
689 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
690 RAM_size);
691
692 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
693 boot_device, RAM_size, kernel_size, graphic_width,
694 graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
695 }
696
697 static const struct hwdef hwdefs[] = {
698 /* SS-5 */
699 {
700 .iommu_base = 0x10000000,
701 .tcx_base = 0x50000000,
702 .cs_base = 0x6c000000,
703 .slavio_base = 0x70000000,
704 .ms_kb_base = 0x71000000,
705 .serial_base = 0x71100000,
706 .nvram_base = 0x71200000,
707 .fd_base = 0x71400000,
708 .counter_base = 0x71d00000,
709 .intctl_base = 0x71e00000,
710 .idreg_base = 0x78000000,
711 .dma_base = 0x78400000,
712 .esp_base = 0x78800000,
713 .le_base = 0x78c00000,
714 .apc_base = 0x6a000000,
715 .aux1_base = 0x71900000,
716 .aux2_base = 0x71910000,
717 .ecc_base = -1,
718 .sun4c_intctl_base = -1,
719 .sun4c_counter_base = -1,
720 .vram_size = 0x00100000,
721 .nvram_size = 0x2000,
722 .esp_irq = 18,
723 .le_irq = 16,
724 .clock_irq = 7,
725 .clock1_irq = 19,
726 .ms_kb_irq = 14,
727 .ser_irq = 15,
728 .fd_irq = 22,
729 .me_irq = 30,
730 .cs_irq = 5,
731 .machine_id = 0x80,
732 .iommu_version = 0x05000000,
733 .intbit_to_level = {
734 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
735 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
736 },
737 .max_mem = 0x10000000,
738 .default_cpu_model = "Fujitsu MB86904",
739 },
740 /* SS-10 */
741 {
742 .iommu_base = 0xfe0000000ULL,
743 .tcx_base = 0xe20000000ULL,
744 .cs_base = -1,
745 .slavio_base = 0xff0000000ULL,
746 .ms_kb_base = 0xff1000000ULL,
747 .serial_base = 0xff1100000ULL,
748 .nvram_base = 0xff1200000ULL,
749 .fd_base = 0xff1700000ULL,
750 .counter_base = 0xff1300000ULL,
751 .intctl_base = 0xff1400000ULL,
752 .idreg_base = 0xef0000000ULL,
753 .dma_base = 0xef0400000ULL,
754 .esp_base = 0xef0800000ULL,
755 .le_base = 0xef0c00000ULL,
756 .apc_base = 0xefa000000ULL, // XXX should not exist
757 .aux1_base = 0xff1800000ULL,
758 .aux2_base = 0xff1a01000ULL,
759 .ecc_base = 0xf00000000ULL,
760 .ecc_version = 0x10000000, // version 0, implementation 1
761 .sun4c_intctl_base = -1,
762 .sun4c_counter_base = -1,
763 .vram_size = 0x00100000,
764 .nvram_size = 0x2000,
765 .esp_irq = 18,
766 .le_irq = 16,
767 .clock_irq = 7,
768 .clock1_irq = 19,
769 .ms_kb_irq = 14,
770 .ser_irq = 15,
771 .fd_irq = 22,
772 .me_irq = 30,
773 .cs_irq = -1,
774 .ecc_irq = 28,
775 .machine_id = 0x72,
776 .iommu_version = 0x03000000,
777 .intbit_to_level = {
778 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
779 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
780 },
781 .max_mem = 0xf00000000ULL,
782 .default_cpu_model = "TI SuperSparc II",
783 },
784 /* SS-600MP */
785 {
786 .iommu_base = 0xfe0000000ULL,
787 .tcx_base = 0xe20000000ULL,
788 .cs_base = -1,
789 .slavio_base = 0xff0000000ULL,
790 .ms_kb_base = 0xff1000000ULL,
791 .serial_base = 0xff1100000ULL,
792 .nvram_base = 0xff1200000ULL,
793 .fd_base = -1,
794 .counter_base = 0xff1300000ULL,
795 .intctl_base = 0xff1400000ULL,
796 .idreg_base = -1,
797 .dma_base = 0xef0081000ULL,
798 .esp_base = 0xef0080000ULL,
799 .le_base = 0xef0060000ULL,
800 .apc_base = 0xefa000000ULL, // XXX should not exist
801 .aux1_base = 0xff1800000ULL,
802 .aux2_base = 0xff1a01000ULL, // XXX should not exist
803 .ecc_base = 0xf00000000ULL,
804 .ecc_version = 0x00000000, // version 0, implementation 0
805 .sun4c_intctl_base = -1,
806 .sun4c_counter_base = -1,
807 .vram_size = 0x00100000,
808 .nvram_size = 0x2000,
809 .esp_irq = 18,
810 .le_irq = 16,
811 .clock_irq = 7,
812 .clock1_irq = 19,
813 .ms_kb_irq = 14,
814 .ser_irq = 15,
815 .fd_irq = 22,
816 .me_irq = 30,
817 .cs_irq = -1,
818 .ecc_irq = 28,
819 .machine_id = 0x71,
820 .iommu_version = 0x01000000,
821 .intbit_to_level = {
822 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
823 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
824 },
825 .max_mem = 0xf00000000ULL,
826 .default_cpu_model = "TI SuperSparc II",
827 },
828 /* SS-20 */
829 {
830 .iommu_base = 0xfe0000000ULL,
831 .tcx_base = 0xe20000000ULL,
832 .cs_base = -1,
833 .slavio_base = 0xff0000000ULL,
834 .ms_kb_base = 0xff1000000ULL,
835 .serial_base = 0xff1100000ULL,
836 .nvram_base = 0xff1200000ULL,
837 .fd_base = 0xff1700000ULL,
838 .counter_base = 0xff1300000ULL,
839 .intctl_base = 0xff1400000ULL,
840 .idreg_base = 0xef0000000ULL,
841 .dma_base = 0xef0400000ULL,
842 .esp_base = 0xef0800000ULL,
843 .le_base = 0xef0c00000ULL,
844 .apc_base = 0xefa000000ULL, // XXX should not exist
845 .aux1_base = 0xff1800000ULL,
846 .aux2_base = 0xff1a01000ULL,
847 .ecc_base = 0xf00000000ULL,
848 .ecc_version = 0x20000000, // version 0, implementation 2
849 .sun4c_intctl_base = -1,
850 .sun4c_counter_base = -1,
851 .vram_size = 0x00100000,
852 .nvram_size = 0x2000,
853 .esp_irq = 18,
854 .le_irq = 16,
855 .clock_irq = 7,
856 .clock1_irq = 19,
857 .ms_kb_irq = 14,
858 .ser_irq = 15,
859 .fd_irq = 22,
860 .me_irq = 30,
861 .cs_irq = -1,
862 .ecc_irq = 28,
863 .machine_id = 0x72,
864 .iommu_version = 0x13000000,
865 .intbit_to_level = {
866 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
867 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
868 },
869 .max_mem = 0xf00000000ULL,
870 .default_cpu_model = "TI SuperSparc II",
871 },
872 /* SS-2 */
873 {
874 .iommu_base = 0xf8000000,
875 .tcx_base = 0xfe000000,
876 .cs_base = -1,
877 .slavio_base = 0xf6000000,
878 .ms_kb_base = 0xf0000000,
879 .serial_base = 0xf1000000,
880 .nvram_base = 0xf2000000,
881 .fd_base = 0xf7200000,
882 .counter_base = -1,
883 .intctl_base = -1,
884 .dma_base = 0xf8400000,
885 .esp_base = 0xf8800000,
886 .le_base = 0xf8c00000,
887 .apc_base = -1,
888 .aux1_base = 0xf7400003,
889 .aux2_base = -1,
890 .sun4c_intctl_base = 0xf5000000,
891 .sun4c_counter_base = 0xf3000000,
892 .vram_size = 0x00100000,
893 .nvram_size = 0x800,
894 .esp_irq = 2,
895 .le_irq = 3,
896 .clock_irq = 5,
897 .clock1_irq = 7,
898 .ms_kb_irq = 1,
899 .ser_irq = 1,
900 .fd_irq = 1,
901 .me_irq = 1,
902 .cs_irq = -1,
903 .machine_id = 0x55,
904 .max_mem = 0x10000000,
905 .default_cpu_model = "Cypress CY7C601",
906 },
907 /* Voyager */
908 {
909 .iommu_base = 0x10000000,
910 .tcx_base = 0x50000000,
911 .cs_base = -1,
912 .slavio_base = 0x70000000,
913 .ms_kb_base = 0x71000000,
914 .serial_base = 0x71100000,
915 .nvram_base = 0x71200000,
916 .fd_base = 0x71400000,
917 .counter_base = 0x71d00000,
918 .intctl_base = 0x71e00000,
919 .idreg_base = 0x78000000,
920 .dma_base = 0x78400000,
921 .esp_base = 0x78800000,
922 .le_base = 0x78c00000,
923 .apc_base = 0x71300000, // pmc
924 .aux1_base = 0x71900000,
925 .aux2_base = 0x71910000,
926 .ecc_base = -1,
927 .sun4c_intctl_base = -1,
928 .sun4c_counter_base = -1,
929 .vram_size = 0x00100000,
930 .nvram_size = 0x2000,
931 .esp_irq = 18,
932 .le_irq = 16,
933 .clock_irq = 7,
934 .clock1_irq = 19,
935 .ms_kb_irq = 14,
936 .ser_irq = 15,
937 .fd_irq = 22,
938 .me_irq = 30,
939 .cs_irq = -1,
940 .machine_id = 0x80,
941 .iommu_version = 0x05000000,
942 .intbit_to_level = {
943 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
944 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
945 },
946 .max_mem = 0x10000000,
947 .default_cpu_model = "Fujitsu MB86904",
948 },
949 /* LX */
950 {
951 .iommu_base = 0x10000000,
952 .tcx_base = 0x50000000,
953 .cs_base = -1,
954 .slavio_base = 0x70000000,
955 .ms_kb_base = 0x71000000,
956 .serial_base = 0x71100000,
957 .nvram_base = 0x71200000,
958 .fd_base = 0x71400000,
959 .counter_base = 0x71d00000,
960 .intctl_base = 0x71e00000,
961 .idreg_base = 0x78000000,
962 .dma_base = 0x78400000,
963 .esp_base = 0x78800000,
964 .le_base = 0x78c00000,
965 .apc_base = -1,
966 .aux1_base = 0x71900000,
967 .aux2_base = 0x71910000,
968 .ecc_base = -1,
969 .sun4c_intctl_base = -1,
970 .sun4c_counter_base = -1,
971 .vram_size = 0x00100000,
972 .nvram_size = 0x2000,
973 .esp_irq = 18,
974 .le_irq = 16,
975 .clock_irq = 7,
976 .clock1_irq = 19,
977 .ms_kb_irq = 14,
978 .ser_irq = 15,
979 .fd_irq = 22,
980 .me_irq = 30,
981 .cs_irq = -1,
982 .machine_id = 0x80,
983 .iommu_version = 0x04000000,
984 .intbit_to_level = {
985 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
986 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
987 },
988 .max_mem = 0x10000000,
989 .default_cpu_model = "TI MicroSparc I",
990 },
991 /* SS-4 */
992 {
993 .iommu_base = 0x10000000,
994 .tcx_base = 0x50000000,
995 .cs_base = 0x6c000000,
996 .slavio_base = 0x70000000,
997 .ms_kb_base = 0x71000000,
998 .serial_base = 0x71100000,
999 .nvram_base = 0x71200000,
1000 .fd_base = 0x71400000,
1001 .counter_base = 0x71d00000,
1002 .intctl_base = 0x71e00000,
1003 .idreg_base = 0x78000000,
1004 .dma_base = 0x78400000,
1005 .esp_base = 0x78800000,
1006 .le_base = 0x78c00000,
1007 .apc_base = 0x6a000000,
1008 .aux1_base = 0x71900000,
1009 .aux2_base = 0x71910000,
1010 .ecc_base = -1,
1011 .sun4c_intctl_base = -1,
1012 .sun4c_counter_base = -1,
1013 .vram_size = 0x00100000,
1014 .nvram_size = 0x2000,
1015 .esp_irq = 18,
1016 .le_irq = 16,
1017 .clock_irq = 7,
1018 .clock1_irq = 19,
1019 .ms_kb_irq = 14,
1020 .ser_irq = 15,
1021 .fd_irq = 22,
1022 .me_irq = 30,
1023 .cs_irq = 5,
1024 .machine_id = 0x80,
1025 .iommu_version = 0x05000000,
1026 .intbit_to_level = {
1027 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1028 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1029 },
1030 .max_mem = 0x10000000,
1031 .default_cpu_model = "Fujitsu MB86904",
1032 },
1033 /* SPARCClassic */
1034 {
1035 .iommu_base = 0x10000000,
1036 .tcx_base = 0x50000000,
1037 .cs_base = -1,
1038 .slavio_base = 0x70000000,
1039 .ms_kb_base = 0x71000000,
1040 .serial_base = 0x71100000,
1041 .nvram_base = 0x71200000,
1042 .fd_base = 0x71400000,
1043 .counter_base = 0x71d00000,
1044 .intctl_base = 0x71e00000,
1045 .idreg_base = 0x78000000,
1046 .dma_base = 0x78400000,
1047 .esp_base = 0x78800000,
1048 .le_base = 0x78c00000,
1049 .apc_base = 0x6a000000,
1050 .aux1_base = 0x71900000,
1051 .aux2_base = 0x71910000,
1052 .ecc_base = -1,
1053 .sun4c_intctl_base = -1,
1054 .sun4c_counter_base = -1,
1055 .vram_size = 0x00100000,
1056 .nvram_size = 0x2000,
1057 .esp_irq = 18,
1058 .le_irq = 16,
1059 .clock_irq = 7,
1060 .clock1_irq = 19,
1061 .ms_kb_irq = 14,
1062 .ser_irq = 15,
1063 .fd_irq = 22,
1064 .me_irq = 30,
1065 .cs_irq = -1,
1066 .machine_id = 0x80,
1067 .iommu_version = 0x05000000,
1068 .intbit_to_level = {
1069 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1070 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1071 },
1072 .max_mem = 0x10000000,
1073 .default_cpu_model = "TI MicroSparc I",
1074 },
1075 /* SPARCbook */
1076 {
1077 .iommu_base = 0x10000000,
1078 .tcx_base = 0x50000000, // XXX
1079 .cs_base = -1,
1080 .slavio_base = 0x70000000,
1081 .ms_kb_base = 0x71000000,
1082 .serial_base = 0x71100000,
1083 .nvram_base = 0x71200000,
1084 .fd_base = 0x71400000,
1085 .counter_base = 0x71d00000,
1086 .intctl_base = 0x71e00000,
1087 .idreg_base = 0x78000000,
1088 .dma_base = 0x78400000,
1089 .esp_base = 0x78800000,
1090 .le_base = 0x78c00000,
1091 .apc_base = 0x6a000000,
1092 .aux1_base = 0x71900000,
1093 .aux2_base = 0x71910000,
1094 .ecc_base = -1,
1095 .sun4c_intctl_base = -1,
1096 .sun4c_counter_base = -1,
1097 .vram_size = 0x00100000,
1098 .nvram_size = 0x2000,
1099 .esp_irq = 18,
1100 .le_irq = 16,
1101 .clock_irq = 7,
1102 .clock1_irq = 19,
1103 .ms_kb_irq = 14,
1104 .ser_irq = 15,
1105 .fd_irq = 22,
1106 .me_irq = 30,
1107 .cs_irq = -1,
1108 .machine_id = 0x80,
1109 .iommu_version = 0x05000000,
1110 .intbit_to_level = {
1111 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
1112 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
1113 },
1114 .max_mem = 0x10000000,
1115 .default_cpu_model = "TI MicroSparc I",
1116 },
1117 };
1118
1119 /* SPARCstation 5 hardware initialisation */
1120 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
1121 const char *boot_device, DisplayState *ds,
1122 const char *kernel_filename, const char *kernel_cmdline,
1123 const char *initrd_filename, const char *cpu_model)
1124 {
1125 sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1126 kernel_cmdline, initrd_filename, cpu_model);
1127 }
1128
1129 /* SPARCstation 10 hardware initialisation */
1130 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1131 const char *boot_device, DisplayState *ds,
1132 const char *kernel_filename, const char *kernel_cmdline,
1133 const char *initrd_filename, const char *cpu_model)
1134 {
1135 sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1136 kernel_cmdline, initrd_filename, cpu_model);
1137 }
1138
1139 /* SPARCserver 600MP hardware initialisation */
1140 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1141 const char *boot_device, DisplayState *ds,
1142 const char *kernel_filename,
1143 const char *kernel_cmdline,
1144 const char *initrd_filename, const char *cpu_model)
1145 {
1146 sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1147 kernel_cmdline, initrd_filename, cpu_model);
1148 }
1149
1150 /* SPARCstation 20 hardware initialisation */
1151 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1152 const char *boot_device, DisplayState *ds,
1153 const char *kernel_filename, const char *kernel_cmdline,
1154 const char *initrd_filename, const char *cpu_model)
1155 {
1156 sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1157 kernel_cmdline, initrd_filename, cpu_model);
1158 }
1159
1160 /* SPARCstation 2 hardware initialisation */
1161 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1162 const char *boot_device, DisplayState *ds,
1163 const char *kernel_filename, const char *kernel_cmdline,
1164 const char *initrd_filename, const char *cpu_model)
1165 {
1166 sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1167 kernel_cmdline, initrd_filename, cpu_model);
1168 }
1169
1170 /* SPARCstation Voyager hardware initialisation */
1171 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1172 const char *boot_device, DisplayState *ds,
1173 const char *kernel_filename, const char *kernel_cmdline,
1174 const char *initrd_filename, const char *cpu_model)
1175 {
1176 sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1177 kernel_cmdline, initrd_filename, cpu_model);
1178 }
1179
1180 /* SPARCstation LX hardware initialisation */
1181 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1182 const char *boot_device, DisplayState *ds,
1183 const char *kernel_filename, const char *kernel_cmdline,
1184 const char *initrd_filename, const char *cpu_model)
1185 {
1186 sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1187 kernel_cmdline, initrd_filename, cpu_model);
1188 }
1189
1190 /* SPARCstation 4 hardware initialisation */
1191 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1192 const char *boot_device, DisplayState *ds,
1193 const char *kernel_filename, const char *kernel_cmdline,
1194 const char *initrd_filename, const char *cpu_model)
1195 {
1196 sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1197 kernel_cmdline, initrd_filename, cpu_model);
1198 }
1199
1200 /* SPARCClassic hardware initialisation */
1201 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1202 const char *boot_device, DisplayState *ds,
1203 const char *kernel_filename, const char *kernel_cmdline,
1204 const char *initrd_filename, const char *cpu_model)
1205 {
1206 sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1207 kernel_cmdline, initrd_filename, cpu_model);
1208 }
1209
1210 /* SPARCbook hardware initialisation */
1211 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1212 const char *boot_device, DisplayState *ds,
1213 const char *kernel_filename, const char *kernel_cmdline,
1214 const char *initrd_filename, const char *cpu_model)
1215 {
1216 sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
1217 kernel_cmdline, initrd_filename, cpu_model);
1218 }
1219
1220 QEMUMachine ss5_machine = {
1221 "SS-5",
1222 "Sun4m platform, SPARCstation 5",
1223 ss5_init,
1224 PROM_SIZE_MAX + TCX_SIZE,
1225 };
1226
1227 QEMUMachine ss10_machine = {
1228 "SS-10",
1229 "Sun4m platform, SPARCstation 10",
1230 ss10_init,
1231 PROM_SIZE_MAX + TCX_SIZE,
1232 };
1233
1234 QEMUMachine ss600mp_machine = {
1235 "SS-600MP",
1236 "Sun4m platform, SPARCserver 600MP",
1237 ss600mp_init,
1238 PROM_SIZE_MAX + TCX_SIZE,
1239 };
1240
1241 QEMUMachine ss20_machine = {
1242 "SS-20",
1243 "Sun4m platform, SPARCstation 20",
1244 ss20_init,
1245 PROM_SIZE_MAX + TCX_SIZE,
1246 };
1247
1248 QEMUMachine ss2_machine = {
1249 "SS-2",
1250 "Sun4c platform, SPARCstation 2",
1251 ss2_init,
1252 PROM_SIZE_MAX + TCX_SIZE,
1253 };
1254
1255 QEMUMachine voyager_machine = {
1256 "Voyager",
1257 "Sun4m platform, SPARCstation Voyager",
1258 vger_init,
1259 PROM_SIZE_MAX + TCX_SIZE,
1260 };
1261
1262 QEMUMachine ss_lx_machine = {
1263 "LX",
1264 "Sun4m platform, SPARCstation LX",
1265 ss_lx_init,
1266 PROM_SIZE_MAX + TCX_SIZE,
1267 };
1268
1269 QEMUMachine ss4_machine = {
1270 "SS-4",
1271 "Sun4m platform, SPARCstation 4",
1272 ss4_init,
1273 PROM_SIZE_MAX + TCX_SIZE,
1274 };
1275
1276 QEMUMachine scls_machine = {
1277 "SPARCClassic",
1278 "Sun4m platform, SPARCClassic",
1279 scls_init,
1280 PROM_SIZE_MAX + TCX_SIZE,
1281 };
1282
1283 QEMUMachine sbook_machine = {
1284 "SPARCbook",
1285 "Sun4m platform, SPARCbook",
1286 sbook_init,
1287 PROM_SIZE_MAX + TCX_SIZE,
1288 };
1289
1290 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1291 /* SS-1000 */
1292 {
1293 .iounit_bases = {
1294 0xfe0200000ULL,
1295 0xfe1200000ULL,
1296 0xfe2200000ULL,
1297 0xfe3200000ULL,
1298 -1,
1299 },
1300 .tcx_base = 0x820000000ULL,
1301 .slavio_base = 0xf00000000ULL,
1302 .ms_kb_base = 0xf00240000ULL,
1303 .serial_base = 0xf00200000ULL,
1304 .nvram_base = 0xf00280000ULL,
1305 .counter_base = 0xf00300000ULL,
1306 .espdma_base = 0x800081000ULL,
1307 .esp_base = 0x800080000ULL,
1308 .ledma_base = 0x800040000ULL,
1309 .le_base = 0x800060000ULL,
1310 .sbi_base = 0xf02800000ULL,
1311 .vram_size = 0x00100000,
1312 .nvram_size = 0x2000,
1313 .esp_irq = 3,
1314 .le_irq = 4,
1315 .clock_irq = 14,
1316 .clock1_irq = 10,
1317 .ms_kb_irq = 12,
1318 .ser_irq = 12,
1319 .machine_id = 0x80,
1320 .iounit_version = 0x03000000,
1321 .max_mem = 0xf00000000ULL,
1322 .default_cpu_model = "TI SuperSparc II",
1323 },
1324 /* SS-2000 */
1325 {
1326 .iounit_bases = {
1327 0xfe0200000ULL,
1328 0xfe1200000ULL,
1329 0xfe2200000ULL,
1330 0xfe3200000ULL,
1331 0xfe4200000ULL,
1332 },
1333 .tcx_base = 0x820000000ULL,
1334 .slavio_base = 0xf00000000ULL,
1335 .ms_kb_base = 0xf00240000ULL,
1336 .serial_base = 0xf00200000ULL,
1337 .nvram_base = 0xf00280000ULL,
1338 .counter_base = 0xf00300000ULL,
1339 .espdma_base = 0x800081000ULL,
1340 .esp_base = 0x800080000ULL,
1341 .ledma_base = 0x800040000ULL,
1342 .le_base = 0x800060000ULL,
1343 .sbi_base = 0xf02800000ULL,
1344 .vram_size = 0x00100000,
1345 .nvram_size = 0x2000,
1346 .esp_irq = 3,
1347 .le_irq = 4,
1348 .clock_irq = 14,
1349 .clock1_irq = 10,
1350 .ms_kb_irq = 12,
1351 .ser_irq = 12,
1352 .machine_id = 0x80,
1353 .iounit_version = 0x03000000,
1354 .max_mem = 0xf00000000ULL,
1355 .default_cpu_model = "TI SuperSparc II",
1356 },
1357 };
1358
1359 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1360 const char *boot_device,
1361 DisplayState *ds, const char *kernel_filename,
1362 const char *kernel_cmdline,
1363 const char *initrd_filename, const char *cpu_model)
1364 {
1365 CPUState *env, *envs[MAX_CPUS];
1366 unsigned int i;
1367 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1368 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1369 *espdma_irq, *ledma_irq;
1370 qemu_irq *esp_reset, *le_reset;
1371 unsigned long prom_offset, kernel_size;
1372 int ret;
1373 char buf[1024];
1374 int drive_index;
1375
1376 /* init CPUs */
1377 if (!cpu_model)
1378 cpu_model = hwdef->default_cpu_model;
1379
1380 for (i = 0; i < smp_cpus; i++) {
1381 env = cpu_init(cpu_model);
1382 if (!env) {
1383 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1384 exit(1);
1385 }
1386 cpu_sparc_set_id(env, i);
1387 envs[i] = env;
1388 if (i == 0) {
1389 qemu_register_reset(main_cpu_reset, env);
1390 } else {
1391 qemu_register_reset(secondary_cpu_reset, env);
1392 env->halted = 1;
1393 }
1394 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
1395 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1396 env->prom_addr = hwdef->slavio_base;
1397 }
1398
1399 for (i = smp_cpus; i < MAX_CPUS; i++)
1400 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1401
1402 /* allocate RAM */
1403 if ((uint64_t)RAM_size > hwdef->max_mem) {
1404 fprintf(stderr,
1405 "qemu: Too much memory for this machine: %d, maximum %d\n",
1406 (unsigned int)(RAM_size / (1024 * 1024)),
1407 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1408 exit(1);
1409 }
1410 cpu_register_physical_memory(0, RAM_size, 0);
1411
1412 /* load boot prom */
1413 prom_offset = RAM_size + hwdef->vram_size;
1414 cpu_register_physical_memory(hwdef->slavio_base,
1415 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1416 TARGET_PAGE_MASK,
1417 prom_offset | IO_MEM_ROM);
1418
1419 if (bios_name == NULL)
1420 bios_name = PROM_FILENAME;
1421 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1422 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1423 if (ret < 0 || ret > PROM_SIZE_MAX)
1424 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1425 if (ret < 0 || ret > PROM_SIZE_MAX) {
1426 fprintf(stderr, "qemu: could not load prom '%s'\n",
1427 buf);
1428 exit(1);
1429 }
1430
1431 /* set up devices */
1432 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1433
1434 for (i = 0; i < MAX_IOUNITS; i++)
1435 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1436 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1437 hwdef->iounit_version,
1438 sbi_irq[hwdef->me_irq]);
1439
1440 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1441 iounits[0], &espdma_irq, &esp_reset);
1442
1443 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1444 iounits[0], &ledma_irq, &le_reset);
1445
1446 if (graphic_depth != 8 && graphic_depth != 24) {
1447 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1448 exit (1);
1449 }
1450 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1451 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1452
1453 if (nd_table[0].model == NULL
1454 || strcmp(nd_table[0].model, "lance") == 0) {
1455 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1456 } else if (strcmp(nd_table[0].model, "?") == 0) {
1457 fprintf(stderr, "qemu: Supported NICs: lance\n");
1458 exit (1);
1459 } else {
1460 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1461 exit (1);
1462 }
1463
1464 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1465 hwdef->nvram_size, 8);
1466
1467 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1468 sbi_cpu_irq, smp_cpus);
1469
1470 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1471 nographic);
1472 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1473 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1474 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1475 serial_hds[1], serial_hds[0]);
1476
1477 if (drive_get_max_bus(IF_SCSI) > 0) {
1478 fprintf(stderr, "qemu: too many SCSI bus\n");
1479 exit(1);
1480 }
1481
1482 main_esp = esp_init(hwdef->esp_base, 2,
1483 espdma_memory_read, espdma_memory_write,
1484 espdma, *espdma_irq, esp_reset);
1485
1486 for (i = 0; i < ESP_MAX_DEVS; i++) {
1487 drive_index = drive_get_index(IF_SCSI, 0, i);
1488 if (drive_index == -1)
1489 continue;
1490 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1491 }
1492
1493 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1494 RAM_size);
1495
1496 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1497 boot_device, RAM_size, kernel_size, graphic_width,
1498 graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
1499 }
1500
1501 /* SPARCserver 1000 hardware initialisation */
1502 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1503 const char *boot_device, DisplayState *ds,
1504 const char *kernel_filename, const char *kernel_cmdline,
1505 const char *initrd_filename, const char *cpu_model)
1506 {
1507 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1508 kernel_cmdline, initrd_filename, cpu_model);
1509 }
1510
1511 /* SPARCcenter 2000 hardware initialisation */
1512 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1513 const char *boot_device, DisplayState *ds,
1514 const char *kernel_filename, const char *kernel_cmdline,
1515 const char *initrd_filename, const char *cpu_model)
1516 {
1517 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1518 kernel_cmdline, initrd_filename, cpu_model);
1519 }
1520
1521 QEMUMachine ss1000_machine = {
1522 "SS-1000",
1523 "Sun4d platform, SPARCserver 1000",
1524 ss1000_init,
1525 PROM_SIZE_MAX + TCX_SIZE,
1526 };
1527
1528 QEMUMachine ss2000_machine = {
1529 "SS-2000",
1530 "Sun4d platform, SPARCcenter 2000",
1531 ss2000_init,
1532 PROM_SIZE_MAX + TCX_SIZE,
1533 };
Samsung s3c2440 and arm920t support for the mini2440 dev board