2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include "host-utils.h"
31 #include "qemu-common.h"
33 #define DO_SINGLE_STEP
35 #define ALPHA_DEBUG_DISAS
38 typedef struct DisasContext DisasContext
;
42 #if !defined (CONFIG_USER_ONLY)
48 /* global register indexes */
50 static TCGv cpu_ir
[31];
53 /* dyngen register indexes */
57 static char cpu_reg_names
[10*4+21*5];
59 #include "gen-icount.h"
61 static void alpha_translate_init(void)
65 static int done_init
= 0;
70 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
72 #if TARGET_LONG_BITS > HOST_LONG_BITS
73 cpu_T
[0] = tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
,
74 offsetof(CPUState
, t0
), "T0");
75 cpu_T
[1] = tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
,
76 offsetof(CPUState
, t1
), "T1");
78 cpu_T
[0] = tcg_global_reg_new(TCG_TYPE_I64
, TCG_AREG1
, "T0");
79 cpu_T
[1] = tcg_global_reg_new(TCG_TYPE_I64
, TCG_AREG2
, "T1");
83 for (i
= 0; i
< 31; i
++) {
84 sprintf(p
, "ir%d", i
);
85 cpu_ir
[i
] = tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
,
86 offsetof(CPUState
, ir
[i
]), p
);
87 p
+= (i
< 10) ? 4 : 5;
90 cpu_pc
= tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
,
91 offsetof(CPUState
, pc
), "pc");
93 /* register helpers */
95 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
101 static always_inline
void gen_op_nop (void)
103 #if defined(GENERATE_NOP)
108 #define GEN32(func, NAME) \
109 static GenOpFunc *NAME ## _table [32] = { \
110 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
111 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
112 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
113 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
114 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
115 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
116 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
117 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
119 static always_inline void func (int n) \
121 NAME ## _table[n](); \
125 /* Special hacks for fir31 */
126 #define gen_op_load_FT0_fir31 gen_op_reset_FT0
127 #define gen_op_load_FT1_fir31 gen_op_reset_FT1
128 #define gen_op_load_FT2_fir31 gen_op_reset_FT2
129 #define gen_op_store_FT0_fir31 gen_op_nop
130 #define gen_op_store_FT1_fir31 gen_op_nop
131 #define gen_op_store_FT2_fir31 gen_op_nop
132 #define gen_op_cmov_fir31 gen_op_nop
133 GEN32(gen_op_load_FT0_fir
, gen_op_load_FT0_fir
);
134 GEN32(gen_op_load_FT1_fir
, gen_op_load_FT1_fir
);
135 GEN32(gen_op_load_FT2_fir
, gen_op_load_FT2_fir
);
136 GEN32(gen_op_store_FT0_fir
, gen_op_store_FT0_fir
);
137 GEN32(gen_op_store_FT1_fir
, gen_op_store_FT1_fir
);
138 GEN32(gen_op_store_FT2_fir
, gen_op_store_FT2_fir
);
139 GEN32(gen_op_cmov_fir
, gen_op_cmov_fir
);
141 static always_inline
void gen_load_fir (DisasContext
*ctx
, int firn
, int Tn
)
145 gen_op_load_FT0_fir(firn
);
148 gen_op_load_FT1_fir(firn
);
151 gen_op_load_FT2_fir(firn
);
156 static always_inline
void gen_store_fir (DisasContext
*ctx
, int firn
, int Tn
)
160 gen_op_store_FT0_fir(firn
);
163 gen_op_store_FT1_fir(firn
);
166 gen_op_store_FT2_fir(firn
);
172 #if defined(CONFIG_USER_ONLY)
173 #define OP_LD_TABLE(width) \
174 static GenOpFunc *gen_op_ld##width[] = { \
175 &gen_op_ld##width##_raw, \
177 #define OP_ST_TABLE(width) \
178 static GenOpFunc *gen_op_st##width[] = { \
179 &gen_op_st##width##_raw, \
182 #define OP_LD_TABLE(width) \
183 static GenOpFunc *gen_op_ld##width[] = { \
184 &gen_op_ld##width##_kernel, \
185 &gen_op_ld##width##_executive, \
186 &gen_op_ld##width##_supervisor, \
187 &gen_op_ld##width##_user, \
189 #define OP_ST_TABLE(width) \
190 static GenOpFunc *gen_op_st##width[] = { \
191 &gen_op_st##width##_kernel, \
192 &gen_op_st##width##_executive, \
193 &gen_op_st##width##_supervisor, \
194 &gen_op_st##width##_user, \
198 #define GEN_LD(width) \
199 OP_LD_TABLE(width); \
200 static always_inline void gen_ld##width (DisasContext *ctx) \
202 (*gen_op_ld##width[ctx->mem_idx])(); \
205 #define GEN_ST(width) \
206 OP_ST_TABLE(width); \
207 static always_inline void gen_st##width (DisasContext *ctx) \
209 (*gen_op_st##width[ctx->mem_idx])(); \
221 #if 0 /* currently unused */
232 static always_inline
void _gen_op_bcond (DisasContext
*ctx
)
234 #if 0 // Qemu does not know how to do this...
235 gen_op_bcond(ctx
->pc
);
237 gen_op_bcond(ctx
->pc
>> 32, ctx
->pc
);
241 static always_inline
void gen_excp (DisasContext
*ctx
,
242 int exception
, int error_code
)
246 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
);
247 tmp1
= tcg_const_i32(exception
);
248 tmp2
= tcg_const_i32(error_code
);
249 tcg_gen_helper_0_2(helper_excp
, tmp1
, tmp2
);
254 static always_inline
void gen_invalid (DisasContext
*ctx
)
256 gen_excp(ctx
, EXCP_OPCDEC
, 0);
259 static always_inline
void gen_load_mem (DisasContext
*ctx
,
260 void (*gen_load_op
)(DisasContext
*ctx
),
261 int ra
, int rb
, int32_t disp16
,
264 if (ra
== 31 && disp16
== 0) {
269 tcg_gen_addi_i64(cpu_T
[0], cpu_ir
[rb
], disp16
);
271 tcg_gen_movi_i64(cpu_T
[0], disp16
);
273 tcg_gen_andi_i64(cpu_T
[0], cpu_T
[0], ~0x7);
276 tcg_gen_mov_i64(cpu_ir
[ra
], cpu_T
[1]);
280 static always_inline
void gen_store_mem (DisasContext
*ctx
,
281 void (*gen_store_op
)(DisasContext
*ctx
),
282 int ra
, int rb
, int32_t disp16
,
286 tcg_gen_addi_i64(cpu_T
[0], cpu_ir
[rb
], disp16
);
288 tcg_gen_movi_i64(cpu_T
[0], disp16
);
290 tcg_gen_andi_i64(cpu_T
[0], cpu_T
[0], ~0x7);
292 tcg_gen_mov_i64(cpu_T
[1], cpu_ir
[ra
]);
294 tcg_gen_movi_i64(cpu_T
[1], 0);
295 (*gen_store_op
)(ctx
);
298 static always_inline
void gen_load_fmem (DisasContext
*ctx
,
299 void (*gen_load_fop
)(DisasContext
*ctx
),
300 int ra
, int rb
, int32_t disp16
)
303 tcg_gen_addi_i64(cpu_T
[0], cpu_ir
[rb
], disp16
);
305 tcg_gen_movi_i64(cpu_T
[0], disp16
);
306 (*gen_load_fop
)(ctx
);
307 gen_store_fir(ctx
, ra
, 1);
310 static always_inline
void gen_store_fmem (DisasContext
*ctx
,
311 void (*gen_store_fop
)(DisasContext
*ctx
),
312 int ra
, int rb
, int32_t disp16
)
315 tcg_gen_addi_i64(cpu_T
[0], cpu_ir
[rb
], disp16
);
317 tcg_gen_movi_i64(cpu_T
[0], disp16
);
318 gen_load_fir(ctx
, ra
, 1);
319 (*gen_store_fop
)(ctx
);
322 static always_inline
void gen_bcond (DisasContext
*ctx
,
324 int ra
, int32_t disp16
, int mask
)
328 l1
= gen_new_label();
329 l2
= gen_new_label();
330 if (likely(ra
!= 31)) {
332 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
333 tcg_gen_andi_i64(tmp
, cpu_ir
[ra
], 1);
334 tcg_gen_brcondi_i64(cond
, tmp
, 0, l1
);
337 tcg_gen_brcondi_i64(cond
, cpu_ir
[ra
], 0, l1
);
339 /* Very uncommon case - Do not bother to optimize. */
340 TCGv tmp
= tcg_const_i64(0);
341 tcg_gen_brcondi_i64(cond
, tmp
, 0, l1
);
344 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
);
347 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
+ (int64_t)(disp16
<< 2));
351 static always_inline
void gen_fbcond (DisasContext
*ctx
,
352 void (*gen_test_op
)(void),
353 int ra
, int32_t disp16
)
355 tcg_gen_movi_i64(cpu_T
[1], ctx
->pc
+ (int64_t)(disp16
<< 2));
356 gen_load_fir(ctx
, ra
, 0);
361 static always_inline
void gen_cmov (DisasContext
*ctx
,
363 int ra
, int rb
, int rc
,
364 int islit
, uint8_t lit
, int mask
)
368 if (unlikely(rc
== 31))
371 l1
= gen_new_label();
375 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
376 tcg_gen_andi_i64(tmp
, cpu_ir
[ra
], 1);
377 tcg_gen_brcondi_i64(inv_cond
, tmp
, 0, l1
);
380 tcg_gen_brcondi_i64(inv_cond
, cpu_ir
[ra
], 0, l1
);
382 /* Very uncommon case - Do not bother to optimize. */
383 TCGv tmp
= tcg_const_i64(0);
384 tcg_gen_brcondi_i64(inv_cond
, tmp
, 0, l1
);
389 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
391 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
395 static always_inline
void gen_farith2 (DisasContext
*ctx
,
396 void (*gen_arith_fop
)(void),
399 gen_load_fir(ctx
, rb
, 0);
401 gen_store_fir(ctx
, rc
, 0);
404 static always_inline
void gen_farith3 (DisasContext
*ctx
,
405 void (*gen_arith_fop
)(void),
406 int ra
, int rb
, int rc
)
408 gen_load_fir(ctx
, ra
, 0);
409 gen_load_fir(ctx
, rb
, 1);
411 gen_store_fir(ctx
, rc
, 0);
414 static always_inline
void gen_fcmov (DisasContext
*ctx
,
415 void (*gen_test_fop
)(void),
416 int ra
, int rb
, int rc
)
418 gen_load_fir(ctx
, ra
, 0);
419 gen_load_fir(ctx
, rb
, 1);
424 static always_inline
void gen_fti (DisasContext
*ctx
,
425 void (*gen_move_fop
)(void),
428 gen_load_fir(ctx
, rc
, 0);
431 tcg_gen_mov_i64(cpu_ir
[ra
], cpu_T
[0]);
434 static always_inline
void gen_itf (DisasContext
*ctx
,
435 void (*gen_move_fop
)(void),
439 tcg_gen_mov_i64(cpu_T
[0], cpu_ir
[ra
]);
441 tcg_gen_movi_i64(cpu_T
[0], 0);
443 gen_store_fir(ctx
, rc
, 0);
446 /* EXTWH, EXTWH, EXTLH, EXTQH */
447 static always_inline
void gen_ext_h(void (*tcg_gen_ext_i64
)(TCGv t0
, TCGv t1
),
448 int ra
, int rb
, int rc
,
449 int islit
, uint8_t lit
)
451 if (unlikely(rc
== 31))
457 tcg_gen_shli_i64(cpu_ir
[rc
], cpu_ir
[ra
], 64 - ((lit
& 7) * 8));
459 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[ra
]);
462 tmp1
= tcg_temp_new(TCG_TYPE_I64
);
463 tcg_gen_andi_i64(tmp1
, cpu_ir
[rb
], 7);
464 tcg_gen_shli_i64(tmp1
, tmp1
, 3);
465 tmp2
= tcg_const_i64(64);
466 tcg_gen_sub_i64(tmp1
, tmp2
, tmp1
);
468 tcg_gen_shl_i64(cpu_ir
[rc
], cpu_ir
[ra
], tmp1
);
472 tcg_gen_ext_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
474 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
477 /* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
478 static always_inline
void gen_ext_l(void (*tcg_gen_ext_i64
)(TCGv t0
, TCGv t1
),
479 int ra
, int rb
, int rc
,
480 int islit
, uint8_t lit
)
482 if (unlikely(rc
== 31))
487 tcg_gen_shri_i64(cpu_ir
[rc
], cpu_ir
[ra
], (lit
& 7) * 8);
489 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
490 tcg_gen_andi_i64(tmp
, cpu_ir
[rb
], 7);
491 tcg_gen_shli_i64(tmp
, tmp
, 3);
492 tcg_gen_shr_i64(cpu_ir
[rc
], cpu_ir
[ra
], tmp
);
496 tcg_gen_ext_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
498 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
501 /* Code to call arith3 helpers */
502 static always_inline
void gen_arith3_helper(void *helper
,
503 int ra
, int rb
, int rc
,
504 int islit
, uint8_t lit
)
506 if (unlikely(rc
== 31))
511 TCGv tmp
= tcg_const_i64(lit
);
512 tcg_gen_helper_1_2(helper
, cpu_ir
[rc
], cpu_ir
[ra
], tmp
);
515 tcg_gen_helper_1_2(helper
, cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
517 TCGv tmp1
= tcg_const_i64(0);
519 TCGv tmp2
= tcg_const_i64(lit
);
520 tcg_gen_helper_1_2(helper
, cpu_ir
[rc
], tmp1
, tmp2
);
523 tcg_gen_helper_1_2(helper
, cpu_ir
[rc
], tmp1
, cpu_ir
[rb
]);
528 static always_inline
void gen_cmp(TCGCond cond
,
529 int ra
, int rb
, int rc
,
530 int islit
, uint8_t lit
)
535 if (unlikely(rc
== 31))
538 l1
= gen_new_label();
539 l2
= gen_new_label();
542 tmp
= tcg_temp_new(TCG_TYPE_I64
);
543 tcg_gen_mov_i64(tmp
, cpu_ir
[ra
]);
545 tmp
= tcg_const_i64(0);
547 tcg_gen_brcondi_i64(cond
, tmp
, lit
, l1
);
549 tcg_gen_brcond_i64(cond
, tmp
, cpu_ir
[rb
], l1
);
551 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
554 tcg_gen_movi_i64(cpu_ir
[rc
], 1);
558 static always_inline
int translate_one (DisasContext
*ctx
, uint32_t insn
)
561 int32_t disp21
, disp16
, disp12
;
563 uint8_t opc
, ra
, rb
, rc
, sbz
, fpfn
, fn7
, fn2
, islit
;
567 /* Decode all instruction fields */
569 ra
= (insn
>> 21) & 0x1F;
570 rb
= (insn
>> 16) & 0x1F;
572 sbz
= (insn
>> 13) & 0x07;
573 islit
= (insn
>> 12) & 1;
574 if (rb
== 31 && !islit
) {
578 lit
= (insn
>> 13) & 0xFF;
579 palcode
= insn
& 0x03FFFFFF;
580 disp21
= ((int32_t)((insn
& 0x001FFFFF) << 11)) >> 11;
581 disp16
= (int16_t)(insn
& 0x0000FFFF);
582 disp12
= (int32_t)((insn
& 0x00000FFF) << 20) >> 20;
583 fn16
= insn
& 0x0000FFFF;
584 fn11
= (insn
>> 5) & 0x000007FF;
586 fn7
= (insn
>> 5) & 0x0000007F;
587 fn2
= (insn
>> 5) & 0x00000003;
589 #if defined ALPHA_DEBUG_DISAS
590 if (logfile
!= NULL
) {
591 fprintf(logfile
, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
592 opc
, ra
, rb
, rc
, disp16
);
598 if (palcode
>= 0x80 && palcode
< 0xC0) {
599 /* Unprivileged PAL call */
600 gen_excp(ctx
, EXCP_CALL_PAL
+ ((palcode
& 0x1F) << 6), 0);
601 #if !defined (CONFIG_USER_ONLY)
602 } else if (palcode
< 0x40) {
603 /* Privileged PAL code */
604 if (ctx
->mem_idx
& 1)
607 gen_excp(ctx
, EXCP_CALL_PALP
+ ((palcode
& 0x1F) << 6), 0);
610 /* Invalid PAL call */
638 if (likely(ra
!= 31)) {
640 tcg_gen_addi_i64(cpu_ir
[ra
], cpu_ir
[rb
], disp16
);
642 tcg_gen_movi_i64(cpu_ir
[ra
], disp16
);
647 if (likely(ra
!= 31)) {
649 tcg_gen_addi_i64(cpu_ir
[ra
], cpu_ir
[rb
], disp16
<< 16);
651 tcg_gen_movi_i64(cpu_ir
[ra
], disp16
<< 16);
656 if (!(ctx
->amask
& AMASK_BWX
))
658 if (likely(ra
!= 31)) {
659 TCGv addr
= tcg_temp_new(TCG_TYPE_I64
);
661 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
663 tcg_gen_movi_i64(addr
, disp16
);
664 tcg_gen_qemu_ld8u(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
670 if (likely(ra
!= 31)) {
671 TCGv addr
= tcg_temp_new(TCG_TYPE_I64
);
673 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
674 tcg_gen_andi_i64(addr
, addr
, ~0x7);
676 tcg_gen_movi_i64(addr
, disp16
& ~0x7);
677 tcg_gen_qemu_ld64(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
683 if (!(ctx
->amask
& AMASK_BWX
))
685 if (likely(ra
!= 31)) {
686 TCGv addr
= tcg_temp_new(TCG_TYPE_I64
);
688 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
690 tcg_gen_movi_i64(addr
, disp16
);
691 tcg_gen_qemu_ld16u(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
699 if (!(ctx
->amask
& AMASK_BWX
))
701 addr
= tcg_temp_new(TCG_TYPE_I64
);
703 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
705 tcg_gen_movi_i64(addr
, disp16
);
707 tcg_gen_qemu_st16(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
709 TCGv zero
= tcg_const_i64(0);
710 tcg_gen_qemu_st16(zero
, addr
, ctx
->mem_idx
);
720 if (!(ctx
->amask
& AMASK_BWX
))
722 addr
= tcg_temp_new(TCG_TYPE_I64
);
724 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
726 tcg_gen_movi_i64(addr
, disp16
);
728 tcg_gen_qemu_st8(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
730 TCGv zero
= tcg_const_i64(0);
731 tcg_gen_qemu_st8(zero
, addr
, ctx
->mem_idx
);
740 TCGv addr
= tcg_temp_new(TCG_TYPE_I64
);
742 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
743 tcg_gen_andi_i64(addr
, addr
, ~0x7);
745 tcg_gen_movi_i64(addr
, disp16
& ~0x7);
747 tcg_gen_qemu_st64(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
749 TCGv zero
= tcg_const_i64(0);
750 tcg_gen_qemu_st64(zero
, addr
, ctx
->mem_idx
);
760 if (likely(rc
!= 31)) {
763 tcg_gen_addi_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
764 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
766 tcg_gen_add_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
767 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
771 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
773 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
779 if (likely(rc
!= 31)) {
781 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
782 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 2);
784 tcg_gen_addi_i64(tmp
, tmp
, lit
);
786 tcg_gen_add_i64(tmp
, tmp
, cpu_ir
[rb
]);
787 tcg_gen_ext32s_i64(cpu_ir
[rc
], tmp
);
791 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
793 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
799 if (likely(rc
!= 31)) {
802 tcg_gen_subi_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
804 tcg_gen_sub_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
805 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
808 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
810 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
811 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
817 if (likely(rc
!= 31)) {
819 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
820 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 2);
822 tcg_gen_subi_i64(tmp
, tmp
, lit
);
824 tcg_gen_sub_i64(tmp
, tmp
, cpu_ir
[rb
]);
825 tcg_gen_ext32s_i64(cpu_ir
[rc
], tmp
);
829 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
831 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
832 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
839 gen_arith3_helper(helper_cmpbge
, ra
, rb
, rc
, islit
, lit
);
843 if (likely(rc
!= 31)) {
845 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
846 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 3);
848 tcg_gen_addi_i64(tmp
, tmp
, lit
);
850 tcg_gen_add_i64(tmp
, tmp
, cpu_ir
[rb
]);
851 tcg_gen_ext32s_i64(cpu_ir
[rc
], tmp
);
855 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
857 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
863 if (likely(rc
!= 31)) {
865 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
866 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 3);
868 tcg_gen_subi_i64(tmp
, tmp
, lit
);
870 tcg_gen_sub_i64(tmp
, tmp
, cpu_ir
[rb
]);
871 tcg_gen_ext32s_i64(cpu_ir
[rc
], tmp
);
875 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
877 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
878 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
885 gen_cmp(TCG_COND_LTU
, ra
, rb
, rc
, islit
, lit
);
889 if (likely(rc
!= 31)) {
892 tcg_gen_addi_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
894 tcg_gen_add_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
897 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
899 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
905 if (likely(rc
!= 31)) {
907 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
908 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 2);
910 tcg_gen_addi_i64(cpu_ir
[rc
], tmp
, lit
);
912 tcg_gen_add_i64(cpu_ir
[rc
], tmp
, cpu_ir
[rb
]);
916 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
918 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
924 if (likely(rc
!= 31)) {
927 tcg_gen_subi_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
929 tcg_gen_sub_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
932 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
934 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
940 if (likely(rc
!= 31)) {
942 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
943 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 2);
945 tcg_gen_subi_i64(cpu_ir
[rc
], tmp
, lit
);
947 tcg_gen_sub_i64(cpu_ir
[rc
], tmp
, cpu_ir
[rb
]);
951 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
953 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
959 gen_cmp(TCG_COND_EQ
, ra
, rb
, rc
, islit
, lit
);
963 if (likely(rc
!= 31)) {
965 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
966 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 3);
968 tcg_gen_addi_i64(cpu_ir
[rc
], tmp
, lit
);
970 tcg_gen_add_i64(cpu_ir
[rc
], tmp
, cpu_ir
[rb
]);
974 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
976 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
982 if (likely(rc
!= 31)) {
984 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
985 tcg_gen_shli_i64(tmp
, cpu_ir
[ra
], 3);
987 tcg_gen_subi_i64(cpu_ir
[rc
], tmp
, lit
);
989 tcg_gen_sub_i64(cpu_ir
[rc
], tmp
, cpu_ir
[rb
]);
993 tcg_gen_movi_i64(cpu_ir
[rc
], -lit
);
995 tcg_gen_neg_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1001 gen_cmp(TCG_COND_LEU
, ra
, rb
, rc
, islit
, lit
);
1005 gen_arith3_helper(helper_addlv
, ra
, rb
, rc
, islit
, lit
);
1009 gen_arith3_helper(helper_sublv
, ra
, rb
, rc
, islit
, lit
);
1013 gen_cmp(TCG_COND_LT
, ra
, rb
, rc
, islit
, lit
);
1017 gen_arith3_helper(helper_addqv
, ra
, rb
, rc
, islit
, lit
);
1021 gen_arith3_helper(helper_subqv
, ra
, rb
, rc
, islit
, lit
);
1025 gen_cmp(TCG_COND_LE
, ra
, rb
, rc
, islit
, lit
);
1035 if (likely(rc
!= 31)) {
1037 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1039 tcg_gen_andi_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1041 tcg_gen_and_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1046 if (likely(rc
!= 31)) {
1049 tcg_gen_andi_i64(cpu_ir
[rc
], cpu_ir
[ra
], ~lit
);
1051 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
1052 tcg_gen_not_i64(tmp
, cpu_ir
[rb
]);
1053 tcg_gen_and_i64(cpu_ir
[rc
], cpu_ir
[ra
], tmp
);
1057 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1062 gen_cmov(ctx
, TCG_COND_EQ
, ra
, rb
, rc
, islit
, lit
, 1);
1066 gen_cmov(ctx
, TCG_COND_NE
, ra
, rb
, rc
, islit
, lit
, 1);
1070 if (likely(rc
!= 31)) {
1073 tcg_gen_ori_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1075 tcg_gen_or_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1078 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
1080 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1086 gen_cmov(ctx
, TCG_COND_NE
, ra
, rb
, rc
, islit
, lit
, 0);
1090 gen_cmov(ctx
, TCG_COND_EQ
, ra
, rb
, rc
, islit
, lit
, 0);
1094 if (likely(rc
!= 31)) {
1097 tcg_gen_ori_i64(cpu_ir
[rc
], cpu_ir
[ra
], ~lit
);
1099 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
1100 tcg_gen_not_i64(tmp
, cpu_ir
[rb
]);
1101 tcg_gen_or_i64(cpu_ir
[rc
], cpu_ir
[ra
], tmp
);
1106 tcg_gen_movi_i64(cpu_ir
[rc
], ~lit
);
1108 tcg_gen_not_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1114 if (likely(rc
!= 31)) {
1117 tcg_gen_xori_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1119 tcg_gen_xor_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1122 tcg_gen_movi_i64(cpu_ir
[rc
], lit
);
1124 tcg_gen_mov_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1130 gen_cmov(ctx
, TCG_COND_GE
, ra
, rb
, rc
, islit
, lit
, 0);
1134 gen_cmov(ctx
, TCG_COND_LT
, ra
, rb
, rc
, islit
, lit
, 0);
1138 if (likely(rc
!= 31)) {
1141 tcg_gen_xori_i64(cpu_ir
[rc
], cpu_ir
[ra
], ~lit
);
1143 TCGv tmp
= tcg_temp_new(TCG_TYPE_I64
);
1144 tcg_gen_not_i64(tmp
, cpu_ir
[rb
]);
1145 tcg_gen_xor_i64(cpu_ir
[rc
], cpu_ir
[ra
], tmp
);
1150 tcg_gen_movi_i64(cpu_ir
[rc
], ~lit
);
1152 tcg_gen_not_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1158 if (likely(rc
!= 31)) {
1160 tcg_gen_movi_i64(cpu_ir
[rc
], helper_amask(lit
));
1162 tcg_gen_helper_1_1(helper_amask
, cpu_ir
[rc
], cpu_ir
[rb
]);
1167 gen_cmov(ctx
, TCG_COND_GT
, ra
, rb
, rc
, islit
, lit
, 0);
1171 gen_cmov(ctx
, TCG_COND_LE
, ra
, rb
, rc
, islit
, lit
, 0);
1176 tcg_gen_helper_1_0(helper_load_implver
, cpu_ir
[rc
]);
1186 gen_arith3_helper(helper_mskbl
, ra
, rb
, rc
, islit
, lit
);
1190 gen_ext_l(&tcg_gen_ext8u_i64
, ra
, rb
, rc
, islit
, lit
);
1194 gen_arith3_helper(helper_insbl
, ra
, rb
, rc
, islit
, lit
);
1198 gen_arith3_helper(helper_mskwl
, ra
, rb
, rc
, islit
, lit
);
1202 gen_ext_l(&tcg_gen_ext16u_i64
, ra
, rb
, rc
, islit
, lit
);
1206 gen_arith3_helper(helper_inswl
, ra
, rb
, rc
, islit
, lit
);
1210 gen_arith3_helper(helper_mskll
, ra
, rb
, rc
, islit
, lit
);
1214 gen_ext_l(&tcg_gen_ext32u_i64
, ra
, rb
, rc
, islit
, lit
);
1218 gen_arith3_helper(helper_insll
, ra
, rb
, rc
, islit
, lit
);
1222 gen_arith3_helper(helper_zap
, ra
, rb
, rc
, islit
, lit
);
1226 gen_arith3_helper(helper_zapnot
, ra
, rb
, rc
, islit
, lit
);
1230 gen_arith3_helper(helper_mskql
, ra
, rb
, rc
, islit
, lit
);
1234 if (likely(rc
!= 31)) {
1237 tcg_gen_shri_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
& 0x3f);
1239 TCGv shift
= tcg_temp_new(TCG_TYPE_I64
);
1240 tcg_gen_andi_i64(shift
, cpu_ir
[rb
], 0x3f);
1241 tcg_gen_shr_i64(cpu_ir
[rc
], cpu_ir
[ra
], shift
);
1242 tcg_temp_free(shift
);
1245 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1250 gen_ext_l(NULL
, ra
, rb
, rc
, islit
, lit
);
1254 if (likely(rc
!= 31)) {
1257 tcg_gen_shli_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
& 0x3f);
1259 TCGv shift
= tcg_temp_new(TCG_TYPE_I64
);
1260 tcg_gen_andi_i64(shift
, cpu_ir
[rb
], 0x3f);
1261 tcg_gen_shl_i64(cpu_ir
[rc
], cpu_ir
[ra
], shift
);
1262 tcg_temp_free(shift
);
1265 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1270 gen_arith3_helper(helper_insql
, ra
, rb
, rc
, islit
, lit
);
1274 if (likely(rc
!= 31)) {
1277 tcg_gen_sari_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
& 0x3f);
1279 TCGv shift
= tcg_temp_new(TCG_TYPE_I64
);
1280 tcg_gen_andi_i64(shift
, cpu_ir
[rb
], 0x3f);
1281 tcg_gen_sar_i64(cpu_ir
[rc
], cpu_ir
[ra
], shift
);
1282 tcg_temp_free(shift
);
1285 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1290 gen_arith3_helper(helper_mskwh
, ra
, rb
, rc
, islit
, lit
);
1294 gen_arith3_helper(helper_inswh
, ra
, rb
, rc
, islit
, lit
);
1298 gen_ext_h(&tcg_gen_ext16u_i64
, ra
, rb
, rc
, islit
, lit
);
1302 gen_arith3_helper(helper_msklh
, ra
, rb
, rc
, islit
, lit
);
1306 gen_arith3_helper(helper_inslh
, ra
, rb
, rc
, islit
, lit
);
1310 gen_ext_h(&tcg_gen_ext16u_i64
, ra
, rb
, rc
, islit
, lit
);
1314 gen_arith3_helper(helper_mskqh
, ra
, rb
, rc
, islit
, lit
);
1318 gen_arith3_helper(helper_insqh
, ra
, rb
, rc
, islit
, lit
);
1322 gen_ext_h(NULL
, ra
, rb
, rc
, islit
, lit
);
1332 if (likely(rc
!= 31)) {
1334 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1337 tcg_gen_muli_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1339 tcg_gen_mul_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1340 tcg_gen_ext32s_i64(cpu_ir
[rc
], cpu_ir
[rc
]);
1346 if (likely(rc
!= 31)) {
1348 tcg_gen_movi_i64(cpu_ir
[rc
], 0);
1350 tcg_gen_muli_i64(cpu_ir
[rc
], cpu_ir
[ra
], lit
);
1352 tcg_gen_mul_i64(cpu_ir
[rc
], cpu_ir
[ra
], cpu_ir
[rb
]);
1357 gen_arith3_helper(helper_umulh
, ra
, rb
, rc
, islit
, lit
);
1361 gen_arith3_helper(helper_mullv
, ra
, rb
, rc
, islit
, lit
);
1365 gen_arith3_helper(helper_mulqv
, ra
, rb
, rc
, islit
, lit
);
1372 switch (fpfn
) { /* f11 & 0x3F */
1375 if (!(ctx
->amask
& AMASK_FIX
))
1377 gen_itf(ctx
, &gen_op_itofs
, ra
, rc
);
1381 if (!(ctx
->amask
& AMASK_FIX
))
1383 gen_farith2(ctx
, &gen_op_sqrtf
, rb
, rc
);
1387 if (!(ctx
->amask
& AMASK_FIX
))
1389 gen_farith2(ctx
, &gen_op_sqrts
, rb
, rc
);
1393 if (!(ctx
->amask
& AMASK_FIX
))
1396 gen_itf(ctx
, &gen_op_itoff
, ra
, rc
);
1403 if (!(ctx
->amask
& AMASK_FIX
))
1405 gen_itf(ctx
, &gen_op_itoft
, ra
, rc
);
1409 if (!(ctx
->amask
& AMASK_FIX
))
1411 gen_farith2(ctx
, &gen_op_sqrtg
, rb
, rc
);
1415 if (!(ctx
->amask
& AMASK_FIX
))
1417 gen_farith2(ctx
, &gen_op_sqrtt
, rb
, rc
);
1424 /* VAX floating point */
1425 /* XXX: rounding mode and trap are ignored (!) */
1426 switch (fpfn
) { /* f11 & 0x3F */
1429 gen_farith3(ctx
, &gen_op_addf
, ra
, rb
, rc
);
1433 gen_farith3(ctx
, &gen_op_subf
, ra
, rb
, rc
);
1437 gen_farith3(ctx
, &gen_op_mulf
, ra
, rb
, rc
);
1441 gen_farith3(ctx
, &gen_op_divf
, ra
, rb
, rc
);
1446 gen_farith2(ctx
, &gen_op_cvtdg
, rb
, rc
);
1453 gen_farith3(ctx
, &gen_op_addg
, ra
, rb
, rc
);
1457 gen_farith3(ctx
, &gen_op_subg
, ra
, rb
, rc
);
1461 gen_farith3(ctx
, &gen_op_mulg
, ra
, rb
, rc
);
1465 gen_farith3(ctx
, &gen_op_divg
, ra
, rb
, rc
);
1469 gen_farith3(ctx
, &gen_op_cmpgeq
, ra
, rb
, rc
);
1473 gen_farith3(ctx
, &gen_op_cmpglt
, ra
, rb
, rc
);
1477 gen_farith3(ctx
, &gen_op_cmpgle
, ra
, rb
, rc
);
1481 gen_farith2(ctx
, &gen_op_cvtgf
, rb
, rc
);
1486 gen_farith2(ctx
, &gen_op_cvtgd
, rb
, rc
);
1493 gen_farith2(ctx
, &gen_op_cvtgq
, rb
, rc
);
1497 gen_farith2(ctx
, &gen_op_cvtqf
, rb
, rc
);
1501 gen_farith2(ctx
, &gen_op_cvtqg
, rb
, rc
);
1508 /* IEEE floating-point */
1509 /* XXX: rounding mode and traps are ignored (!) */
1510 switch (fpfn
) { /* f11 & 0x3F */
1513 gen_farith3(ctx
, &gen_op_adds
, ra
, rb
, rc
);
1517 gen_farith3(ctx
, &gen_op_subs
, ra
, rb
, rc
);
1521 gen_farith3(ctx
, &gen_op_muls
, ra
, rb
, rc
);
1525 gen_farith3(ctx
, &gen_op_divs
, ra
, rb
, rc
);
1529 gen_farith3(ctx
, &gen_op_addt
, ra
, rb
, rc
);
1533 gen_farith3(ctx
, &gen_op_subt
, ra
, rb
, rc
);
1537 gen_farith3(ctx
, &gen_op_mult
, ra
, rb
, rc
);
1541 gen_farith3(ctx
, &gen_op_divt
, ra
, rb
, rc
);
1545 gen_farith3(ctx
, &gen_op_cmptun
, ra
, rb
, rc
);
1549 gen_farith3(ctx
, &gen_op_cmpteq
, ra
, rb
, rc
);
1553 gen_farith3(ctx
, &gen_op_cmptlt
, ra
, rb
, rc
);
1557 gen_farith3(ctx
, &gen_op_cmptle
, ra
, rb
, rc
);
1560 /* XXX: incorrect */
1561 if (fn11
== 0x2AC) {
1563 gen_farith2(ctx
, &gen_op_cvtst
, rb
, rc
);
1566 gen_farith2(ctx
, &gen_op_cvtts
, rb
, rc
);
1571 gen_farith2(ctx
, &gen_op_cvttq
, rb
, rc
);
1575 gen_farith2(ctx
, &gen_op_cvtqs
, rb
, rc
);
1579 gen_farith2(ctx
, &gen_op_cvtqt
, rb
, rc
);
1589 gen_farith2(ctx
, &gen_op_cvtlq
, rb
, rc
);
1594 if (ra
== 31 && rc
== 31) {
1599 gen_load_fir(ctx
, rb
, 0);
1600 gen_store_fir(ctx
, rc
, 0);
1603 gen_farith3(ctx
, &gen_op_cpys
, ra
, rb
, rc
);
1608 gen_farith2(ctx
, &gen_op_cpysn
, rb
, rc
);
1612 gen_farith2(ctx
, &gen_op_cpyse
, rb
, rc
);
1616 gen_load_fir(ctx
, ra
, 0);
1617 gen_op_store_fpcr();
1622 gen_store_fir(ctx
, ra
, 0);
1626 gen_fcmov(ctx
, &gen_op_cmpfeq
, ra
, rb
, rc
);
1630 gen_fcmov(ctx
, &gen_op_cmpfne
, ra
, rb
, rc
);
1634 gen_fcmov(ctx
, &gen_op_cmpflt
, ra
, rb
, rc
);
1638 gen_fcmov(ctx
, &gen_op_cmpfge
, ra
, rb
, rc
);
1642 gen_fcmov(ctx
, &gen_op_cmpfle
, ra
, rb
, rc
);
1646 gen_fcmov(ctx
, &gen_op_cmpfgt
, ra
, rb
, rc
);
1650 gen_farith2(ctx
, &gen_op_cvtql
, rb
, rc
);
1654 gen_farith2(ctx
, &gen_op_cvtqlv
, rb
, rc
);
1658 gen_farith2(ctx
, &gen_op_cvtqlsv
, rb
, rc
);
1665 switch ((uint16_t)disp16
) {
1668 /* No-op. Just exit from the current tb */
1673 /* No-op. Just exit from the current tb */
1695 tcg_gen_helper_1_0(helper_load_pcc
, cpu_ir
[ra
]);
1700 tcg_gen_helper_1_0(helper_rc
, cpu_ir
[ra
]);
1704 /* XXX: TODO: evict tb cache at address rb */
1714 tcg_gen_helper_1_0(helper_rs
, cpu_ir
[ra
]);
1725 /* HW_MFPR (PALcode) */
1726 #if defined (CONFIG_USER_ONLY)
1731 gen_op_mfpr(insn
& 0xFF);
1733 tcg_gen_mov_i64(cpu_ir
[ra
], cpu_T
[0]);
1738 tcg_gen_movi_i64(cpu_ir
[ra
], ctx
->pc
);
1740 tcg_gen_andi_i64(cpu_pc
, cpu_ir
[rb
], ~3);
1742 tcg_gen_movi_i64(cpu_pc
, 0);
1743 /* Those four jumps only differ by the branch prediction hint */
1761 /* HW_LD (PALcode) */
1762 #if defined (CONFIG_USER_ONLY)
1768 tcg_gen_mov_i64(cpu_T
[0], cpu_ir
[rb
]);
1770 tcg_gen_movi_i64(cpu_T
[0], 0);
1771 tcg_gen_movi_i64(cpu_T
[1], disp12
);
1772 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1773 switch ((insn
>> 12) & 0xF) {
1775 /* Longword physical access */
1779 /* Quadword physical access */
1783 /* Longword physical access with lock */
1787 /* Quadword physical access with lock */
1791 /* Longword virtual PTE fetch */
1792 gen_op_ldl_kernel();
1795 /* Quadword virtual PTE fetch */
1796 gen_op_ldq_kernel();
1805 /* Longword virtual access */
1806 gen_op_ld_phys_to_virt();
1810 /* Quadword virtual access */
1811 gen_op_ld_phys_to_virt();
1815 /* Longword virtual access with protection check */
1819 /* Quadword virtual access with protection check */
1823 /* Longword virtual access with altenate access mode */
1824 gen_op_set_alt_mode();
1825 gen_op_ld_phys_to_virt();
1827 gen_op_restore_mode();
1830 /* Quadword virtual access with altenate access mode */
1831 gen_op_set_alt_mode();
1832 gen_op_ld_phys_to_virt();
1834 gen_op_restore_mode();
1837 /* Longword virtual access with alternate access mode and
1840 gen_op_set_alt_mode();
1842 gen_op_restore_mode();
1845 /* Quadword virtual access with alternate access mode and
1848 gen_op_set_alt_mode();
1850 gen_op_restore_mode();
1854 tcg_gen_mov_i64(cpu_ir
[ra
], cpu_T
[1]);
1861 if (!(ctx
->amask
& AMASK_BWX
))
1863 if (likely(rc
!= 31)) {
1865 tcg_gen_movi_i64(cpu_ir
[rc
], (int64_t)((int8_t)lit
));
1867 tcg_gen_ext8s_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1872 if (!(ctx
->amask
& AMASK_BWX
))
1874 if (likely(rc
!= 31)) {
1876 tcg_gen_movi_i64(cpu_ir
[rc
], (int64_t)((int16_t)lit
));
1878 tcg_gen_ext16s_i64(cpu_ir
[rc
], cpu_ir
[rb
]);
1883 if (!(ctx
->amask
& AMASK_CIX
))
1885 if (likely(rc
!= 31)) {
1887 tcg_gen_movi_i64(cpu_ir
[rc
], ctpop64(lit
));
1889 tcg_gen_helper_1_1(helper_ctpop
, cpu_ir
[rc
], cpu_ir
[rb
]);
1894 if (!(ctx
->amask
& AMASK_MVI
))
1901 if (!(ctx
->amask
& AMASK_CIX
))
1903 if (likely(rc
!= 31)) {
1905 tcg_gen_movi_i64(cpu_ir
[rc
], clz64(lit
));
1907 tcg_gen_helper_1_1(helper_ctlz
, cpu_ir
[rc
], cpu_ir
[rb
]);
1912 if (!(ctx
->amask
& AMASK_CIX
))
1914 if (likely(rc
!= 31)) {
1916 tcg_gen_movi_i64(cpu_ir
[rc
], ctz64(lit
));
1918 tcg_gen_helper_1_1(helper_cttz
, cpu_ir
[rc
], cpu_ir
[rb
]);
1923 if (!(ctx
->amask
& AMASK_MVI
))
1930 if (!(ctx
->amask
& AMASK_MVI
))
1937 if (!(ctx
->amask
& AMASK_MVI
))
1944 if (!(ctx
->amask
& AMASK_MVI
))
1951 if (!(ctx
->amask
& AMASK_MVI
))
1958 if (!(ctx
->amask
& AMASK_MVI
))
1965 if (!(ctx
->amask
& AMASK_MVI
))
1972 if (!(ctx
->amask
& AMASK_MVI
))
1979 if (!(ctx
->amask
& AMASK_MVI
))
1986 if (!(ctx
->amask
& AMASK_MVI
))
1993 if (!(ctx
->amask
& AMASK_MVI
))
2000 if (!(ctx
->amask
& AMASK_MVI
))
2007 if (!(ctx
->amask
& AMASK_FIX
))
2009 gen_fti(ctx
, &gen_op_ftoit
, ra
, rb
);
2013 if (!(ctx
->amask
& AMASK_FIX
))
2015 gen_fti(ctx
, &gen_op_ftois
, ra
, rb
);
2022 /* HW_MTPR (PALcode) */
2023 #if defined (CONFIG_USER_ONLY)
2029 tcg_gen_mov_i64(cpu_T
[0], cpu_ir
[ra
]);
2031 tcg_gen_movi_i64(cpu_T
[0], 0);
2032 gen_op_mtpr(insn
& 0xFF);
2037 /* HW_REI (PALcode) */
2038 #if defined (CONFIG_USER_ONLY)
2048 tcg_gen_mov_i64(cpu_T
[0], cpu_ir
[rb
]);
2050 tcg_gen_movi_i64(cpu_T
[0], 0);
2051 tcg_gen_movi_i64(cpu_T
[1], (((int64_t)insn
<< 51) >> 51));
2052 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
2059 /* HW_ST (PALcode) */
2060 #if defined (CONFIG_USER_ONLY)
2066 tcg_gen_addi_i64(cpu_T
[0], cpu_ir
[rb
], disp12
);
2068 tcg_gen_movi_i64(cpu_T
[0], disp12
);
2070 tcg_gen_mov_i64(cpu_T
[1], cpu_ir
[ra
]);
2072 tcg_gen_movi_i64(cpu_T
[1], 0);
2073 switch ((insn
>> 12) & 0xF) {
2075 /* Longword physical access */
2079 /* Quadword physical access */
2083 /* Longword physical access with lock */
2087 /* Quadword physical access with lock */
2091 /* Longword virtual access */
2092 gen_op_st_phys_to_virt();
2096 /* Quadword virtual access */
2097 gen_op_st_phys_to_virt();
2119 /* Longword virtual access with alternate access mode */
2120 gen_op_set_alt_mode();
2121 gen_op_st_phys_to_virt();
2123 gen_op_restore_mode();
2126 /* Quadword virtual access with alternate access mode */
2127 gen_op_set_alt_mode();
2128 gen_op_st_phys_to_virt();
2130 gen_op_restore_mode();
2145 gen_load_fmem(ctx
, &gen_ldf
, ra
, rb
, disp16
);
2153 gen_load_fmem(ctx
, &gen_ldg
, ra
, rb
, disp16
);
2160 gen_load_fmem(ctx
, &gen_lds
, ra
, rb
, disp16
);
2164 gen_load_fmem(ctx
, &gen_ldt
, ra
, rb
, disp16
);
2169 gen_store_fmem(ctx
, &gen_stf
, ra
, rb
, disp16
);
2177 gen_store_fmem(ctx
, &gen_stg
, ra
, rb
, disp16
);
2184 gen_store_fmem(ctx
, &gen_sts
, ra
, rb
, disp16
);
2188 gen_store_fmem(ctx
, &gen_stt
, ra
, rb
, disp16
);
2192 if (likely(ra
!= 31)) {
2193 TCGv addr
= tcg_temp_new(TCG_TYPE_I64
);
2195 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
2197 tcg_gen_movi_i64(addr
, disp16
);
2198 tcg_gen_qemu_ld32s(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
2199 tcg_temp_free(addr
);
2204 if (likely(ra
!= 31)) {
2205 TCGv addr
= tcg_temp_new(TCG_TYPE_I64
);
2207 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
2209 tcg_gen_movi_i64(addr
, disp16
);
2210 tcg_gen_qemu_ld64(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
2211 tcg_temp_free(addr
);
2216 gen_load_mem(ctx
, &gen_ldl_l
, ra
, rb
, disp16
, 0);
2220 gen_load_mem(ctx
, &gen_ldq_l
, ra
, rb
, disp16
, 0);
2225 TCGv addr
= tcg_temp_new(TCG_TYPE_I64
);
2227 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
2229 tcg_gen_movi_i64(addr
, disp16
);
2231 tcg_gen_qemu_st32(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
2233 TCGv zero
= tcg_const_i64(0);
2234 tcg_gen_qemu_st32(zero
, addr
, ctx
->mem_idx
);
2235 tcg_temp_free(zero
);
2237 tcg_temp_free(addr
);
2243 TCGv addr
= tcg_temp_new(TCG_TYPE_I64
);
2245 tcg_gen_addi_i64(addr
, cpu_ir
[rb
], disp16
);
2247 tcg_gen_movi_i64(addr
, disp16
);
2249 tcg_gen_qemu_st64(cpu_ir
[ra
], addr
, ctx
->mem_idx
);
2251 TCGv zero
= tcg_const_i64(0);
2252 tcg_gen_qemu_st64(zero
, addr
, ctx
->mem_idx
);
2253 tcg_temp_free(zero
);
2255 tcg_temp_free(addr
);
2260 gen_store_mem(ctx
, &gen_stl_c
, ra
, rb
, disp16
, 0);
2264 gen_store_mem(ctx
, &gen_stq_c
, ra
, rb
, disp16
, 0);
2269 tcg_gen_movi_i64(cpu_ir
[ra
], ctx
->pc
);
2270 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
+ (int64_t)(disp21
<< 2));
2275 gen_fbcond(ctx
, &gen_op_cmpfeq
, ra
, disp16
);
2280 gen_fbcond(ctx
, &gen_op_cmpflt
, ra
, disp16
);
2285 gen_fbcond(ctx
, &gen_op_cmpfle
, ra
, disp16
);
2291 tcg_gen_movi_i64(cpu_ir
[ra
], ctx
->pc
);
2292 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
+ (int64_t)(disp21
<< 2));
2297 gen_fbcond(ctx
, &gen_op_cmpfne
, ra
, disp16
);
2302 gen_fbcond(ctx
, &gen_op_cmpfge
, ra
, disp16
);
2307 gen_fbcond(ctx
, &gen_op_cmpfgt
, ra
, disp16
);
2312 gen_bcond(ctx
, TCG_COND_EQ
, ra
, disp16
, 1);
2317 gen_bcond(ctx
, TCG_COND_EQ
, ra
, disp16
, 0);
2322 gen_bcond(ctx
, TCG_COND_LT
, ra
, disp16
, 0);
2327 gen_bcond(ctx
, TCG_COND_LE
, ra
, disp16
, 0);
2332 gen_bcond(ctx
, TCG_COND_NE
, ra
, disp16
, 1);
2337 gen_bcond(ctx
, TCG_COND_NE
, ra
, disp16
, 0);
2342 gen_bcond(ctx
, TCG_COND_GE
, ra
, disp16
, 0);
2347 gen_bcond(ctx
, TCG_COND_GT
, ra
, disp16
, 0);
2359 static always_inline
void gen_intermediate_code_internal (CPUState
*env
,
2360 TranslationBlock
*tb
,
2363 #if defined ALPHA_DEBUG_DISAS
2364 static int insn_count
;
2366 DisasContext ctx
, *ctxp
= &ctx
;
2367 target_ulong pc_start
;
2369 uint16_t *gen_opc_end
;
2376 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2378 ctx
.amask
= env
->amask
;
2379 #if defined (CONFIG_USER_ONLY)
2382 ctx
.mem_idx
= ((env
->ps
>> 3) & 3);
2383 ctx
.pal_mode
= env
->ipr
[IPR_EXC_ADDR
] & 1;
2386 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2388 max_insns
= CF_COUNT_MASK
;
2391 for (ret
= 0; ret
== 0;) {
2392 if (env
->nb_breakpoints
> 0) {
2393 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
2394 if (env
->breakpoints
[j
] == ctx
.pc
) {
2395 gen_excp(&ctx
, EXCP_DEBUG
, 0);
2401 j
= gen_opc_ptr
- gen_opc_buf
;
2405 gen_opc_instr_start
[lj
++] = 0;
2406 gen_opc_pc
[lj
] = ctx
.pc
;
2407 gen_opc_instr_start
[lj
] = 1;
2408 gen_opc_icount
[lj
] = num_insns
;
2411 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
2413 #if defined ALPHA_DEBUG_DISAS
2415 if (logfile
!= NULL
) {
2416 fprintf(logfile
, "pc " TARGET_FMT_lx
" mem_idx %d\n",
2417 ctx
.pc
, ctx
.mem_idx
);
2420 insn
= ldl_code(ctx
.pc
);
2421 #if defined ALPHA_DEBUG_DISAS
2423 if (logfile
!= NULL
) {
2424 fprintf(logfile
, "opcode %08x %d\n", insn
, insn_count
);
2429 ret
= translate_one(ctxp
, insn
);
2432 /* if we reach a page boundary or are single stepping, stop
2435 if (((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
2436 (env
->singlestep_enabled
) ||
2437 num_insns
>= max_insns
) {
2440 #if defined (DO_SINGLE_STEP)
2444 if (ret
!= 1 && ret
!= 3) {
2445 tcg_gen_movi_i64(cpu_pc
, ctx
.pc
);
2447 #if defined (DO_TB_FLUSH)
2448 tcg_gen_helper_0_0(helper_tb_flush
);
2450 if (tb
->cflags
& CF_LAST_IO
)
2452 /* Generate the return instruction */
2454 gen_icount_end(tb
, num_insns
);
2455 *gen_opc_ptr
= INDEX_op_end
;
2457 j
= gen_opc_ptr
- gen_opc_buf
;
2460 gen_opc_instr_start
[lj
++] = 0;
2462 tb
->size
= ctx
.pc
- pc_start
;
2463 tb
->icount
= num_insns
;
2465 #if defined ALPHA_DEBUG_DISAS
2466 if (loglevel
& CPU_LOG_TB_CPU
) {
2467 cpu_dump_state(env
, logfile
, fprintf
, 0);
2469 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2470 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
2471 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 1);
2472 fprintf(logfile
, "\n");
2477 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
2479 gen_intermediate_code_internal(env
, tb
, 0);
2482 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
2484 gen_intermediate_code_internal(env
, tb
, 1);
2487 CPUAlphaState
* cpu_alpha_init (const char *cpu_model
)
2492 env
= qemu_mallocz(sizeof(CPUAlphaState
));
2496 alpha_translate_init();
2498 /* XXX: should not be hardcoded */
2499 env
->implver
= IMPLVER_2106x
;
2501 #if defined (CONFIG_USER_ONLY)
2505 /* Initialize IPR */
2506 hwpcb
= env
->ipr
[IPR_PCBB
];
2507 env
->ipr
[IPR_ASN
] = 0;
2508 env
->ipr
[IPR_ASTEN
] = 0;
2509 env
->ipr
[IPR_ASTSR
] = 0;
2510 env
->ipr
[IPR_DATFX
] = 0;
2512 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2513 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2514 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2515 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2516 env
->ipr
[IPR_FEN
] = 0;
2517 env
->ipr
[IPR_IPL
] = 31;
2518 env
->ipr
[IPR_MCES
] = 0;
2519 env
->ipr
[IPR_PERFMON
] = 0; /* Implementation specific */
2520 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2521 env
->ipr
[IPR_SISR
] = 0;
2522 env
->ipr
[IPR_VIRBND
] = -1ULL;
2527 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
2528 unsigned long searched_pc
, int pc_pos
, void *puc
)
2530 env
->pc
= gen_opc_pc
[pc_pos
];