hw/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3 /* PC-style peripherals (also used by other machines).  */
   4
   5 /* serial.c */
   6
   7 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
   8                          CharDriverState *chr);
   9 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
  10                              qemu_irq irq, int baudbase,
  11                              CharDriverState *chr, int ioregister);
  12 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
  13 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
  14 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
  15 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
  16 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
  17 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
  18
  19 /* parallel.c */
  20
  21 typedef struct ParallelState ParallelState;
  22 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
  23 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
  24
  25 /* i8259.c */
  26
  27 typedef struct PicState2 PicState2;
  28 extern PicState2 *isa_pic;
  29 void pic_set_irq(int irq, int level);
  30 void pic_set_irq_new(void *opaque, int irq, int level);
  31 qemu_irq *i8259_init(qemu_irq parent_irq);
  32 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
  33                           void *alt_irq_opaque);
  34 int pic_read_irq(PicState2 *s);
  35 void pic_update_irq(PicState2 *s);
  36 uint32_t pic_intack_read(PicState2 *s);
  37 void pic_info(void);
  38 void irq_info(void);
  39
  40 /* APIC */
  41 typedef struct IOAPICState IOAPICState;
  42
  43 int apic_init(CPUState *env);
  44 int apic_accept_pic_intr(CPUState *env);
  45 void apic_deliver_pic_intr(CPUState *env, int level);
  46 int apic_get_interrupt(CPUState *env);
  47 IOAPICState *ioapic_init(void);
  48 void ioapic_set_irq(void *opaque, int vector, int level);
  49
  50 /* i8254.c */
  51
  52 #define PIT_FREQ 1193182
  53
  54 typedef struct PITState PITState;
  55
  56 PITState *pit_init(int base, qemu_irq irq);
  57 void pit_set_gate(PITState *pit, int channel, int val);
  58 int pit_get_gate(PITState *pit, int channel);
  59 int pit_get_initial_count(PITState *pit, int channel);
  60 int pit_get_mode(PITState *pit, int channel);
  61 int pit_get_out(PITState *pit, int channel, int64_t current_time);
  62
  63 /* vmport.c */
  64 void vmport_init(void);
  65 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
  66
  67 /* vmmouse.c */
  68 void *vmmouse_init(void *m);
  69
  70 /* pckbd.c */
  71
  72 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
  73 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
  74                    target_phys_addr_t base, int it_shift);
  75
  76 /* mc146818rtc.c */
  77
  78 typedef struct RTCState RTCState;
  79
  80 RTCState *rtc_init(int base, qemu_irq irq);
  81 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
  82 void rtc_set_memory(RTCState *s, int addr, int val);
  83 void rtc_set_date(RTCState *s, const struct tm *tm);
  84
  85 /* pc.c */
  86 extern int fd_bootchk;
  87
  88 void ioport_set_a20(int enable);
  89 int ioport_get_a20(void);
  90
  91 /* acpi.c */
  92 extern int acpi_enabled;
  93 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
  94                        qemu_irq sci_irq);
  95 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
  96 void acpi_bios_init(void);
  97
  98 /* pcspk.c */
  99 void pcspk_init(PITState *);
 100 int pcspk_audio_init(AudioState *, qemu_irq *pic);
 101
 102 /* piix_pci.c */
 103 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
 104 void i440fx_set_smm(PCIDevice *d, int val);
 105 int piix3_init(PCIBus *bus, int devfn);
 106 void i440fx_init_memory_mappings(PCIDevice *d);
 107
 108 int piix4_init(PCIBus *bus, int devfn);
 109
 110 /* vga.c */
 111
 112 #ifndef TARGET_SPARC
 113 #define VGA_RAM_SIZE (8192 * 1024)
 114 #else
 115 #define VGA_RAM_SIZE (9 * 1024 * 1024)
 116 #endif
 117
 118 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
 119                  unsigned long vga_ram_offset, int vga_ram_size);
 120 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 121                  unsigned long vga_ram_offset, int vga_ram_size,
 122                  unsigned long vga_bios_offset, int vga_bios_size);
 123 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
 124                     unsigned long vga_ram_offset, int vga_ram_size,
 125                     target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
 126                     int it_shift);
 127
 128 /* cirrus_vga.c */
 129 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 130                          unsigned long vga_ram_offset, int vga_ram_size);
 131 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
 132                          unsigned long vga_ram_offset, int vga_ram_size);
 133
 134 /* ide.c */
 135 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
 136                   BlockDriverState *hd0, BlockDriverState *hd1);
 137 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
 138                          int secondary_ide_enabled);
 139 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 140                         qemu_irq *pic);
 141 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 142                         qemu_irq *pic);
 143
 144 /* ne2000.c */
 145
 146 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
 147
 148 #endif