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SMP half-idle fix.
[qemu/mini2440.git] / cpu-exec.c
blob058688fc77650ce68f3b2c5e39a66c1515f4ab95
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
51 #define reg_T2
52 #endif
53
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
58 {
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61 #endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67 #if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72 #endif
73 longjmp(env->jmp_env, 1);
74 }
75
76
77 static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80 {
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag = 1;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151 }
152
153 static inline TranslationBlock *tb_find_fast(void)
154 {
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162 #if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167 #elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
174 cs_base = 0;
175 pc = env->regs[15];
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
181 #else
182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
184 | env->psrs;
185 #endif
186 cs_base = env->npc;
187 pc = env->pc;
188 #elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
191 cs_base = 0;
192 pc = env->nip;
193 #elif defined(TARGET_MIPS)
194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
195 cs_base = 0;
196 pc = env->PC;
197 #elif defined(TARGET_M68K)
198 flags = env->fpcr & M68K_FPCR_PREC;
199 cs_base = 0;
200 pc = env->pc;
201 #elif defined(TARGET_SH4)
202 flags = env->sr & (SR_MD | SR_RB);
203 cs_base = 0; /* XXXXX */
204 pc = env->pc;
205 #else
206 #error unsupported CPU
207 #endif
208 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
209 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
210 tb->flags != flags, 0)) {
211 tb = tb_find_slow(pc, cs_base, flags);
212 /* Note: we do it here to avoid a gcc bug on Mac OS X when
213 doing it in tb_find_slow */
214 if (tb_invalidated_flag) {
215 /* as some TB could have been invalidated because
216 of memory exceptions while generating the code, we
217 must recompute the hash index here */
218 T0 = 0;
219 }
220 }
221 return tb;
222 }
223
224
225 /* main execution loop */
226
227 int cpu_exec(CPUState *env1)
228 {
229 #define DECLARE_HOST_REGS 1
230 #include "hostregs_helper.h"
231 #if defined(TARGET_SPARC)
232 #if defined(reg_REGWPTR)
233 uint32_t *saved_regwptr;
234 #endif
235 #endif
236 #if defined(__sparc__) && !defined(HOST_SOLARIS)
237 int saved_i7;
238 target_ulong tmp_T0;
239 #endif
240 int ret, interrupt_request;
241 void (*gen_func)(void);
242 TranslationBlock *tb;
243 uint8_t *tc_ptr;
244
245 #if defined(TARGET_I386)
246 /* handle exit of HALTED state */
247 if (env1->hflags & HF_HALTED_MASK) {
248 /* disable halt condition */
249 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
250 (env1->eflags & IF_MASK)) {
251 env1->hflags &= ~HF_HALTED_MASK;
252 } else {
253 return EXCP_HALTED;
254 }
255 }
256 #elif defined(TARGET_PPC)
257 if (env1->halted) {
258 if (env1->msr[MSR_EE] &&
259 (env1->interrupt_request &
260 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
261 env1->halted = 0;
262 } else {
263 return EXCP_HALTED;
264 }
265 }
266 #elif defined(TARGET_SPARC)
267 if (env1->halted) {
268 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
269 (env1->psret != 0)) {
270 env1->halted = 0;
271 } else {
272 return EXCP_HALTED;
273 }
274 }
275 #elif defined(TARGET_ARM)
276 if (env1->halted) {
277 /* An interrupt wakes the CPU even if the I and F CPSR bits are
278 set. */
279 if (env1->interrupt_request
280 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
281 env1->halted = 0;
282 } else {
283 return EXCP_HALTED;
284 }
285 }
286 #elif defined(TARGET_MIPS)
287 if (env1->halted) {
288 if (env1->interrupt_request &
289 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
290 env1->halted = 0;
291 } else {
292 return EXCP_HALTED;
293 }
294 }
295 #endif
296
297 cpu_single_env = env1;
298
299 /* first we save global registers */
300 #define SAVE_HOST_REGS 1
301 #include "hostregs_helper.h"
302 env = env1;
303 #if defined(__sparc__) && !defined(HOST_SOLARIS)
304 /* we also save i7 because longjmp may not restore it */
305 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
306 #endif
307
308 #if defined(TARGET_I386)
309 env_to_regs();
310 /* put eflags in CPU temporary format */
311 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
312 DF = 1 - (2 * ((env->eflags >> 10) & 1));
313 CC_OP = CC_OP_EFLAGS;
314 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
315 #elif defined(TARGET_ARM)
316 #elif defined(TARGET_SPARC)
317 #if defined(reg_REGWPTR)
318 saved_regwptr = REGWPTR;
319 #endif
320 #elif defined(TARGET_PPC)
321 #elif defined(TARGET_M68K)
322 env->cc_op = CC_OP_FLAGS;
323 env->cc_dest = env->sr & 0xf;
324 env->cc_x = (env->sr >> 4) & 1;
325 #elif defined(TARGET_MIPS)
326 #elif defined(TARGET_SH4)
327 /* XXXXX */
328 #else
329 #error unsupported target CPU
330 #endif
331 env->exception_index = -1;
332
333 /* prepare setjmp context for exception handling */
334 for(;;) {
335 if (setjmp(env->jmp_env) == 0) {
336 env->current_tb = NULL;
337 /* if an exception is pending, we execute it here */
338 if (env->exception_index >= 0) {
339 if (env->exception_index >= EXCP_INTERRUPT) {
340 /* exit request from the cpu execution loop */
341 ret = env->exception_index;
342 break;
343 } else if (env->user_mode_only) {
344 /* if user mode only, we simulate a fake exception
345 which will be handled outside the cpu execution
346 loop */
347 #if defined(TARGET_I386)
348 do_interrupt_user(env->exception_index,
349 env->exception_is_int,
350 env->error_code,
351 env->exception_next_eip);
352 #endif
353 ret = env->exception_index;
354 break;
355 } else {
356 #if defined(TARGET_I386)
357 /* simulate a real cpu exception. On i386, it can
358 trigger new exceptions, but we do not handle
359 double or triple faults yet. */
360 do_interrupt(env->exception_index,
361 env->exception_is_int,
362 env->error_code,
363 env->exception_next_eip, 0);
364 #elif defined(TARGET_PPC)
365 do_interrupt(env);
366 #elif defined(TARGET_MIPS)
367 do_interrupt(env);
368 #elif defined(TARGET_SPARC)
369 do_interrupt(env->exception_index);
370 #elif defined(TARGET_ARM)
371 do_interrupt(env);
372 #elif defined(TARGET_SH4)
373 do_interrupt(env);
374 #endif
375 }
376 env->exception_index = -1;
377 }
378 #ifdef USE_KQEMU
379 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
380 int ret;
381 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
382 ret = kqemu_cpu_exec(env);
383 /* put eflags in CPU temporary format */
384 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
385 DF = 1 - (2 * ((env->eflags >> 10) & 1));
386 CC_OP = CC_OP_EFLAGS;
387 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
388 if (ret == 1) {
389 /* exception */
390 longjmp(env->jmp_env, 1);
391 } else if (ret == 2) {
392 /* softmmu execution needed */
393 } else {
394 if (env->interrupt_request != 0) {
395 /* hardware interrupt will be executed just after */
396 } else {
397 /* otherwise, we restart */
398 longjmp(env->jmp_env, 1);
399 }
400 }
401 }
402 #endif
403
404 T0 = 0; /* force lookup of first TB */
405 for(;;) {
406 #if defined(__sparc__) && !defined(HOST_SOLARIS)
407 /* g1 can be modified by some libc? functions */
408 tmp_T0 = T0;
409 #endif
410 interrupt_request = env->interrupt_request;
411 if (__builtin_expect(interrupt_request, 0)) {
412 #if defined(TARGET_I386)
413 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
414 !(env->hflags & HF_SMM_MASK)) {
415 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
416 do_smm_enter();
417 #if defined(__sparc__) && !defined(HOST_SOLARIS)
418 tmp_T0 = 0;
419 #else
420 T0 = 0;
421 #endif
422 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
423 (env->eflags & IF_MASK) &&
424 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
425 int intno;
426 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
427 intno = cpu_get_pic_interrupt(env);
428 if (loglevel & CPU_LOG_TB_IN_ASM) {
429 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
430 }
431 do_interrupt(intno, 0, 0, 0, 1);
432 /* ensure that no TB jump will be modified as
433 the program flow was changed */
434 #if defined(__sparc__) && !defined(HOST_SOLARIS)
435 tmp_T0 = 0;
436 #else
437 T0 = 0;
438 #endif
439 }
440 #elif defined(TARGET_PPC)
441 #if 0
442 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
443 cpu_ppc_reset(env);
444 }
445 #endif
446 if (msr_ee != 0) {
447 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
448 /* Raise it */
449 env->exception_index = EXCP_EXTERNAL;
450 env->error_code = 0;
451 do_interrupt(env);
452 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
453 #if defined(__sparc__) && !defined(HOST_SOLARIS)
454 tmp_T0 = 0;
455 #else
456 T0 = 0;
457 #endif
458 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
459 /* Raise it */
460 env->exception_index = EXCP_DECR;
461 env->error_code = 0;
462 do_interrupt(env);
463 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
464 #if defined(__sparc__) && !defined(HOST_SOLARIS)
465 tmp_T0 = 0;
466 #else
467 T0 = 0;
468 #endif
469 }
470 }
471 #elif defined(TARGET_MIPS)
472 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
473 (env->CP0_Status & (1 << CP0St_IE)) &&
474 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
475 !(env->hflags & MIPS_HFLAG_EXL) &&
476 !(env->hflags & MIPS_HFLAG_ERL) &&
477 !(env->hflags & MIPS_HFLAG_DM)) {
478 /* Raise it */
479 env->exception_index = EXCP_EXT_INTERRUPT;
480 env->error_code = 0;
481 do_interrupt(env);
482 #if defined(__sparc__) && !defined(HOST_SOLARIS)
483 tmp_T0 = 0;
484 #else
485 T0 = 0;
486 #endif
487 }
488 #elif defined(TARGET_SPARC)
489 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
490 (env->psret != 0)) {
491 int pil = env->interrupt_index & 15;
492 int type = env->interrupt_index & 0xf0;
493
494 if (((type == TT_EXTINT) &&
495 (pil == 15 || pil > env->psrpil)) ||
496 type != TT_EXTINT) {
497 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
498 do_interrupt(env->interrupt_index);
499 env->interrupt_index = 0;
500 #if defined(__sparc__) && !defined(HOST_SOLARIS)
501 tmp_T0 = 0;
502 #else
503 T0 = 0;
504 #endif
505 }
506 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
507 //do_interrupt(0, 0, 0, 0, 0);
508 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
509 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
510 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
511 env->halted = 1;
512 env->exception_index = EXCP_HLT;
513 cpu_loop_exit();
514 }
515 #elif defined(TARGET_ARM)
516 if (interrupt_request & CPU_INTERRUPT_FIQ
517 && !(env->uncached_cpsr & CPSR_F)) {
518 env->exception_index = EXCP_FIQ;
519 do_interrupt(env);
520 }
521 if (interrupt_request & CPU_INTERRUPT_HARD
522 && !(env->uncached_cpsr & CPSR_I)) {
523 env->exception_index = EXCP_IRQ;
524 do_interrupt(env);
525 }
526 #elif defined(TARGET_SH4)
527 /* XXXXX */
528 #endif
529 /* Don't use the cached interupt_request value,
530 do_interrupt may have updated the EXITTB flag. */
531 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
532 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
533 /* ensure that no TB jump will be modified as
534 the program flow was changed */
535 #if defined(__sparc__) && !defined(HOST_SOLARIS)
536 tmp_T0 = 0;
537 #else
538 T0 = 0;
539 #endif
540 }
541 if (interrupt_request & CPU_INTERRUPT_EXIT) {
542 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
543 env->exception_index = EXCP_INTERRUPT;
544 cpu_loop_exit();
545 }
546 }
547 #ifdef DEBUG_EXEC
548 if ((loglevel & CPU_LOG_TB_CPU)) {
549 #if defined(TARGET_I386)
550 /* restore flags in standard format */
551 #ifdef reg_EAX
552 env->regs[R_EAX] = EAX;
553 #endif
554 #ifdef reg_EBX
555 env->regs[R_EBX] = EBX;
556 #endif
557 #ifdef reg_ECX
558 env->regs[R_ECX] = ECX;
559 #endif
560 #ifdef reg_EDX
561 env->regs[R_EDX] = EDX;
562 #endif
563 #ifdef reg_ESI
564 env->regs[R_ESI] = ESI;
565 #endif
566 #ifdef reg_EDI
567 env->regs[R_EDI] = EDI;
568 #endif
569 #ifdef reg_EBP
570 env->regs[R_EBP] = EBP;
571 #endif
572 #ifdef reg_ESP
573 env->regs[R_ESP] = ESP;
574 #endif
575 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
576 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
577 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
578 #elif defined(TARGET_ARM)
579 cpu_dump_state(env, logfile, fprintf, 0);
580 #elif defined(TARGET_SPARC)
581 REGWPTR = env->regbase + (env->cwp * 16);
582 env->regwptr = REGWPTR;
583 cpu_dump_state(env, logfile, fprintf, 0);
584 #elif defined(TARGET_PPC)
585 cpu_dump_state(env, logfile, fprintf, 0);
586 #elif defined(TARGET_M68K)
587 cpu_m68k_flush_flags(env, env->cc_op);
588 env->cc_op = CC_OP_FLAGS;
589 env->sr = (env->sr & 0xffe0)
590 | env->cc_dest | (env->cc_x << 4);
591 cpu_dump_state(env, logfile, fprintf, 0);
592 #elif defined(TARGET_MIPS)
593 cpu_dump_state(env, logfile, fprintf, 0);
594 #elif defined(TARGET_SH4)
595 cpu_dump_state(env, logfile, fprintf, 0);
596 #else
597 #error unsupported target CPU
598 #endif
599 }
600 #endif
601 tb = tb_find_fast();
602 #ifdef DEBUG_EXEC
603 if ((loglevel & CPU_LOG_EXEC)) {
604 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
605 (long)tb->tc_ptr, tb->pc,
606 lookup_symbol(tb->pc));
607 }
608 #endif
609 #if defined(__sparc__) && !defined(HOST_SOLARIS)
610 T0 = tmp_T0;
611 #endif
612 /* see if we can patch the calling TB. When the TB
613 spans two pages, we cannot safely do a direct
614 jump. */
615 {
616 if (T0 != 0 &&
617 #if USE_KQEMU
618 (env->kqemu_enabled != 2) &&
619 #endif
620 tb->page_addr[1] == -1
621 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
622 && (tb->cflags & CF_CODE_COPY) ==
623 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
624 #endif
625 ) {
626 spin_lock(&tb_lock);
627 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
628 #if defined(USE_CODE_COPY)
629 /* propagates the FP use info */
630 ((TranslationBlock *)(T0 & ~3))->cflags |=
631 (tb->cflags & CF_FP_USED);
632 #endif
633 spin_unlock(&tb_lock);
634 }
635 }
636 tc_ptr = tb->tc_ptr;
637 env->current_tb = tb;
638 /* execute the generated code */
639 gen_func = (void *)tc_ptr;
640 #if defined(__sparc__)
641 __asm__ __volatile__("call %0\n\t"
642 "mov %%o7,%%i0"
643 : /* no outputs */
644 : "r" (gen_func)
645 : "i0", "i1", "i2", "i3", "i4", "i5",
646 "l0", "l1", "l2", "l3", "l4", "l5",
647 "l6", "l7");
648 #elif defined(__arm__)
649 asm volatile ("mov pc, %0\n\t"
650 ".global exec_loop\n\t"
651 "exec_loop:\n\t"
652 : /* no outputs */
653 : "r" (gen_func)
654 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
655 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
656 {
657 if (!(tb->cflags & CF_CODE_COPY)) {
658 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
659 save_native_fp_state(env);
660 }
661 gen_func();
662 } else {
663 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
664 restore_native_fp_state(env);
665 }
666 /* we work with native eflags */
667 CC_SRC = cc_table[CC_OP].compute_all();
668 CC_OP = CC_OP_EFLAGS;
669 asm(".globl exec_loop\n"
670 "\n"
671 "debug1:\n"
672 " pushl %%ebp\n"
673 " fs movl %10, %9\n"
674 " fs movl %11, %%eax\n"
675 " andl $0x400, %%eax\n"
676 " fs orl %8, %%eax\n"
677 " pushl %%eax\n"
678 " popf\n"
679 " fs movl %%esp, %12\n"
680 " fs movl %0, %%eax\n"
681 " fs movl %1, %%ecx\n"
682 " fs movl %2, %%edx\n"
683 " fs movl %3, %%ebx\n"
684 " fs movl %4, %%esp\n"
685 " fs movl %5, %%ebp\n"
686 " fs movl %6, %%esi\n"
687 " fs movl %7, %%edi\n"
688 " fs jmp *%9\n"
689 "exec_loop:\n"
690 " fs movl %%esp, %4\n"
691 " fs movl %12, %%esp\n"
692 " fs movl %%eax, %0\n"
693 " fs movl %%ecx, %1\n"
694 " fs movl %%edx, %2\n"
695 " fs movl %%ebx, %3\n"
696 " fs movl %%ebp, %5\n"
697 " fs movl %%esi, %6\n"
698 " fs movl %%edi, %7\n"
699 " pushf\n"
700 " popl %%eax\n"
701 " movl %%eax, %%ecx\n"
702 " andl $0x400, %%ecx\n"
703 " shrl $9, %%ecx\n"
704 " andl $0x8d5, %%eax\n"
705 " fs movl %%eax, %8\n"
706 " movl $1, %%eax\n"
707 " subl %%ecx, %%eax\n"
708 " fs movl %%eax, %11\n"
709 " fs movl %9, %%ebx\n" /* get T0 value */
710 " popl %%ebp\n"
711 :
712 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
713 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
714 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
715 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
716 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
717 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
718 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
719 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
720 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
721 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
722 "a" (gen_func),
723 "m" (*(uint8_t *)offsetof(CPUState, df)),
724 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
725 : "%ecx", "%edx"
726 );
727 }
728 }
729 #elif defined(__ia64)
730 struct fptr {
731 void *ip;
732 void *gp;
733 } fp;
734
735 fp.ip = tc_ptr;
736 fp.gp = code_gen_buffer + 2 * (1 << 20);
737 (*(void (*)(void)) &fp)();
738 #else
739 gen_func();
740 #endif
741 env->current_tb = NULL;
742 /* reset soft MMU for next block (it can currently
743 only be set by a memory fault) */
744 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
745 if (env->hflags & HF_SOFTMMU_MASK) {
746 env->hflags &= ~HF_SOFTMMU_MASK;
747 /* do not allow linking to another block */
748 T0 = 0;
749 }
750 #endif
751 #if defined(USE_KQEMU)
752 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
753 if (kqemu_is_ok(env) &&
754 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
755 cpu_loop_exit();
756 }
757 #endif
758 }
759 } else {
760 env_to_regs();
761 }
762 } /* for(;;) */
763
764
765 #if defined(TARGET_I386)
766 #if defined(USE_CODE_COPY)
767 if (env->native_fp_regs) {
768 save_native_fp_state(env);
769 }
770 #endif
771 /* restore flags in standard format */
772 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
773 #elif defined(TARGET_ARM)
774 /* XXX: Save/restore host fpu exception state?. */
775 #elif defined(TARGET_SPARC)
776 #if defined(reg_REGWPTR)
777 REGWPTR = saved_regwptr;
778 #endif
779 #elif defined(TARGET_PPC)
780 #elif defined(TARGET_M68K)
781 cpu_m68k_flush_flags(env, env->cc_op);
782 env->cc_op = CC_OP_FLAGS;
783 env->sr = (env->sr & 0xffe0)
784 | env->cc_dest | (env->cc_x << 4);
785 #elif defined(TARGET_MIPS)
786 #elif defined(TARGET_SH4)
787 /* XXXXX */
788 #else
789 #error unsupported target CPU
790 #endif
791
792 /* restore global registers */
793 #if defined(__sparc__) && !defined(HOST_SOLARIS)
794 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
795 #endif
796 #include "hostregs_helper.h"
797
798 /* fail safe : never use cpu_single_env outside cpu_exec() */
799 cpu_single_env = NULL;
800 return ret;
801 }
802
803 /* must only be called from the generated code as an exception can be
804 generated */
805 void tb_invalidate_page_range(target_ulong start, target_ulong end)
806 {
807 /* XXX: cannot enable it yet because it yields to MMU exception
808 where NIP != read address on PowerPC */
809 #if 0
810 target_ulong phys_addr;
811 phys_addr = get_phys_addr_code(env, start);
812 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
813 #endif
814 }
815
816 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
817
818 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
819 {
820 CPUX86State *saved_env;
821
822 saved_env = env;
823 env = s;
824 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
825 selector &= 0xffff;
826 cpu_x86_load_seg_cache(env, seg_reg, selector,
827 (selector << 4), 0xffff, 0);
828 } else {
829 load_seg(seg_reg, selector);
830 }
831 env = saved_env;
832 }
833
834 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
835 {
836 CPUX86State *saved_env;
837
838 saved_env = env;
839 env = s;
840
841 helper_fsave((target_ulong)ptr, data32);
842
843 env = saved_env;
844 }
845
846 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
847 {
848 CPUX86State *saved_env;
849
850 saved_env = env;
851 env = s;
852
853 helper_frstor((target_ulong)ptr, data32);
854
855 env = saved_env;
856 }
857
858 #endif /* TARGET_I386 */
859
860 #if !defined(CONFIG_SOFTMMU)
861
862 #if defined(TARGET_I386)
863
864 /* 'pc' is the host PC at which the exception was raised. 'address' is
865 the effective address of the memory exception. 'is_write' is 1 if a
866 write caused the exception and otherwise 0'. 'old_set' is the
867 signal set which should be restored */
868 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
869 int is_write, sigset_t *old_set,
870 void *puc)
871 {
872 TranslationBlock *tb;
873 int ret;
874
875 if (cpu_single_env)
876 env = cpu_single_env; /* XXX: find a correct solution for multithread */
877 #if defined(DEBUG_SIGNAL)
878 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
879 pc, address, is_write, *(unsigned long *)old_set);
880 #endif
881 /* XXX: locking issue */
882 if (is_write && page_unprotect(h2g(address), pc, puc)) {
883 return 1;
884 }
885
886 /* see if it is an MMU fault */
887 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
888 ((env->hflags & HF_CPL_MASK) == 3), 0);
889 if (ret < 0)
890 return 0; /* not an MMU fault */
891 if (ret == 0)
892 return 1; /* the MMU fault was handled without causing real CPU fault */
893 /* now we have a real cpu fault */
894 tb = tb_find_pc(pc);
895 if (tb) {
896 /* the PC is inside the translated code. It means that we have
897 a virtual CPU fault */
898 cpu_restore_state(tb, env, pc, puc);
899 }
900 if (ret == 1) {
901 #if 0
902 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
903 env->eip, env->cr[2], env->error_code);
904 #endif
905 /* we restore the process signal mask as the sigreturn should
906 do it (XXX: use sigsetjmp) */
907 sigprocmask(SIG_SETMASK, old_set, NULL);
908 raise_exception_err(env->exception_index, env->error_code);
909 } else {
910 /* activate soft MMU for this block */
911 env->hflags |= HF_SOFTMMU_MASK;
912 cpu_resume_from_signal(env, puc);
913 }
914 /* never comes here */
915 return 1;
916 }
917
918 #elif defined(TARGET_ARM)
919 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
920 int is_write, sigset_t *old_set,
921 void *puc)
922 {
923 TranslationBlock *tb;
924 int ret;
925
926 if (cpu_single_env)
927 env = cpu_single_env; /* XXX: find a correct solution for multithread */
928 #if defined(DEBUG_SIGNAL)
929 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
930 pc, address, is_write, *(unsigned long *)old_set);
931 #endif
932 /* XXX: locking issue */
933 if (is_write && page_unprotect(h2g(address), pc, puc)) {
934 return 1;
935 }
936 /* see if it is an MMU fault */
937 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
938 if (ret < 0)
939 return 0; /* not an MMU fault */
940 if (ret == 0)
941 return 1; /* the MMU fault was handled without causing real CPU fault */
942 /* now we have a real cpu fault */
943 tb = tb_find_pc(pc);
944 if (tb) {
945 /* the PC is inside the translated code. It means that we have
946 a virtual CPU fault */
947 cpu_restore_state(tb, env, pc, puc);
948 }
949 /* we restore the process signal mask as the sigreturn should
950 do it (XXX: use sigsetjmp) */
951 sigprocmask(SIG_SETMASK, old_set, NULL);
952 cpu_loop_exit();
953 }
954 #elif defined(TARGET_SPARC)
955 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
956 int is_write, sigset_t *old_set,
957 void *puc)
958 {
959 TranslationBlock *tb;
960 int ret;
961
962 if (cpu_single_env)
963 env = cpu_single_env; /* XXX: find a correct solution for multithread */
964 #if defined(DEBUG_SIGNAL)
965 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
966 pc, address, is_write, *(unsigned long *)old_set);
967 #endif
968 /* XXX: locking issue */
969 if (is_write && page_unprotect(h2g(address), pc, puc)) {
970 return 1;
971 }
972 /* see if it is an MMU fault */
973 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
974 if (ret < 0)
975 return 0; /* not an MMU fault */
976 if (ret == 0)
977 return 1; /* the MMU fault was handled without causing real CPU fault */
978 /* now we have a real cpu fault */
979 tb = tb_find_pc(pc);
980 if (tb) {
981 /* the PC is inside the translated code. It means that we have
982 a virtual CPU fault */
983 cpu_restore_state(tb, env, pc, puc);
984 }
985 /* we restore the process signal mask as the sigreturn should
986 do it (XXX: use sigsetjmp) */
987 sigprocmask(SIG_SETMASK, old_set, NULL);
988 cpu_loop_exit();
989 }
990 #elif defined (TARGET_PPC)
991 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
992 int is_write, sigset_t *old_set,
993 void *puc)
994 {
995 TranslationBlock *tb;
996 int ret;
997
998 if (cpu_single_env)
999 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1000 #if defined(DEBUG_SIGNAL)
1001 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1002 pc, address, is_write, *(unsigned long *)old_set);
1003 #endif
1004 /* XXX: locking issue */
1005 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1006 return 1;
1007 }
1008
1009 /* see if it is an MMU fault */
1010 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1011 if (ret < 0)
1012 return 0; /* not an MMU fault */
1013 if (ret == 0)
1014 return 1; /* the MMU fault was handled without causing real CPU fault */
1015
1016 /* now we have a real cpu fault */
1017 tb = tb_find_pc(pc);
1018 if (tb) {
1019 /* the PC is inside the translated code. It means that we have
1020 a virtual CPU fault */
1021 cpu_restore_state(tb, env, pc, puc);
1022 }
1023 if (ret == 1) {
1024 #if 0
1025 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1026 env->nip, env->error_code, tb);
1027 #endif
1028 /* we restore the process signal mask as the sigreturn should
1029 do it (XXX: use sigsetjmp) */
1030 sigprocmask(SIG_SETMASK, old_set, NULL);
1031 do_raise_exception_err(env->exception_index, env->error_code);
1032 } else {
1033 /* activate soft MMU for this block */
1034 cpu_resume_from_signal(env, puc);
1035 }
1036 /* never comes here */
1037 return 1;
1038 }
1039
1040 #elif defined(TARGET_M68K)
1041 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1042 int is_write, sigset_t *old_set,
1043 void *puc)
1044 {
1045 TranslationBlock *tb;
1046 int ret;
1047
1048 if (cpu_single_env)
1049 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1050 #if defined(DEBUG_SIGNAL)
1051 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1052 pc, address, is_write, *(unsigned long *)old_set);
1053 #endif
1054 /* XXX: locking issue */
1055 if (is_write && page_unprotect(address, pc, puc)) {
1056 return 1;
1057 }
1058 /* see if it is an MMU fault */
1059 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1060 if (ret < 0)
1061 return 0; /* not an MMU fault */
1062 if (ret == 0)
1063 return 1; /* the MMU fault was handled without causing real CPU fault */
1064 /* now we have a real cpu fault */
1065 tb = tb_find_pc(pc);
1066 if (tb) {
1067 /* the PC is inside the translated code. It means that we have
1068 a virtual CPU fault */
1069 cpu_restore_state(tb, env, pc, puc);
1070 }
1071 /* we restore the process signal mask as the sigreturn should
1072 do it (XXX: use sigsetjmp) */
1073 sigprocmask(SIG_SETMASK, old_set, NULL);
1074 cpu_loop_exit();
1075 /* never comes here */
1076 return 1;
1077 }
1078
1079 #elif defined (TARGET_MIPS)
1080 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1081 int is_write, sigset_t *old_set,
1082 void *puc)
1083 {
1084 TranslationBlock *tb;
1085 int ret;
1086
1087 if (cpu_single_env)
1088 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1089 #if defined(DEBUG_SIGNAL)
1090 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1091 pc, address, is_write, *(unsigned long *)old_set);
1092 #endif
1093 /* XXX: locking issue */
1094 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1095 return 1;
1096 }
1097
1098 /* see if it is an MMU fault */
1099 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1100 if (ret < 0)
1101 return 0; /* not an MMU fault */
1102 if (ret == 0)
1103 return 1; /* the MMU fault was handled without causing real CPU fault */
1104
1105 /* now we have a real cpu fault */
1106 tb = tb_find_pc(pc);
1107 if (tb) {
1108 /* the PC is inside the translated code. It means that we have
1109 a virtual CPU fault */
1110 cpu_restore_state(tb, env, pc, puc);
1111 }
1112 if (ret == 1) {
1113 #if 0
1114 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1115 env->nip, env->error_code, tb);
1116 #endif
1117 /* we restore the process signal mask as the sigreturn should
1118 do it (XXX: use sigsetjmp) */
1119 sigprocmask(SIG_SETMASK, old_set, NULL);
1120 do_raise_exception_err(env->exception_index, env->error_code);
1121 } else {
1122 /* activate soft MMU for this block */
1123 cpu_resume_from_signal(env, puc);
1124 }
1125 /* never comes here */
1126 return 1;
1127 }
1128
1129 #elif defined (TARGET_SH4)
1130 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1131 int is_write, sigset_t *old_set,
1132 void *puc)
1133 {
1134 TranslationBlock *tb;
1135 int ret;
1136
1137 if (cpu_single_env)
1138 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1139 #if defined(DEBUG_SIGNAL)
1140 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1141 pc, address, is_write, *(unsigned long *)old_set);
1142 #endif
1143 /* XXX: locking issue */
1144 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1145 return 1;
1146 }
1147
1148 /* see if it is an MMU fault */
1149 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1150 if (ret < 0)
1151 return 0; /* not an MMU fault */
1152 if (ret == 0)
1153 return 1; /* the MMU fault was handled without causing real CPU fault */
1154
1155 /* now we have a real cpu fault */
1156 tb = tb_find_pc(pc);
1157 if (tb) {
1158 /* the PC is inside the translated code. It means that we have
1159 a virtual CPU fault */
1160 cpu_restore_state(tb, env, pc, puc);
1161 }
1162 #if 0
1163 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1164 env->nip, env->error_code, tb);
1165 #endif
1166 /* we restore the process signal mask as the sigreturn should
1167 do it (XXX: use sigsetjmp) */
1168 sigprocmask(SIG_SETMASK, old_set, NULL);
1169 cpu_loop_exit();
1170 /* never comes here */
1171 return 1;
1172 }
1173 #else
1174 #error unsupported target CPU
1175 #endif
1176
1177 #if defined(__i386__)
1178
1179 #if defined(__APPLE__)
1180 # include <sys/ucontext.h>
1181
1182 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1183 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1184 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1185 #else
1186 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1187 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1188 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1189 #endif
1190
1191 #if defined(USE_CODE_COPY)
1192 static void cpu_send_trap(unsigned long pc, int trap,
1193 struct ucontext *uc)
1194 {
1195 TranslationBlock *tb;
1196
1197 if (cpu_single_env)
1198 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1199 /* now we have a real cpu fault */
1200 tb = tb_find_pc(pc);
1201 if (tb) {
1202 /* the PC is inside the translated code. It means that we have
1203 a virtual CPU fault */
1204 cpu_restore_state(tb, env, pc, uc);
1205 }
1206 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1207 raise_exception_err(trap, env->error_code);
1208 }
1209 #endif
1210
1211 int cpu_signal_handler(int host_signum, void *pinfo,
1212 void *puc)
1213 {
1214 siginfo_t *info = pinfo;
1215 struct ucontext *uc = puc;
1216 unsigned long pc;
1217 int trapno;
1218
1219 #ifndef REG_EIP
1220 /* for glibc 2.1 */
1221 #define REG_EIP EIP
1222 #define REG_ERR ERR
1223 #define REG_TRAPNO TRAPNO
1224 #endif
1225 pc = EIP_sig(uc);
1226 trapno = TRAP_sig(uc);
1227 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1228 if (trapno == 0x00 || trapno == 0x05) {
1229 /* send division by zero or bound exception */
1230 cpu_send_trap(pc, trapno, uc);
1231 return 1;
1232 } else
1233 #endif
1234 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1235 trapno == 0xe ?
1236 (ERROR_sig(uc) >> 1) & 1 : 0,
1237 &uc->uc_sigmask, puc);
1238 }
1239
1240 #elif defined(__x86_64__)
1241
1242 int cpu_signal_handler(int host_signum, void *pinfo,
1243 void *puc)
1244 {
1245 siginfo_t *info = pinfo;
1246 struct ucontext *uc = puc;
1247 unsigned long pc;
1248
1249 pc = uc->uc_mcontext.gregs[REG_RIP];
1250 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1251 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1252 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1253 &uc->uc_sigmask, puc);
1254 }
1255
1256 #elif defined(__powerpc__)
1257
1258 /***********************************************************************
1259 * signal context platform-specific definitions
1260 * From Wine
1261 */
1262 #ifdef linux
1263 /* All Registers access - only for local access */
1264 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1265 /* Gpr Registers access */
1266 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1267 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1268 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1269 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1270 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1271 # define LR_sig(context) REG_sig(link, context) /* Link register */
1272 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1273 /* Float Registers access */
1274 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1275 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1276 /* Exception Registers access */
1277 # define DAR_sig(context) REG_sig(dar, context)
1278 # define DSISR_sig(context) REG_sig(dsisr, context)
1279 # define TRAP_sig(context) REG_sig(trap, context)
1280 #endif /* linux */
1281
1282 #ifdef __APPLE__
1283 # include <sys/ucontext.h>
1284 typedef struct ucontext SIGCONTEXT;
1285 /* All Registers access - only for local access */
1286 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1287 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1288 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1289 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1290 /* Gpr Registers access */
1291 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1292 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1293 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1294 # define CTR_sig(context) REG_sig(ctr, context)
1295 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1296 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1297 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1298 /* Float Registers access */
1299 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1300 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1301 /* Exception Registers access */
1302 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1303 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1304 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1305 #endif /* __APPLE__ */
1306
1307 int cpu_signal_handler(int host_signum, void *pinfo,
1308 void *puc)
1309 {
1310 siginfo_t *info = pinfo;
1311 struct ucontext *uc = puc;
1312 unsigned long pc;
1313 int is_write;
1314
1315 pc = IAR_sig(uc);
1316 is_write = 0;
1317 #if 0
1318 /* ppc 4xx case */
1319 if (DSISR_sig(uc) & 0x00800000)
1320 is_write = 1;
1321 #else
1322 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1323 is_write = 1;
1324 #endif
1325 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1326 is_write, &uc->uc_sigmask, puc);
1327 }
1328
1329 #elif defined(__alpha__)
1330
1331 int cpu_signal_handler(int host_signum, void *pinfo,
1332 void *puc)
1333 {
1334 siginfo_t *info = pinfo;
1335 struct ucontext *uc = puc;
1336 uint32_t *pc = uc->uc_mcontext.sc_pc;
1337 uint32_t insn = *pc;
1338 int is_write = 0;
1339
1340 /* XXX: need kernel patch to get write flag faster */
1341 switch (insn >> 26) {
1342 case 0x0d: // stw
1343 case 0x0e: // stb
1344 case 0x0f: // stq_u
1345 case 0x24: // stf
1346 case 0x25: // stg
1347 case 0x26: // sts
1348 case 0x27: // stt
1349 case 0x2c: // stl
1350 case 0x2d: // stq
1351 case 0x2e: // stl_c
1352 case 0x2f: // stq_c
1353 is_write = 1;
1354 }
1355
1356 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1357 is_write, &uc->uc_sigmask, puc);
1358 }
1359 #elif defined(__sparc__)
1360
1361 int cpu_signal_handler(int host_signum, void *pinfo,
1362 void *puc)
1363 {
1364 siginfo_t *info = pinfo;
1365 uint32_t *regs = (uint32_t *)(info + 1);
1366 void *sigmask = (regs + 20);
1367 unsigned long pc;
1368 int is_write;
1369 uint32_t insn;
1370
1371 /* XXX: is there a standard glibc define ? */
1372 pc = regs[1];
1373 /* XXX: need kernel patch to get write flag faster */
1374 is_write = 0;
1375 insn = *(uint32_t *)pc;
1376 if ((insn >> 30) == 3) {
1377 switch((insn >> 19) & 0x3f) {
1378 case 0x05: // stb
1379 case 0x06: // sth
1380 case 0x04: // st
1381 case 0x07: // std
1382 case 0x24: // stf
1383 case 0x27: // stdf
1384 case 0x25: // stfsr
1385 is_write = 1;
1386 break;
1387 }
1388 }
1389 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1390 is_write, sigmask, NULL);
1391 }
1392
1393 #elif defined(__arm__)
1394
1395 int cpu_signal_handler(int host_signum, void *pinfo,
1396 void *puc)
1397 {
1398 siginfo_t *info = pinfo;
1399 struct ucontext *uc = puc;
1400 unsigned long pc;
1401 int is_write;
1402
1403 pc = uc->uc_mcontext.gregs[R15];
1404 /* XXX: compute is_write */
1405 is_write = 0;
1406 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1407 is_write,
1408 &uc->uc_sigmask, puc);
1409 }
1410
1411 #elif defined(__mc68000)
1412
1413 int cpu_signal_handler(int host_signum, void *pinfo,
1414 void *puc)
1415 {
1416 siginfo_t *info = pinfo;
1417 struct ucontext *uc = puc;
1418 unsigned long pc;
1419 int is_write;
1420
1421 pc = uc->uc_mcontext.gregs[16];
1422 /* XXX: compute is_write */
1423 is_write = 0;
1424 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1425 is_write,
1426 &uc->uc_sigmask, puc);
1427 }
1428
1429 #elif defined(__ia64)
1430
1431 #ifndef __ISR_VALID
1432 /* This ought to be in <bits/siginfo.h>... */
1433 # define __ISR_VALID 1
1434 #endif
1435
1436 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1437 {
1438 siginfo_t *info = pinfo;
1439 struct ucontext *uc = puc;
1440 unsigned long ip;
1441 int is_write = 0;
1442
1443 ip = uc->uc_mcontext.sc_ip;
1444 switch (host_signum) {
1445 case SIGILL:
1446 case SIGFPE:
1447 case SIGSEGV:
1448 case SIGBUS:
1449 case SIGTRAP:
1450 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1451 /* ISR.W (write-access) is bit 33: */
1452 is_write = (info->si_isr >> 33) & 1;
1453 break;
1454
1455 default:
1456 break;
1457 }
1458 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1459 is_write,
1460 &uc->uc_sigmask, puc);
1461 }
1462
1463 #elif defined(__s390__)
1464
1465 int cpu_signal_handler(int host_signum, void *pinfo,
1466 void *puc)
1467 {
1468 siginfo_t *info = pinfo;
1469 struct ucontext *uc = puc;
1470 unsigned long pc;
1471 int is_write;
1472
1473 pc = uc->uc_mcontext.psw.addr;
1474 /* XXX: compute is_write */
1475 is_write = 0;
1476 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1477 is_write,
1478 &uc->uc_sigmask, puc);
1479 }
1480
1481 #else
1482
1483 #error host CPU specific signal handler needed
1484
1485 #endif
1486
1487 #endif /* !defined(CONFIG_SOFTMMU) */
Samsung s3c2440 and arm920t support for the mini2440 dev board