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Rename slavio_serial functions to escc, add clock rate and it_shift parameters
[qemu/mini2440.git] / hw / sun4m.c
blobbb44d4757eb9e1207bfec12ae49823ab52b03cb8
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39
40 //#define DEBUG_IRQ
41
42 /*
43 * Sun4m architecture was used in the following machines:
44 *
45 * SPARCserver 6xxMP/xx
46 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47 * SPARCclassic X (4/10)
48 * SPARCstation LX/ZX (4/30)
49 * SPARCstation Voyager
50 * SPARCstation 10/xx, SPARCserver 10/xx
51 * SPARCstation 5, SPARCserver 5
52 * SPARCstation 20/xx, SPARCserver 20
53 * SPARCstation 4
54 *
55 * Sun4d architecture was used in the following machines:
56 *
57 * SPARCcenter 2000
58 * SPARCserver 1000
59 *
60 * Sun4c architecture was used in the following machines:
61 * SPARCstation 1/1+, SPARCserver 1/1+
62 * SPARCstation SLC
63 * SPARCstation IPC
64 * SPARCstation ELC
65 * SPARCstation IPX
66 *
67 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 */
69
70 #ifdef DEBUG_IRQ
71 #define DPRINTF(fmt, args...) \
72 do { printf("CPUIRQ: " fmt , ##args); } while (0)
73 #else
74 #define DPRINTF(fmt, args...)
75 #endif
76
77 #define KERNEL_LOAD_ADDR 0x00004000
78 #define CMDLINE_ADDR 0x007ff000
79 #define INITRD_LOAD_ADDR 0x00800000
80 #define PROM_SIZE_MAX (1024 * 1024)
81 #define PROM_VADDR 0xffd00000
82 #define PROM_FILENAME "openbios-sparc32"
83 #define CFG_ADDR 0xd00000510ULL
84 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85
86 // Control plane, 8-bit and 24-bit planes
87 #define TCX_SIZE (9 * 1024 * 1024)
88
89 #define MAX_CPUS 16
90 #define MAX_PILS 16
91
92 #define ESCC_CLOCK 4915200
93
94 struct sun4m_hwdef {
95 target_phys_addr_t iommu_base, slavio_base;
96 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
97 target_phys_addr_t serial_base, fd_base;
98 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
99 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
100 target_phys_addr_t ecc_base;
101 uint32_t ecc_version;
102 long vram_size, nvram_size;
103 // IRQ numbers are not PIL ones, but master interrupt controller
104 // register bit numbers
105 int esp_irq, le_irq, clock_irq, clock1_irq;
106 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
107 uint8_t nvram_machine_id;
108 uint16_t machine_id;
109 uint32_t iommu_version;
110 uint32_t intbit_to_level[32];
111 uint64_t max_mem;
112 const char * const default_cpu_model;
113 };
114
115 #define MAX_IOUNITS 5
116
117 struct sun4d_hwdef {
118 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
119 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
120 target_phys_addr_t serial_base;
121 target_phys_addr_t espdma_base, esp_base;
122 target_phys_addr_t ledma_base, le_base;
123 target_phys_addr_t tcx_base;
124 target_phys_addr_t sbi_base;
125 unsigned long vram_size, nvram_size;
126 // IRQ numbers are not PIL ones, but SBI register bit numbers
127 int esp_irq, le_irq, clock_irq, clock1_irq;
128 int ser_irq, ms_kb_irq, me_irq;
129 uint8_t nvram_machine_id;
130 uint16_t machine_id;
131 uint32_t iounit_version;
132 uint64_t max_mem;
133 const char * const default_cpu_model;
134 };
135
136 struct sun4c_hwdef {
137 target_phys_addr_t iommu_base, slavio_base;
138 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
139 target_phys_addr_t serial_base, fd_base;
140 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
141 target_phys_addr_t tcx_base, aux1_base;
142 long vram_size, nvram_size;
143 // IRQ numbers are not PIL ones, but master interrupt controller
144 // register bit numbers
145 int esp_irq, le_irq, clock_irq, clock1_irq;
146 int ser_irq, ms_kb_irq, fd_irq, me_irq;
147 uint8_t nvram_machine_id;
148 uint16_t machine_id;
149 uint32_t iommu_version;
150 uint32_t intbit_to_level[32];
151 uint64_t max_mem;
152 const char * const default_cpu_model;
153 };
154
155 int DMA_get_channel_mode (int nchan)
156 {
157 return 0;
158 }
159 int DMA_read_memory (int nchan, void *buf, int pos, int size)
160 {
161 return 0;
162 }
163 int DMA_write_memory (int nchan, void *buf, int pos, int size)
164 {
165 return 0;
166 }
167 void DMA_hold_DREQ (int nchan) {}
168 void DMA_release_DREQ (int nchan) {}
169 void DMA_schedule(int nchan) {}
170 void DMA_init (int high_page_enable) {}
171 void DMA_register_channel (int nchan,
172 DMA_transfer_handler transfer_handler,
173 void *opaque)
174 {
175 }
176
177 static int nvram_boot_set(void *opaque, const char *boot_device)
178 {
179 unsigned int i;
180 uint8_t image[sizeof(ohwcfg_v3_t)];
181 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
182 m48t59_t *nvram = (m48t59_t *)opaque;
183
184 for (i = 0; i < sizeof(image); i++)
185 image[i] = m48t59_read(nvram, i) & 0xff;
186
187 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
188 boot_device);
189 header->nboot_devices = strlen(boot_device) & 0xff;
190 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
191
192 for (i = 0; i < sizeof(image); i++)
193 m48t59_write(nvram, i, image[i]);
194
195 return 0;
196 }
197
198 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
199 const char *boot_devices, ram_addr_t RAM_size,
200 uint32_t kernel_size,
201 int width, int height, int depth,
202 int nvram_machine_id, const char *arch)
203 {
204 unsigned int i;
205 uint32_t start, end;
206 uint8_t image[0x1ff0];
207 ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
208 struct sparc_arch_cfg *sparc_header;
209 struct OpenBIOS_nvpart_v1 *part_header;
210
211 memset(image, '\0', sizeof(image));
212
213 // Try to match PPC NVRAM
214 pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
215 "QEMU_BIOS");
216 header->struct_version = cpu_to_be32(3); /* structure v3 */
217
218 header->nvram_size = cpu_to_be16(0x2000);
219 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
220 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
221 pstrcpy((char *)header->arch, sizeof(header->arch), arch);
222 header->nb_cpus = smp_cpus & 0xff;
223 header->RAM0_base = 0;
224 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
225 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
226 boot_devices);
227 header->nboot_devices = strlen(boot_devices) & 0xff;
228 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
229 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
230 if (cmdline) {
231 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
232 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
233 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
234 }
235 // XXX add initrd_image, initrd_size
236 header->width = cpu_to_be16(width);
237 header->height = cpu_to_be16(height);
238 header->depth = cpu_to_be16(depth);
239 if (nographic)
240 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
241
242 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
243
244 // Architecture specific header
245 start = sizeof(ohwcfg_v3_t);
246 sparc_header = (struct sparc_arch_cfg *)&image[start];
247 sparc_header->valid = 0;
248 start += sizeof(struct sparc_arch_cfg);
249
250 // OpenBIOS nvram variables
251 // Variable partition
252 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
253 part_header->signature = OPENBIOS_PART_SYSTEM;
254 pstrcpy(part_header->name, sizeof(part_header->name), "system");
255
256 end = start + sizeof(struct OpenBIOS_nvpart_v1);
257 for (i = 0; i < nb_prom_envs; i++)
258 end = OpenBIOS_set_var(image, end, prom_envs[i]);
259
260 // End marker
261 image[end++] = '\0';
262
263 end = start + ((end - start + 15) & ~15);
264 OpenBIOS_finish_partition(part_header, end - start);
265
266 // free partition
267 start = end;
268 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
269 part_header->signature = OPENBIOS_PART_FREE;
270 pstrcpy(part_header->name, sizeof(part_header->name), "free");
271
272 end = 0x1fd0;
273 OpenBIOS_finish_partition(part_header, end - start);
274
275 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
276 nvram_machine_id);
277
278 for (i = 0; i < sizeof(image); i++)
279 m48t59_write(nvram, i, image[i]);
280
281 qemu_register_boot_set(nvram_boot_set, nvram);
282 }
283
284 static void *slavio_intctl;
285
286 void pic_info(void)
287 {
288 if (slavio_intctl)
289 slavio_pic_info(slavio_intctl);
290 }
291
292 void irq_info(void)
293 {
294 if (slavio_intctl)
295 slavio_irq_info(slavio_intctl);
296 }
297
298 void cpu_check_irqs(CPUState *env)
299 {
300 if (env->pil_in && (env->interrupt_index == 0 ||
301 (env->interrupt_index & ~15) == TT_EXTINT)) {
302 unsigned int i;
303
304 for (i = 15; i > 0; i--) {
305 if (env->pil_in & (1 << i)) {
306 int old_interrupt = env->interrupt_index;
307
308 env->interrupt_index = TT_EXTINT | i;
309 if (old_interrupt != env->interrupt_index) {
310 DPRINTF("Set CPU IRQ %d\n", i);
311 cpu_interrupt(env, CPU_INTERRUPT_HARD);
312 }
313 break;
314 }
315 }
316 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
317 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
318 env->interrupt_index = 0;
319 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
320 }
321 }
322
323 static void cpu_set_irq(void *opaque, int irq, int level)
324 {
325 CPUState *env = opaque;
326
327 if (level) {
328 DPRINTF("Raise CPU IRQ %d\n", irq);
329 env->halted = 0;
330 env->pil_in |= 1 << irq;
331 cpu_check_irqs(env);
332 } else {
333 DPRINTF("Lower CPU IRQ %d\n", irq);
334 env->pil_in &= ~(1 << irq);
335 cpu_check_irqs(env);
336 }
337 }
338
339 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
340 {
341 }
342
343 static void *slavio_misc;
344
345 void qemu_system_powerdown(void)
346 {
347 slavio_set_power_fail(slavio_misc, 1);
348 }
349
350 static void main_cpu_reset(void *opaque)
351 {
352 CPUState *env = opaque;
353
354 cpu_reset(env);
355 env->halted = 0;
356 }
357
358 static void secondary_cpu_reset(void *opaque)
359 {
360 CPUState *env = opaque;
361
362 cpu_reset(env);
363 env->halted = 1;
364 }
365
366 static void cpu_halt_signal(void *opaque, int irq, int level)
367 {
368 if (level && cpu_single_env)
369 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
370 }
371
372 static unsigned long sun4m_load_kernel(const char *kernel_filename,
373 const char *initrd_filename,
374 ram_addr_t RAM_size)
375 {
376 int linux_boot;
377 unsigned int i;
378 long initrd_size, kernel_size;
379
380 linux_boot = (kernel_filename != NULL);
381
382 kernel_size = 0;
383 if (linux_boot) {
384 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
385 NULL);
386 if (kernel_size < 0)
387 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
388 RAM_size - KERNEL_LOAD_ADDR);
389 if (kernel_size < 0)
390 kernel_size = load_image_targphys(kernel_filename,
391 KERNEL_LOAD_ADDR,
392 RAM_size - KERNEL_LOAD_ADDR);
393 if (kernel_size < 0) {
394 fprintf(stderr, "qemu: could not load kernel '%s'\n",
395 kernel_filename);
396 exit(1);
397 }
398
399 /* load initrd */
400 initrd_size = 0;
401 if (initrd_filename) {
402 initrd_size = load_image_targphys(initrd_filename,
403 INITRD_LOAD_ADDR,
404 RAM_size - INITRD_LOAD_ADDR);
405 if (initrd_size < 0) {
406 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
407 initrd_filename);
408 exit(1);
409 }
410 }
411 if (initrd_size > 0) {
412 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
413 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
414 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
415 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
416 break;
417 }
418 }
419 }
420 }
421 return kernel_size;
422 }
423
424 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
425 const char *boot_device,
426 DisplayState *ds, const char *kernel_filename,
427 const char *kernel_cmdline,
428 const char *initrd_filename, const char *cpu_model)
429
430 {
431 CPUState *env, *envs[MAX_CPUS];
432 unsigned int i;
433 void *iommu, *espdma, *ledma, *main_esp, *nvram;
434 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
435 *espdma_irq, *ledma_irq;
436 qemu_irq *esp_reset, *le_reset;
437 qemu_irq *fdc_tc;
438 qemu_irq *cpu_halt;
439 ram_addr_t ram_offset, prom_offset, tcx_offset, idreg_offset;
440 unsigned long kernel_size;
441 int ret;
442 char buf[1024];
443 BlockDriverState *fd[MAX_FD];
444 int drive_index;
445 void *fw_cfg;
446
447 /* init CPUs */
448 if (!cpu_model)
449 cpu_model = hwdef->default_cpu_model;
450
451 for(i = 0; i < smp_cpus; i++) {
452 env = cpu_init(cpu_model);
453 if (!env) {
454 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
455 exit(1);
456 }
457 cpu_sparc_set_id(env, i);
458 envs[i] = env;
459 if (i == 0) {
460 qemu_register_reset(main_cpu_reset, env);
461 } else {
462 qemu_register_reset(secondary_cpu_reset, env);
463 env->halted = 1;
464 }
465 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
466 env->prom_addr = hwdef->slavio_base;
467 }
468
469 for (i = smp_cpus; i < MAX_CPUS; i++)
470 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
471
472
473 /* allocate RAM */
474 if ((uint64_t)RAM_size > hwdef->max_mem) {
475 fprintf(stderr,
476 "qemu: Too much memory for this machine: %d, maximum %d\n",
477 (unsigned int)(RAM_size / (1024 * 1024)),
478 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
479 exit(1);
480 }
481 ram_offset = qemu_ram_alloc(RAM_size);
482 cpu_register_physical_memory(0, RAM_size, ram_offset);
483
484 /* load boot prom */
485 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
486 cpu_register_physical_memory(hwdef->slavio_base,
487 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
488 TARGET_PAGE_MASK,
489 prom_offset | IO_MEM_ROM);
490
491 if (bios_name == NULL)
492 bios_name = PROM_FILENAME;
493 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
494 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
495 if (ret < 0 || ret > PROM_SIZE_MAX)
496 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
497 if (ret < 0 || ret > PROM_SIZE_MAX) {
498 fprintf(stderr, "qemu: could not load prom '%s'\n",
499 buf);
500 exit(1);
501 }
502
503 /* set up devices */
504 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
505 hwdef->intctl_base + 0x10000ULL,
506 &hwdef->intbit_to_level[0],
507 &slavio_irq, &slavio_cpu_irq,
508 cpu_irqs,
509 hwdef->clock_irq);
510
511 if (hwdef->idreg_base) {
512 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
513
514 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
515 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
516 idreg_offset | IO_MEM_ROM);
517 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
518 sizeof(idreg_data));
519 }
520
521 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
522 slavio_irq[hwdef->me_irq]);
523
524 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
525 iommu, &espdma_irq, &esp_reset);
526
527 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
528 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
529 &le_reset);
530
531 if (graphic_depth != 8 && graphic_depth != 24) {
532 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
533 exit (1);
534 }
535 tcx_offset = qemu_ram_alloc(hwdef->vram_size);
536 tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
537 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
538
539 if (nd_table[0].model == NULL)
540 nd_table[0].model = "lance";
541 if (strcmp(nd_table[0].model, "lance") == 0) {
542 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
543 } else if (strcmp(nd_table[0].model, "?") == 0) {
544 fprintf(stderr, "qemu: Supported NICs: lance\n");
545 exit (1);
546 } else {
547 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
548 exit (1);
549 }
550
551 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
552 hwdef->nvram_size, 8);
553
554 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
555 slavio_cpu_irq, smp_cpus);
556
557 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
558 nographic, ESCC_CLOCK, 1);
559 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
560 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
561 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], serial_hds[1],
562 serial_hds[0], ESCC_CLOCK, 1);
563
564 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
565 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
566 hwdef->aux1_base, hwdef->aux2_base,
567 slavio_irq[hwdef->me_irq], cpu_halt[0],
568 &fdc_tc);
569
570 if (hwdef->fd_base) {
571 /* there is zero or one floppy drive */
572 memset(fd, 0, sizeof(fd));
573 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
574 if (drive_index != -1)
575 fd[0] = drives_table[drive_index].bdrv;
576
577 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
578 fdc_tc);
579 }
580
581 if (drive_get_max_bus(IF_SCSI) > 0) {
582 fprintf(stderr, "qemu: too many SCSI bus\n");
583 exit(1);
584 }
585
586 main_esp = esp_init(hwdef->esp_base, 2,
587 espdma_memory_read, espdma_memory_write,
588 espdma, *espdma_irq, esp_reset);
589
590 for (i = 0; i < ESP_MAX_DEVS; i++) {
591 drive_index = drive_get_index(IF_SCSI, 0, i);
592 if (drive_index == -1)
593 continue;
594 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
595 }
596
597 if (hwdef->cs_base)
598 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
599
600 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
601 RAM_size);
602
603 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
604 boot_device, RAM_size, kernel_size, graphic_width,
605 graphic_height, graphic_depth, hwdef->nvram_machine_id,
606 "Sun4m");
607
608 if (hwdef->ecc_base)
609 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
610 hwdef->ecc_version);
611
612 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
613 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
614 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
615 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
616 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
617 }
618
619 enum {
620 ss2_id = 0,
621 ss5_id = 32,
622 vger_id,
623 lx_id,
624 ss4_id,
625 scls_id,
626 sbook_id,
627 ss10_id = 64,
628 ss20_id,
629 ss600mp_id,
630 ss1000_id = 96,
631 ss2000_id,
632 };
633
634 static const struct sun4m_hwdef sun4m_hwdefs[] = {
635 /* SS-5 */
636 {
637 .iommu_base = 0x10000000,
638 .tcx_base = 0x50000000,
639 .cs_base = 0x6c000000,
640 .slavio_base = 0x70000000,
641 .ms_kb_base = 0x71000000,
642 .serial_base = 0x71100000,
643 .nvram_base = 0x71200000,
644 .fd_base = 0x71400000,
645 .counter_base = 0x71d00000,
646 .intctl_base = 0x71e00000,
647 .idreg_base = 0x78000000,
648 .dma_base = 0x78400000,
649 .esp_base = 0x78800000,
650 .le_base = 0x78c00000,
651 .apc_base = 0x6a000000,
652 .aux1_base = 0x71900000,
653 .aux2_base = 0x71910000,
654 .vram_size = 0x00100000,
655 .nvram_size = 0x2000,
656 .esp_irq = 18,
657 .le_irq = 16,
658 .clock_irq = 7,
659 .clock1_irq = 19,
660 .ms_kb_irq = 14,
661 .ser_irq = 15,
662 .fd_irq = 22,
663 .me_irq = 30,
664 .cs_irq = 5,
665 .nvram_machine_id = 0x80,
666 .machine_id = ss5_id,
667 .iommu_version = 0x05000000,
668 .intbit_to_level = {
669 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
670 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
671 },
672 .max_mem = 0x10000000,
673 .default_cpu_model = "Fujitsu MB86904",
674 },
675 /* SS-10 */
676 {
677 .iommu_base = 0xfe0000000ULL,
678 .tcx_base = 0xe20000000ULL,
679 .slavio_base = 0xff0000000ULL,
680 .ms_kb_base = 0xff1000000ULL,
681 .serial_base = 0xff1100000ULL,
682 .nvram_base = 0xff1200000ULL,
683 .fd_base = 0xff1700000ULL,
684 .counter_base = 0xff1300000ULL,
685 .intctl_base = 0xff1400000ULL,
686 .idreg_base = 0xef0000000ULL,
687 .dma_base = 0xef0400000ULL,
688 .esp_base = 0xef0800000ULL,
689 .le_base = 0xef0c00000ULL,
690 .apc_base = 0xefa000000ULL, // XXX should not exist
691 .aux1_base = 0xff1800000ULL,
692 .aux2_base = 0xff1a01000ULL,
693 .ecc_base = 0xf00000000ULL,
694 .ecc_version = 0x10000000, // version 0, implementation 1
695 .vram_size = 0x00100000,
696 .nvram_size = 0x2000,
697 .esp_irq = 18,
698 .le_irq = 16,
699 .clock_irq = 7,
700 .clock1_irq = 19,
701 .ms_kb_irq = 14,
702 .ser_irq = 15,
703 .fd_irq = 22,
704 .me_irq = 30,
705 .ecc_irq = 28,
706 .nvram_machine_id = 0x72,
707 .machine_id = ss10_id,
708 .iommu_version = 0x03000000,
709 .intbit_to_level = {
710 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
711 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
712 },
713 .max_mem = 0xf00000000ULL,
714 .default_cpu_model = "TI SuperSparc II",
715 },
716 /* SS-600MP */
717 {
718 .iommu_base = 0xfe0000000ULL,
719 .tcx_base = 0xe20000000ULL,
720 .slavio_base = 0xff0000000ULL,
721 .ms_kb_base = 0xff1000000ULL,
722 .serial_base = 0xff1100000ULL,
723 .nvram_base = 0xff1200000ULL,
724 .counter_base = 0xff1300000ULL,
725 .intctl_base = 0xff1400000ULL,
726 .dma_base = 0xef0081000ULL,
727 .esp_base = 0xef0080000ULL,
728 .le_base = 0xef0060000ULL,
729 .apc_base = 0xefa000000ULL, // XXX should not exist
730 .aux1_base = 0xff1800000ULL,
731 .aux2_base = 0xff1a01000ULL, // XXX should not exist
732 .ecc_base = 0xf00000000ULL,
733 .ecc_version = 0x00000000, // version 0, implementation 0
734 .vram_size = 0x00100000,
735 .nvram_size = 0x2000,
736 .esp_irq = 18,
737 .le_irq = 16,
738 .clock_irq = 7,
739 .clock1_irq = 19,
740 .ms_kb_irq = 14,
741 .ser_irq = 15,
742 .fd_irq = 22,
743 .me_irq = 30,
744 .ecc_irq = 28,
745 .nvram_machine_id = 0x71,
746 .machine_id = ss600mp_id,
747 .iommu_version = 0x01000000,
748 .intbit_to_level = {
749 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
750 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
751 },
752 .max_mem = 0xf00000000ULL,
753 .default_cpu_model = "TI SuperSparc II",
754 },
755 /* SS-20 */
756 {
757 .iommu_base = 0xfe0000000ULL,
758 .tcx_base = 0xe20000000ULL,
759 .slavio_base = 0xff0000000ULL,
760 .ms_kb_base = 0xff1000000ULL,
761 .serial_base = 0xff1100000ULL,
762 .nvram_base = 0xff1200000ULL,
763 .fd_base = 0xff1700000ULL,
764 .counter_base = 0xff1300000ULL,
765 .intctl_base = 0xff1400000ULL,
766 .idreg_base = 0xef0000000ULL,
767 .dma_base = 0xef0400000ULL,
768 .esp_base = 0xef0800000ULL,
769 .le_base = 0xef0c00000ULL,
770 .apc_base = 0xefa000000ULL, // XXX should not exist
771 .aux1_base = 0xff1800000ULL,
772 .aux2_base = 0xff1a01000ULL,
773 .ecc_base = 0xf00000000ULL,
774 .ecc_version = 0x20000000, // version 0, implementation 2
775 .vram_size = 0x00100000,
776 .nvram_size = 0x2000,
777 .esp_irq = 18,
778 .le_irq = 16,
779 .clock_irq = 7,
780 .clock1_irq = 19,
781 .ms_kb_irq = 14,
782 .ser_irq = 15,
783 .fd_irq = 22,
784 .me_irq = 30,
785 .ecc_irq = 28,
786 .nvram_machine_id = 0x72,
787 .machine_id = ss20_id,
788 .iommu_version = 0x13000000,
789 .intbit_to_level = {
790 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
791 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
792 },
793 .max_mem = 0xf00000000ULL,
794 .default_cpu_model = "TI SuperSparc II",
795 },
796 /* Voyager */
797 {
798 .iommu_base = 0x10000000,
799 .tcx_base = 0x50000000,
800 .slavio_base = 0x70000000,
801 .ms_kb_base = 0x71000000,
802 .serial_base = 0x71100000,
803 .nvram_base = 0x71200000,
804 .fd_base = 0x71400000,
805 .counter_base = 0x71d00000,
806 .intctl_base = 0x71e00000,
807 .idreg_base = 0x78000000,
808 .dma_base = 0x78400000,
809 .esp_base = 0x78800000,
810 .le_base = 0x78c00000,
811 .apc_base = 0x71300000, // pmc
812 .aux1_base = 0x71900000,
813 .aux2_base = 0x71910000,
814 .vram_size = 0x00100000,
815 .nvram_size = 0x2000,
816 .esp_irq = 18,
817 .le_irq = 16,
818 .clock_irq = 7,
819 .clock1_irq = 19,
820 .ms_kb_irq = 14,
821 .ser_irq = 15,
822 .fd_irq = 22,
823 .me_irq = 30,
824 .nvram_machine_id = 0x80,
825 .machine_id = vger_id,
826 .iommu_version = 0x05000000,
827 .intbit_to_level = {
828 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
829 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
830 },
831 .max_mem = 0x10000000,
832 .default_cpu_model = "Fujitsu MB86904",
833 },
834 /* LX */
835 {
836 .iommu_base = 0x10000000,
837 .tcx_base = 0x50000000,
838 .slavio_base = 0x70000000,
839 .ms_kb_base = 0x71000000,
840 .serial_base = 0x71100000,
841 .nvram_base = 0x71200000,
842 .fd_base = 0x71400000,
843 .counter_base = 0x71d00000,
844 .intctl_base = 0x71e00000,
845 .idreg_base = 0x78000000,
846 .dma_base = 0x78400000,
847 .esp_base = 0x78800000,
848 .le_base = 0x78c00000,
849 .aux1_base = 0x71900000,
850 .aux2_base = 0x71910000,
851 .vram_size = 0x00100000,
852 .nvram_size = 0x2000,
853 .esp_irq = 18,
854 .le_irq = 16,
855 .clock_irq = 7,
856 .clock1_irq = 19,
857 .ms_kb_irq = 14,
858 .ser_irq = 15,
859 .fd_irq = 22,
860 .me_irq = 30,
861 .nvram_machine_id = 0x80,
862 .machine_id = lx_id,
863 .iommu_version = 0x04000000,
864 .intbit_to_level = {
865 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
866 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
867 },
868 .max_mem = 0x10000000,
869 .default_cpu_model = "TI MicroSparc I",
870 },
871 /* SS-4 */
872 {
873 .iommu_base = 0x10000000,
874 .tcx_base = 0x50000000,
875 .cs_base = 0x6c000000,
876 .slavio_base = 0x70000000,
877 .ms_kb_base = 0x71000000,
878 .serial_base = 0x71100000,
879 .nvram_base = 0x71200000,
880 .fd_base = 0x71400000,
881 .counter_base = 0x71d00000,
882 .intctl_base = 0x71e00000,
883 .idreg_base = 0x78000000,
884 .dma_base = 0x78400000,
885 .esp_base = 0x78800000,
886 .le_base = 0x78c00000,
887 .apc_base = 0x6a000000,
888 .aux1_base = 0x71900000,
889 .aux2_base = 0x71910000,
890 .vram_size = 0x00100000,
891 .nvram_size = 0x2000,
892 .esp_irq = 18,
893 .le_irq = 16,
894 .clock_irq = 7,
895 .clock1_irq = 19,
896 .ms_kb_irq = 14,
897 .ser_irq = 15,
898 .fd_irq = 22,
899 .me_irq = 30,
900 .cs_irq = 5,
901 .nvram_machine_id = 0x80,
902 .machine_id = ss4_id,
903 .iommu_version = 0x05000000,
904 .intbit_to_level = {
905 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
906 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
907 },
908 .max_mem = 0x10000000,
909 .default_cpu_model = "Fujitsu MB86904",
910 },
911 /* SPARCClassic */
912 {
913 .iommu_base = 0x10000000,
914 .tcx_base = 0x50000000,
915 .slavio_base = 0x70000000,
916 .ms_kb_base = 0x71000000,
917 .serial_base = 0x71100000,
918 .nvram_base = 0x71200000,
919 .fd_base = 0x71400000,
920 .counter_base = 0x71d00000,
921 .intctl_base = 0x71e00000,
922 .idreg_base = 0x78000000,
923 .dma_base = 0x78400000,
924 .esp_base = 0x78800000,
925 .le_base = 0x78c00000,
926 .apc_base = 0x6a000000,
927 .aux1_base = 0x71900000,
928 .aux2_base = 0x71910000,
929 .vram_size = 0x00100000,
930 .nvram_size = 0x2000,
931 .esp_irq = 18,
932 .le_irq = 16,
933 .clock_irq = 7,
934 .clock1_irq = 19,
935 .ms_kb_irq = 14,
936 .ser_irq = 15,
937 .fd_irq = 22,
938 .me_irq = 30,
939 .nvram_machine_id = 0x80,
940 .machine_id = scls_id,
941 .iommu_version = 0x05000000,
942 .intbit_to_level = {
943 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
944 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
945 },
946 .max_mem = 0x10000000,
947 .default_cpu_model = "TI MicroSparc I",
948 },
949 /* SPARCbook */
950 {
951 .iommu_base = 0x10000000,
952 .tcx_base = 0x50000000, // XXX
953 .slavio_base = 0x70000000,
954 .ms_kb_base = 0x71000000,
955 .serial_base = 0x71100000,
956 .nvram_base = 0x71200000,
957 .fd_base = 0x71400000,
958 .counter_base = 0x71d00000,
959 .intctl_base = 0x71e00000,
960 .idreg_base = 0x78000000,
961 .dma_base = 0x78400000,
962 .esp_base = 0x78800000,
963 .le_base = 0x78c00000,
964 .apc_base = 0x6a000000,
965 .aux1_base = 0x71900000,
966 .aux2_base = 0x71910000,
967 .vram_size = 0x00100000,
968 .nvram_size = 0x2000,
969 .esp_irq = 18,
970 .le_irq = 16,
971 .clock_irq = 7,
972 .clock1_irq = 19,
973 .ms_kb_irq = 14,
974 .ser_irq = 15,
975 .fd_irq = 22,
976 .me_irq = 30,
977 .nvram_machine_id = 0x80,
978 .machine_id = sbook_id,
979 .iommu_version = 0x05000000,
980 .intbit_to_level = {
981 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
982 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
983 },
984 .max_mem = 0x10000000,
985 .default_cpu_model = "TI MicroSparc I",
986 },
987 };
988
989 /* SPARCstation 5 hardware initialisation */
990 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
991 const char *boot_device, DisplayState *ds,
992 const char *kernel_filename, const char *kernel_cmdline,
993 const char *initrd_filename, const char *cpu_model)
994 {
995 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
996 kernel_cmdline, initrd_filename, cpu_model);
997 }
998
999 /* SPARCstation 10 hardware initialisation */
1000 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1001 const char *boot_device, DisplayState *ds,
1002 const char *kernel_filename, const char *kernel_cmdline,
1003 const char *initrd_filename, const char *cpu_model)
1004 {
1005 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1006 kernel_cmdline, initrd_filename, cpu_model);
1007 }
1008
1009 /* SPARCserver 600MP hardware initialisation */
1010 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1011 const char *boot_device, DisplayState *ds,
1012 const char *kernel_filename,
1013 const char *kernel_cmdline,
1014 const char *initrd_filename, const char *cpu_model)
1015 {
1016 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1017 kernel_cmdline, initrd_filename, cpu_model);
1018 }
1019
1020 /* SPARCstation 20 hardware initialisation */
1021 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1022 const char *boot_device, DisplayState *ds,
1023 const char *kernel_filename, const char *kernel_cmdline,
1024 const char *initrd_filename, const char *cpu_model)
1025 {
1026 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1027 kernel_cmdline, initrd_filename, cpu_model);
1028 }
1029
1030 /* SPARCstation Voyager hardware initialisation */
1031 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1032 const char *boot_device, DisplayState *ds,
1033 const char *kernel_filename, const char *kernel_cmdline,
1034 const char *initrd_filename, const char *cpu_model)
1035 {
1036 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1037 kernel_cmdline, initrd_filename, cpu_model);
1038 }
1039
1040 /* SPARCstation LX hardware initialisation */
1041 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1042 const char *boot_device, DisplayState *ds,
1043 const char *kernel_filename, const char *kernel_cmdline,
1044 const char *initrd_filename, const char *cpu_model)
1045 {
1046 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1047 kernel_cmdline, initrd_filename, cpu_model);
1048 }
1049
1050 /* SPARCstation 4 hardware initialisation */
1051 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1052 const char *boot_device, DisplayState *ds,
1053 const char *kernel_filename, const char *kernel_cmdline,
1054 const char *initrd_filename, const char *cpu_model)
1055 {
1056 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1057 kernel_cmdline, initrd_filename, cpu_model);
1058 }
1059
1060 /* SPARCClassic hardware initialisation */
1061 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1062 const char *boot_device, DisplayState *ds,
1063 const char *kernel_filename, const char *kernel_cmdline,
1064 const char *initrd_filename, const char *cpu_model)
1065 {
1066 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1067 kernel_cmdline, initrd_filename, cpu_model);
1068 }
1069
1070 /* SPARCbook hardware initialisation */
1071 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1072 const char *boot_device, DisplayState *ds,
1073 const char *kernel_filename, const char *kernel_cmdline,
1074 const char *initrd_filename, const char *cpu_model)
1075 {
1076 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1077 kernel_cmdline, initrd_filename, cpu_model);
1078 }
1079
1080 QEMUMachine ss5_machine = {
1081 .name = "SS-5",
1082 .desc = "Sun4m platform, SPARCstation 5",
1083 .init = ss5_init,
1084 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1085 .nodisk_ok = 1,
1086 .use_scsi = 1,
1087 };
1088
1089 QEMUMachine ss10_machine = {
1090 .name = "SS-10",
1091 .desc = "Sun4m platform, SPARCstation 10",
1092 .init = ss10_init,
1093 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1094 .nodisk_ok = 1,
1095 .use_scsi = 1,
1096 .max_cpus = 4,
1097 };
1098
1099 QEMUMachine ss600mp_machine = {
1100 .name = "SS-600MP",
1101 .desc = "Sun4m platform, SPARCserver 600MP",
1102 .init = ss600mp_init,
1103 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1104 .nodisk_ok = 1,
1105 .use_scsi = 1,
1106 .max_cpus = 4,
1107 };
1108
1109 QEMUMachine ss20_machine = {
1110 .name = "SS-20",
1111 .desc = "Sun4m platform, SPARCstation 20",
1112 .init = ss20_init,
1113 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1114 .nodisk_ok = 1,
1115 .use_scsi = 1,
1116 .max_cpus = 4,
1117 };
1118
1119 QEMUMachine voyager_machine = {
1120 .name = "Voyager",
1121 .desc = "Sun4m platform, SPARCstation Voyager",
1122 .init = vger_init,
1123 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1124 .nodisk_ok = 1,
1125 .use_scsi = 1,
1126 };
1127
1128 QEMUMachine ss_lx_machine = {
1129 .name = "LX",
1130 .desc = "Sun4m platform, SPARCstation LX",
1131 .init = ss_lx_init,
1132 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1133 .nodisk_ok = 1,
1134 .use_scsi = 1,
1135 };
1136
1137 QEMUMachine ss4_machine = {
1138 .name = "SS-4",
1139 .desc = "Sun4m platform, SPARCstation 4",
1140 .init = ss4_init,
1141 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1142 .nodisk_ok = 1,
1143 .use_scsi = 1,
1144 };
1145
1146 QEMUMachine scls_machine = {
1147 .name = "SPARCClassic",
1148 .desc = "Sun4m platform, SPARCClassic",
1149 .init = scls_init,
1150 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1151 .nodisk_ok = 1,
1152 .use_scsi = 1,
1153 };
1154
1155 QEMUMachine sbook_machine = {
1156 .name = "SPARCbook",
1157 .desc = "Sun4m platform, SPARCbook",
1158 .init = sbook_init,
1159 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1160 .nodisk_ok = 1,
1161 .use_scsi = 1,
1162 };
1163
1164 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1165 /* SS-1000 */
1166 {
1167 .iounit_bases = {
1168 0xfe0200000ULL,
1169 0xfe1200000ULL,
1170 0xfe2200000ULL,
1171 0xfe3200000ULL,
1172 -1,
1173 },
1174 .tcx_base = 0x820000000ULL,
1175 .slavio_base = 0xf00000000ULL,
1176 .ms_kb_base = 0xf00240000ULL,
1177 .serial_base = 0xf00200000ULL,
1178 .nvram_base = 0xf00280000ULL,
1179 .counter_base = 0xf00300000ULL,
1180 .espdma_base = 0x800081000ULL,
1181 .esp_base = 0x800080000ULL,
1182 .ledma_base = 0x800040000ULL,
1183 .le_base = 0x800060000ULL,
1184 .sbi_base = 0xf02800000ULL,
1185 .vram_size = 0x00100000,
1186 .nvram_size = 0x2000,
1187 .esp_irq = 3,
1188 .le_irq = 4,
1189 .clock_irq = 14,
1190 .clock1_irq = 10,
1191 .ms_kb_irq = 12,
1192 .ser_irq = 12,
1193 .nvram_machine_id = 0x80,
1194 .machine_id = ss1000_id,
1195 .iounit_version = 0x03000000,
1196 .max_mem = 0xf00000000ULL,
1197 .default_cpu_model = "TI SuperSparc II",
1198 },
1199 /* SS-2000 */
1200 {
1201 .iounit_bases = {
1202 0xfe0200000ULL,
1203 0xfe1200000ULL,
1204 0xfe2200000ULL,
1205 0xfe3200000ULL,
1206 0xfe4200000ULL,
1207 },
1208 .tcx_base = 0x820000000ULL,
1209 .slavio_base = 0xf00000000ULL,
1210 .ms_kb_base = 0xf00240000ULL,
1211 .serial_base = 0xf00200000ULL,
1212 .nvram_base = 0xf00280000ULL,
1213 .counter_base = 0xf00300000ULL,
1214 .espdma_base = 0x800081000ULL,
1215 .esp_base = 0x800080000ULL,
1216 .ledma_base = 0x800040000ULL,
1217 .le_base = 0x800060000ULL,
1218 .sbi_base = 0xf02800000ULL,
1219 .vram_size = 0x00100000,
1220 .nvram_size = 0x2000,
1221 .esp_irq = 3,
1222 .le_irq = 4,
1223 .clock_irq = 14,
1224 .clock1_irq = 10,
1225 .ms_kb_irq = 12,
1226 .ser_irq = 12,
1227 .nvram_machine_id = 0x80,
1228 .machine_id = ss2000_id,
1229 .iounit_version = 0x03000000,
1230 .max_mem = 0xf00000000ULL,
1231 .default_cpu_model = "TI SuperSparc II",
1232 },
1233 };
1234
1235 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1236 const char *boot_device,
1237 DisplayState *ds, const char *kernel_filename,
1238 const char *kernel_cmdline,
1239 const char *initrd_filename, const char *cpu_model)
1240 {
1241 CPUState *env, *envs[MAX_CPUS];
1242 unsigned int i;
1243 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1244 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1245 *espdma_irq, *ledma_irq;
1246 qemu_irq *esp_reset, *le_reset;
1247 ram_addr_t ram_offset, prom_offset, tcx_offset;
1248 unsigned long kernel_size;
1249 int ret;
1250 char buf[1024];
1251 int drive_index;
1252 void *fw_cfg;
1253
1254 /* init CPUs */
1255 if (!cpu_model)
1256 cpu_model = hwdef->default_cpu_model;
1257
1258 for (i = 0; i < smp_cpus; i++) {
1259 env = cpu_init(cpu_model);
1260 if (!env) {
1261 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1262 exit(1);
1263 }
1264 cpu_sparc_set_id(env, i);
1265 envs[i] = env;
1266 if (i == 0) {
1267 qemu_register_reset(main_cpu_reset, env);
1268 } else {
1269 qemu_register_reset(secondary_cpu_reset, env);
1270 env->halted = 1;
1271 }
1272 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1273 env->prom_addr = hwdef->slavio_base;
1274 }
1275
1276 for (i = smp_cpus; i < MAX_CPUS; i++)
1277 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1278
1279 /* allocate RAM */
1280 if ((uint64_t)RAM_size > hwdef->max_mem) {
1281 fprintf(stderr,
1282 "qemu: Too much memory for this machine: %d, maximum %d\n",
1283 (unsigned int)(RAM_size / (1024 * 1024)),
1284 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1285 exit(1);
1286 }
1287 ram_offset = qemu_ram_alloc(RAM_size);
1288 cpu_register_physical_memory(0, RAM_size, ram_offset);
1289
1290 /* load boot prom */
1291 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1292 cpu_register_physical_memory(hwdef->slavio_base,
1293 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1294 TARGET_PAGE_MASK,
1295 prom_offset | IO_MEM_ROM);
1296
1297 if (bios_name == NULL)
1298 bios_name = PROM_FILENAME;
1299 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1300 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1301 if (ret < 0 || ret > PROM_SIZE_MAX)
1302 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1303 if (ret < 0 || ret > PROM_SIZE_MAX) {
1304 fprintf(stderr, "qemu: could not load prom '%s'\n",
1305 buf);
1306 exit(1);
1307 }
1308
1309 /* set up devices */
1310 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1311
1312 for (i = 0; i < MAX_IOUNITS; i++)
1313 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1314 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1315 hwdef->iounit_version,
1316 sbi_irq[hwdef->me_irq]);
1317
1318 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1319 iounits[0], &espdma_irq, &esp_reset);
1320
1321 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1322 iounits[0], &ledma_irq, &le_reset);
1323
1324 if (graphic_depth != 8 && graphic_depth != 24) {
1325 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1326 exit (1);
1327 }
1328 tcx_offset = qemu_ram_alloc(hwdef->vram_size);
1329 tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
1330 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1331
1332 if (nd_table[0].model == NULL)
1333 nd_table[0].model = "lance";
1334 if (strcmp(nd_table[0].model, "lance") == 0) {
1335 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1336 } else if (strcmp(nd_table[0].model, "?") == 0) {
1337 fprintf(stderr, "qemu: Supported NICs: lance\n");
1338 exit (1);
1339 } else {
1340 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1341 exit (1);
1342 }
1343
1344 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1345 hwdef->nvram_size, 8);
1346
1347 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1348 sbi_cpu_irq, smp_cpus);
1349
1350 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1351 nographic, ESCC_CLOCK, 1);
1352 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1353 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1354 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], serial_hds[1],
1355 serial_hds[0], ESCC_CLOCK, 1);
1356
1357 if (drive_get_max_bus(IF_SCSI) > 0) {
1358 fprintf(stderr, "qemu: too many SCSI bus\n");
1359 exit(1);
1360 }
1361
1362 main_esp = esp_init(hwdef->esp_base, 2,
1363 espdma_memory_read, espdma_memory_write,
1364 espdma, *espdma_irq, esp_reset);
1365
1366 for (i = 0; i < ESP_MAX_DEVS; i++) {
1367 drive_index = drive_get_index(IF_SCSI, 0, i);
1368 if (drive_index == -1)
1369 continue;
1370 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1371 }
1372
1373 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1374 RAM_size);
1375
1376 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1377 boot_device, RAM_size, kernel_size, graphic_width,
1378 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1379 "Sun4d");
1380
1381 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1382 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1383 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1384 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1385 }
1386
1387 /* SPARCserver 1000 hardware initialisation */
1388 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1389 const char *boot_device, DisplayState *ds,
1390 const char *kernel_filename, const char *kernel_cmdline,
1391 const char *initrd_filename, const char *cpu_model)
1392 {
1393 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1394 kernel_cmdline, initrd_filename, cpu_model);
1395 }
1396
1397 /* SPARCcenter 2000 hardware initialisation */
1398 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1399 const char *boot_device, DisplayState *ds,
1400 const char *kernel_filename, const char *kernel_cmdline,
1401 const char *initrd_filename, const char *cpu_model)
1402 {
1403 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1404 kernel_cmdline, initrd_filename, cpu_model);
1405 }
1406
1407 QEMUMachine ss1000_machine = {
1408 .name = "SS-1000",
1409 .desc = "Sun4d platform, SPARCserver 1000",
1410 .init = ss1000_init,
1411 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1412 .nodisk_ok = 1,
1413 .use_scsi = 1,
1414 .max_cpus = 8,
1415 };
1416
1417 QEMUMachine ss2000_machine = {
1418 .name = "SS-2000",
1419 .desc = "Sun4d platform, SPARCcenter 2000",
1420 .init = ss2000_init,
1421 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1422 .nodisk_ok = 1,
1423 .use_scsi = 1,
1424 .max_cpus = 20,
1425 };
1426
1427 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1428 /* SS-2 */
1429 {
1430 .iommu_base = 0xf8000000,
1431 .tcx_base = 0xfe000000,
1432 .slavio_base = 0xf6000000,
1433 .intctl_base = 0xf5000000,
1434 .counter_base = 0xf3000000,
1435 .ms_kb_base = 0xf0000000,
1436 .serial_base = 0xf1000000,
1437 .nvram_base = 0xf2000000,
1438 .fd_base = 0xf7200000,
1439 .dma_base = 0xf8400000,
1440 .esp_base = 0xf8800000,
1441 .le_base = 0xf8c00000,
1442 .aux1_base = 0xf7400003,
1443 .vram_size = 0x00100000,
1444 .nvram_size = 0x800,
1445 .esp_irq = 2,
1446 .le_irq = 3,
1447 .clock_irq = 5,
1448 .clock1_irq = 7,
1449 .ms_kb_irq = 1,
1450 .ser_irq = 1,
1451 .fd_irq = 1,
1452 .me_irq = 1,
1453 .nvram_machine_id = 0x55,
1454 .machine_id = ss2_id,
1455 .max_mem = 0x10000000,
1456 .default_cpu_model = "Cypress CY7C601",
1457 },
1458 };
1459
1460 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1461 const char *boot_device,
1462 DisplayState *ds, const char *kernel_filename,
1463 const char *kernel_cmdline,
1464 const char *initrd_filename, const char *cpu_model)
1465 {
1466 CPUState *env;
1467 unsigned int i;
1468 void *iommu, *espdma, *ledma, *main_esp, *nvram;
1469 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1470 qemu_irq *esp_reset, *le_reset;
1471 qemu_irq *fdc_tc;
1472 ram_addr_t ram_offset, prom_offset, tcx_offset;
1473 unsigned long kernel_size;
1474 int ret;
1475 char buf[1024];
1476 BlockDriverState *fd[MAX_FD];
1477 int drive_index;
1478 void *fw_cfg;
1479
1480 /* init CPU */
1481 if (!cpu_model)
1482 cpu_model = hwdef->default_cpu_model;
1483
1484 env = cpu_init(cpu_model);
1485 if (!env) {
1486 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1487 exit(1);
1488 }
1489
1490 cpu_sparc_set_id(env, 0);
1491
1492 qemu_register_reset(main_cpu_reset, env);
1493 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1494 env->prom_addr = hwdef->slavio_base;
1495
1496 /* allocate RAM */
1497 if ((uint64_t)RAM_size > hwdef->max_mem) {
1498 fprintf(stderr,
1499 "qemu: Too much memory for this machine: %d, maximum %d\n",
1500 (unsigned int)(RAM_size / (1024 * 1024)),
1501 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1502 exit(1);
1503 }
1504 ram_offset = qemu_ram_alloc(RAM_size);
1505 cpu_register_physical_memory(0, RAM_size, ram_offset);
1506
1507 /* load boot prom */
1508 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1509 cpu_register_physical_memory(hwdef->slavio_base,
1510 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1511 TARGET_PAGE_MASK,
1512 prom_offset | IO_MEM_ROM);
1513
1514 if (bios_name == NULL)
1515 bios_name = PROM_FILENAME;
1516 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1517 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1518 if (ret < 0 || ret > PROM_SIZE_MAX)
1519 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1520 if (ret < 0 || ret > PROM_SIZE_MAX) {
1521 fprintf(stderr, "qemu: could not load prom '%s'\n",
1522 buf);
1523 exit(1);
1524 }
1525
1526 /* set up devices */
1527 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1528 &slavio_irq, cpu_irqs);
1529
1530 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1531 slavio_irq[hwdef->me_irq]);
1532
1533 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1534 iommu, &espdma_irq, &esp_reset);
1535
1536 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1537 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1538 &le_reset);
1539
1540 if (graphic_depth != 8 && graphic_depth != 24) {
1541 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1542 exit (1);
1543 }
1544 tcx_offset = qemu_ram_alloc(hwdef->vram_size);
1545 tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
1546 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1547
1548 if (nd_table[0].model == NULL)
1549 nd_table[0].model = "lance";
1550 if (strcmp(nd_table[0].model, "lance") == 0) {
1551 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1552 } else if (strcmp(nd_table[0].model, "?") == 0) {
1553 fprintf(stderr, "qemu: Supported NICs: lance\n");
1554 exit (1);
1555 } else {
1556 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1557 exit (1);
1558 }
1559
1560 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1561 hwdef->nvram_size, 2);
1562
1563 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1564 nographic, ESCC_CLOCK, 1);
1565 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1566 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1567 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], serial_hds[1],
1568 serial_hds[0], ESCC_CLOCK, 1);
1569
1570 slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0,
1571 slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
1572
1573 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1574 /* there is zero or one floppy drive */
1575 memset(fd, 0, sizeof(fd));
1576 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1577 if (drive_index != -1)
1578 fd[0] = drives_table[drive_index].bdrv;
1579
1580 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1581 fdc_tc);
1582 }
1583
1584 if (drive_get_max_bus(IF_SCSI) > 0) {
1585 fprintf(stderr, "qemu: too many SCSI bus\n");
1586 exit(1);
1587 }
1588
1589 main_esp = esp_init(hwdef->esp_base, 2,
1590 espdma_memory_read, espdma_memory_write,
1591 espdma, *espdma_irq, esp_reset);
1592
1593 for (i = 0; i < ESP_MAX_DEVS; i++) {
1594 drive_index = drive_get_index(IF_SCSI, 0, i);
1595 if (drive_index == -1)
1596 continue;
1597 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1598 }
1599
1600 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1601 RAM_size);
1602
1603 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1604 boot_device, RAM_size, kernel_size, graphic_width,
1605 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1606 "Sun4c");
1607
1608 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1609 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1610 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1611 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1612 }
1613
1614 /* SPARCstation 2 hardware initialisation */
1615 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1616 const char *boot_device, DisplayState *ds,
1617 const char *kernel_filename, const char *kernel_cmdline,
1618 const char *initrd_filename, const char *cpu_model)
1619 {
1620 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1621 kernel_cmdline, initrd_filename, cpu_model);
1622 }
1623
1624 QEMUMachine ss2_machine = {
1625 .name = "SS-2",
1626 .desc = "Sun4c platform, SPARCstation 2",
1627 .init = ss2_init,
1628 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1629 .nodisk_ok = 1,
1630 .use_scsi = 1,
1631 };
Samsung s3c2440 and arm920t support for the mini2440 dev board