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Fix ARMv6 translation table base address calculation.
[qemu/mini2440.git] / target-ppc / op_helper.c
blob32b347100d9023e661ed10c6a85cbbbc0a4b1125
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "exec.h"
21 #include "host-utils.h"
22
23 #include "helper_regs.h"
24 #include "op_helper.h"
25
26 #define MEMSUFFIX _raw
27 #include "op_helper.h"
28 #include "op_helper_mem.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #define MEMSUFFIX _user
31 #include "op_helper.h"
32 #include "op_helper_mem.h"
33 #define MEMSUFFIX _kernel
34 #include "op_helper.h"
35 #include "op_helper_mem.h"
36 #define MEMSUFFIX _hypv
37 #include "op_helper.h"
38 #include "op_helper_mem.h"
39 #endif
40
41 //#define DEBUG_OP
42 //#define DEBUG_EXCEPTIONS
43 //#define DEBUG_SOFTWARE_TLB
44
45 /*****************************************************************************/
46 /* Exceptions processing helpers */
47
48 void do_raise_exception_err (uint32_t exception, int error_code)
49 {
50 #if 0
51 printf("Raise exception %3x code : %d\n", exception, error_code);
52 #endif
53 env->exception_index = exception;
54 env->error_code = error_code;
55 cpu_loop_exit();
56 }
57
58 void do_raise_exception (uint32_t exception)
59 {
60 do_raise_exception_err(exception, 0);
61 }
62
63 /*****************************************************************************/
64 /* Registers load and stores */
65 uint32_t helper_load_cr (void)
66 {
67 return (env->crf[0] << 28) |
68 (env->crf[1] << 24) |
69 (env->crf[2] << 20) |
70 (env->crf[3] << 16) |
71 (env->crf[4] << 12) |
72 (env->crf[5] << 8) |
73 (env->crf[6] << 4) |
74 (env->crf[7] << 0);
75 }
76
77 void helper_store_cr (target_ulong val, uint32_t mask)
78 {
79 int i, sh;
80
81 for (i = 0, sh = 7; i < 8; i++, sh--) {
82 if (mask & (1 << sh))
83 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
84 }
85 }
86
87 #if defined(TARGET_PPC64)
88 void do_store_pri (int prio)
89 {
90 env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
91 env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
92 }
93 #endif
94
95 target_ulong ppc_load_dump_spr (int sprn)
96 {
97 if (loglevel != 0) {
98 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
99 sprn, sprn, env->spr[sprn]);
100 }
101
102 return env->spr[sprn];
103 }
104
105 void ppc_store_dump_spr (int sprn, target_ulong val)
106 {
107 if (loglevel != 0) {
108 fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
109 sprn, sprn, env->spr[sprn], val);
110 }
111 env->spr[sprn] = val;
112 }
113
114 /*****************************************************************************/
115 /* Fixed point operations helpers */
116 void do_adde (void)
117 {
118 T2 = T0;
119 T0 += T1 + xer_ca;
120 if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
121 (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
122 env->xer &= ~(1 << XER_CA);
123 } else {
124 env->xer |= (1 << XER_CA);
125 }
126 }
127
128 #if defined(TARGET_PPC64)
129 void do_adde_64 (void)
130 {
131 T2 = T0;
132 T0 += T1 + xer_ca;
133 if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
134 (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
135 env->xer &= ~(1 << XER_CA);
136 } else {
137 env->xer |= (1 << XER_CA);
138 }
139 }
140 #endif
141
142 void do_addmeo (void)
143 {
144 int ov;
145 T1 = T0;
146 T0 += xer_ca + (-1);
147 ov = ((uint32_t)T1 & ((uint32_t)T1 ^ (uint32_t)T0)) >> 31;
148 if (ov) {
149 env->xer |= (1 << XER_OV) | (1 << XER_SO);
150 } else {
151 env->xer &= ~(1 << XER_OV);
152 }
153 if (likely((uint32_t)T1 != 0))
154 env->xer |= (1 << XER_CA);
155 }
156
157 #if defined(TARGET_PPC64)
158 void do_addmeo_64 (void)
159 {
160 int ov;
161 T1 = T0;
162 T0 += xer_ca + (-1);
163 ov = ((uint64_t)T1 & ((uint64_t)T1 ^ (uint64_t)T0)) >> 63;
164 if (ov) {
165 env->xer |= (1 << XER_OV) | (1 << XER_SO);
166 } else {
167 env->xer &= ~(1 << XER_OV);
168 }
169 if (likely((uint64_t)T1 != 0))
170 env->xer |= (1 << XER_CA);
171 }
172 #endif
173
174 void do_divwo (void)
175 {
176 if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
177 (int32_t)T1 == 0))) {
178 env->xer &= ~(1 << XER_OV);
179 T0 = (int32_t)T0 / (int32_t)T1;
180 } else {
181 env->xer |= (1 << XER_OV) | (1 << XER_SO);
182 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
183 }
184 }
185
186 #if defined(TARGET_PPC64)
187 void do_divdo (void)
188 {
189 if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == (int64_t)-1LL) ||
190 (int64_t)T1 == 0))) {
191 env->xer &= ~(1 << XER_OV);
192 T0 = (int64_t)T0 / (int64_t)T1;
193 } else {
194 env->xer |= (1 << XER_OV) | (1 << XER_SO);
195 T0 = UINT64_MAX * ((uint64_t)T0 >> 63);
196 }
197 }
198 #endif
199
200 void do_divwuo (void)
201 {
202 if (likely((uint32_t)T1 != 0)) {
203 env->xer &= ~(1 << XER_OV);
204 T0 = (uint32_t)T0 / (uint32_t)T1;
205 } else {
206 env->xer |= (1 << XER_OV) | (1 << XER_SO);
207 T0 = 0;
208 }
209 }
210
211 #if defined(TARGET_PPC64)
212 void do_divduo (void)
213 {
214 if (likely((uint64_t)T1 != 0)) {
215 env->xer &= ~(1 << XER_OV);
216 T0 = (uint64_t)T0 / (uint64_t)T1;
217 } else {
218 env->xer |= (1 << XER_OV) | (1 << XER_SO);
219 T0 = 0;
220 }
221 }
222 #endif
223
224 void do_mullwo (void)
225 {
226 int64_t res = (int64_t)(int32_t)T0 * (int64_t)(int32_t)T1;
227
228 if (likely((int32_t)res == res)) {
229 env->xer &= ~(1 << XER_OV);
230 } else {
231 env->xer |= (1 << XER_OV) | (1 << XER_SO);
232 }
233 T0 = (int32_t)res;
234 }
235
236 #if defined(TARGET_PPC64)
237 void do_mulldo (void)
238 {
239 int64_t th;
240 uint64_t tl;
241
242 muls64(&tl, (uint64_t *)&th, T0, T1);
243 T0 = (int64_t)tl;
244 /* If th != 0 && th != -1, then we had an overflow */
245 if (likely((uint64_t)(th + 1) <= 1)) {
246 env->xer &= ~(1 << XER_OV);
247 } else {
248 env->xer |= (1 << XER_OV) | (1 << XER_SO);
249 }
250 }
251 #endif
252
253 void do_nego (void)
254 {
255 if (likely((int32_t)T0 != INT32_MIN)) {
256 env->xer &= ~(1 << XER_OV);
257 T0 = -(int32_t)T0;
258 } else {
259 env->xer |= (1 << XER_OV) | (1 << XER_SO);
260 }
261 }
262
263 #if defined(TARGET_PPC64)
264 void do_nego_64 (void)
265 {
266 if (likely((int64_t)T0 != INT64_MIN)) {
267 env->xer &= ~(1 << XER_OV);
268 T0 = -(int64_t)T0;
269 } else {
270 env->xer |= (1 << XER_OV) | (1 << XER_SO);
271 }
272 }
273 #endif
274
275 void do_subfe (void)
276 {
277 T0 = T1 + ~T0 + xer_ca;
278 if (likely((uint32_t)T0 >= (uint32_t)T1 &&
279 (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
280 env->xer &= ~(1 << XER_CA);
281 } else {
282 env->xer |= (1 << XER_CA);
283 }
284 }
285
286 #if defined(TARGET_PPC64)
287 void do_subfe_64 (void)
288 {
289 T0 = T1 + ~T0 + xer_ca;
290 if (likely((uint64_t)T0 >= (uint64_t)T1 &&
291 (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
292 env->xer &= ~(1 << XER_CA);
293 } else {
294 env->xer |= (1 << XER_CA);
295 }
296 }
297 #endif
298
299 void do_subfmeo (void)
300 {
301 int ov;
302 T1 = T0;
303 T0 = ~T0 + xer_ca - 1;
304 ov = ((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0)) >> 31;
305 if (ov) {
306 env->xer |= (1 << XER_OV) | (1 << XER_SO);
307 } else {
308 env->xer &= ~(1 << XER_OV);
309 }
310 if (likely((uint32_t)T1 != UINT32_MAX))
311 env->xer |= (1 << XER_CA);
312 }
313
314 #if defined(TARGET_PPC64)
315 void do_subfmeo_64 (void)
316 {
317 int ov;
318 T1 = T0;
319 T0 = ~T0 + xer_ca - 1;
320 ov = ((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0)) >> 63;
321 if (ov) {
322 env->xer |= (1 << XER_OV) | (1 << XER_SO);
323 } else {
324 env->xer &= ~(1 << XER_OV);
325 }
326 if (likely((uint64_t)T1 != UINT64_MAX))
327 env->xer |= (1 << XER_CA);
328 }
329 #endif
330
331 void do_subfzeo (void)
332 {
333 int ov;
334 T1 = T0;
335 T0 = ~T0 + xer_ca;
336 ov = (((uint32_t)~T1 ^ UINT32_MAX) &
337 ((uint32_t)(~T1) ^ (uint32_t)T0)) >> 31;
338 if (ov) {
339 env->xer |= (1 << XER_OV) | (1 << XER_SO);
340 } else {
341 env->xer &= ~(1 << XER_OV);
342 }
343 if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
344 env->xer &= ~(1 << XER_CA);
345 } else {
346 env->xer |= (1 << XER_CA);
347 }
348 }
349
350 #if defined(TARGET_PPC64)
351 void do_subfzeo_64 (void)
352 {
353 int ov;
354 T1 = T0;
355 T0 = ~T0 + xer_ca;
356 ov = (((uint64_t)~T1 ^ UINT64_MAX) &
357 ((uint64_t)(~T1) ^ (uint64_t)T0)) >> 63;
358 if (ov) {
359 env->xer |= (1 << XER_OV) | (1 << XER_SO);
360 } else {
361 env->xer &= ~(1 << XER_OV);
362 }
363 if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
364 env->xer &= ~(1 << XER_CA);
365 } else {
366 env->xer |= (1 << XER_CA);
367 }
368 }
369 #endif
370
371 target_ulong helper_cntlzw (target_ulong t)
372 {
373 return clz32(t);
374 }
375
376 #if defined(TARGET_PPC64)
377 target_ulong helper_cntlzd (target_ulong t)
378 {
379 return clz64(t);
380 }
381 #endif
382
383 /* shift right arithmetic helper */
384 target_ulong helper_sraw (target_ulong value, target_ulong shift)
385 {
386 int32_t ret;
387
388 if (likely(!(shift & 0x20))) {
389 if (likely((uint32_t)shift != 0)) {
390 shift &= 0x1f;
391 ret = (int32_t)value >> shift;
392 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
393 env->xer &= ~(1 << XER_CA);
394 } else {
395 env->xer |= (1 << XER_CA);
396 }
397 } else {
398 ret = (int32_t)value;
399 env->xer &= ~(1 << XER_CA);
400 }
401 } else {
402 ret = (int32_t)value >> 31;
403 if (ret) {
404 env->xer |= (1 << XER_CA);
405 } else {
406 env->xer &= ~(1 << XER_CA);
407 }
408 }
409 return (target_long)ret;
410 }
411
412 #if defined(TARGET_PPC64)
413 target_ulong helper_srad (target_ulong value, target_ulong shift)
414 {
415 int64_t ret;
416
417 if (likely(!(shift & 0x40))) {
418 if (likely((uint64_t)shift != 0)) {
419 shift &= 0x3f;
420 ret = (int64_t)value >> shift;
421 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
422 env->xer &= ~(1 << XER_CA);
423 } else {
424 env->xer |= (1 << XER_CA);
425 }
426 } else {
427 ret = (int64_t)value;
428 env->xer &= ~(1 << XER_CA);
429 }
430 } else {
431 ret = (int64_t)value >> 63;
432 if (ret) {
433 env->xer |= (1 << XER_CA);
434 } else {
435 env->xer &= ~(1 << XER_CA);
436 }
437 }
438 return ret;
439 }
440 #endif
441
442 target_ulong helper_popcntb (target_ulong val)
443 {
444 uint32_t ret;
445 int i;
446
447 ret = 0;
448 for (i = 0; i < 32; i += 8)
449 ret |= ctpop8((val >> i) & 0xFF) << i;
450 return ret;
451 }
452
453 #if defined(TARGET_PPC64)
454 target_ulong helper_popcntb_64 (target_ulong val)
455 {
456 uint64_t ret;
457 int i;
458
459 ret = 0;
460 for (i = 0; i < 64; i += 8)
461 ret |= ctpop8((val >> i) & 0xFF) << i;
462 return ret;
463 }
464 #endif
465
466 /*****************************************************************************/
467 /* Floating point operations helpers */
468 static always_inline int fpisneg (float64 d)
469 {
470 CPU_DoubleU u;
471
472 u.d = d;
473
474 return u.ll >> 63 != 0;
475 }
476
477 static always_inline int isden (float64 d)
478 {
479 CPU_DoubleU u;
480
481 u.d = d;
482
483 return ((u.ll >> 52) & 0x7FF) == 0;
484 }
485
486 static always_inline int iszero (float64 d)
487 {
488 CPU_DoubleU u;
489
490 u.d = d;
491
492 return (u.ll & ~0x8000000000000000ULL) == 0;
493 }
494
495 static always_inline int isinfinity (float64 d)
496 {
497 CPU_DoubleU u;
498
499 u.d = d;
500
501 return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
502 (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
503 }
504
505 #ifdef CONFIG_SOFTFLOAT
506 static always_inline int isfinite (float64 d)
507 {
508 CPU_DoubleU u;
509
510 u.d = d;
511
512 return (((u.ll >> 52) & 0x7FF) != 0x7FF);
513 }
514
515 static always_inline int isnormal (float64 d)
516 {
517 CPU_DoubleU u;
518
519 u.d = d;
520
521 uint32_t exp = (u.ll >> 52) & 0x7FF;
522 return ((0 < exp) && (exp < 0x7FF));
523 }
524 #endif
525
526 void do_compute_fprf (int set_fprf)
527 {
528 int isneg;
529
530 isneg = fpisneg(FT0);
531 if (unlikely(float64_is_nan(FT0))) {
532 if (float64_is_signaling_nan(FT0)) {
533 /* Signaling NaN: flags are undefined */
534 T0 = 0x00;
535 } else {
536 /* Quiet NaN */
537 T0 = 0x11;
538 }
539 } else if (unlikely(isinfinity(FT0))) {
540 /* +/- infinity */
541 if (isneg)
542 T0 = 0x09;
543 else
544 T0 = 0x05;
545 } else {
546 if (iszero(FT0)) {
547 /* +/- zero */
548 if (isneg)
549 T0 = 0x12;
550 else
551 T0 = 0x02;
552 } else {
553 if (isden(FT0)) {
554 /* Denormalized numbers */
555 T0 = 0x10;
556 } else {
557 /* Normalized numbers */
558 T0 = 0x00;
559 }
560 if (isneg) {
561 T0 |= 0x08;
562 } else {
563 T0 |= 0x04;
564 }
565 }
566 }
567 if (set_fprf) {
568 /* We update FPSCR_FPRF */
569 env->fpscr &= ~(0x1F << FPSCR_FPRF);
570 env->fpscr |= T0 << FPSCR_FPRF;
571 }
572 /* We just need fpcc to update Rc1 */
573 T0 &= 0xF;
574 }
575
576 /* Floating-point invalid operations exception */
577 static always_inline void fload_invalid_op_excp (int op)
578 {
579 int ve;
580
581 ve = fpscr_ve;
582 if (op & POWERPC_EXCP_FP_VXSNAN) {
583 /* Operation on signaling NaN */
584 env->fpscr |= 1 << FPSCR_VXSNAN;
585 }
586 if (op & POWERPC_EXCP_FP_VXSOFT) {
587 /* Software-defined condition */
588 env->fpscr |= 1 << FPSCR_VXSOFT;
589 }
590 switch (op & ~(POWERPC_EXCP_FP_VXSOFT | POWERPC_EXCP_FP_VXSNAN)) {
591 case POWERPC_EXCP_FP_VXISI:
592 /* Magnitude subtraction of infinities */
593 env->fpscr |= 1 << FPSCR_VXISI;
594 goto update_arith;
595 case POWERPC_EXCP_FP_VXIDI:
596 /* Division of infinity by infinity */
597 env->fpscr |= 1 << FPSCR_VXIDI;
598 goto update_arith;
599 case POWERPC_EXCP_FP_VXZDZ:
600 /* Division of zero by zero */
601 env->fpscr |= 1 << FPSCR_VXZDZ;
602 goto update_arith;
603 case POWERPC_EXCP_FP_VXIMZ:
604 /* Multiplication of zero by infinity */
605 env->fpscr |= 1 << FPSCR_VXIMZ;
606 goto update_arith;
607 case POWERPC_EXCP_FP_VXVC:
608 /* Ordered comparison of NaN */
609 env->fpscr |= 1 << FPSCR_VXVC;
610 env->fpscr &= ~(0xF << FPSCR_FPCC);
611 env->fpscr |= 0x11 << FPSCR_FPCC;
612 /* We must update the target FPR before raising the exception */
613 if (ve != 0) {
614 env->exception_index = POWERPC_EXCP_PROGRAM;
615 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
616 /* Update the floating-point enabled exception summary */
617 env->fpscr |= 1 << FPSCR_FEX;
618 /* Exception is differed */
619 ve = 0;
620 }
621 break;
622 case POWERPC_EXCP_FP_VXSQRT:
623 /* Square root of a negative number */
624 env->fpscr |= 1 << FPSCR_VXSQRT;
625 update_arith:
626 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
627 if (ve == 0) {
628 /* Set the result to quiet NaN */
629 FT0 = UINT64_MAX;
630 env->fpscr &= ~(0xF << FPSCR_FPCC);
631 env->fpscr |= 0x11 << FPSCR_FPCC;
632 }
633 break;
634 case POWERPC_EXCP_FP_VXCVI:
635 /* Invalid conversion */
636 env->fpscr |= 1 << FPSCR_VXCVI;
637 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
638 if (ve == 0) {
639 /* Set the result to quiet NaN */
640 FT0 = UINT64_MAX;
641 env->fpscr &= ~(0xF << FPSCR_FPCC);
642 env->fpscr |= 0x11 << FPSCR_FPCC;
643 }
644 break;
645 }
646 /* Update the floating-point invalid operation summary */
647 env->fpscr |= 1 << FPSCR_VX;
648 /* Update the floating-point exception summary */
649 env->fpscr |= 1 << FPSCR_FX;
650 if (ve != 0) {
651 /* Update the floating-point enabled exception summary */
652 env->fpscr |= 1 << FPSCR_FEX;
653 if (msr_fe0 != 0 || msr_fe1 != 0)
654 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
655 }
656 }
657
658 static always_inline void float_zero_divide_excp (void)
659 {
660 CPU_DoubleU u0, u1;
661
662 env->fpscr |= 1 << FPSCR_ZX;
663 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
664 /* Update the floating-point exception summary */
665 env->fpscr |= 1 << FPSCR_FX;
666 if (fpscr_ze != 0) {
667 /* Update the floating-point enabled exception summary */
668 env->fpscr |= 1 << FPSCR_FEX;
669 if (msr_fe0 != 0 || msr_fe1 != 0) {
670 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
671 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
672 }
673 } else {
674 /* Set the result to infinity */
675 u0.d = FT0;
676 u1.d = FT1;
677 u0.ll = ((u0.ll ^ u1.ll) & 0x8000000000000000ULL);
678 u0.ll |= 0x7FFULL << 52;
679 FT0 = u0.d;
680 }
681 }
682
683 static always_inline void float_overflow_excp (void)
684 {
685 env->fpscr |= 1 << FPSCR_OX;
686 /* Update the floating-point exception summary */
687 env->fpscr |= 1 << FPSCR_FX;
688 if (fpscr_oe != 0) {
689 /* XXX: should adjust the result */
690 /* Update the floating-point enabled exception summary */
691 env->fpscr |= 1 << FPSCR_FEX;
692 /* We must update the target FPR before raising the exception */
693 env->exception_index = POWERPC_EXCP_PROGRAM;
694 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
695 } else {
696 env->fpscr |= 1 << FPSCR_XX;
697 env->fpscr |= 1 << FPSCR_FI;
698 }
699 }
700
701 static always_inline void float_underflow_excp (void)
702 {
703 env->fpscr |= 1 << FPSCR_UX;
704 /* Update the floating-point exception summary */
705 env->fpscr |= 1 << FPSCR_FX;
706 if (fpscr_ue != 0) {
707 /* XXX: should adjust the result */
708 /* Update the floating-point enabled exception summary */
709 env->fpscr |= 1 << FPSCR_FEX;
710 /* We must update the target FPR before raising the exception */
711 env->exception_index = POWERPC_EXCP_PROGRAM;
712 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
713 }
714 }
715
716 static always_inline void float_inexact_excp (void)
717 {
718 env->fpscr |= 1 << FPSCR_XX;
719 /* Update the floating-point exception summary */
720 env->fpscr |= 1 << FPSCR_FX;
721 if (fpscr_xe != 0) {
722 /* Update the floating-point enabled exception summary */
723 env->fpscr |= 1 << FPSCR_FEX;
724 /* We must update the target FPR before raising the exception */
725 env->exception_index = POWERPC_EXCP_PROGRAM;
726 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
727 }
728 }
729
730 static always_inline void fpscr_set_rounding_mode (void)
731 {
732 int rnd_type;
733
734 /* Set rounding mode */
735 switch (fpscr_rn) {
736 case 0:
737 /* Best approximation (round to nearest) */
738 rnd_type = float_round_nearest_even;
739 break;
740 case 1:
741 /* Smaller magnitude (round toward zero) */
742 rnd_type = float_round_to_zero;
743 break;
744 case 2:
745 /* Round toward +infinite */
746 rnd_type = float_round_up;
747 break;
748 default:
749 case 3:
750 /* Round toward -infinite */
751 rnd_type = float_round_down;
752 break;
753 }
754 set_float_rounding_mode(rnd_type, &env->fp_status);
755 }
756
757 void do_fpscr_setbit (int bit)
758 {
759 int prev;
760
761 prev = (env->fpscr >> bit) & 1;
762 env->fpscr |= 1 << bit;
763 if (prev == 0) {
764 switch (bit) {
765 case FPSCR_VX:
766 env->fpscr |= 1 << FPSCR_FX;
767 if (fpscr_ve)
768 goto raise_ve;
769 case FPSCR_OX:
770 env->fpscr |= 1 << FPSCR_FX;
771 if (fpscr_oe)
772 goto raise_oe;
773 break;
774 case FPSCR_UX:
775 env->fpscr |= 1 << FPSCR_FX;
776 if (fpscr_ue)
777 goto raise_ue;
778 break;
779 case FPSCR_ZX:
780 env->fpscr |= 1 << FPSCR_FX;
781 if (fpscr_ze)
782 goto raise_ze;
783 break;
784 case FPSCR_XX:
785 env->fpscr |= 1 << FPSCR_FX;
786 if (fpscr_xe)
787 goto raise_xe;
788 break;
789 case FPSCR_VXSNAN:
790 case FPSCR_VXISI:
791 case FPSCR_VXIDI:
792 case FPSCR_VXZDZ:
793 case FPSCR_VXIMZ:
794 case FPSCR_VXVC:
795 case FPSCR_VXSOFT:
796 case FPSCR_VXSQRT:
797 case FPSCR_VXCVI:
798 env->fpscr |= 1 << FPSCR_VX;
799 env->fpscr |= 1 << FPSCR_FX;
800 if (fpscr_ve != 0)
801 goto raise_ve;
802 break;
803 case FPSCR_VE:
804 if (fpscr_vx != 0) {
805 raise_ve:
806 env->error_code = POWERPC_EXCP_FP;
807 if (fpscr_vxsnan)
808 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
809 if (fpscr_vxisi)
810 env->error_code |= POWERPC_EXCP_FP_VXISI;
811 if (fpscr_vxidi)
812 env->error_code |= POWERPC_EXCP_FP_VXIDI;
813 if (fpscr_vxzdz)
814 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
815 if (fpscr_vximz)
816 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
817 if (fpscr_vxvc)
818 env->error_code |= POWERPC_EXCP_FP_VXVC;
819 if (fpscr_vxsoft)
820 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
821 if (fpscr_vxsqrt)
822 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
823 if (fpscr_vxcvi)
824 env->error_code |= POWERPC_EXCP_FP_VXCVI;
825 goto raise_excp;
826 }
827 break;
828 case FPSCR_OE:
829 if (fpscr_ox != 0) {
830 raise_oe:
831 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
832 goto raise_excp;
833 }
834 break;
835 case FPSCR_UE:
836 if (fpscr_ux != 0) {
837 raise_ue:
838 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
839 goto raise_excp;
840 }
841 break;
842 case FPSCR_ZE:
843 if (fpscr_zx != 0) {
844 raise_ze:
845 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
846 goto raise_excp;
847 }
848 break;
849 case FPSCR_XE:
850 if (fpscr_xx != 0) {
851 raise_xe:
852 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
853 goto raise_excp;
854 }
855 break;
856 case FPSCR_RN1:
857 case FPSCR_RN:
858 fpscr_set_rounding_mode();
859 break;
860 default:
861 break;
862 raise_excp:
863 /* Update the floating-point enabled exception summary */
864 env->fpscr |= 1 << FPSCR_FEX;
865 /* We have to update Rc1 before raising the exception */
866 env->exception_index = POWERPC_EXCP_PROGRAM;
867 break;
868 }
869 }
870 }
871
872 #if defined(WORDS_BIGENDIAN)
873 #define WORD0 0
874 #define WORD1 1
875 #else
876 #define WORD0 1
877 #define WORD1 0
878 #endif
879 void do_store_fpscr (uint32_t mask)
880 {
881 /*
882 * We use only the 32 LSB of the incoming fpr
883 */
884 CPU_DoubleU u;
885 uint32_t prev, new;
886 int i;
887
888 u.d = FT0;
889 prev = env->fpscr;
890 new = u.l.lower;
891 new &= ~0x90000000;
892 new |= prev & 0x90000000;
893 for (i = 0; i < 7; i++) {
894 if (mask & (1 << i)) {
895 env->fpscr &= ~(0xF << (4 * i));
896 env->fpscr |= new & (0xF << (4 * i));
897 }
898 }
899 /* Update VX and FEX */
900 if (fpscr_ix != 0)
901 env->fpscr |= 1 << FPSCR_VX;
902 else
903 env->fpscr &= ~(1 << FPSCR_VX);
904 if ((fpscr_ex & fpscr_eex) != 0) {
905 env->fpscr |= 1 << FPSCR_FEX;
906 env->exception_index = POWERPC_EXCP_PROGRAM;
907 /* XXX: we should compute it properly */
908 env->error_code = POWERPC_EXCP_FP;
909 }
910 else
911 env->fpscr &= ~(1 << FPSCR_FEX);
912 fpscr_set_rounding_mode();
913 }
914 #undef WORD0
915 #undef WORD1
916
917 #ifdef CONFIG_SOFTFLOAT
918 void do_float_check_status (void)
919 {
920 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
921 (env->error_code & POWERPC_EXCP_FP)) {
922 /* Differred floating-point exception after target FPR update */
923 if (msr_fe0 != 0 || msr_fe1 != 0)
924 do_raise_exception_err(env->exception_index, env->error_code);
925 } else if (env->fp_status.float_exception_flags & float_flag_overflow) {
926 float_overflow_excp();
927 } else if (env->fp_status.float_exception_flags & float_flag_underflow) {
928 float_underflow_excp();
929 } else if (env->fp_status.float_exception_flags & float_flag_inexact) {
930 float_inexact_excp();
931 }
932 }
933 #endif
934
935 #if USE_PRECISE_EMULATION
936 void do_fadd (void)
937 {
938 if (unlikely(float64_is_signaling_nan(FT0) ||
939 float64_is_signaling_nan(FT1))) {
940 /* sNaN addition */
941 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
942 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
943 fpisneg(FT0) == fpisneg(FT1))) {
944 FT0 = float64_add(FT0, FT1, &env->fp_status);
945 } else {
946 /* Magnitude subtraction of infinities */
947 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
948 }
949 }
950
951 void do_fsub (void)
952 {
953 if (unlikely(float64_is_signaling_nan(FT0) ||
954 float64_is_signaling_nan(FT1))) {
955 /* sNaN subtraction */
956 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
957 } else if (likely(isfinite(FT0) || isfinite(FT1) ||
958 fpisneg(FT0) != fpisneg(FT1))) {
959 FT0 = float64_sub(FT0, FT1, &env->fp_status);
960 } else {
961 /* Magnitude subtraction of infinities */
962 fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
963 }
964 }
965
966 void do_fmul (void)
967 {
968 if (unlikely(float64_is_signaling_nan(FT0) ||
969 float64_is_signaling_nan(FT1))) {
970 /* sNaN multiplication */
971 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
972 } else if (unlikely((isinfinity(FT0) && iszero(FT1)) ||
973 (iszero(FT0) && isinfinity(FT1)))) {
974 /* Multiplication of zero by infinity */
975 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
976 } else {
977 FT0 = float64_mul(FT0, FT1, &env->fp_status);
978 }
979 }
980
981 void do_fdiv (void)
982 {
983 if (unlikely(float64_is_signaling_nan(FT0) ||
984 float64_is_signaling_nan(FT1))) {
985 /* sNaN division */
986 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
987 } else if (unlikely(isinfinity(FT0) && isinfinity(FT1))) {
988 /* Division of infinity by infinity */
989 fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
990 } else if (unlikely(iszero(FT1))) {
991 if (iszero(FT0)) {
992 /* Division of zero by zero */
993 fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
994 } else {
995 /* Division by zero */
996 float_zero_divide_excp();
997 }
998 } else {
999 FT0 = float64_div(FT0, FT1, &env->fp_status);
1000 }
1001 }
1002 #endif /* USE_PRECISE_EMULATION */
1003
1004 void do_fctiw (void)
1005 {
1006 CPU_DoubleU p;
1007
1008 if (unlikely(float64_is_signaling_nan(FT0))) {
1009 /* sNaN conversion */
1010 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1011 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1012 /* qNan / infinity conversion */
1013 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1014 } else {
1015 p.ll = float64_to_int32(FT0, &env->fp_status);
1016 #if USE_PRECISE_EMULATION
1017 /* XXX: higher bits are not supposed to be significant.
1018 * to make tests easier, return the same as a real PowerPC 750
1019 */
1020 p.ll |= 0xFFF80000ULL << 32;
1021 #endif
1022 FT0 = p.d;
1023 }
1024 }
1025
1026 void do_fctiwz (void)
1027 {
1028 CPU_DoubleU p;
1029
1030 if (unlikely(float64_is_signaling_nan(FT0))) {
1031 /* sNaN conversion */
1032 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1033 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1034 /* qNan / infinity conversion */
1035 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1036 } else {
1037 p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status);
1038 #if USE_PRECISE_EMULATION
1039 /* XXX: higher bits are not supposed to be significant.
1040 * to make tests easier, return the same as a real PowerPC 750
1041 */
1042 p.ll |= 0xFFF80000ULL << 32;
1043 #endif
1044 FT0 = p.d;
1045 }
1046 }
1047
1048 #if defined(TARGET_PPC64)
1049 void do_fcfid (void)
1050 {
1051 CPU_DoubleU p;
1052
1053 p.d = FT0;
1054 FT0 = int64_to_float64(p.ll, &env->fp_status);
1055 }
1056
1057 void do_fctid (void)
1058 {
1059 CPU_DoubleU p;
1060
1061 if (unlikely(float64_is_signaling_nan(FT0))) {
1062 /* sNaN conversion */
1063 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1064 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1065 /* qNan / infinity conversion */
1066 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1067 } else {
1068 p.ll = float64_to_int64(FT0, &env->fp_status);
1069 FT0 = p.d;
1070 }
1071 }
1072
1073 void do_fctidz (void)
1074 {
1075 CPU_DoubleU p;
1076
1077 if (unlikely(float64_is_signaling_nan(FT0))) {
1078 /* sNaN conversion */
1079 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1080 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1081 /* qNan / infinity conversion */
1082 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1083 } else {
1084 p.ll = float64_to_int64_round_to_zero(FT0, &env->fp_status);
1085 FT0 = p.d;
1086 }
1087 }
1088
1089 #endif
1090
1091 static always_inline void do_fri (int rounding_mode)
1092 {
1093 if (unlikely(float64_is_signaling_nan(FT0))) {
1094 /* sNaN round */
1095 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
1096 } else if (unlikely(float64_is_nan(FT0) || isinfinity(FT0))) {
1097 /* qNan / infinity round */
1098 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1099 } else {
1100 set_float_rounding_mode(rounding_mode, &env->fp_status);
1101 FT0 = float64_round_to_int(FT0, &env->fp_status);
1102 /* Restore rounding mode from FPSCR */
1103 fpscr_set_rounding_mode();
1104 }
1105 }
1106
1107 void do_frin (void)
1108 {
1109 do_fri(float_round_nearest_even);
1110 }
1111
1112 void do_friz (void)
1113 {
1114 do_fri(float_round_to_zero);
1115 }
1116
1117 void do_frip (void)
1118 {
1119 do_fri(float_round_up);
1120 }
1121
1122 void do_frim (void)
1123 {
1124 do_fri(float_round_down);
1125 }
1126
1127 #if USE_PRECISE_EMULATION
1128 void do_fmadd (void)
1129 {
1130 if (unlikely(float64_is_signaling_nan(FT0) ||
1131 float64_is_signaling_nan(FT1) ||
1132 float64_is_signaling_nan(FT2))) {
1133 /* sNaN operation */
1134 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1135 } else {
1136 #ifdef FLOAT128
1137 /* This is the way the PowerPC specification defines it */
1138 float128 ft0_128, ft1_128;
1139
1140 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1141 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1142 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1143 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1144 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1145 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1146 #else
1147 /* This is OK on x86 hosts */
1148 FT0 = (FT0 * FT1) + FT2;
1149 #endif
1150 }
1151 }
1152
1153 void do_fmsub (void)
1154 {
1155 if (unlikely(float64_is_signaling_nan(FT0) ||
1156 float64_is_signaling_nan(FT1) ||
1157 float64_is_signaling_nan(FT2))) {
1158 /* sNaN operation */
1159 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1160 } else {
1161 #ifdef FLOAT128
1162 /* This is the way the PowerPC specification defines it */
1163 float128 ft0_128, ft1_128;
1164
1165 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1166 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1167 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1168 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1169 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1170 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1171 #else
1172 /* This is OK on x86 hosts */
1173 FT0 = (FT0 * FT1) - FT2;
1174 #endif
1175 }
1176 }
1177 #endif /* USE_PRECISE_EMULATION */
1178
1179 void do_fnmadd (void)
1180 {
1181 if (unlikely(float64_is_signaling_nan(FT0) ||
1182 float64_is_signaling_nan(FT1) ||
1183 float64_is_signaling_nan(FT2))) {
1184 /* sNaN operation */
1185 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1186 } else {
1187 #if USE_PRECISE_EMULATION
1188 #ifdef FLOAT128
1189 /* This is the way the PowerPC specification defines it */
1190 float128 ft0_128, ft1_128;
1191
1192 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1193 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1194 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1195 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1196 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1197 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1198 #else
1199 /* This is OK on x86 hosts */
1200 FT0 = (FT0 * FT1) + FT2;
1201 #endif
1202 #else
1203 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1204 FT0 = float64_add(FT0, FT2, &env->fp_status);
1205 #endif
1206 if (likely(!isnan(FT0)))
1207 FT0 = float64_chs(FT0);
1208 }
1209 }
1210
1211 void do_fnmsub (void)
1212 {
1213 if (unlikely(float64_is_signaling_nan(FT0) ||
1214 float64_is_signaling_nan(FT1) ||
1215 float64_is_signaling_nan(FT2))) {
1216 /* sNaN operation */
1217 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1218 } else {
1219 #if USE_PRECISE_EMULATION
1220 #ifdef FLOAT128
1221 /* This is the way the PowerPC specification defines it */
1222 float128 ft0_128, ft1_128;
1223
1224 ft0_128 = float64_to_float128(FT0, &env->fp_status);
1225 ft1_128 = float64_to_float128(FT1, &env->fp_status);
1226 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
1227 ft1_128 = float64_to_float128(FT2, &env->fp_status);
1228 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1229 FT0 = float128_to_float64(ft0_128, &env->fp_status);
1230 #else
1231 /* This is OK on x86 hosts */
1232 FT0 = (FT0 * FT1) - FT2;
1233 #endif
1234 #else
1235 FT0 = float64_mul(FT0, FT1, &env->fp_status);
1236 FT0 = float64_sub(FT0, FT2, &env->fp_status);
1237 #endif
1238 if (likely(!isnan(FT0)))
1239 FT0 = float64_chs(FT0);
1240 }
1241 }
1242
1243 #if USE_PRECISE_EMULATION
1244 void do_frsp (void)
1245 {
1246 if (unlikely(float64_is_signaling_nan(FT0))) {
1247 /* sNaN square root */
1248 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1249 } else {
1250 FT0 = float64_to_float32(FT0, &env->fp_status);
1251 }
1252 }
1253 #endif /* USE_PRECISE_EMULATION */
1254
1255 void do_fsqrt (void)
1256 {
1257 if (unlikely(float64_is_signaling_nan(FT0))) {
1258 /* sNaN square root */
1259 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1260 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1261 /* Square root of a negative nonzero number */
1262 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1263 } else {
1264 FT0 = float64_sqrt(FT0, &env->fp_status);
1265 }
1266 }
1267
1268 void do_fre (void)
1269 {
1270 CPU_DoubleU p;
1271
1272 if (unlikely(float64_is_signaling_nan(FT0))) {
1273 /* sNaN reciprocal */
1274 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1275 } else if (unlikely(iszero(FT0))) {
1276 /* Zero reciprocal */
1277 float_zero_divide_excp();
1278 } else if (likely(isnormal(FT0))) {
1279 FT0 = float64_div(1.0, FT0, &env->fp_status);
1280 } else {
1281 p.d = FT0;
1282 if (p.ll == 0x8000000000000000ULL) {
1283 p.ll = 0xFFF0000000000000ULL;
1284 } else if (p.ll == 0x0000000000000000ULL) {
1285 p.ll = 0x7FF0000000000000ULL;
1286 } else if (isnan(FT0)) {
1287 p.ll = 0x7FF8000000000000ULL;
1288 } else if (fpisneg(FT0)) {
1289 p.ll = 0x8000000000000000ULL;
1290 } else {
1291 p.ll = 0x0000000000000000ULL;
1292 }
1293 FT0 = p.d;
1294 }
1295 }
1296
1297 void do_fres (void)
1298 {
1299 CPU_DoubleU p;
1300
1301 if (unlikely(float64_is_signaling_nan(FT0))) {
1302 /* sNaN reciprocal */
1303 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1304 } else if (unlikely(iszero(FT0))) {
1305 /* Zero reciprocal */
1306 float_zero_divide_excp();
1307 } else if (likely(isnormal(FT0))) {
1308 #if USE_PRECISE_EMULATION
1309 FT0 = float64_div(1.0, FT0, &env->fp_status);
1310 FT0 = float64_to_float32(FT0, &env->fp_status);
1311 #else
1312 FT0 = float32_div(1.0, FT0, &env->fp_status);
1313 #endif
1314 } else {
1315 p.d = FT0;
1316 if (p.ll == 0x8000000000000000ULL) {
1317 p.ll = 0xFFF0000000000000ULL;
1318 } else if (p.ll == 0x0000000000000000ULL) {
1319 p.ll = 0x7FF0000000000000ULL;
1320 } else if (isnan(FT0)) {
1321 p.ll = 0x7FF8000000000000ULL;
1322 } else if (fpisneg(FT0)) {
1323 p.ll = 0x8000000000000000ULL;
1324 } else {
1325 p.ll = 0x0000000000000000ULL;
1326 }
1327 FT0 = p.d;
1328 }
1329 }
1330
1331 void do_frsqrte (void)
1332 {
1333 CPU_DoubleU p;
1334
1335 if (unlikely(float64_is_signaling_nan(FT0))) {
1336 /* sNaN reciprocal square root */
1337 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1338 } else if (unlikely(fpisneg(FT0) && !iszero(FT0))) {
1339 /* Reciprocal square root of a negative nonzero number */
1340 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
1341 } else if (likely(isnormal(FT0))) {
1342 FT0 = float64_sqrt(FT0, &env->fp_status);
1343 FT0 = float32_div(1.0, FT0, &env->fp_status);
1344 } else {
1345 p.d = FT0;
1346 if (p.ll == 0x8000000000000000ULL) {
1347 p.ll = 0xFFF0000000000000ULL;
1348 } else if (p.ll == 0x0000000000000000ULL) {
1349 p.ll = 0x7FF0000000000000ULL;
1350 } else if (isnan(FT0)) {
1351 p.ll |= 0x000FFFFFFFFFFFFFULL;
1352 } else if (fpisneg(FT0)) {
1353 p.ll = 0x7FF8000000000000ULL;
1354 } else {
1355 p.ll = 0x0000000000000000ULL;
1356 }
1357 FT0 = p.d;
1358 }
1359 }
1360
1361 void do_fsel (void)
1362 {
1363 if (!fpisneg(FT0) || iszero(FT0))
1364 FT0 = FT1;
1365 else
1366 FT0 = FT2;
1367 }
1368
1369 uint32_t helper_fcmpu (void)
1370 {
1371 uint32_t ret = 0;
1372
1373 if (unlikely(float64_is_signaling_nan(FT0) ||
1374 float64_is_signaling_nan(FT1))) {
1375 /* sNaN comparison */
1376 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1377 } else {
1378 if (float64_lt(FT0, FT1, &env->fp_status)) {
1379 ret = 0x08UL;
1380 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1381 ret = 0x04UL;
1382 } else {
1383 ret = 0x02UL;
1384 }
1385 }
1386 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1387 env->fpscr |= ret << FPSCR_FPRF;
1388 return ret;
1389 }
1390
1391 uint32_t helper_fcmpo (void)
1392 {
1393 uint32_t ret = 0;
1394
1395 if (unlikely(float64_is_nan(FT0) ||
1396 float64_is_nan(FT1))) {
1397 if (float64_is_signaling_nan(FT0) ||
1398 float64_is_signaling_nan(FT1)) {
1399 /* sNaN comparison */
1400 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1401 POWERPC_EXCP_FP_VXVC);
1402 } else {
1403 /* qNaN comparison */
1404 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1405 }
1406 } else {
1407 if (float64_lt(FT0, FT1, &env->fp_status)) {
1408 ret = 0x08UL;
1409 } else if (!float64_le(FT0, FT1, &env->fp_status)) {
1410 ret = 0x04UL;
1411 } else {
1412 ret = 0x02UL;
1413 }
1414 }
1415 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1416 env->fpscr |= ret << FPSCR_FPRF;
1417 return ret;
1418 }
1419
1420 #if !defined (CONFIG_USER_ONLY)
1421 void cpu_dump_rfi (target_ulong RA, target_ulong msr);
1422
1423 void do_store_msr (void)
1424 {
1425 T0 = hreg_store_msr(env, T0, 0);
1426 if (T0 != 0) {
1427 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1428 do_raise_exception(T0);
1429 }
1430 }
1431
1432 static always_inline void __do_rfi (target_ulong nip, target_ulong msr,
1433 target_ulong msrm, int keep_msrh)
1434 {
1435 #if defined(TARGET_PPC64)
1436 if (msr & (1ULL << MSR_SF)) {
1437 nip = (uint64_t)nip;
1438 msr &= (uint64_t)msrm;
1439 } else {
1440 nip = (uint32_t)nip;
1441 msr = (uint32_t)(msr & msrm);
1442 if (keep_msrh)
1443 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
1444 }
1445 #else
1446 nip = (uint32_t)nip;
1447 msr &= (uint32_t)msrm;
1448 #endif
1449 /* XXX: beware: this is false if VLE is supported */
1450 env->nip = nip & ~((target_ulong)0x00000003);
1451 hreg_store_msr(env, msr, 1);
1452 #if defined (DEBUG_OP)
1453 cpu_dump_rfi(env->nip, env->msr);
1454 #endif
1455 /* No need to raise an exception here,
1456 * as rfi is always the last insn of a TB
1457 */
1458 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1459 }
1460
1461 void do_rfi (void)
1462 {
1463 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1464 ~((target_ulong)0xFFFF0000), 1);
1465 }
1466
1467 #if defined(TARGET_PPC64)
1468 void do_rfid (void)
1469 {
1470 __do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1471 ~((target_ulong)0xFFFF0000), 0);
1472 }
1473
1474 void do_hrfid (void)
1475 {
1476 __do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1477 ~((target_ulong)0xFFFF0000), 0);
1478 }
1479 #endif
1480 #endif
1481
1482 void do_tw (int flags)
1483 {
1484 if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
1485 ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
1486 ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
1487 ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
1488 ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
1489 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1490 }
1491 }
1492
1493 #if defined(TARGET_PPC64)
1494 void do_td (int flags)
1495 {
1496 if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
1497 ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
1498 ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
1499 ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
1500 ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
1501 do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
1502 }
1503 #endif
1504
1505 /*****************************************************************************/
1506 /* PowerPC 601 specific instructions (POWER bridge) */
1507 void do_POWER_abso (void)
1508 {
1509 if ((int32_t)T0 == INT32_MIN) {
1510 T0 = INT32_MAX;
1511 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1512 } else if ((int32_t)T0 < 0) {
1513 T0 = -T0;
1514 env->xer &= ~(1 << XER_OV);
1515 } else {
1516 env->xer &= ~(1 << XER_OV);
1517 }
1518 }
1519
1520 void do_POWER_clcs (void)
1521 {
1522 switch (T0) {
1523 case 0x0CUL:
1524 /* Instruction cache line size */
1525 T0 = env->icache_line_size;
1526 break;
1527 case 0x0DUL:
1528 /* Data cache line size */
1529 T0 = env->dcache_line_size;
1530 break;
1531 case 0x0EUL:
1532 /* Minimum cache line size */
1533 T0 = env->icache_line_size < env->dcache_line_size ?
1534 env->icache_line_size : env->dcache_line_size;
1535 break;
1536 case 0x0FUL:
1537 /* Maximum cache line size */
1538 T0 = env->icache_line_size > env->dcache_line_size ?
1539 env->icache_line_size : env->dcache_line_size;
1540 break;
1541 default:
1542 /* Undefined */
1543 break;
1544 }
1545 }
1546
1547 void do_POWER_div (void)
1548 {
1549 uint64_t tmp;
1550
1551 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1552 (int32_t)T1 == 0) {
1553 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1554 env->spr[SPR_MQ] = 0;
1555 } else {
1556 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1557 env->spr[SPR_MQ] = tmp % T1;
1558 T0 = tmp / (int32_t)T1;
1559 }
1560 }
1561
1562 void do_POWER_divo (void)
1563 {
1564 int64_t tmp;
1565
1566 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1567 (int32_t)T1 == 0) {
1568 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1569 env->spr[SPR_MQ] = 0;
1570 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1571 } else {
1572 tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
1573 env->spr[SPR_MQ] = tmp % T1;
1574 tmp /= (int32_t)T1;
1575 if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
1576 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1577 } else {
1578 env->xer &= ~(1 << XER_OV);
1579 }
1580 T0 = tmp;
1581 }
1582 }
1583
1584 void do_POWER_divs (void)
1585 {
1586 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1587 (int32_t)T1 == 0) {
1588 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1589 env->spr[SPR_MQ] = 0;
1590 } else {
1591 env->spr[SPR_MQ] = T0 % T1;
1592 T0 = (int32_t)T0 / (int32_t)T1;
1593 }
1594 }
1595
1596 void do_POWER_divso (void)
1597 {
1598 if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == (int32_t)-1) ||
1599 (int32_t)T1 == 0) {
1600 T0 = UINT32_MAX * ((uint32_t)T0 >> 31);
1601 env->spr[SPR_MQ] = 0;
1602 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1603 } else {
1604 T0 = (int32_t)T0 / (int32_t)T1;
1605 env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
1606 env->xer &= ~(1 << XER_OV);
1607 }
1608 }
1609
1610 void do_POWER_dozo (void)
1611 {
1612 if ((int32_t)T1 > (int32_t)T0) {
1613 T2 = T0;
1614 T0 = T1 - T0;
1615 if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
1616 ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
1617 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1618 } else {
1619 env->xer &= ~(1 << XER_OV);
1620 }
1621 } else {
1622 T0 = 0;
1623 env->xer &= ~(1 << XER_OV);
1624 }
1625 }
1626
1627 void do_POWER_maskg (void)
1628 {
1629 uint32_t ret;
1630
1631 if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
1632 ret = UINT32_MAX;
1633 } else {
1634 ret = (UINT32_MAX >> ((uint32_t)T0)) ^
1635 ((UINT32_MAX >> ((uint32_t)T1)) >> 1);
1636 if ((uint32_t)T0 > (uint32_t)T1)
1637 ret = ~ret;
1638 }
1639 T0 = ret;
1640 }
1641
1642 void do_POWER_mulo (void)
1643 {
1644 uint64_t tmp;
1645
1646 tmp = (uint64_t)T0 * (uint64_t)T1;
1647 env->spr[SPR_MQ] = tmp >> 32;
1648 T0 = tmp;
1649 if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
1650 env->xer |= (1 << XER_OV) | (1 << XER_SO);
1651 } else {
1652 env->xer &= ~(1 << XER_OV);
1653 }
1654 }
1655
1656 #if !defined (CONFIG_USER_ONLY)
1657 void do_POWER_rac (void)
1658 {
1659 mmu_ctx_t ctx;
1660 int nb_BATs;
1661
1662 /* We don't have to generate many instances of this instruction,
1663 * as rac is supervisor only.
1664 */
1665 /* XXX: FIX THIS: Pretend we have no BAT */
1666 nb_BATs = env->nb_BATs;
1667 env->nb_BATs = 0;
1668 if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT) == 0)
1669 T0 = ctx.raddr;
1670 env->nb_BATs = nb_BATs;
1671 }
1672
1673 void do_POWER_rfsvc (void)
1674 {
1675 __do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
1676 }
1677
1678 void do_store_hid0_601 (void)
1679 {
1680 uint32_t hid0;
1681
1682 hid0 = env->spr[SPR_HID0];
1683 if ((T0 ^ hid0) & 0x00000008) {
1684 /* Change current endianness */
1685 env->hflags &= ~(1 << MSR_LE);
1686 env->hflags_nmsr &= ~(1 << MSR_LE);
1687 env->hflags_nmsr |= (1 << MSR_LE) & (((T0 >> 3) & 1) << MSR_LE);
1688 env->hflags |= env->hflags_nmsr;
1689 if (loglevel != 0) {
1690 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
1691 __func__, T0 & 0x8 ? 'l' : 'b', env->hflags);
1692 }
1693 }
1694 env->spr[SPR_HID0] = T0;
1695 }
1696 #endif
1697
1698 /*****************************************************************************/
1699 /* 602 specific instructions */
1700 /* mfrom is the most crazy instruction ever seen, imho ! */
1701 /* Real implementation uses a ROM table. Do the same */
1702 #define USE_MFROM_ROM_TABLE
1703 void do_op_602_mfrom (void)
1704 {
1705 if (likely(T0 < 602)) {
1706 #if defined(USE_MFROM_ROM_TABLE)
1707 #include "mfrom_table.c"
1708 T0 = mfrom_ROM_table[T0];
1709 #else
1710 double d;
1711 /* Extremly decomposed:
1712 * -T0 / 256
1713 * T0 = 256 * log10(10 + 1.0) + 0.5
1714 */
1715 d = T0;
1716 d = float64_div(d, 256, &env->fp_status);
1717 d = float64_chs(d);
1718 d = exp10(d); // XXX: use float emulation function
1719 d = float64_add(d, 1.0, &env->fp_status);
1720 d = log10(d); // XXX: use float emulation function
1721 d = float64_mul(d, 256, &env->fp_status);
1722 d = float64_add(d, 0.5, &env->fp_status);
1723 T0 = float64_round_to_int(d, &env->fp_status);
1724 #endif
1725 } else {
1726 T0 = 0;
1727 }
1728 }
1729
1730 /*****************************************************************************/
1731 /* Embedded PowerPC specific helpers */
1732 void do_405_check_sat (void)
1733 {
1734 if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
1735 !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
1736 /* Saturate result */
1737 if (T2 >> 31) {
1738 T0 = INT32_MIN;
1739 } else {
1740 T0 = INT32_MAX;
1741 }
1742 }
1743 }
1744
1745 /* XXX: to be improved to check access rights when in user-mode */
1746 void do_load_dcr (void)
1747 {
1748 target_ulong val;
1749
1750 if (unlikely(env->dcr_env == NULL)) {
1751 if (loglevel != 0) {
1752 fprintf(logfile, "No DCR environment\n");
1753 }
1754 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1755 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1756 } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
1757 if (loglevel != 0) {
1758 fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
1759 }
1760 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1761 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1762 } else {
1763 T0 = val;
1764 }
1765 }
1766
1767 void do_store_dcr (void)
1768 {
1769 if (unlikely(env->dcr_env == NULL)) {
1770 if (loglevel != 0) {
1771 fprintf(logfile, "No DCR environment\n");
1772 }
1773 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1774 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
1775 } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
1776 if (loglevel != 0) {
1777 fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
1778 }
1779 do_raise_exception_err(POWERPC_EXCP_PROGRAM,
1780 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
1781 }
1782 }
1783
1784 #if !defined(CONFIG_USER_ONLY)
1785 void do_40x_rfci (void)
1786 {
1787 __do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1788 ~((target_ulong)0xFFFF0000), 0);
1789 }
1790
1791 void do_rfci (void)
1792 {
1793 __do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1794 ~((target_ulong)0x3FFF0000), 0);
1795 }
1796
1797 void do_rfdi (void)
1798 {
1799 __do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1800 ~((target_ulong)0x3FFF0000), 0);
1801 }
1802
1803 void do_rfmci (void)
1804 {
1805 __do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1806 ~((target_ulong)0x3FFF0000), 0);
1807 }
1808
1809 void do_load_403_pb (int num)
1810 {
1811 T0 = env->pb[num];
1812 }
1813
1814 void do_store_403_pb (int num)
1815 {
1816 if (likely(env->pb[num] != T0)) {
1817 env->pb[num] = T0;
1818 /* Should be optimized */
1819 tlb_flush(env, 1);
1820 }
1821 }
1822 #endif
1823
1824 /* 440 specific */
1825 void do_440_dlmzb (void)
1826 {
1827 target_ulong mask;
1828 int i;
1829
1830 i = 1;
1831 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1832 if ((T0 & mask) == 0)
1833 goto done;
1834 i++;
1835 }
1836 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
1837 if ((T1 & mask) == 0)
1838 break;
1839 i++;
1840 }
1841 done:
1842 T0 = i;
1843 }
1844
1845 /* SPE extension helpers */
1846 /* Use a table to make this quicker */
1847 static uint8_t hbrev[16] = {
1848 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1849 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1850 };
1851
1852 static always_inline uint8_t byte_reverse (uint8_t val)
1853 {
1854 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1855 }
1856
1857 static always_inline uint32_t word_reverse (uint32_t val)
1858 {
1859 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1860 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1861 }
1862
1863 #define MASKBITS 16 // Random value - to be fixed (implementation dependant)
1864 void do_brinc (void)
1865 {
1866 uint32_t a, b, d, mask;
1867
1868 mask = UINT32_MAX >> (32 - MASKBITS);
1869 a = T0 & mask;
1870 b = T1 & mask;
1871 d = word_reverse(1 + word_reverse(a | ~b));
1872 T0 = (T0 & ~mask) | (d & b);
1873 }
1874
1875 #define DO_SPE_OP2(name) \
1876 void do_ev##name (void) \
1877 { \
1878 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
1879 (uint64_t)_do_e##name(T0_64, T1_64); \
1880 }
1881
1882 #define DO_SPE_OP1(name) \
1883 void do_ev##name (void) \
1884 { \
1885 T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
1886 (uint64_t)_do_e##name(T0_64); \
1887 }
1888
1889 /* Fixed-point vector arithmetic */
1890 static always_inline uint32_t _do_eabs (uint32_t val)
1891 {
1892 if ((val & 0x80000000) && val != 0x80000000)
1893 val -= val;
1894
1895 return val;
1896 }
1897
1898 static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
1899 {
1900 return op1 + op2;
1901 }
1902
1903 static always_inline int _do_ecntlsw (uint32_t val)
1904 {
1905 if (val & 0x80000000)
1906 return clz32(~val);
1907 else
1908 return clz32(val);
1909 }
1910
1911 static always_inline int _do_ecntlzw (uint32_t val)
1912 {
1913 return clz32(val);
1914 }
1915
1916 static always_inline uint32_t _do_eneg (uint32_t val)
1917 {
1918 if (val != 0x80000000)
1919 val -= val;
1920
1921 return val;
1922 }
1923
1924 static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
1925 {
1926 return rotl32(op1, op2);
1927 }
1928
1929 static always_inline uint32_t _do_erndw (uint32_t val)
1930 {
1931 return (val + 0x000080000000) & 0xFFFF0000;
1932 }
1933
1934 static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
1935 {
1936 /* No error here: 6 bits are used */
1937 return op1 << (op2 & 0x3F);
1938 }
1939
1940 static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
1941 {
1942 /* No error here: 6 bits are used */
1943 return op1 >> (op2 & 0x3F);
1944 }
1945
1946 static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
1947 {
1948 /* No error here: 6 bits are used */
1949 return op1 >> (op2 & 0x3F);
1950 }
1951
1952 static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
1953 {
1954 return op2 - op1;
1955 }
1956
1957 /* evabs */
1958 DO_SPE_OP1(abs);
1959 /* evaddw */
1960 DO_SPE_OP2(addw);
1961 /* evcntlsw */
1962 DO_SPE_OP1(cntlsw);
1963 /* evcntlzw */
1964 DO_SPE_OP1(cntlzw);
1965 /* evneg */
1966 DO_SPE_OP1(neg);
1967 /* evrlw */
1968 DO_SPE_OP2(rlw);
1969 /* evrnd */
1970 DO_SPE_OP1(rndw);
1971 /* evslw */
1972 DO_SPE_OP2(slw);
1973 /* evsrws */
1974 DO_SPE_OP2(srws);
1975 /* evsrwu */
1976 DO_SPE_OP2(srwu);
1977 /* evsubfw */
1978 DO_SPE_OP2(subfw);
1979
1980 /* evsel is a little bit more complicated... */
1981 static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
1982 {
1983 if (n)
1984 return op1;
1985 else
1986 return op2;
1987 }
1988
1989 void do_evsel (void)
1990 {
1991 T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
1992 (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
1993 }
1994
1995 /* Fixed-point vector comparisons */
1996 #define DO_SPE_CMP(name) \
1997 void do_ev##name (void) \
1998 { \
1999 T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
2000 T1_64 >> 32) << 32, \
2001 _do_e##name(T0_64, T1_64)); \
2002 }
2003
2004 static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
2005 {
2006 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
2007 }
2008 static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
2009 {
2010 return op1 == op2 ? 1 : 0;
2011 }
2012
2013 static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
2014 {
2015 return op1 > op2 ? 1 : 0;
2016 }
2017
2018 static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
2019 {
2020 return op1 > op2 ? 1 : 0;
2021 }
2022
2023 static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
2024 {
2025 return op1 < op2 ? 1 : 0;
2026 }
2027
2028 static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
2029 {
2030 return op1 < op2 ? 1 : 0;
2031 }
2032
2033 /* evcmpeq */
2034 DO_SPE_CMP(cmpeq);
2035 /* evcmpgts */
2036 DO_SPE_CMP(cmpgts);
2037 /* evcmpgtu */
2038 DO_SPE_CMP(cmpgtu);
2039 /* evcmplts */
2040 DO_SPE_CMP(cmplts);
2041 /* evcmpltu */
2042 DO_SPE_CMP(cmpltu);
2043
2044 /* Single precision floating-point conversions from/to integer */
2045 static always_inline uint32_t _do_efscfsi (int32_t val)
2046 {
2047 CPU_FloatU u;
2048
2049 u.f = int32_to_float32(val, &env->spe_status);
2050
2051 return u.l;
2052 }
2053
2054 static always_inline uint32_t _do_efscfui (uint32_t val)
2055 {
2056 CPU_FloatU u;
2057
2058 u.f = uint32_to_float32(val, &env->spe_status);
2059
2060 return u.l;
2061 }
2062
2063 static always_inline int32_t _do_efsctsi (uint32_t val)
2064 {
2065 CPU_FloatU u;
2066
2067 u.l = val;
2068 /* NaN are not treated the same way IEEE 754 does */
2069 if (unlikely(isnan(u.f)))
2070 return 0;
2071
2072 return float32_to_int32(u.f, &env->spe_status);
2073 }
2074
2075 static always_inline uint32_t _do_efsctui (uint32_t val)
2076 {
2077 CPU_FloatU u;
2078
2079 u.l = val;
2080 /* NaN are not treated the same way IEEE 754 does */
2081 if (unlikely(isnan(u.f)))
2082 return 0;
2083
2084 return float32_to_uint32(u.f, &env->spe_status);
2085 }
2086
2087 static always_inline int32_t _do_efsctsiz (uint32_t val)
2088 {
2089 CPU_FloatU u;
2090
2091 u.l = val;
2092 /* NaN are not treated the same way IEEE 754 does */
2093 if (unlikely(isnan(u.f)))
2094 return 0;
2095
2096 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2097 }
2098
2099 static always_inline uint32_t _do_efsctuiz (uint32_t val)
2100 {
2101 CPU_FloatU u;
2102
2103 u.l = val;
2104 /* NaN are not treated the same way IEEE 754 does */
2105 if (unlikely(isnan(u.f)))
2106 return 0;
2107
2108 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2109 }
2110
2111 void do_efscfsi (void)
2112 {
2113 T0_64 = _do_efscfsi(T0_64);
2114 }
2115
2116 void do_efscfui (void)
2117 {
2118 T0_64 = _do_efscfui(T0_64);
2119 }
2120
2121 void do_efsctsi (void)
2122 {
2123 T0_64 = _do_efsctsi(T0_64);
2124 }
2125
2126 void do_efsctui (void)
2127 {
2128 T0_64 = _do_efsctui(T0_64);
2129 }
2130
2131 void do_efsctsiz (void)
2132 {
2133 T0_64 = _do_efsctsiz(T0_64);
2134 }
2135
2136 void do_efsctuiz (void)
2137 {
2138 T0_64 = _do_efsctuiz(T0_64);
2139 }
2140
2141 /* Single precision floating-point conversion to/from fractional */
2142 static always_inline uint32_t _do_efscfsf (uint32_t val)
2143 {
2144 CPU_FloatU u;
2145 float32 tmp;
2146
2147 u.f = int32_to_float32(val, &env->spe_status);
2148 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2149 u.f = float32_div(u.f, tmp, &env->spe_status);
2150
2151 return u.l;
2152 }
2153
2154 static always_inline uint32_t _do_efscfuf (uint32_t val)
2155 {
2156 CPU_FloatU u;
2157 float32 tmp;
2158
2159 u.f = uint32_to_float32(val, &env->spe_status);
2160 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2161 u.f = float32_div(u.f, tmp, &env->spe_status);
2162
2163 return u.l;
2164 }
2165
2166 static always_inline int32_t _do_efsctsf (uint32_t val)
2167 {
2168 CPU_FloatU u;
2169 float32 tmp;
2170
2171 u.l = val;
2172 /* NaN are not treated the same way IEEE 754 does */
2173 if (unlikely(isnan(u.f)))
2174 return 0;
2175 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2176 u.f = float32_mul(u.f, tmp, &env->spe_status);
2177
2178 return float32_to_int32(u.f, &env->spe_status);
2179 }
2180
2181 static always_inline uint32_t _do_efsctuf (uint32_t val)
2182 {
2183 CPU_FloatU u;
2184 float32 tmp;
2185
2186 u.l = val;
2187 /* NaN are not treated the same way IEEE 754 does */
2188 if (unlikely(isnan(u.f)))
2189 return 0;
2190 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2191 u.f = float32_mul(u.f, tmp, &env->spe_status);
2192
2193 return float32_to_uint32(u.f, &env->spe_status);
2194 }
2195
2196 static always_inline int32_t _do_efsctsfz (uint32_t val)
2197 {
2198 CPU_FloatU u;
2199 float32 tmp;
2200
2201 u.l = val;
2202 /* NaN are not treated the same way IEEE 754 does */
2203 if (unlikely(isnan(u.f)))
2204 return 0;
2205 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2206 u.f = float32_mul(u.f, tmp, &env->spe_status);
2207
2208 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2209 }
2210
2211 static always_inline uint32_t _do_efsctufz (uint32_t val)
2212 {
2213 CPU_FloatU u;
2214 float32 tmp;
2215
2216 u.l = val;
2217 /* NaN are not treated the same way IEEE 754 does */
2218 if (unlikely(isnan(u.f)))
2219 return 0;
2220 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2221 u.f = float32_mul(u.f, tmp, &env->spe_status);
2222
2223 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2224 }
2225
2226 void do_efscfsf (void)
2227 {
2228 T0_64 = _do_efscfsf(T0_64);
2229 }
2230
2231 void do_efscfuf (void)
2232 {
2233 T0_64 = _do_efscfuf(T0_64);
2234 }
2235
2236 void do_efsctsf (void)
2237 {
2238 T0_64 = _do_efsctsf(T0_64);
2239 }
2240
2241 void do_efsctuf (void)
2242 {
2243 T0_64 = _do_efsctuf(T0_64);
2244 }
2245
2246 void do_efsctsfz (void)
2247 {
2248 T0_64 = _do_efsctsfz(T0_64);
2249 }
2250
2251 void do_efsctufz (void)
2252 {
2253 T0_64 = _do_efsctufz(T0_64);
2254 }
2255
2256 /* Double precision floating point helpers */
2257 static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
2258 {
2259 /* XXX: TODO: test special values (NaN, infinites, ...) */
2260 return _do_efdtstlt(op1, op2);
2261 }
2262
2263 static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
2264 {
2265 /* XXX: TODO: test special values (NaN, infinites, ...) */
2266 return _do_efdtstgt(op1, op2);
2267 }
2268
2269 static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
2270 {
2271 /* XXX: TODO: test special values (NaN, infinites, ...) */
2272 return _do_efdtsteq(op1, op2);
2273 }
2274
2275 void do_efdcmplt (void)
2276 {
2277 T0 = _do_efdcmplt(T0_64, T1_64);
2278 }
2279
2280 void do_efdcmpgt (void)
2281 {
2282 T0 = _do_efdcmpgt(T0_64, T1_64);
2283 }
2284
2285 void do_efdcmpeq (void)
2286 {
2287 T0 = _do_efdcmpeq(T0_64, T1_64);
2288 }
2289
2290 /* Double precision floating-point conversion to/from integer */
2291 static always_inline uint64_t _do_efdcfsi (int64_t val)
2292 {
2293 CPU_DoubleU u;
2294
2295 u.d = int64_to_float64(val, &env->spe_status);
2296
2297 return u.ll;
2298 }
2299
2300 static always_inline uint64_t _do_efdcfui (uint64_t val)
2301 {
2302 CPU_DoubleU u;
2303
2304 u.d = uint64_to_float64(val, &env->spe_status);
2305
2306 return u.ll;
2307 }
2308
2309 static always_inline int64_t _do_efdctsi (uint64_t val)
2310 {
2311 CPU_DoubleU u;
2312
2313 u.ll = val;
2314 /* NaN are not treated the same way IEEE 754 does */
2315 if (unlikely(isnan(u.d)))
2316 return 0;
2317
2318 return float64_to_int64(u.d, &env->spe_status);
2319 }
2320
2321 static always_inline uint64_t _do_efdctui (uint64_t val)
2322 {
2323 CPU_DoubleU u;
2324
2325 u.ll = val;
2326 /* NaN are not treated the same way IEEE 754 does */
2327 if (unlikely(isnan(u.d)))
2328 return 0;
2329
2330 return float64_to_uint64(u.d, &env->spe_status);
2331 }
2332
2333 static always_inline int64_t _do_efdctsiz (uint64_t val)
2334 {
2335 CPU_DoubleU u;
2336
2337 u.ll = val;
2338 /* NaN are not treated the same way IEEE 754 does */
2339 if (unlikely(isnan(u.d)))
2340 return 0;
2341
2342 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2343 }
2344
2345 static always_inline uint64_t _do_efdctuiz (uint64_t val)
2346 {
2347 CPU_DoubleU u;
2348
2349 u.ll = val;
2350 /* NaN are not treated the same way IEEE 754 does */
2351 if (unlikely(isnan(u.d)))
2352 return 0;
2353
2354 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2355 }
2356
2357 void do_efdcfsi (void)
2358 {
2359 T0_64 = _do_efdcfsi(T0_64);
2360 }
2361
2362 void do_efdcfui (void)
2363 {
2364 T0_64 = _do_efdcfui(T0_64);
2365 }
2366
2367 void do_efdctsi (void)
2368 {
2369 T0_64 = _do_efdctsi(T0_64);
2370 }
2371
2372 void do_efdctui (void)
2373 {
2374 T0_64 = _do_efdctui(T0_64);
2375 }
2376
2377 void do_efdctsiz (void)
2378 {
2379 T0_64 = _do_efdctsiz(T0_64);
2380 }
2381
2382 void do_efdctuiz (void)
2383 {
2384 T0_64 = _do_efdctuiz(T0_64);
2385 }
2386
2387 /* Double precision floating-point conversion to/from fractional */
2388 static always_inline uint64_t _do_efdcfsf (int64_t val)
2389 {
2390 CPU_DoubleU u;
2391 float64 tmp;
2392
2393 u.d = int32_to_float64(val, &env->spe_status);
2394 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2395 u.d = float64_div(u.d, tmp, &env->spe_status);
2396
2397 return u.ll;
2398 }
2399
2400 static always_inline uint64_t _do_efdcfuf (uint64_t val)
2401 {
2402 CPU_DoubleU u;
2403 float64 tmp;
2404
2405 u.d = uint32_to_float64(val, &env->spe_status);
2406 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2407 u.d = float64_div(u.d, tmp, &env->spe_status);
2408
2409 return u.ll;
2410 }
2411
2412 static always_inline int64_t _do_efdctsf (uint64_t val)
2413 {
2414 CPU_DoubleU u;
2415 float64 tmp;
2416
2417 u.ll = val;
2418 /* NaN are not treated the same way IEEE 754 does */
2419 if (unlikely(isnan(u.d)))
2420 return 0;
2421 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2422 u.d = float64_mul(u.d, tmp, &env->spe_status);
2423
2424 return float64_to_int32(u.d, &env->spe_status);
2425 }
2426
2427 static always_inline uint64_t _do_efdctuf (uint64_t val)
2428 {
2429 CPU_DoubleU u;
2430 float64 tmp;
2431
2432 u.ll = val;
2433 /* NaN are not treated the same way IEEE 754 does */
2434 if (unlikely(isnan(u.d)))
2435 return 0;
2436 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2437 u.d = float64_mul(u.d, tmp, &env->spe_status);
2438
2439 return float64_to_uint32(u.d, &env->spe_status);
2440 }
2441
2442 static always_inline int64_t _do_efdctsfz (uint64_t val)
2443 {
2444 CPU_DoubleU u;
2445 float64 tmp;
2446
2447 u.ll = val;
2448 /* NaN are not treated the same way IEEE 754 does */
2449 if (unlikely(isnan(u.d)))
2450 return 0;
2451 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2452 u.d = float64_mul(u.d, tmp, &env->spe_status);
2453
2454 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2455 }
2456
2457 static always_inline uint64_t _do_efdctufz (uint64_t val)
2458 {
2459 CPU_DoubleU u;
2460 float64 tmp;
2461
2462 u.ll = val;
2463 /* NaN are not treated the same way IEEE 754 does */
2464 if (unlikely(isnan(u.d)))
2465 return 0;
2466 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2467 u.d = float64_mul(u.d, tmp, &env->spe_status);
2468
2469 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2470 }
2471
2472 void do_efdcfsf (void)
2473 {
2474 T0_64 = _do_efdcfsf(T0_64);
2475 }
2476
2477 void do_efdcfuf (void)
2478 {
2479 T0_64 = _do_efdcfuf(T0_64);
2480 }
2481
2482 void do_efdctsf (void)
2483 {
2484 T0_64 = _do_efdctsf(T0_64);
2485 }
2486
2487 void do_efdctuf (void)
2488 {
2489 T0_64 = _do_efdctuf(T0_64);
2490 }
2491
2492 void do_efdctsfz (void)
2493 {
2494 T0_64 = _do_efdctsfz(T0_64);
2495 }
2496
2497 void do_efdctufz (void)
2498 {
2499 T0_64 = _do_efdctufz(T0_64);
2500 }
2501
2502 /* Floating point conversion between single and double precision */
2503 static always_inline uint32_t _do_efscfd (uint64_t val)
2504 {
2505 CPU_DoubleU u1;
2506 CPU_FloatU u2;
2507
2508 u1.ll = val;
2509 u2.f = float64_to_float32(u1.d, &env->spe_status);
2510
2511 return u2.l;
2512 }
2513
2514 static always_inline uint64_t _do_efdcfs (uint32_t val)
2515 {
2516 CPU_DoubleU u2;
2517 CPU_FloatU u1;
2518
2519 u1.l = val;
2520 u2.d = float32_to_float64(u1.f, &env->spe_status);
2521
2522 return u2.ll;
2523 }
2524
2525 void do_efscfd (void)
2526 {
2527 T0_64 = _do_efscfd(T0_64);
2528 }
2529
2530 void do_efdcfs (void)
2531 {
2532 T0_64 = _do_efdcfs(T0_64);
2533 }
2534
2535 /* Single precision fixed-point vector arithmetic */
2536 /* evfsabs */
2537 DO_SPE_OP1(fsabs);
2538 /* evfsnabs */
2539 DO_SPE_OP1(fsnabs);
2540 /* evfsneg */
2541 DO_SPE_OP1(fsneg);
2542 /* evfsadd */
2543 DO_SPE_OP2(fsadd);
2544 /* evfssub */
2545 DO_SPE_OP2(fssub);
2546 /* evfsmul */
2547 DO_SPE_OP2(fsmul);
2548 /* evfsdiv */
2549 DO_SPE_OP2(fsdiv);
2550
2551 /* Single-precision floating-point comparisons */
2552 static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
2553 {
2554 /* XXX: TODO: test special values (NaN, infinites, ...) */
2555 return _do_efststlt(op1, op2);
2556 }
2557
2558 static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
2559 {
2560 /* XXX: TODO: test special values (NaN, infinites, ...) */
2561 return _do_efststgt(op1, op2);
2562 }
2563
2564 static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
2565 {
2566 /* XXX: TODO: test special values (NaN, infinites, ...) */
2567 return _do_efststeq(op1, op2);
2568 }
2569
2570 void do_efscmplt (void)
2571 {
2572 T0 = _do_efscmplt(T0_64, T1_64);
2573 }
2574
2575 void do_efscmpgt (void)
2576 {
2577 T0 = _do_efscmpgt(T0_64, T1_64);
2578 }
2579
2580 void do_efscmpeq (void)
2581 {
2582 T0 = _do_efscmpeq(T0_64, T1_64);
2583 }
2584
2585 /* Single-precision floating-point vector comparisons */
2586 /* evfscmplt */
2587 DO_SPE_CMP(fscmplt);
2588 /* evfscmpgt */
2589 DO_SPE_CMP(fscmpgt);
2590 /* evfscmpeq */
2591 DO_SPE_CMP(fscmpeq);
2592 /* evfststlt */
2593 DO_SPE_CMP(fststlt);
2594 /* evfststgt */
2595 DO_SPE_CMP(fststgt);
2596 /* evfststeq */
2597 DO_SPE_CMP(fststeq);
2598
2599 /* Single-precision floating-point vector conversions */
2600 /* evfscfsi */
2601 DO_SPE_OP1(fscfsi);
2602 /* evfscfui */
2603 DO_SPE_OP1(fscfui);
2604 /* evfscfuf */
2605 DO_SPE_OP1(fscfuf);
2606 /* evfscfsf */
2607 DO_SPE_OP1(fscfsf);
2608 /* evfsctsi */
2609 DO_SPE_OP1(fsctsi);
2610 /* evfsctui */
2611 DO_SPE_OP1(fsctui);
2612 /* evfsctsiz */
2613 DO_SPE_OP1(fsctsiz);
2614 /* evfsctuiz */
2615 DO_SPE_OP1(fsctuiz);
2616 /* evfsctsf */
2617 DO_SPE_OP1(fsctsf);
2618 /* evfsctuf */
2619 DO_SPE_OP1(fsctuf);
2620
2621 /*****************************************************************************/
2622 /* Softmmu support */
2623 #if !defined (CONFIG_USER_ONLY)
2624
2625 #define MMUSUFFIX _mmu
2626
2627 #define SHIFT 0
2628 #include "softmmu_template.h"
2629
2630 #define SHIFT 1
2631 #include "softmmu_template.h"
2632
2633 #define SHIFT 2
2634 #include "softmmu_template.h"
2635
2636 #define SHIFT 3
2637 #include "softmmu_template.h"
2638
2639 /* try to fill the TLB and return an exception if error. If retaddr is
2640 NULL, it means that the function was called in C code (i.e. not
2641 from generated code or from helper.c) */
2642 /* XXX: fix it to restore all registers */
2643 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
2644 {
2645 TranslationBlock *tb;
2646 CPUState *saved_env;
2647 unsigned long pc;
2648 int ret;
2649
2650 /* XXX: hack to restore env in all cases, even if not called from
2651 generated code */
2652 saved_env = env;
2653 env = cpu_single_env;
2654 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
2655 if (unlikely(ret != 0)) {
2656 if (likely(retaddr)) {
2657 /* now we have a real cpu fault */
2658 pc = (unsigned long)retaddr;
2659 tb = tb_find_pc(pc);
2660 if (likely(tb)) {
2661 /* the PC is inside the translated code. It means that we have
2662 a virtual CPU fault */
2663 cpu_restore_state(tb, env, pc, NULL);
2664 }
2665 }
2666 do_raise_exception_err(env->exception_index, env->error_code);
2667 }
2668 env = saved_env;
2669 }
2670
2671 /* Software driven TLBs management */
2672 /* PowerPC 602/603 software TLB load instructions helpers */
2673 void do_load_6xx_tlb (int is_code)
2674 {
2675 target_ulong RPN, CMP, EPN;
2676 int way;
2677
2678 RPN = env->spr[SPR_RPA];
2679 if (is_code) {
2680 CMP = env->spr[SPR_ICMP];
2681 EPN = env->spr[SPR_IMISS];
2682 } else {
2683 CMP = env->spr[SPR_DCMP];
2684 EPN = env->spr[SPR_DMISS];
2685 }
2686 way = (env->spr[SPR_SRR1] >> 17) & 1;
2687 #if defined (DEBUG_SOFTWARE_TLB)
2688 if (loglevel != 0) {
2689 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2690 " PTE1 " ADDRX " way %d\n",
2691 __func__, T0, EPN, CMP, RPN, way);
2692 }
2693 #endif
2694 /* Store this TLB */
2695 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2696 way, is_code, CMP, RPN);
2697 }
2698
2699 void do_load_74xx_tlb (int is_code)
2700 {
2701 target_ulong RPN, CMP, EPN;
2702 int way;
2703
2704 RPN = env->spr[SPR_PTELO];
2705 CMP = env->spr[SPR_PTEHI];
2706 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2707 way = env->spr[SPR_TLBMISS] & 0x3;
2708 #if defined (DEBUG_SOFTWARE_TLB)
2709 if (loglevel != 0) {
2710 fprintf(logfile, "%s: EPN " TDX " " ADDRX " PTE0 " ADDRX
2711 " PTE1 " ADDRX " way %d\n",
2712 __func__, T0, EPN, CMP, RPN, way);
2713 }
2714 #endif
2715 /* Store this TLB */
2716 ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
2717 way, is_code, CMP, RPN);
2718 }
2719
2720 static always_inline target_ulong booke_tlb_to_page_size (int size)
2721 {
2722 return 1024 << (2 * size);
2723 }
2724
2725 static always_inline int booke_page_size_to_tlb (target_ulong page_size)
2726 {
2727 int size;
2728
2729 switch (page_size) {
2730 case 0x00000400UL:
2731 size = 0x0;
2732 break;
2733 case 0x00001000UL:
2734 size = 0x1;
2735 break;
2736 case 0x00004000UL:
2737 size = 0x2;
2738 break;
2739 case 0x00010000UL:
2740 size = 0x3;
2741 break;
2742 case 0x00040000UL:
2743 size = 0x4;
2744 break;
2745 case 0x00100000UL:
2746 size = 0x5;
2747 break;
2748 case 0x00400000UL:
2749 size = 0x6;
2750 break;
2751 case 0x01000000UL:
2752 size = 0x7;
2753 break;
2754 case 0x04000000UL:
2755 size = 0x8;
2756 break;
2757 case 0x10000000UL:
2758 size = 0x9;
2759 break;
2760 case 0x40000000UL:
2761 size = 0xA;
2762 break;
2763 #if defined (TARGET_PPC64)
2764 case 0x000100000000ULL:
2765 size = 0xB;
2766 break;
2767 case 0x000400000000ULL:
2768 size = 0xC;
2769 break;
2770 case 0x001000000000ULL:
2771 size = 0xD;
2772 break;
2773 case 0x004000000000ULL:
2774 size = 0xE;
2775 break;
2776 case 0x010000000000ULL:
2777 size = 0xF;
2778 break;
2779 #endif
2780 default:
2781 size = -1;
2782 break;
2783 }
2784
2785 return size;
2786 }
2787
2788 /* Helpers for 4xx TLB management */
2789 void do_4xx_tlbre_lo (void)
2790 {
2791 ppcemb_tlb_t *tlb;
2792 int size;
2793
2794 T0 &= 0x3F;
2795 tlb = &env->tlb[T0].tlbe;
2796 T0 = tlb->EPN;
2797 if (tlb->prot & PAGE_VALID)
2798 T0 |= 0x400;
2799 size = booke_page_size_to_tlb(tlb->size);
2800 if (size < 0 || size > 0x7)
2801 size = 1;
2802 T0 |= size << 7;
2803 env->spr[SPR_40x_PID] = tlb->PID;
2804 }
2805
2806 void do_4xx_tlbre_hi (void)
2807 {
2808 ppcemb_tlb_t *tlb;
2809
2810 T0 &= 0x3F;
2811 tlb = &env->tlb[T0].tlbe;
2812 T0 = tlb->RPN;
2813 if (tlb->prot & PAGE_EXEC)
2814 T0 |= 0x200;
2815 if (tlb->prot & PAGE_WRITE)
2816 T0 |= 0x100;
2817 }
2818
2819 void do_4xx_tlbwe_hi (void)
2820 {
2821 ppcemb_tlb_t *tlb;
2822 target_ulong page, end;
2823
2824 #if defined (DEBUG_SOFTWARE_TLB)
2825 if (loglevel != 0) {
2826 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2827 }
2828 #endif
2829 T0 &= 0x3F;
2830 tlb = &env->tlb[T0].tlbe;
2831 /* Invalidate previous TLB (if it's valid) */
2832 if (tlb->prot & PAGE_VALID) {
2833 end = tlb->EPN + tlb->size;
2834 #if defined (DEBUG_SOFTWARE_TLB)
2835 if (loglevel != 0) {
2836 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
2837 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2838 }
2839 #endif
2840 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2841 tlb_flush_page(env, page);
2842 }
2843 tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
2844 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2845 * If this ever occurs, one should use the ppcemb target instead
2846 * of the ppc or ppc64 one
2847 */
2848 if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
2849 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2850 "are not supported (%d)\n",
2851 tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
2852 }
2853 tlb->EPN = T1 & ~(tlb->size - 1);
2854 if (T1 & 0x40)
2855 tlb->prot |= PAGE_VALID;
2856 else
2857 tlb->prot &= ~PAGE_VALID;
2858 if (T1 & 0x20) {
2859 /* XXX: TO BE FIXED */
2860 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2861 }
2862 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
2863 tlb->attr = T1 & 0xFF;
2864 #if defined (DEBUG_SOFTWARE_TLB)
2865 if (loglevel != 0) {
2866 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2867 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2868 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2869 tlb->prot & PAGE_READ ? 'r' : '-',
2870 tlb->prot & PAGE_WRITE ? 'w' : '-',
2871 tlb->prot & PAGE_EXEC ? 'x' : '-',
2872 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2873 }
2874 #endif
2875 /* Invalidate new TLB (if valid) */
2876 if (tlb->prot & PAGE_VALID) {
2877 end = tlb->EPN + tlb->size;
2878 #if defined (DEBUG_SOFTWARE_TLB)
2879 if (loglevel != 0) {
2880 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
2881 " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
2882 }
2883 #endif
2884 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2885 tlb_flush_page(env, page);
2886 }
2887 }
2888
2889 void do_4xx_tlbwe_lo (void)
2890 {
2891 ppcemb_tlb_t *tlb;
2892
2893 #if defined (DEBUG_SOFTWARE_TLB)
2894 if (loglevel != 0) {
2895 fprintf(logfile, "%s T0 " TDX " T1 " TDX "\n", __func__, T0, T1);
2896 }
2897 #endif
2898 T0 &= 0x3F;
2899 tlb = &env->tlb[T0].tlbe;
2900 tlb->RPN = T1 & 0xFFFFFC00;
2901 tlb->prot = PAGE_READ;
2902 if (T1 & 0x200)
2903 tlb->prot |= PAGE_EXEC;
2904 if (T1 & 0x100)
2905 tlb->prot |= PAGE_WRITE;
2906 #if defined (DEBUG_SOFTWARE_TLB)
2907 if (loglevel != 0) {
2908 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
2909 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
2910 (int)T0, tlb->RPN, tlb->EPN, tlb->size,
2911 tlb->prot & PAGE_READ ? 'r' : '-',
2912 tlb->prot & PAGE_WRITE ? 'w' : '-',
2913 tlb->prot & PAGE_EXEC ? 'x' : '-',
2914 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2915 }
2916 #endif
2917 }
2918
2919 /* PowerPC 440 TLB management */
2920 void do_440_tlbwe (int word)
2921 {
2922 ppcemb_tlb_t *tlb;
2923 target_ulong EPN, RPN, size;
2924 int do_flush_tlbs;
2925
2926 #if defined (DEBUG_SOFTWARE_TLB)
2927 if (loglevel != 0) {
2928 fprintf(logfile, "%s word %d T0 " TDX " T1 " TDX "\n",
2929 __func__, word, T0, T1);
2930 }
2931 #endif
2932 do_flush_tlbs = 0;
2933 T0 &= 0x3F;
2934 tlb = &env->tlb[T0].tlbe;
2935 switch (word) {
2936 default:
2937 /* Just here to please gcc */
2938 case 0:
2939 EPN = T1 & 0xFFFFFC00;
2940 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
2941 do_flush_tlbs = 1;
2942 tlb->EPN = EPN;
2943 size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
2944 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2945 do_flush_tlbs = 1;
2946 tlb->size = size;
2947 tlb->attr &= ~0x1;
2948 tlb->attr |= (T1 >> 8) & 1;
2949 if (T1 & 0x200) {
2950 tlb->prot |= PAGE_VALID;
2951 } else {
2952 if (tlb->prot & PAGE_VALID) {
2953 tlb->prot &= ~PAGE_VALID;
2954 do_flush_tlbs = 1;
2955 }
2956 }
2957 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
2958 if (do_flush_tlbs)
2959 tlb_flush(env, 1);
2960 break;
2961 case 1:
2962 RPN = T1 & 0xFFFFFC0F;
2963 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
2964 tlb_flush(env, 1);
2965 tlb->RPN = RPN;
2966 break;
2967 case 2:
2968 tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
2969 tlb->prot = tlb->prot & PAGE_VALID;
2970 if (T1 & 0x1)
2971 tlb->prot |= PAGE_READ << 4;
2972 if (T1 & 0x2)
2973 tlb->prot |= PAGE_WRITE << 4;
2974 if (T1 & 0x4)
2975 tlb->prot |= PAGE_EXEC << 4;
2976 if (T1 & 0x8)
2977 tlb->prot |= PAGE_READ;
2978 if (T1 & 0x10)
2979 tlb->prot |= PAGE_WRITE;
2980 if (T1 & 0x20)
2981 tlb->prot |= PAGE_EXEC;
2982 break;
2983 }
2984 }
2985
2986 void do_440_tlbre (int word)
2987 {
2988 ppcemb_tlb_t *tlb;
2989 int size;
2990
2991 T0 &= 0x3F;
2992 tlb = &env->tlb[T0].tlbe;
2993 switch (word) {
2994 default:
2995 /* Just here to please gcc */
2996 case 0:
2997 T0 = tlb->EPN;
2998 size = booke_page_size_to_tlb(tlb->size);
2999 if (size < 0 || size > 0xF)
3000 size = 1;
3001 T0 |= size << 4;
3002 if (tlb->attr & 0x1)
3003 T0 |= 0x100;
3004 if (tlb->prot & PAGE_VALID)
3005 T0 |= 0x200;
3006 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3007 env->spr[SPR_440_MMUCR] |= tlb->PID;
3008 break;
3009 case 1:
3010 T0 = tlb->RPN;
3011 break;
3012 case 2:
3013 T0 = tlb->attr & ~0x1;
3014 if (tlb->prot & (PAGE_READ << 4))
3015 T0 |= 0x1;
3016 if (tlb->prot & (PAGE_WRITE << 4))
3017 T0 |= 0x2;
3018 if (tlb->prot & (PAGE_EXEC << 4))
3019 T0 |= 0x4;
3020 if (tlb->prot & PAGE_READ)
3021 T0 |= 0x8;
3022 if (tlb->prot & PAGE_WRITE)
3023 T0 |= 0x10;
3024 if (tlb->prot & PAGE_EXEC)
3025 T0 |= 0x20;
3026 break;
3027 }
3028 }
3029 #endif /* !CONFIG_USER_ONLY */
Samsung s3c2440 and arm920t support for the mini2440 dev board