hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licenced under the GNU GPL v2.
   7  */
   8
   9 #include "hw.h"
  10 #include "arm-misc.h"
  11 #include "devices.h"
  12 #include "net.h"
  13 #include "sysemu.h"
  14 #include "boards.h"
  15 #include "pc.h"
  16 #include "qemu-timer.h"
  17 #include "block.h"
  18 #include "flash.h"
  19 #include "console.h"
  20 #include "audio/audio.h"
  21 #include "i2c.h"
  22
  23 #define MP_ETH_BASE             0x80008000
  24 #define MP_ETH_SIZE             0x00001000
  25
  26 #define MP_UART1_BASE           0x8000C840
  27 #define MP_UART2_BASE           0x8000C940
  28
  29 #define MP_FLASHCFG_BASE        0x90006000
  30 #define MP_FLASHCFG_SIZE        0x00001000
  31
  32 #define MP_AUDIO_BASE           0x90007000
  33 #define MP_AUDIO_SIZE           0x00001000
  34
  35 #define MP_PIC_BASE             0x90008000
  36 #define MP_PIC_SIZE             0x00001000
  37
  38 #define MP_PIT_BASE             0x90009000
  39 #define MP_PIT_SIZE             0x00001000
  40
  41 #define MP_LCD_BASE             0x9000c000
  42 #define MP_LCD_SIZE             0x00001000
  43
  44 #define MP_SRAM_BASE            0xC0000000
  45 #define MP_SRAM_SIZE            0x00020000
  46
  47 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  48 #define MP_FLASH_SIZE_MAX       32*1024*1024
  49
  50 #define MP_TIMER1_IRQ           4
  51 /* ... */
  52 #define MP_TIMER4_IRQ           7
  53 #define MP_EHCI_IRQ             8
  54 #define MP_ETH_IRQ              9
  55 #define MP_UART1_IRQ            11
  56 #define MP_UART2_IRQ            11
  57 #define MP_GPIO_IRQ             12
  58 #define MP_RTC_IRQ              28
  59 #define MP_AUDIO_IRQ            30
  60
  61 static uint32_t gpio_in_state = 0xffffffff;
  62 static uint32_t gpio_out_state;
  63 static ram_addr_t sram_off;
  64
  65 /* Address conversion helpers */
  66 static void *target2host_addr(uint32_t addr)
  67 {
  68     if (addr < MP_SRAM_BASE) {
  69         if (addr >= MP_RAM_DEFAULT_SIZE)
  70             return NULL;
  71         return (void *)(phys_ram_base + addr);
  72     } else {
  73         if (addr >= MP_SRAM_BASE + MP_SRAM_SIZE)
  74             return NULL;
  75         return (void *)(phys_ram_base + sram_off + addr - MP_SRAM_BASE);
  76     }
  77 }
  78
  79 static uint32_t host2target_addr(void *addr)
  80 {
  81     if (addr < ((void *)phys_ram_base) + sram_off)
  82         return (unsigned long)addr - (unsigned long)phys_ram_base;
  83     else
  84         return (unsigned long)addr - (unsigned long)phys_ram_base -
  85             sram_off + MP_SRAM_BASE;
  86 }
  87
  88
  89 typedef enum i2c_state {
  90     STOPPED = 0,
  91     INITIALIZING,
  92     SENDING_BIT7,
  93     SENDING_BIT6,
  94     SENDING_BIT5,
  95     SENDING_BIT4,
  96     SENDING_BIT3,
  97     SENDING_BIT2,
  98     SENDING_BIT1,
  99     SENDING_BIT0,
 100     WAITING_FOR_ACK,
 101     RECEIVING_BIT7,
 102     RECEIVING_BIT6,
 103     RECEIVING_BIT5,
 104     RECEIVING_BIT4,
 105     RECEIVING_BIT3,
 106     RECEIVING_BIT2,
 107     RECEIVING_BIT1,
 108     RECEIVING_BIT0,
 109     SENDING_ACK
 110 } i2c_state;
 111
 112 typedef struct i2c_interface {
 113     i2c_bus *bus;
 114     i2c_state state;
 115     int last_data;
 116     int last_clock;
 117     uint8_t buffer;
 118     int current_addr;
 119 } i2c_interface;
 120
 121 static void i2c_enter_stop(i2c_interface *i2c)
 122 {
 123     if (i2c->current_addr >= 0)
 124         i2c_end_transfer(i2c->bus);
 125     i2c->current_addr = -1;
 126     i2c->state = STOPPED;
 127 }
 128
 129 static void i2c_state_update(i2c_interface *i2c, int data, int clock)
 130 {
 131     if (!i2c)
 132         return;
 133
 134     switch (i2c->state) {
 135     case STOPPED:
 136         if (data == 0 && i2c->last_data == 1 && clock == 1)
 137             i2c->state = INITIALIZING;
 138         break;
 139
 140     case INITIALIZING:
 141         if (clock == 0 && i2c->last_clock == 1 && data == 0)
 142             i2c->state = SENDING_BIT7;
 143         else
 144             i2c_enter_stop(i2c);
 145         break;
 146
 147     case SENDING_BIT7 ... SENDING_BIT0:
 148         if (clock == 0 && i2c->last_clock == 1) {
 149             i2c->buffer = (i2c->buffer << 1) | data;
 150             i2c->state++; /* will end up in WAITING_FOR_ACK */
 151         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 152             i2c_enter_stop(i2c);
 153         break;
 154
 155     case WAITING_FOR_ACK:
 156         if (clock == 0 && i2c->last_clock == 1) {
 157             if (i2c->current_addr < 0) {
 158                 i2c->current_addr = i2c->buffer;
 159                 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
 160                                    i2c->buffer & 1);
 161             } else
 162                 i2c_send(i2c->bus, i2c->buffer);
 163             if (i2c->current_addr & 1) {
 164                 i2c->state = RECEIVING_BIT7;
 165                 i2c->buffer = i2c_recv(i2c->bus);
 166             } else
 167                 i2c->state = SENDING_BIT7;
 168         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 169             i2c_enter_stop(i2c);
 170         break;
 171
 172     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 173         if (clock == 0 && i2c->last_clock == 1) {
 174             i2c->state++; /* will end up in SENDING_ACK */
 175             i2c->buffer <<= 1;
 176         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 177             i2c_enter_stop(i2c);
 178         break;
 179
 180     case SENDING_ACK:
 181         if (clock == 0 && i2c->last_clock == 1) {
 182             i2c->state = RECEIVING_BIT7;
 183             if (data == 0)
 184                 i2c->buffer = i2c_recv(i2c->bus);
 185             else
 186                 i2c_nack(i2c->bus);
 187         } else if (data == 1 && i2c->last_data == 0 && clock == 1)
 188             i2c_enter_stop(i2c);
 189         break;
 190     }
 191
 192     i2c->last_data = data;
 193     i2c->last_clock = clock;
 194 }
 195
 196 static int i2c_get_data(i2c_interface *i2c)
 197 {
 198     if (!i2c)
 199         return 0;
 200
 201     switch (i2c->state) {
 202     case RECEIVING_BIT7 ... RECEIVING_BIT0:
 203         return (i2c->buffer >> 7);
 204
 205     case WAITING_FOR_ACK:
 206     default:
 207         return 0;
 208     }
 209 }
 210
 211 static i2c_interface *mixer_i2c;
 212
 213 #ifdef HAS_AUDIO
 214
 215 /* Audio register offsets */
 216 #define MP_AUDIO_PLAYBACK_MODE  0x00
 217 #define MP_AUDIO_CLOCK_DIV      0x18
 218 #define MP_AUDIO_IRQ_STATUS     0x20
 219 #define MP_AUDIO_IRQ_ENABLE     0x24
 220 #define MP_AUDIO_TX_START_LO    0x28
 221 #define MP_AUDIO_TX_THRESHOLD   0x2C
 222 #define MP_AUDIO_TX_STATUS      0x38
 223 #define MP_AUDIO_TX_START_HI    0x40
 224
 225 /* Status register and IRQ enable bits */
 226 #define MP_AUDIO_TX_HALF        (1 << 6)
 227 #define MP_AUDIO_TX_FULL        (1 << 7)
 228
 229 /* Playback mode bits */
 230 #define MP_AUDIO_16BIT_SAMPLE   (1 << 0)
 231 #define MP_AUDIO_PLAYBACK_EN    (1 << 7)
 232 #define MP_AUDIO_CLOCK_24MHZ    (1 << 9)
 233
 234 /* Wolfson 8750 I2C address */
 235 #define MP_WM_ADDR              0x34
 236
 237 const char audio_name[] = "mv88w8618";
 238
 239 typedef struct musicpal_audio_state {
 240     uint32_t base;
 241     qemu_irq irq;
 242     uint32_t playback_mode;
 243     uint32_t status;
 244     uint32_t irq_enable;
 245     unsigned long phys_buf;
 246     void *target_buffer;
 247     unsigned int threshold;
 248     unsigned int play_pos;
 249     unsigned int last_free;
 250     uint32_t clock_div;
 251     i2c_slave *wm;
 252 } musicpal_audio_state;
 253
 254 static void audio_callback(void *opaque, int free_out, int free_in)
 255 {
 256     musicpal_audio_state *s = opaque;
 257     int16_t *codec_buffer;
 258     int pos, block_size;
 259
 260     if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
 261         return;
 262
 263     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
 264         free_out <<= 2;
 265     else
 266         free_out <<= 1;
 267
 268     block_size = s->threshold/2;
 269     if (free_out - s->last_free < block_size)
 270         return;
 271
 272     if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
 273         memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
 274                (uint32_t *)(s->target_buffer + s->play_pos),
 275                block_size);
 276     else {
 277         codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
 278         for (pos = 0; pos < block_size; pos += 2) {
 279             *codec_buffer++ = cpu_to_le16(256 *
 280                     *(int8_t *)(s->target_buffer + s->play_pos + pos));
 281             *codec_buffer++ = cpu_to_le16(256 *
 282                     *(int8_t *)(s->target_buffer + s->play_pos + pos + 1));
 283         }
 284     }
 285     wm8750_dac_commit(s->wm);
 286
 287     s->last_free = free_out - block_size;
 288
 289     if (s->play_pos == 0) {
 290         s->status |= MP_AUDIO_TX_HALF;
 291         s->play_pos = block_size;
 292     } else {
 293         s->status |= MP_AUDIO_TX_FULL;
 294         s->play_pos = 0;
 295     }
 296
 297     if (s->status & s->irq_enable)
 298         qemu_irq_raise(s->irq);
 299 }
 300
 301 static void musicpal_audio_clock_update(musicpal_audio_state *s)
 302 {
 303     int rate;
 304
 305     if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
 306         rate = 24576000 / 64; /* 24.576MHz */
 307     else
 308         rate = 11289600 / 64; /* 11.2896MHz */
 309
 310     rate /= ((s->clock_div >> 8) & 0xff) + 1;
 311
 312     wm8750_set_bclk_in(s->wm, rate / 2);
 313 }
 314
 315 static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
 316 {
 317     musicpal_audio_state *s = opaque;
 318
 319     offset -= s->base;
 320     switch (offset) {
 321     case MP_AUDIO_PLAYBACK_MODE:
 322         return s->playback_mode;
 323
 324     case MP_AUDIO_CLOCK_DIV:
 325         return s->clock_div;
 326
 327     case MP_AUDIO_IRQ_STATUS:
 328         return s->status;
 329
 330     case MP_AUDIO_IRQ_ENABLE:
 331         return s->irq_enable;
 332
 333     case MP_AUDIO_TX_STATUS:
 334         return s->play_pos >> 2;
 335
 336     default:
 337         return 0;
 338     }
 339 }
 340
 341 static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
 342                                  uint32_t value)
 343 {
 344     musicpal_audio_state *s = opaque;
 345
 346     offset -= s->base;
 347     switch (offset) {
 348     case MP_AUDIO_PLAYBACK_MODE:
 349         if (value & MP_AUDIO_PLAYBACK_EN &&
 350             !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
 351             s->status = 0;
 352             s->last_free = 0;
 353             s->play_pos = 0;
 354         }
 355         s->playback_mode = value;
 356         musicpal_audio_clock_update(s);
 357         break;
 358
 359     case MP_AUDIO_CLOCK_DIV:
 360         s->clock_div = value;
 361         s->last_free = 0;
 362         s->play_pos = 0;
 363         musicpal_audio_clock_update(s);
 364         break;
 365
 366     case MP_AUDIO_IRQ_STATUS:
 367         s->status &= ~value;
 368         break;
 369
 370     case MP_AUDIO_IRQ_ENABLE:
 371         s->irq_enable = value;
 372         if (s->status & s->irq_enable)
 373             qemu_irq_raise(s->irq);
 374         break;
 375
 376     case MP_AUDIO_TX_START_LO:
 377         s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
 378         s->target_buffer = target2host_addr(s->phys_buf);
 379         s->play_pos = 0;
 380         s->last_free = 0;
 381         break;
 382
 383     case MP_AUDIO_TX_THRESHOLD:
 384         s->threshold = (value + 1) * 4;
 385         break;
 386
 387     case MP_AUDIO_TX_START_HI:
 388         s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
 389         s->target_buffer = target2host_addr(s->phys_buf);
 390         s->play_pos = 0;
 391         s->last_free = 0;
 392         break;
 393     }
 394 }
 395
 396 static void musicpal_audio_reset(void *opaque)
 397 {
 398     musicpal_audio_state *s = opaque;
 399
 400     s->playback_mode = 0;
 401     s->status = 0;
 402     s->irq_enable = 0;
 403 }
 404
 405 static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
 406     musicpal_audio_read,
 407     musicpal_audio_read,
 408     musicpal_audio_read
 409 };
 410
 411 static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
 412     musicpal_audio_write,
 413     musicpal_audio_write,
 414     musicpal_audio_write
 415 };
 416
 417 static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
 418 {
 419     AudioState *audio;
 420     musicpal_audio_state *s;
 421     i2c_interface *i2c;
 422     int iomemtype;
 423
 424     audio = AUD_init();
 425     if (!audio) {
 426         AUD_log(audio_name, "No audio state\n");
 427         return NULL;
 428     }
 429
 430     s = qemu_mallocz(sizeof(musicpal_audio_state));
 431     if (!s)
 432         return NULL;
 433     s->base = base;
 434     s->irq = irq;
 435
 436     i2c = qemu_mallocz(sizeof(i2c_interface));
 437     if (!i2c)
 438         return NULL;
 439     i2c->bus = i2c_init_bus();
 440     i2c->current_addr = -1;
 441
 442     s->wm = wm8750_init(i2c->bus, audio);
 443     if (!s->wm)
 444         return NULL;
 445     i2c_set_slave_address(s->wm, MP_WM_ADDR);
 446     wm8750_data_req_set(s->wm, audio_callback, s);
 447
 448     iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
 449                        musicpal_audio_writefn, s);
 450     cpu_register_physical_memory(base, MP_AUDIO_SIZE, iomemtype);
 451
 452     qemu_register_reset(musicpal_audio_reset, s);
 453
 454     return i2c;
 455 }
 456 #else  /* !HAS_AUDIO */
 457 static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
 458 {
 459     return NULL;
 460 }
 461 #endif /* !HAS_AUDIO */
 462
 463 /* Ethernet register offsets */
 464 #define MP_ETH_SMIR             0x010
 465 #define MP_ETH_PCXR             0x408
 466 #define MP_ETH_SDCMR            0x448
 467 #define MP_ETH_ICR              0x450
 468 #define MP_ETH_IMR              0x458
 469 #define MP_ETH_FRDP0            0x480
 470 #define MP_ETH_FRDP1            0x484
 471 #define MP_ETH_FRDP2            0x488
 472 #define MP_ETH_FRDP3            0x48C
 473 #define MP_ETH_CRDP0            0x4A0
 474 #define MP_ETH_CRDP1            0x4A4
 475 #define MP_ETH_CRDP2            0x4A8
 476 #define MP_ETH_CRDP3            0x4AC
 477 #define MP_ETH_CTDP0            0x4E0
 478 #define MP_ETH_CTDP1            0x4E4
 479 #define MP_ETH_CTDP2            0x4E8
 480 #define MP_ETH_CTDP3            0x4EC
 481
 482 /* MII PHY access */
 483 #define MP_ETH_SMIR_DATA        0x0000FFFF
 484 #define MP_ETH_SMIR_ADDR        0x03FF0000
 485 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 486 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 487
 488 /* PHY registers */
 489 #define MP_ETH_PHY1_BMSR        0x00210000
 490 #define MP_ETH_PHY1_PHYSID1     0x00410000
 491 #define MP_ETH_PHY1_PHYSID2     0x00610000
 492
 493 #define MP_PHY_BMSR_LINK        0x0004
 494 #define MP_PHY_BMSR_AUTONEG     0x0008
 495
 496 #define MP_PHY_88E3015          0x01410E20
 497
 498 /* TX descriptor status */
 499 #define MP_ETH_TX_OWN           (1 << 31)
 500
 501 /* RX descriptor status */
 502 #define MP_ETH_RX_OWN           (1 << 31)
 503
 504 /* Interrupt cause/mask bits */
 505 #define MP_ETH_IRQ_RX_BIT       0
 506 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 507 #define MP_ETH_IRQ_TXHI_BIT     2
 508 #define MP_ETH_IRQ_TXLO_BIT     3
 509
 510 /* Port config bits */
 511 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 512
 513 /* SDMA command bits */
 514 #define MP_ETH_CMD_TXHI         (1 << 23)
 515 #define MP_ETH_CMD_TXLO         (1 << 22)
 516
 517 typedef struct mv88w8618_tx_desc {
 518     uint32_t cmdstat;
 519     uint16_t res;
 520     uint16_t bytes;
 521     uint32_t buffer;
 522     uint32_t next;
 523 } mv88w8618_tx_desc;
 524
 525 typedef struct mv88w8618_rx_desc {
 526     uint32_t cmdstat;
 527     uint16_t bytes;
 528     uint16_t buffer_size;
 529     uint32_t buffer;
 530     uint32_t next;
 531 } mv88w8618_rx_desc;
 532
 533 typedef struct mv88w8618_eth_state {
 534     uint32_t base;
 535     qemu_irq irq;
 536     uint32_t smir;
 537     uint32_t icr;
 538     uint32_t imr;
 539     int vlan_header;
 540     mv88w8618_tx_desc *tx_queue[2];
 541     mv88w8618_rx_desc *rx_queue[4];
 542     mv88w8618_rx_desc *frx_queue[4];
 543     mv88w8618_rx_desc *cur_rx[4];
 544     VLANClientState *vc;
 545 } mv88w8618_eth_state;
 546
 547 static int eth_can_receive(void *opaque)
 548 {
 549     return 1;
 550 }
 551
 552 static void eth_receive(void *opaque, const uint8_t *buf, int size)
 553 {
 554     mv88w8618_eth_state *s = opaque;
 555     mv88w8618_rx_desc *desc;
 556     int i;
 557
 558     for (i = 0; i < 4; i++) {
 559         desc = s->cur_rx[i];
 560         if (!desc)
 561             continue;
 562         do {
 563             if (le32_to_cpu(desc->cmdstat) & MP_ETH_RX_OWN &&
 564                 le16_to_cpu(desc->buffer_size) >= size) {
 565                 memcpy(target2host_addr(le32_to_cpu(desc->buffer) +
 566                                         s->vlan_header),
 567                        buf, size);
 568                 desc->bytes = cpu_to_le16(size + s->vlan_header);
 569                 desc->cmdstat &= cpu_to_le32(~MP_ETH_RX_OWN);
 570                 s->cur_rx[i] = target2host_addr(le32_to_cpu(desc->next));
 571
 572                 s->icr |= MP_ETH_IRQ_RX;
 573                 if (s->icr & s->imr)
 574                     qemu_irq_raise(s->irq);
 575                 return;
 576             }
 577             desc = target2host_addr(le32_to_cpu(desc->next));
 578         } while (desc != s->rx_queue[i]);
 579     }
 580 }
 581
 582 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 583 {
 584     mv88w8618_tx_desc *desc = s->tx_queue[queue_index];
 585
 586     do {
 587         if (le32_to_cpu(desc->cmdstat) & MP_ETH_TX_OWN) {
 588             qemu_send_packet(s->vc,
 589                              target2host_addr(le32_to_cpu(desc->buffer)),
 590                              le16_to_cpu(desc->bytes));
 591             desc->cmdstat &= cpu_to_le32(~MP_ETH_TX_OWN);
 592             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 593         }
 594         desc = target2host_addr(le32_to_cpu(desc->next));
 595     } while (desc != s->tx_queue[queue_index]);
 596 }
 597
 598 static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
 599 {
 600     mv88w8618_eth_state *s = opaque;
 601
 602     offset -= s->base;
 603     switch (offset) {
 604     case MP_ETH_SMIR:
 605         if (s->smir & MP_ETH_SMIR_OPCODE) {
 606             switch (s->smir & MP_ETH_SMIR_ADDR) {
 607             case MP_ETH_PHY1_BMSR:
 608                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 609                        MP_ETH_SMIR_RDVALID;
 610             case MP_ETH_PHY1_PHYSID1:
 611                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 612             case MP_ETH_PHY1_PHYSID2:
 613                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 614             default:
 615                 return MP_ETH_SMIR_RDVALID;
 616             }
 617         }
 618         return 0;
 619
 620     case MP_ETH_ICR:
 621         return s->icr;
 622
 623     case MP_ETH_IMR:
 624         return s->imr;
 625
 626     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 627         return host2target_addr(s->frx_queue[(offset - MP_ETH_FRDP0)/4]);
 628
 629     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 630         return host2target_addr(s->rx_queue[(offset - MP_ETH_CRDP0)/4]);
 631
 632     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 633         return host2target_addr(s->tx_queue[(offset - MP_ETH_CTDP0)/4]);
 634
 635     default:
 636         return 0;
 637     }
 638 }
 639
 640 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 641                                 uint32_t value)
 642 {
 643     mv88w8618_eth_state *s = opaque;
 644
 645     offset -= s->base;
 646     switch (offset) {
 647     case MP_ETH_SMIR:
 648         s->smir = value;
 649         break;
 650
 651     case MP_ETH_PCXR:
 652         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 653         break;
 654
 655     case MP_ETH_SDCMR:
 656         if (value & MP_ETH_CMD_TXHI)
 657             eth_send(s, 1);
 658         if (value & MP_ETH_CMD_TXLO)
 659             eth_send(s, 0);
 660         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
 661             qemu_irq_raise(s->irq);
 662         break;
 663
 664     case MP_ETH_ICR:
 665         s->icr &= value;
 666         break;
 667
 668     case MP_ETH_IMR:
 669         s->imr = value;
 670         if (s->icr & s->imr)
 671             qemu_irq_raise(s->irq);
 672         break;
 673
 674     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 675         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = target2host_addr(value);
 676         break;
 677
 678     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 679         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 680             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = target2host_addr(value);
 681         break;
 682
 683     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 684         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = target2host_addr(value);
 685         break;
 686     }
 687 }
 688
 689 static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
 690     mv88w8618_eth_read,
 691     mv88w8618_eth_read,
 692     mv88w8618_eth_read
 693 };
 694
 695 static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
 696     mv88w8618_eth_write,
 697     mv88w8618_eth_write,
 698     mv88w8618_eth_write
 699 };
 700
 701 static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq)
 702 {
 703     mv88w8618_eth_state *s;
 704     int iomemtype;
 705
 706     s = qemu_mallocz(sizeof(mv88w8618_eth_state));
 707     if (!s)
 708         return;
 709     s->base = base;
 710     s->irq = irq;
 711     s->vc = qemu_new_vlan_client(nd->vlan, eth_receive, eth_can_receive, s);
 712     iomemtype = cpu_register_io_memory(0, mv88w8618_eth_readfn,
 713                                        mv88w8618_eth_writefn, s);
 714     cpu_register_physical_memory(base, MP_ETH_SIZE, iomemtype);
 715 }
 716
 717 /* LCD register offsets */
 718 #define MP_LCD_IRQCTRL          0x180
 719 #define MP_LCD_IRQSTAT          0x184
 720 #define MP_LCD_SPICTRL          0x1ac
 721 #define MP_LCD_INST             0x1bc
 722 #define MP_LCD_DATA             0x1c0
 723
 724 /* Mode magics */
 725 #define MP_LCD_SPI_DATA         0x00100011
 726 #define MP_LCD_SPI_CMD          0x00104011
 727 #define MP_LCD_SPI_INVALID      0x00000000
 728
 729 /* Commmands */
 730 #define MP_LCD_INST_SETPAGE0    0xB0
 731 /* ... */
 732 #define MP_LCD_INST_SETPAGE7    0xB7
 733
 734 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 735
 736 typedef struct musicpal_lcd_state {
 737     uint32_t base;
 738     uint32_t mode;
 739     uint32_t irqctrl;
 740     int page;
 741     int page_off;
 742     DisplayState *ds;
 743     uint8_t video_ram[128*64/8];
 744 } musicpal_lcd_state;
 745
 746 static uint32_t lcd_brightness;
 747
 748 static uint8_t scale_lcd_color(uint8_t col)
 749 {
 750     int tmp = col;
 751
 752     switch (lcd_brightness) {
 753     case 0x00000007: /* 0 */
 754         return 0;
 755
 756     case 0x00020000: /* 1 */
 757         return (tmp * 1) / 7;
 758
 759     case 0x00020001: /* 2 */
 760         return (tmp * 2) / 7;
 761
 762     case 0x00040000: /* 3 */
 763         return (tmp * 3) / 7;
 764
 765     case 0x00010006: /* 4 */
 766         return (tmp * 4) / 7;
 767
 768     case 0x00020005: /* 5 */
 769         return (tmp * 5) / 7;
 770
 771     case 0x00040003: /* 6 */
 772         return (tmp * 6) / 7;
 773
 774     case 0x00030004: /* 7 */
 775     default:
 776         return col;
 777     }
 778 }
 779
 780 #define SET_LCD_PIXEL(depth, type) \
 781 static inline void glue(set_lcd_pixel, depth) \
 782         (musicpal_lcd_state *s, int x, int y, type col) \
 783 { \
 784     int dx, dy; \
 785     type *pixel = &((type *) s->ds->data)[(y * 128 * 3 + x) * 3]; \
 786 \
 787     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 788         for (dx = 0; dx < 3; dx++, pixel++) \
 789             *pixel = col; \
 790 }
 791 SET_LCD_PIXEL(8, uint8_t)
 792 SET_LCD_PIXEL(16, uint16_t)
 793 SET_LCD_PIXEL(32, uint32_t)
 794
 795 #include "pixel_ops.h"
 796
 797 static void lcd_refresh(void *opaque)
 798 {
 799     musicpal_lcd_state *s = opaque;
 800     int x, y, col;
 801
 802     switch (s->ds->depth) {
 803     case 0:
 804         return;
 805 #define LCD_REFRESH(depth, func) \
 806     case depth: \
 807         col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 808                    scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 809                    scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
 810         for (x = 0; x < 128; x++) \
 811             for (y = 0; y < 64; y++) \
 812                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
 813                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 814                 else \
 815                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 816         break;
 817     LCD_REFRESH(8, rgb_to_pixel8)
 818     LCD_REFRESH(16, rgb_to_pixel16)
 819     LCD_REFRESH(32, (s->ds->bgr ? rgb_to_pixel32bgr : rgb_to_pixel32))
 820     default:
 821         cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
 822                   s->ds->depth);
 823     }
 824
 825     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 826 }
 827
 828 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
 829 {
 830     musicpal_lcd_state *s = opaque;
 831
 832     offset -= s->base;
 833     switch (offset) {
 834     case MP_LCD_IRQCTRL:
 835         return s->irqctrl;
 836
 837     default:
 838         return 0;
 839     }
 840 }
 841
 842 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 843                                uint32_t value)
 844 {
 845     musicpal_lcd_state *s = opaque;
 846
 847     offset -= s->base;
 848     switch (offset) {
 849     case MP_LCD_IRQCTRL:
 850         s->irqctrl = value;
 851         break;
 852
 853     case MP_LCD_SPICTRL:
 854         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
 855             s->mode = value;
 856         else
 857             s->mode = MP_LCD_SPI_INVALID;
 858         break;
 859
 860     case MP_LCD_INST:
 861         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 862             s->page = value - MP_LCD_INST_SETPAGE0;
 863             s->page_off = 0;
 864         }
 865         break;
 866
 867     case MP_LCD_DATA:
 868         if (s->mode == MP_LCD_SPI_CMD) {
 869             if (value >= MP_LCD_INST_SETPAGE0 &&
 870                 value <= MP_LCD_INST_SETPAGE7) {
 871                 s->page = value - MP_LCD_INST_SETPAGE0;
 872                 s->page_off = 0;
 873             }
 874         } else if (s->mode == MP_LCD_SPI_DATA) {
 875             s->video_ram[s->page*128 + s->page_off] = value;
 876             s->page_off = (s->page_off + 1) & 127;
 877         }
 878         break;
 879     }
 880 }
 881
 882 static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
 883     musicpal_lcd_read,
 884     musicpal_lcd_read,
 885     musicpal_lcd_read
 886 };
 887
 888 static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
 889     musicpal_lcd_write,
 890     musicpal_lcd_write,
 891     musicpal_lcd_write
 892 };
 893
 894 static void musicpal_lcd_init(DisplayState *ds, uint32_t base)
 895 {
 896     musicpal_lcd_state *s;
 897     int iomemtype;
 898
 899     s = qemu_mallocz(sizeof(musicpal_lcd_state));
 900     if (!s)
 901         return;
 902     s->base = base;
 903     s->ds = ds;
 904     iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
 905                                        musicpal_lcd_writefn, s);
 906     cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype);
 907
 908     graphic_console_init(ds, lcd_refresh, NULL, NULL, NULL, s);
 909     dpy_resize(ds, 128*3, 64*3);
 910 }
 911
 912 /* PIC register offsets */
 913 #define MP_PIC_STATUS           0x00
 914 #define MP_PIC_ENABLE_SET       0x08
 915 #define MP_PIC_ENABLE_CLR       0x0C
 916
 917 typedef struct mv88w8618_pic_state
 918 {
 919     uint32_t base;
 920     uint32_t level;
 921     uint32_t enabled;
 922     qemu_irq parent_irq;
 923 } mv88w8618_pic_state;
 924
 925 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 926 {
 927     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 928 }
 929
 930 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 931 {
 932     mv88w8618_pic_state *s = opaque;
 933
 934     if (level)
 935         s->level |= 1 << irq;
 936     else
 937         s->level &= ~(1 << irq);
 938     mv88w8618_pic_update(s);
 939 }
 940
 941 static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
 942 {
 943     mv88w8618_pic_state *s = opaque;
 944
 945     offset -= s->base;
 946     switch (offset) {
 947     case MP_PIC_STATUS:
 948         return s->level & s->enabled;
 949
 950     default:
 951         return 0;
 952     }
 953 }
 954
 955 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 956                                 uint32_t value)
 957 {
 958     mv88w8618_pic_state *s = opaque;
 959
 960     offset -= s->base;
 961     switch (offset) {
 962     case MP_PIC_ENABLE_SET:
 963         s->enabled |= value;
 964         break;
 965
 966     case MP_PIC_ENABLE_CLR:
 967         s->enabled &= ~value;
 968         s->level &= ~value;
 969         break;
 970     }
 971     mv88w8618_pic_update(s);
 972 }
 973
 974 static void mv88w8618_pic_reset(void *opaque)
 975 {
 976     mv88w8618_pic_state *s = opaque;
 977
 978     s->level = 0;
 979     s->enabled = 0;
 980 }
 981
 982 static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
 983     mv88w8618_pic_read,
 984     mv88w8618_pic_read,
 985     mv88w8618_pic_read
 986 };
 987
 988 static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
 989     mv88w8618_pic_write,
 990     mv88w8618_pic_write,
 991     mv88w8618_pic_write
 992 };
 993
 994 static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
 995 {
 996     mv88w8618_pic_state *s;
 997     int iomemtype;
 998     qemu_irq *qi;
 999
1000     s = qemu_mallocz(sizeof(mv88w8618_pic_state));
1001     if (!s)
1002         return NULL;
1003     qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
1004     s->base = base;
1005     s->parent_irq = parent_irq;
1006     iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1007                                        mv88w8618_pic_writefn, s);
1008     cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype);
1009
1010     qemu_register_reset(mv88w8618_pic_reset, s);
1011
1012     return qi;
1013 }
1014
1015 /* PIT register offsets */
1016 #define MP_PIT_TIMER1_LENGTH    0x00
1017 /* ... */
1018 #define MP_PIT_TIMER4_LENGTH    0x0C
1019 #define MP_PIT_CONTROL          0x10
1020 #define MP_PIT_TIMER1_VALUE     0x14
1021 /* ... */
1022 #define MP_PIT_TIMER4_VALUE     0x20
1023 #define MP_BOARD_RESET          0x34
1024
1025 /* Magic board reset value (probably some watchdog behind it) */
1026 #define MP_BOARD_RESET_MAGIC    0x10000
1027
1028 typedef struct mv88w8618_timer_state {
1029     ptimer_state *timer;
1030     uint32_t limit;
1031     int freq;
1032     qemu_irq irq;
1033 } mv88w8618_timer_state;
1034
1035 typedef struct mv88w8618_pit_state {
1036     void *timer[4];
1037     uint32_t control;
1038     uint32_t base;
1039 } mv88w8618_pit_state;
1040
1041 static void mv88w8618_timer_tick(void *opaque)
1042 {
1043     mv88w8618_timer_state *s = opaque;
1044
1045     qemu_irq_raise(s->irq);
1046 }
1047
1048 static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq)
1049 {
1050     mv88w8618_timer_state *s;
1051     QEMUBH *bh;
1052
1053     s = qemu_mallocz(sizeof(mv88w8618_timer_state));
1054     s->irq = irq;
1055     s->freq = freq;
1056
1057     bh = qemu_bh_new(mv88w8618_timer_tick, s);
1058     s->timer = ptimer_init(bh);
1059
1060     return s;
1061 }
1062
1063 static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1064 {
1065     mv88w8618_pit_state *s = opaque;
1066     mv88w8618_timer_state *t;
1067
1068     offset -= s->base;
1069     switch (offset) {
1070     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1071         t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1072         return ptimer_get_count(t->timer);
1073
1074     default:
1075         return 0;
1076     }
1077 }
1078
1079 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1080                                 uint32_t value)
1081 {
1082     mv88w8618_pit_state *s = opaque;
1083     mv88w8618_timer_state *t;
1084     int i;
1085
1086     offset -= s->base;
1087     switch (offset) {
1088     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1089         t = s->timer[offset >> 2];
1090         t->limit = value;
1091         ptimer_set_limit(t->timer, t->limit, 1);
1092         break;
1093
1094     case MP_PIT_CONTROL:
1095         for (i = 0; i < 4; i++) {
1096             if (value & 0xf) {
1097                 t = s->timer[i];
1098                 ptimer_set_limit(t->timer, t->limit, 0);
1099                 ptimer_set_freq(t->timer, t->freq);
1100                 ptimer_run(t->timer, 0);
1101             }
1102             value >>= 4;
1103         }
1104         break;
1105
1106     case MP_BOARD_RESET:
1107         if (value == MP_BOARD_RESET_MAGIC)
1108             qemu_system_reset_request();
1109         break;
1110     }
1111 }
1112
1113 static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1114     mv88w8618_pit_read,
1115     mv88w8618_pit_read,
1116     mv88w8618_pit_read
1117 };
1118
1119 static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1120     mv88w8618_pit_write,
1121     mv88w8618_pit_write,
1122     mv88w8618_pit_write
1123 };
1124
1125 static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq)
1126 {
1127     int iomemtype;
1128     mv88w8618_pit_state *s;
1129
1130     s = qemu_mallocz(sizeof(mv88w8618_pit_state));
1131     if (!s)
1132         return;
1133
1134     s->base = base;
1135     /* Letting them all run at 1 MHz is likely just a pragmatic
1136      * simplification. */
1137     s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]);
1138     s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]);
1139     s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]);
1140     s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]);
1141
1142     iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
1143                                        mv88w8618_pit_writefn, s);
1144     cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype);
1145 }
1146
1147 /* Flash config register offsets */
1148 #define MP_FLASHCFG_CFGR0    0x04
1149
1150 typedef struct mv88w8618_flashcfg_state {
1151     uint32_t base;
1152     uint32_t cfgr0;
1153 } mv88w8618_flashcfg_state;
1154
1155 static uint32_t mv88w8618_flashcfg_read(void *opaque,
1156                                         target_phys_addr_t offset)
1157 {
1158     mv88w8618_flashcfg_state *s = opaque;
1159
1160     offset -= s->base;
1161     switch (offset) {
1162     case MP_FLASHCFG_CFGR0:
1163         return s->cfgr0;
1164
1165     default:
1166         return 0;
1167     }
1168 }
1169
1170 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1171                                      uint32_t value)
1172 {
1173     mv88w8618_flashcfg_state *s = opaque;
1174
1175     offset -= s->base;
1176     switch (offset) {
1177     case MP_FLASHCFG_CFGR0:
1178         s->cfgr0 = value;
1179         break;
1180     }
1181 }
1182
1183 static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1184     mv88w8618_flashcfg_read,
1185     mv88w8618_flashcfg_read,
1186     mv88w8618_flashcfg_read
1187 };
1188
1189 static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1190     mv88w8618_flashcfg_write,
1191     mv88w8618_flashcfg_write,
1192     mv88w8618_flashcfg_write
1193 };
1194
1195 static void mv88w8618_flashcfg_init(uint32_t base)
1196 {
1197     int iomemtype;
1198     mv88w8618_flashcfg_state *s;
1199
1200     s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
1201     if (!s)
1202         return;
1203
1204     s->base = base;
1205     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1206     iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
1207                        mv88w8618_flashcfg_writefn, s);
1208     cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype);
1209 }
1210
1211 /* Various registers in the 0x80000000 domain */
1212 #define MP_BOARD_REVISION       0x2018
1213
1214 #define MP_WLAN_MAGIC1          0xc11c
1215 #define MP_WLAN_MAGIC2          0xc124
1216
1217 #define MP_GPIO_OE_LO           0xd008
1218 #define MP_GPIO_OUT_LO          0xd00c
1219 #define MP_GPIO_IN_LO           0xd010
1220 #define MP_GPIO_ISR_LO          0xd020
1221 #define MP_GPIO_OE_HI           0xd508
1222 #define MP_GPIO_OUT_HI          0xd50c
1223 #define MP_GPIO_IN_HI           0xd510
1224 #define MP_GPIO_ISR_HI          0xd520
1225
1226 /* GPIO bits & masks */
1227 #define MP_GPIO_WHEEL_VOL       (1 << 8)
1228 #define MP_GPIO_WHEEL_VOL_INV   (1 << 9)
1229 #define MP_GPIO_WHEEL_NAV       (1 << 10)
1230 #define MP_GPIO_WHEEL_NAV_INV   (1 << 11)
1231 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1232 #define MP_GPIO_BTN_FAVORITS    (1 << 19)
1233 #define MP_GPIO_BTN_MENU        (1 << 20)
1234 #define MP_GPIO_BTN_VOLUME      (1 << 21)
1235 #define MP_GPIO_BTN_NAVIGATION  (1 << 22)
1236 #define MP_GPIO_I2C_DATA_BIT    29
1237 #define MP_GPIO_I2C_DATA        (1 << MP_GPIO_I2C_DATA_BIT)
1238 #define MP_GPIO_I2C_CLOCK_BIT   30
1239
1240 /* LCD brightness bits in GPIO_OE_HI */
1241 #define MP_OE_LCD_BRIGHTNESS    0x0007
1242
1243 static uint32_t musicpal_read(void *opaque, target_phys_addr_t offset)
1244 {
1245     offset -= 0x80000000;
1246     switch (offset) {
1247     case MP_BOARD_REVISION:
1248         return 0x0031;
1249
1250     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1251         return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1252
1253     case MP_GPIO_OUT_LO:
1254         return gpio_out_state & 0xFFFF;
1255     case MP_GPIO_OUT_HI:
1256         return gpio_out_state >> 16;
1257
1258     case MP_GPIO_IN_LO:
1259         return gpio_in_state & 0xFFFF;
1260     case MP_GPIO_IN_HI:
1261         /* Update received I2C data */
1262         gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1263                         (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1264         return gpio_in_state >> 16;
1265
1266     /* This is a simplification of reality */
1267     case MP_GPIO_ISR_LO:
1268         return ~gpio_in_state & 0xFFFF;
1269     case MP_GPIO_ISR_HI:
1270         return ~gpio_in_state >> 16;
1271
1272     /* Workaround to allow loading the binary-only wlandrv.ko crap
1273      * from the original Freecom firmware. */
1274     case MP_WLAN_MAGIC1:
1275         return ~3;
1276     case MP_WLAN_MAGIC2:
1277         return -1;
1278
1279     default:
1280         return 0;
1281     }
1282 }
1283
1284 static void musicpal_write(void *opaque, target_phys_addr_t offset,
1285                            uint32_t value)
1286 {
1287     offset -= 0x80000000;
1288     switch (offset) {
1289     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1290         lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1291                          (value & MP_OE_LCD_BRIGHTNESS);
1292         break;
1293
1294     case MP_GPIO_OUT_LO:
1295         gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1296         break;
1297     case MP_GPIO_OUT_HI:
1298         gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1299         lcd_brightness = (lcd_brightness & 0xFFFF) |
1300                          (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1301         i2c_state_update(mixer_i2c,
1302                          (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1303                          (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1304         break;
1305
1306     }
1307 }
1308
1309 /* Keyboard codes & masks */
1310 #define KEY_PRESSED             0x80
1311 #define KEY_CODE                0x7f
1312
1313 #define KEYCODE_TAB             0x0f
1314 #define KEYCODE_ENTER           0x1c
1315 #define KEYCODE_F               0x21
1316 #define KEYCODE_M               0x32
1317
1318 #define KEYCODE_EXTENDED        0xe0
1319 #define KEYCODE_UP              0x48
1320 #define KEYCODE_DOWN            0x50
1321 #define KEYCODE_LEFT            0x4b
1322 #define KEYCODE_RIGHT           0x4d
1323
1324 static void musicpal_key_event(void *opaque, int keycode)
1325 {
1326     qemu_irq irq = opaque;
1327     uint32_t event = 0;
1328     static int kbd_extended;
1329
1330     if (keycode == KEYCODE_EXTENDED) {
1331         kbd_extended = 1;
1332         return;
1333     }
1334
1335     if (kbd_extended)
1336         switch (keycode & KEY_CODE) {
1337         case KEYCODE_UP:
1338             event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1339             break;
1340
1341         case KEYCODE_DOWN:
1342             event = MP_GPIO_WHEEL_NAV;
1343             break;
1344
1345         case KEYCODE_LEFT:
1346             event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1347             break;
1348
1349         case KEYCODE_RIGHT:
1350             event = MP_GPIO_WHEEL_VOL;
1351             break;
1352         }
1353     else
1354         switch (keycode & KEY_CODE) {
1355         case KEYCODE_F:
1356             event = MP_GPIO_BTN_FAVORITS;
1357             break;
1358
1359         case KEYCODE_TAB:
1360             event = MP_GPIO_BTN_VOLUME;
1361             break;
1362
1363         case KEYCODE_ENTER:
1364             event = MP_GPIO_BTN_NAVIGATION;
1365             break;
1366
1367         case KEYCODE_M:
1368             event = MP_GPIO_BTN_MENU;
1369             break;
1370         }
1371
1372     if (keycode & KEY_PRESSED)
1373         gpio_in_state |= event;
1374     else if (gpio_in_state & event) {
1375         gpio_in_state &= ~event;
1376         qemu_irq_raise(irq);
1377     }
1378
1379     kbd_extended = 0;
1380 }
1381
1382 static CPUReadMemoryFunc *musicpal_readfn[] = {
1383     musicpal_read,
1384     musicpal_read,
1385     musicpal_read,
1386 };
1387
1388 static CPUWriteMemoryFunc *musicpal_writefn[] = {
1389     musicpal_write,
1390     musicpal_write,
1391     musicpal_write,
1392 };
1393
1394 static struct arm_boot_info musicpal_binfo = {
1395     .loader_start = 0x0,
1396     .board_id = 0x20e,
1397 };
1398
1399 static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
1400                const char *boot_device, DisplayState *ds,
1401                const char *kernel_filename, const char *kernel_cmdline,
1402                const char *initrd_filename, const char *cpu_model)
1403 {
1404     CPUState *env;
1405     qemu_irq *pic;
1406     int index;
1407     int iomemtype;
1408     unsigned long flash_size;
1409
1410     if (!cpu_model)
1411         cpu_model = "arm926";
1412
1413     env = cpu_init(cpu_model);
1414     if (!env) {
1415         fprintf(stderr, "Unable to find CPU definition\n");
1416         exit(1);
1417     }
1418     pic = arm_pic_init_cpu(env);
1419
1420     /* For now we use a fixed - the original - RAM size */
1421     cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1422                                  qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1423
1424     sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1425     cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1426
1427     /* Catch various stuff not handled by separate subsystems */
1428     iomemtype = cpu_register_io_memory(0, musicpal_readfn,
1429                                        musicpal_writefn, env);
1430     cpu_register_physical_memory(0x80000000, 0x10000, iomemtype);
1431
1432     pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]);
1433     mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
1434
1435     if (serial_hds[0])
1436         serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], /*1825000,*/
1437                    serial_hds[0], 1);
1438     if (serial_hds[1])
1439         serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], /*1825000,*/
1440                    serial_hds[1], 1);
1441
1442     /* Register flash */
1443     index = drive_get_index(IF_PFLASH, 0, 0);
1444     if (index != -1) {
1445         flash_size = bdrv_getlength(drives_table[index].bdrv);
1446         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1447             flash_size != 32*1024*1024) {
1448             fprintf(stderr, "Invalid flash image size\n");
1449             exit(1);
1450         }
1451
1452         /*
1453          * The original U-Boot accesses the flash at 0xFE000000 instead of
1454          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1455          * image is smaller than 32 MB.
1456          */
1457         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1458                               drives_table[index].bdrv, 0x10000,
1459                               (flash_size + 0xffff) >> 16,
1460                               MP_FLASH_SIZE_MAX / flash_size,
1461                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1462                               0x5555, 0x2AAA);
1463     }
1464     mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
1465
1466     musicpal_lcd_init(ds, MP_LCD_BASE);
1467
1468     qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1469
1470     /*
1471      * Wait a bit to catch menu button during U-Boot start-up
1472      * (to trigger emergency update).
1473      */
1474     sleep(1);
1475
1476     mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
1477
1478     mixer_i2c = musicpal_audio_init(MP_AUDIO_BASE, pic[MP_AUDIO_IRQ]);
1479
1480     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1481     musicpal_binfo.kernel_filename = kernel_filename;
1482     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1483     musicpal_binfo.initrd_filename = initrd_filename;
1484     arm_load_kernel(env, &musicpal_binfo);
1485 }
1486
1487 QEMUMachine musicpal_machine = {
1488     "musicpal",
1489     "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1490     musicpal_init,
1491     MP_RAM_DEFAULT_SIZE + MP_SRAM_SIZE + MP_FLASH_SIZE_MAX + RAMSIZE_FIXED
1492 };