target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ARM_H
  21 #define CPU_ARM_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #include "cpu-defs.h"
  26
  27 #include "softfloat.h"
  28
  29 #define TARGET_HAS_ICE 1
  30
  31 #define EXCP_UDEF            1   /* undefined instruction */
  32 #define EXCP_SWI             2   /* software interrupt */
  33 #define EXCP_PREFETCH_ABORT  3
  34 #define EXCP_DATA_ABORT      4
  35 #define EXCP_IRQ             5
  36 #define EXCP_FIQ             6
  37 #define EXCP_BKPT            7
  38
  39 /* We currently assume float and double are IEEE single and double
  40    precision respectively.
  41    Doing runtime conversions is tricky because VFP registers may contain
  42    integer values (eg. as the result of a FTOSI instruction).
  43    s<2n> maps to the least significant half of d<n>
  44    s<2n+1> maps to the most significant half of d<n>
  45  */
  46
  47 typedef struct CPUARMState {
  48     /* Regs for current mode.  */
  49     uint32_t regs[16];
  50     /* Frequently accessed CPSR bits are stored separately for efficiently.
  51        This contains all the other bits.  Use cpsr_{read,write} to accless
  52        the whole CPSR.  */
  53     uint32_t uncached_cpsr;
  54     uint32_t spsr;
  55
  56     /* Banked registers.  */
  57     uint32_t banked_spsr[6];
  58     uint32_t banked_r13[6];
  59     uint32_t banked_r14[6];
  60
  61     /* These hold r8-r12.  */
  62     uint32_t usr_regs[5];
  63     uint32_t fiq_regs[5];
  64
  65     /* cpsr flag cache for faster execution */
  66     uint32_t CF; /* 0 or 1 */
  67     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  68     uint32_t NZF; /* N is bit 31. Z is computed from NZF */
  69     uint32_t QF; /* 0 or 1 */
  70
  71     int thumb; /* 0 = arm mode, 1 = thumb mode */
  72
  73     /* System control coprocessor (cp15) */
  74     struct {
  75         uint32_t c1_sys; /* System control register.  */
  76         uint32_t c1_coproc; /* Coprocessor access register.  */
  77         uint32_t c2; /* MMU translation table base.  */
  78         uint32_t c3; /* MMU domain access control register.  */
  79         uint32_t c5_insn; /* Fault status registers.  */
  80         uint32_t c5_data;
  81         uint32_t c6_insn; /* Fault address registers.  */
  82         uint32_t c6_data;
  83         uint32_t c9_insn; /* Cache lockdown registers.  */
  84         uint32_t c9_data;
  85         uint32_t c13_fcse; /* FCSE PID.  */
  86         uint32_t c13_context; /* Context ID.  */
  87     } cp15;
  88
  89     /* exception/interrupt handling */
  90     jmp_buf jmp_env;
  91     int exception_index;
  92     int interrupt_request;
  93     int user_mode_only;
  94     int halted;
  95
  96     /* VFP coprocessor state.  */
  97     struct {
  98         float64 regs[16];
  99
 100         /* We store these fpcsr fields separately for convenience.  */
 101         int vec_len;
 102         int vec_stride;
 103
 104         uint32_t fpscr;
 105
 106         /* Temporary variables if we don't have spare fp regs.  */
 107         float32 tmp0s, tmp1s;
 108         float64 tmp0d, tmp1d;
 109
 110         float_status fp_status;
 111     } vfp;
 112
 113     CPU_COMMON
 114
 115 } CPUARMState;
 116
 117 CPUARMState *cpu_arm_init(void);
 118 int cpu_arm_exec(CPUARMState *s);
 119 void cpu_arm_close(CPUARMState *s);
 120 void do_interrupt(CPUARMState *);
 121 void switch_mode(CPUARMState *, int);
 122
 123 /* you can call this signal handler from your SIGBUS and SIGSEGV
 124    signal handlers to inform the virtual CPU of exceptions. non zero
 125    is returned if the signal was handled by the virtual CPU.  */
 126 struct siginfo;
 127 int cpu_arm_signal_handler(int host_signum, struct siginfo *info,
 128                            void *puc);
 129
 130 #define CPSR_M (0x1f)
 131 #define CPSR_T (1 << 5)
 132 #define CPSR_F (1 << 6)
 133 #define CPSR_I (1 << 7)
 134 #define CPSR_A (1 << 8)
 135 #define CPSR_E (1 << 9)
 136 #define CPSR_IT_2_7 (0xfc00)
 137 /* Bits 20-23 reserved.  */
 138 #define CPSR_J (1 << 24)
 139 #define CPSR_IT_0_1 (3 << 25)
 140 #define CPSR_Q (1 << 27)
 141 #define CPSR_NZCV (0xf << 28)
 142
 143 #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
 144 /* Return the current CPSR value.  */
 145 static inline uint32_t cpsr_read(CPUARMState *env)
 146 {
 147     int ZF;
 148     ZF = (env->NZF == 0);
 149     return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
 150         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 151         | (env->thumb << 5);
 152 }
 153
 154 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 155 static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 156 {
 157     /* NOTE: N = 1 and Z = 1 cannot be stored currently */
 158     if (mask & CPSR_NZCV) {
 159         env->NZF = (val & 0xc0000000) ^ 0x40000000;
 160         env->CF = (val >> 29) & 1;
 161         env->VF = (val << 3) & 0x80000000;
 162     }
 163     if (mask & CPSR_Q)
 164         env->QF = ((val & CPSR_Q) != 0);
 165     if (mask & CPSR_T)
 166         env->thumb = ((val & CPSR_T) != 0);
 167
 168     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
 169         switch_mode(env, val & CPSR_M);
 170     }
 171     mask &= ~CACHED_CPSR_BITS;
 172     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
 173 }
 174
 175 enum arm_cpu_mode {
 176   ARM_CPU_MODE_USR = 0x10,
 177   ARM_CPU_MODE_FIQ = 0x11,
 178   ARM_CPU_MODE_IRQ = 0x12,
 179   ARM_CPU_MODE_SVC = 0x13,
 180   ARM_CPU_MODE_ABT = 0x17,
 181   ARM_CPU_MODE_UND = 0x1b,
 182   ARM_CPU_MODE_SYS = 0x1f
 183 };
 184
 185 #if defined(CONFIG_USER_ONLY)
 186 #define TARGET_PAGE_BITS 12
 187 #else
 188 /* The ARM MMU allows 1k pages.  */
 189 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 190    architecture revisions.  Maybe an a configure option to disable them.  */
 191 #define TARGET_PAGE_BITS 10
 192 #endif
 193 #include "cpu-all.h"
 194
 195 #endif