target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <signal.h>
  26 #include <assert.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30
  31 enum {
  32     TLBRET_DIRTY = -4,
  33     TLBRET_INVALID = -3,
  34     TLBRET_NOMATCH = -2,
  35     TLBRET_BADADDR = -1,
  36     TLBRET_MATCH = 0
  37 };
  38
  39 /* no MMU emulation */
  40 int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
  41                         target_ulong address, int rw, int access_type)
  42 {
  43     *physical = address;
  44     *prot = PAGE_READ | PAGE_WRITE;
  45     return TLBRET_MATCH;
  46 }
  47
  48 /* fixed mapping MMU emulation */
  49 int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
  50                            target_ulong address, int rw, int access_type)
  51 {
  52     if (address <= (int32_t)0x7FFFFFFFUL) {
  53         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  54             *physical = address + 0x40000000UL;
  55         else
  56             *physical = address;
  57     } else if (address <= (int32_t)0xBFFFFFFFUL)
  58         *physical = address & 0x1FFFFFFF;
  59     else
  60         *physical = address;
  61
  62     *prot = PAGE_READ | PAGE_WRITE;
  63     return TLBRET_MATCH;
  64 }
  65
  66 /* MIPS32/MIPS64 R4000-style MMU emulation */
  67 int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
  68                      target_ulong address, int rw, int access_type)
  69 {
  70     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  71     int i;
  72
  73     for (i = 0; i < env->tlb_in_use; i++) {
  74         r4k_tlb_t *tlb = &env->mmu.r4k.tlb[i];
  75         /* 1k pages are not supported. */
  76         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  77         target_ulong tag = address & ~mask;
  78         target_ulong VPN = tlb->VPN & ~mask;
  79 #ifdef TARGET_MIPS64
  80         tag &= 0xC00000FFFFFFFFFFULL;
  81 #endif
  82
  83         /* Check ASID, virtual page number & size */
  84         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  85             /* TLB match */
  86             int n = !!(address & mask & ~(mask >> 1));
  87             /* Check access rights */
  88             if (!(n ? tlb->V1 : tlb->V0))
  89                 return TLBRET_INVALID;
  90             if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
  91                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  92                 *prot = PAGE_READ;
  93                 if (n ? tlb->D1 : tlb->D0)
  94                     *prot |= PAGE_WRITE;
  95                 return TLBRET_MATCH;
  96             }
  97             return TLBRET_DIRTY;
  98         }
  99     }
 100     return TLBRET_NOMATCH;
 101 }
 102
 103 static int get_physical_address (CPUState *env, target_ulong *physical,
 104                                 int *prot, target_ulong address,
 105                                 int rw, int access_type)
 106 {
 107     /* User mode can only access useg/xuseg */
 108     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 109 #ifdef TARGET_MIPS64
 110     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 111     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 112     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 113 #endif
 114     int ret = TLBRET_MATCH;
 115
 116 #if 0
 117     if (logfile) {
 118         fprintf(logfile, "user mode %d h %08x\n",
 119                 user_mode, env->hflags);
 120     }
 121 #endif
 122
 123 #ifdef TARGET_MIPS64
 124     if (user_mode && address > 0x3FFFFFFFFFFFFFFFULL)
 125         return TLBRET_BADADDR;
 126 #else
 127     if (user_mode && address > 0x7FFFFFFFUL)
 128         return TLBRET_BADADDR;
 129 #endif
 130
 131     if (address <= (int32_t)0x7FFFFFFFUL) {
 132         /* useg */
 133         if (!(env->CP0_Status & (1 << CP0St_ERL) && user_mode)) {
 134             ret = env->map_address(env, physical, prot, address, rw, access_type);
 135         } else {
 136             *physical = address & 0xFFFFFFFF;
 137             *prot = PAGE_READ | PAGE_WRITE;
 138         }
 139 #ifdef TARGET_MIPS64
 140 /*
 141    XXX: Assuming :
 142    - PABITS = 36 (correct for MIPS64R1)
 143    - SEGBITS = 40
 144 */
 145     } else if (address < 0x3FFFFFFFFFFFFFFFULL) {
 146         /* xuseg */
 147         if (UX && address < 0x000000FFFFFFFFFFULL) {
 148             ret = env->map_address(env, physical, prot, address, rw, access_type);
 149         } else {
 150             ret = TLBRET_BADADDR;
 151         }
 152     } else if (address < 0x7FFFFFFFFFFFFFFFULL) {
 153         /* xsseg */
 154         if (SX && address < 0x400000FFFFFFFFFFULL) {
 155             ret = env->map_address(env, physical, prot, address, rw, access_type);
 156         } else {
 157             ret = TLBRET_BADADDR;
 158         }
 159     } else if (address < 0xBFFFFFFFFFFFFFFFULL) {
 160         /* xkphys */
 161         /* XXX: check supervisor mode */
 162         if (KX && (address & 0x03FFFFFFFFFFFFFFULL) < 0X0000000FFFFFFFFFULL)
 163         {
 164             *physical = address & 0X000000FFFFFFFFFFULL;
 165             *prot = PAGE_READ | PAGE_WRITE;
 166         } else {
 167             ret = TLBRET_BADADDR;
 168         }
 169     } else if (address < 0xFFFFFFFF7FFFFFFFULL) {
 170         /* xkseg */
 171         /* XXX: check supervisor mode */
 172         if (KX && address < 0xC00000FF7FFFFFFFULL) {
 173             ret = env->map_address(env, physical, prot, address, rw, access_type);
 174         } else {
 175             ret = TLBRET_BADADDR;
 176         }
 177 #endif
 178     } else if (address < (int32_t)0xA0000000UL) {
 179         /* kseg0 */
 180         /* XXX: check supervisor mode */
 181         *physical = address - (int32_t)0x80000000UL;
 182         *prot = PAGE_READ | PAGE_WRITE;
 183     } else if (address < (int32_t)0xC0000000UL) {
 184         /* kseg1 */
 185         /* XXX: check supervisor mode */
 186         *physical = address - (int32_t)0xA0000000UL;
 187         *prot = PAGE_READ | PAGE_WRITE;
 188     } else if (address < (int32_t)0xE0000000UL) {
 189         /* kseg2 */
 190         ret = env->map_address(env, physical, prot, address, rw, access_type);
 191     } else {
 192         /* kseg3 */
 193         /* XXX: check supervisor mode */
 194         /* XXX: debug segment is not emulated */
 195         ret = env->map_address(env, physical, prot, address, rw, access_type);
 196     }
 197 #if 0
 198     if (logfile) {
 199         fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
 200                 address, rw, access_type, *physical, *prot, ret);
 201     }
 202 #endif
 203
 204     return ret;
 205 }
 206
 207 #if defined(CONFIG_USER_ONLY)
 208 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 209 {
 210     return addr;
 211 }
 212 #else
 213 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 214 {
 215     target_ulong phys_addr;
 216     int prot;
 217
 218     if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
 219         return -1;
 220     return phys_addr;
 221 }
 222
 223 void cpu_mips_init_mmu (CPUState *env)
 224 {
 225 }
 226 #endif /* !defined(CONFIG_USER_ONLY) */
 227
 228 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 229                                int is_user, int is_softmmu)
 230 {
 231     target_ulong physical;
 232     int prot;
 233     int exception = 0, error_code = 0;
 234     int access_type;
 235     int ret = 0;
 236
 237     if (logfile) {
 238 #if 0
 239         cpu_dump_state(env, logfile, fprintf, 0);
 240 #endif
 241         fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d is_user %d smmu %d\n",
 242                 __func__, env->PC, address, rw, is_user, is_softmmu);
 243     }
 244
 245     rw &= 1;
 246
 247     /* data access */
 248     /* XXX: put correct access by using cpu_restore_state()
 249        correctly */
 250     access_type = ACCESS_INT;
 251     if (env->user_mode_only) {
 252         /* user mode only emulation */
 253         ret = TLBRET_NOMATCH;
 254         goto do_fault;
 255     }
 256     ret = get_physical_address(env, &physical, &prot,
 257                                address, rw, access_type);
 258     if (logfile) {
 259         fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
 260                 __func__, address, ret, physical, prot);
 261     }
 262     if (ret == TLBRET_MATCH) {
 263        ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
 264                           physical & TARGET_PAGE_MASK, prot,
 265                           is_user, is_softmmu);
 266     } else if (ret < 0) {
 267     do_fault:
 268         switch (ret) {
 269         default:
 270         case TLBRET_BADADDR:
 271             /* Reference to kernel address from user mode or supervisor mode */
 272             /* Reference to supervisor address from user mode */
 273             if (rw)
 274                 exception = EXCP_AdES;
 275             else
 276                 exception = EXCP_AdEL;
 277             break;
 278         case TLBRET_NOMATCH:
 279             /* No TLB match for a mapped address */
 280             if (rw)
 281                 exception = EXCP_TLBS;
 282             else
 283                 exception = EXCP_TLBL;
 284             error_code = 1;
 285             break;
 286         case TLBRET_INVALID:
 287             /* TLB match with no valid bit */
 288             if (rw)
 289                 exception = EXCP_TLBS;
 290             else
 291                 exception = EXCP_TLBL;
 292             break;
 293         case TLBRET_DIRTY:
 294             /* TLB match but 'D' bit is cleared */
 295             exception = EXCP_LTLBL;
 296             break;
 297
 298         }
 299         /* Raise exception */
 300         env->CP0_BadVAddr = address;
 301         env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 302                            ((address >> 9) &   0x007ffff0);
 303         env->CP0_EntryHi =
 304             (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 305 #ifdef TARGET_MIPS64
 306         env->CP0_EntryHi &= 0xc00000ffffffffffULL;
 307         env->CP0_XContext = (env->CP0_XContext & 0xfffffffe00000000ULL) |
 308                             ((address >> 31) & 0x0000000180000000ULL) |
 309                             ((address >> 9) & 0x000000007ffffff0ULL);
 310 #endif
 311         env->exception_index = exception;
 312         env->error_code = error_code;
 313         ret = 1;
 314     }
 315
 316     return ret;
 317 }
 318
 319 #if defined(CONFIG_USER_ONLY)
 320 void do_interrupt (CPUState *env)
 321 {
 322     env->exception_index = EXCP_NONE;
 323 }
 324 #else
 325 void do_interrupt (CPUState *env)
 326 {
 327     target_ulong offset;
 328     int cause = -1;
 329
 330     if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
 331         fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
 332                 __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
 333     }
 334     if (env->exception_index == EXCP_EXT_INTERRUPT &&
 335         (env->hflags & MIPS_HFLAG_DM))
 336         env->exception_index = EXCP_DINT;
 337     offset = 0x180;
 338     switch (env->exception_index) {
 339     case EXCP_DSS:
 340         env->CP0_Debug |= 1 << CP0DB_DSS;
 341         /* Debug single step cannot be raised inside a delay slot and
 342          * resume will always occur on the next instruction
 343          * (but we assume the pc has always been updated during
 344          *  code translation).
 345          */
 346         env->CP0_DEPC = env->PC;
 347         goto enter_debug_mode;
 348     case EXCP_DINT:
 349         env->CP0_Debug |= 1 << CP0DB_DINT;
 350         goto set_DEPC;
 351     case EXCP_DIB:
 352         env->CP0_Debug |= 1 << CP0DB_DIB;
 353         goto set_DEPC;
 354     case EXCP_DBp:
 355         env->CP0_Debug |= 1 << CP0DB_DBp;
 356         goto set_DEPC;
 357     case EXCP_DDBS:
 358         env->CP0_Debug |= 1 << CP0DB_DDBS;
 359         goto set_DEPC;
 360     case EXCP_DDBL:
 361         env->CP0_Debug |= 1 << CP0DB_DDBL;
 362     set_DEPC:
 363         if (env->hflags & MIPS_HFLAG_BMASK) {
 364             /* If the exception was raised from a delay slot,
 365                come back to the jump.  */
 366             env->CP0_DEPC = env->PC - 4;
 367             env->hflags &= ~MIPS_HFLAG_BMASK;
 368         } else {
 369             env->CP0_DEPC = env->PC;
 370         }
 371     enter_debug_mode:
 372         env->hflags |= MIPS_HFLAG_DM;
 373         env->hflags |= MIPS_HFLAG_64;
 374         env->hflags &= ~MIPS_HFLAG_UM;
 375         /* EJTAG probe trap enable is not implemented... */
 376         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 377             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 378         env->PC = (int32_t)0xBFC00480;
 379         break;
 380     case EXCP_RESET:
 381         cpu_reset(env);
 382         break;
 383     case EXCP_SRESET:
 384         env->CP0_Status |= (1 << CP0St_SR);
 385         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 386         goto set_error_EPC;
 387     case EXCP_NMI:
 388         env->CP0_Status |= (1 << CP0St_NMI);
 389     set_error_EPC:
 390         if (env->hflags & MIPS_HFLAG_BMASK) {
 391             /* If the exception was raised from a delay slot,
 392                come back to the jump.  */
 393             env->CP0_ErrorEPC = env->PC - 4;
 394             env->hflags &= ~MIPS_HFLAG_BMASK;
 395         } else {
 396             env->CP0_ErrorEPC = env->PC;
 397         }
 398         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 399         env->hflags |= MIPS_HFLAG_64;
 400         env->hflags &= ~MIPS_HFLAG_UM;
 401         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 402             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 403         env->PC = (int32_t)0xBFC00000;
 404         break;
 405     case EXCP_MCHECK:
 406         cause = 24;
 407         goto set_EPC;
 408     case EXCP_EXT_INTERRUPT:
 409         cause = 0;
 410         if (env->CP0_Cause & (1 << CP0Ca_IV))
 411             offset = 0x200;
 412         goto set_EPC;
 413     case EXCP_DWATCH:
 414         cause = 23;
 415         /* XXX: TODO: manage defered watch exceptions */
 416         goto set_EPC;
 417     case EXCP_AdEL:
 418         cause = 4;
 419         goto set_EPC;
 420     case EXCP_AdES:
 421         cause = 5;
 422         goto set_EPC;
 423     case EXCP_TLBL:
 424         cause = 2;
 425         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 426 #ifdef TARGET_MIPS64
 427             int R = env->CP0_BadVAddr >> 62;
 428             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 429             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 430             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 431
 432             if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
 433                 offset = 0x080;
 434             else
 435 #endif
 436                 offset = 0x000;
 437         }
 438         goto set_EPC;
 439     case EXCP_IBE:
 440         cause = 6;
 441         goto set_EPC;
 442     case EXCP_DBE:
 443         cause = 7;
 444         goto set_EPC;
 445     case EXCP_SYSCALL:
 446         cause = 8;
 447         goto set_EPC;
 448     case EXCP_BREAK:
 449         cause = 9;
 450         goto set_EPC;
 451     case EXCP_RI:
 452         cause = 10;
 453         goto set_EPC;
 454     case EXCP_CpU:
 455         cause = 11;
 456         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 457                          (env->error_code << CP0Ca_CE);
 458         goto set_EPC;
 459     case EXCP_OVERFLOW:
 460         cause = 12;
 461         goto set_EPC;
 462     case EXCP_TRAP:
 463         cause = 13;
 464         goto set_EPC;
 465     case EXCP_FPE:
 466         cause = 15;
 467         goto set_EPC;
 468     case EXCP_LTLBL:
 469         cause = 1;
 470         goto set_EPC;
 471     case EXCP_TLBS:
 472         cause = 3;
 473         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 474 #ifdef TARGET_MIPS64
 475             int R = env->CP0_BadVAddr >> 62;
 476             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 477             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 478             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 479
 480             if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
 481                 offset = 0x080;
 482             else
 483 #endif
 484                 offset = 0x000;
 485         }
 486     set_EPC:
 487         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 488             if (env->hflags & MIPS_HFLAG_BMASK) {
 489                 /* If the exception was raised from a delay slot,
 490                    come back to the jump.  */
 491                 env->CP0_EPC = env->PC - 4;
 492                 env->CP0_Cause |= (1 << CP0Ca_BD);
 493             } else {
 494                 env->CP0_EPC = env->PC;
 495                 env->CP0_Cause &= ~(1 << CP0Ca_BD);
 496             }
 497             env->CP0_Status |= (1 << CP0St_EXL);
 498             env->hflags |= MIPS_HFLAG_64;
 499             env->hflags &= ~MIPS_HFLAG_UM;
 500         }
 501         env->hflags &= ~MIPS_HFLAG_BMASK;
 502         if (env->CP0_Status & (1 << CP0St_BEV)) {
 503             env->PC = (int32_t)0xBFC00200;
 504         } else {
 505             env->PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 506         }
 507         env->PC += offset;
 508         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 509         break;
 510     default:
 511         if (logfile) {
 512             fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
 513                     env->exception_index);
 514         }
 515         printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 516         exit(1);
 517     }
 518     if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
 519         fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
 520                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 521                 __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
 522                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 523                 env->CP0_DEPC);
 524     }
 525     env->exception_index = EXCP_NONE;
 526 }
 527 #endif /* !defined(CONFIG_USER_ONLY) */
 528
 529 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
 530 {
 531     r4k_tlb_t *tlb;
 532     target_ulong addr;
 533     target_ulong end;
 534     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 535     target_ulong mask;
 536
 537     tlb = &env->mmu.r4k.tlb[idx];
 538     /* The qemu TLB is flushed when the ASID changes, so no need to
 539        flush these entries again.  */
 540     if (tlb->G == 0 && tlb->ASID != ASID) {
 541         return;
 542     }
 543
 544     if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
 545         /* For tlbwr, we can shadow the discarded entry into
 546            a new (fake) TLB entry, as long as the guest can not
 547            tell that it's there.  */
 548         env->mmu.r4k.tlb[env->tlb_in_use] = *tlb;
 549         env->tlb_in_use++;
 550         return;
 551     }
 552
 553     /* 1k pages are not supported. */
 554     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 555     if (tlb->V0) {
 556         addr = tlb->VPN & ~mask;
 557 #ifdef TARGET_MIPS64
 558         if (addr >= 0xC00000FF80000000ULL) {
 559             addr |= 0x3FFFFF0000000000ULL;
 560         }
 561 #endif
 562         end = addr | (mask >> 1);
 563         while (addr < end) {
 564             tlb_flush_page (env, addr);
 565             addr += TARGET_PAGE_SIZE;
 566         }
 567     }
 568     if (tlb->V1) {
 569         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 570 #ifdef TARGET_MIPS64
 571         if (addr >= 0xC00000FF80000000ULL) {
 572             addr |= 0x3FFFFF0000000000ULL;
 573         }
 574 #endif
 575         end = addr | mask;
 576         while (addr < end) {
 577             tlb_flush_page (env, addr);
 578             addr += TARGET_PAGE_SIZE;
 579         }
 580     }
 581 }