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Thumb shifter carry flag fixes.
[qemu/mini2440.git] / cpu-exec.c
blob4f7f215c01aee3830956d6661675ed1c0d8d37ee
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 void cpu_loop_exit(void)
44 {
45 /* NOTE: the register at this point must be saved by hand because
46 longjmp restore them */
47 regs_to_env();
48 longjmp(env->jmp_env, 1);
49 }
50
51 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
52 #define reg_T2
53 #endif
54
55 /* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
57 */
58 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 {
60 #if !defined(CONFIG_SOFTMMU)
61 struct ucontext *uc = puc;
62 #endif
63
64 env = env1;
65
66 /* XXX: restore cpu registers saved in host registers */
67
68 #if !defined(CONFIG_SOFTMMU)
69 if (puc) {
70 /* XXX: use siglongjmp ? */
71 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
72 }
73 #endif
74 longjmp(env->jmp_env, 1);
75 }
76
77
78 static TranslationBlock *tb_find_slow(target_ulong pc,
79 target_ulong cs_base,
80 unsigned int flags)
81 {
82 TranslationBlock *tb, **ptb1;
83 int code_gen_size;
84 unsigned int h;
85 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
86 uint8_t *tc_ptr;
87
88 spin_lock(&tb_lock);
89
90 tb_invalidated_flag = 0;
91
92 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93
94 /* find translated block using physical mappings */
95 phys_pc = get_phys_addr_code(env, pc);
96 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 phys_page2 = -1;
98 h = tb_phys_hash_func(phys_pc);
99 ptb1 = &tb_phys_hash[h];
100 for(;;) {
101 tb = *ptb1;
102 if (!tb)
103 goto not_found;
104 if (tb->pc == pc &&
105 tb->page_addr[0] == phys_page1 &&
106 tb->cs_base == cs_base &&
107 tb->flags == flags) {
108 /* check next page if needed */
109 if (tb->page_addr[1] != -1) {
110 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 TARGET_PAGE_SIZE;
112 phys_page2 = get_phys_addr_code(env, virt_page2);
113 if (tb->page_addr[1] == phys_page2)
114 goto found;
115 } else {
116 goto found;
117 }
118 }
119 ptb1 = &tb->phys_hash_next;
120 }
121 not_found:
122 /* if no translated code available, then translate it now */
123 tb = tb_alloc(pc);
124 if (!tb) {
125 /* flush must be done */
126 tb_flush(env);
127 /* cannot fail at this point */
128 tb = tb_alloc(pc);
129 /* don't forget to invalidate previous TB info */
130 tb_invalidated_flag = 1;
131 }
132 tc_ptr = code_gen_ptr;
133 tb->tc_ptr = tc_ptr;
134 tb->cs_base = cs_base;
135 tb->flags = flags;
136 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
137 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138
139 /* check next page if needed */
140 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 phys_page2 = -1;
142 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
143 phys_page2 = get_phys_addr_code(env, virt_page2);
144 }
145 tb_link_phys(tb, phys_pc, phys_page2);
146
147 found:
148 /* we add the TB in the virtual pc hash table */
149 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
150 spin_unlock(&tb_lock);
151 return tb;
152 }
153
154 static inline TranslationBlock *tb_find_fast(void)
155 {
156 TranslationBlock *tb;
157 target_ulong cs_base, pc;
158 unsigned int flags;
159
160 /* we record a subset of the CPU state. It will
161 always be the same before a given translated block
162 is executed. */
163 #if defined(TARGET_I386)
164 flags = env->hflags;
165 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
166 cs_base = env->segs[R_CS].base;
167 pc = cs_base + env->eip;
168 #elif defined(TARGET_ARM)
169 flags = env->thumb | (env->vfp.vec_len << 1)
170 | (env->vfp.vec_stride << 4);
171 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
172 flags |= (1 << 6);
173 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
174 flags |= (1 << 7);
175 cs_base = 0;
176 pc = env->regs[15];
177 #elif defined(TARGET_SPARC)
178 #ifdef TARGET_SPARC64
179 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
180 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
181 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
182 #else
183 // FPU enable . MMU enabled . MMU no-fault . Supervisor
184 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
185 | env->psrs;
186 #endif
187 cs_base = env->npc;
188 pc = env->pc;
189 #elif defined(TARGET_PPC)
190 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
191 (msr_se << MSR_SE) | (msr_le << MSR_LE);
192 cs_base = 0;
193 pc = env->nip;
194 #elif defined(TARGET_MIPS)
195 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
196 cs_base = 0;
197 pc = env->PC;
198 #elif defined(TARGET_M68K)
199 flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
200 | (env->sr & SR_S) /* Bit 13 */
201 | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
202 cs_base = 0;
203 pc = env->pc;
204 #elif defined(TARGET_SH4)
205 flags = env->sr & (SR_MD | SR_RB);
206 cs_base = 0; /* XXXXX */
207 pc = env->pc;
208 #elif defined(TARGET_ALPHA)
209 flags = env->ps;
210 cs_base = 0;
211 pc = env->pc;
212 #else
213 #error unsupported CPU
214 #endif
215 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
216 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
217 tb->flags != flags, 0)) {
218 tb = tb_find_slow(pc, cs_base, flags);
219 /* Note: we do it here to avoid a gcc bug on Mac OS X when
220 doing it in tb_find_slow */
221 if (tb_invalidated_flag) {
222 /* as some TB could have been invalidated because
223 of memory exceptions while generating the code, we
224 must recompute the hash index here */
225 T0 = 0;
226 }
227 }
228 return tb;
229 }
230
231
232 /* main execution loop */
233
234 int cpu_exec(CPUState *env1)
235 {
236 #define DECLARE_HOST_REGS 1
237 #include "hostregs_helper.h"
238 #if defined(TARGET_SPARC)
239 #if defined(reg_REGWPTR)
240 uint32_t *saved_regwptr;
241 #endif
242 #endif
243 #if defined(__sparc__) && !defined(HOST_SOLARIS)
244 int saved_i7;
245 target_ulong tmp_T0;
246 #endif
247 int ret, interrupt_request;
248 void (*gen_func)(void);
249 TranslationBlock *tb;
250 uint8_t *tc_ptr;
251
252 if (cpu_halted(env1) == EXCP_HALTED)
253 return EXCP_HALTED;
254
255 cpu_single_env = env1;
256
257 /* first we save global registers */
258 #define SAVE_HOST_REGS 1
259 #include "hostregs_helper.h"
260 env = env1;
261 #if defined(__sparc__) && !defined(HOST_SOLARIS)
262 /* we also save i7 because longjmp may not restore it */
263 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
264 #endif
265
266 env_to_regs();
267 #if defined(TARGET_I386)
268 /* put eflags in CPU temporary format */
269 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
270 DF = 1 - (2 * ((env->eflags >> 10) & 1));
271 CC_OP = CC_OP_EFLAGS;
272 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
273 #elif defined(TARGET_SPARC)
274 #if defined(reg_REGWPTR)
275 saved_regwptr = REGWPTR;
276 #endif
277 #elif defined(TARGET_M68K)
278 env->cc_op = CC_OP_FLAGS;
279 env->cc_dest = env->sr & 0xf;
280 env->cc_x = (env->sr >> 4) & 1;
281 #elif defined(TARGET_ALPHA)
282 #elif defined(TARGET_ARM)
283 #elif defined(TARGET_PPC)
284 #elif defined(TARGET_MIPS)
285 #elif defined(TARGET_SH4)
286 /* XXXXX */
287 #else
288 #error unsupported target CPU
289 #endif
290 env->exception_index = -1;
291
292 /* prepare setjmp context for exception handling */
293 for(;;) {
294 if (setjmp(env->jmp_env) == 0) {
295 env->current_tb = NULL;
296 /* if an exception is pending, we execute it here */
297 if (env->exception_index >= 0) {
298 if (env->exception_index >= EXCP_INTERRUPT) {
299 /* exit request from the cpu execution loop */
300 ret = env->exception_index;
301 break;
302 } else if (env->user_mode_only) {
303 /* if user mode only, we simulate a fake exception
304 which will be handled outside the cpu execution
305 loop */
306 #if defined(TARGET_I386)
307 do_interrupt_user(env->exception_index,
308 env->exception_is_int,
309 env->error_code,
310 env->exception_next_eip);
311 #endif
312 ret = env->exception_index;
313 break;
314 } else {
315 #if defined(TARGET_I386)
316 /* simulate a real cpu exception. On i386, it can
317 trigger new exceptions, but we do not handle
318 double or triple faults yet. */
319 do_interrupt(env->exception_index,
320 env->exception_is_int,
321 env->error_code,
322 env->exception_next_eip, 0);
323 /* successfully delivered */
324 env->old_exception = -1;
325 #elif defined(TARGET_PPC)
326 do_interrupt(env);
327 #elif defined(TARGET_MIPS)
328 do_interrupt(env);
329 #elif defined(TARGET_SPARC)
330 do_interrupt(env->exception_index);
331 #elif defined(TARGET_ARM)
332 do_interrupt(env);
333 #elif defined(TARGET_SH4)
334 do_interrupt(env);
335 #elif defined(TARGET_ALPHA)
336 do_interrupt(env);
337 #elif defined(TARGET_M68K)
338 do_interrupt(0);
339 #endif
340 }
341 env->exception_index = -1;
342 }
343 #ifdef USE_KQEMU
344 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
345 int ret;
346 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
347 ret = kqemu_cpu_exec(env);
348 /* put eflags in CPU temporary format */
349 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
350 DF = 1 - (2 * ((env->eflags >> 10) & 1));
351 CC_OP = CC_OP_EFLAGS;
352 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
353 if (ret == 1) {
354 /* exception */
355 longjmp(env->jmp_env, 1);
356 } else if (ret == 2) {
357 /* softmmu execution needed */
358 } else {
359 if (env->interrupt_request != 0) {
360 /* hardware interrupt will be executed just after */
361 } else {
362 /* otherwise, we restart */
363 longjmp(env->jmp_env, 1);
364 }
365 }
366 }
367 #endif
368
369 T0 = 0; /* force lookup of first TB */
370 for(;;) {
371 #if defined(__sparc__) && !defined(HOST_SOLARIS)
372 /* g1 can be modified by some libc? functions */
373 tmp_T0 = T0;
374 #endif
375 interrupt_request = env->interrupt_request;
376 if (__builtin_expect(interrupt_request, 0)) {
377 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
378 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
379 env->exception_index = EXCP_DEBUG;
380 cpu_loop_exit();
381 }
382 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
383 defined(TARGET_PPC) || defined(TARGET_ALPHA)
384 if (interrupt_request & CPU_INTERRUPT_HALT) {
385 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
386 env->halted = 1;
387 env->exception_index = EXCP_HLT;
388 cpu_loop_exit();
389 }
390 #endif
391 #if defined(TARGET_I386)
392 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
393 !(env->hflags & HF_SMM_MASK)) {
394 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
395 do_smm_enter();
396 #if defined(__sparc__) && !defined(HOST_SOLARIS)
397 tmp_T0 = 0;
398 #else
399 T0 = 0;
400 #endif
401 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
402 (env->eflags & IF_MASK) &&
403 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
404 int intno;
405 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
406 intno = cpu_get_pic_interrupt(env);
407 if (loglevel & CPU_LOG_TB_IN_ASM) {
408 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
409 }
410 do_interrupt(intno, 0, 0, 0, 1);
411 /* ensure that no TB jump will be modified as
412 the program flow was changed */
413 #if defined(__sparc__) && !defined(HOST_SOLARIS)
414 tmp_T0 = 0;
415 #else
416 T0 = 0;
417 #endif
418 }
419 #elif defined(TARGET_PPC)
420 #if 0
421 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
422 cpu_ppc_reset(env);
423 }
424 #endif
425 if (interrupt_request & CPU_INTERRUPT_HARD) {
426 ppc_hw_interrupt(env);
427 if (env->pending_interrupts == 0)
428 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
429 #if defined(__sparc__) && !defined(HOST_SOLARIS)
430 tmp_T0 = 0;
431 #else
432 T0 = 0;
433 #endif
434 }
435 #elif defined(TARGET_MIPS)
436 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
437 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
438 (env->CP0_Status & (1 << CP0St_IE)) &&
439 !(env->CP0_Status & (1 << CP0St_EXL)) &&
440 !(env->CP0_Status & (1 << CP0St_ERL)) &&
441 !(env->hflags & MIPS_HFLAG_DM)) {
442 /* Raise it */
443 env->exception_index = EXCP_EXT_INTERRUPT;
444 env->error_code = 0;
445 do_interrupt(env);
446 #if defined(__sparc__) && !defined(HOST_SOLARIS)
447 tmp_T0 = 0;
448 #else
449 T0 = 0;
450 #endif
451 }
452 #elif defined(TARGET_SPARC)
453 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
454 (env->psret != 0)) {
455 int pil = env->interrupt_index & 15;
456 int type = env->interrupt_index & 0xf0;
457
458 if (((type == TT_EXTINT) &&
459 (pil == 15 || pil > env->psrpil)) ||
460 type != TT_EXTINT) {
461 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
462 do_interrupt(env->interrupt_index);
463 env->interrupt_index = 0;
464 #if defined(__sparc__) && !defined(HOST_SOLARIS)
465 tmp_T0 = 0;
466 #else
467 T0 = 0;
468 #endif
469 }
470 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
471 //do_interrupt(0, 0, 0, 0, 0);
472 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
473 }
474 #elif defined(TARGET_ARM)
475 if (interrupt_request & CPU_INTERRUPT_FIQ
476 && !(env->uncached_cpsr & CPSR_F)) {
477 env->exception_index = EXCP_FIQ;
478 do_interrupt(env);
479 }
480 if (interrupt_request & CPU_INTERRUPT_HARD
481 && !(env->uncached_cpsr & CPSR_I)) {
482 env->exception_index = EXCP_IRQ;
483 do_interrupt(env);
484 }
485 #elif defined(TARGET_SH4)
486 /* XXXXX */
487 #elif defined(TARGET_ALPHA)
488 if (interrupt_request & CPU_INTERRUPT_HARD) {
489 do_interrupt(env);
490 }
491 #elif defined(TARGET_M68K)
492 if (interrupt_request & CPU_INTERRUPT_HARD
493 && ((env->sr & SR_I) >> SR_I_SHIFT)
494 < env->pending_level) {
495 /* Real hardware gets the interrupt vector via an
496 IACK cycle at this point. Current emulated
497 hardware doesn't rely on this, so we
498 provide/save the vector when the interrupt is
499 first signalled. */
500 env->exception_index = env->pending_vector;
501 do_interrupt(1);
502 }
503 #endif
504 /* Don't use the cached interupt_request value,
505 do_interrupt may have updated the EXITTB flag. */
506 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
507 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
508 /* ensure that no TB jump will be modified as
509 the program flow was changed */
510 #if defined(__sparc__) && !defined(HOST_SOLARIS)
511 tmp_T0 = 0;
512 #else
513 T0 = 0;
514 #endif
515 }
516 if (interrupt_request & CPU_INTERRUPT_EXIT) {
517 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
518 env->exception_index = EXCP_INTERRUPT;
519 cpu_loop_exit();
520 }
521 }
522 #ifdef DEBUG_EXEC
523 if ((loglevel & CPU_LOG_TB_CPU)) {
524 /* restore flags in standard format */
525 regs_to_env();
526 #if defined(TARGET_I386)
527 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
528 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
529 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
530 #elif defined(TARGET_ARM)
531 cpu_dump_state(env, logfile, fprintf, 0);
532 #elif defined(TARGET_SPARC)
533 REGWPTR = env->regbase + (env->cwp * 16);
534 env->regwptr = REGWPTR;
535 cpu_dump_state(env, logfile, fprintf, 0);
536 #elif defined(TARGET_PPC)
537 cpu_dump_state(env, logfile, fprintf, 0);
538 #elif defined(TARGET_M68K)
539 cpu_m68k_flush_flags(env, env->cc_op);
540 env->cc_op = CC_OP_FLAGS;
541 env->sr = (env->sr & 0xffe0)
542 | env->cc_dest | (env->cc_x << 4);
543 cpu_dump_state(env, logfile, fprintf, 0);
544 #elif defined(TARGET_MIPS)
545 cpu_dump_state(env, logfile, fprintf, 0);
546 #elif defined(TARGET_SH4)
547 cpu_dump_state(env, logfile, fprintf, 0);
548 #elif defined(TARGET_ALPHA)
549 cpu_dump_state(env, logfile, fprintf, 0);
550 #else
551 #error unsupported target CPU
552 #endif
553 }
554 #endif
555 tb = tb_find_fast();
556 #ifdef DEBUG_EXEC
557 if ((loglevel & CPU_LOG_EXEC)) {
558 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
559 (long)tb->tc_ptr, tb->pc,
560 lookup_symbol(tb->pc));
561 }
562 #endif
563 #if defined(__sparc__) && !defined(HOST_SOLARIS)
564 T0 = tmp_T0;
565 #endif
566 /* see if we can patch the calling TB. When the TB
567 spans two pages, we cannot safely do a direct
568 jump. */
569 {
570 if (T0 != 0 &&
571 #if USE_KQEMU
572 (env->kqemu_enabled != 2) &&
573 #endif
574 tb->page_addr[1] == -1
575 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
576 && (tb->cflags & CF_CODE_COPY) ==
577 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
578 #endif
579 ) {
580 spin_lock(&tb_lock);
581 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
582 #if defined(USE_CODE_COPY)
583 /* propagates the FP use info */
584 ((TranslationBlock *)(T0 & ~3))->cflags |=
585 (tb->cflags & CF_FP_USED);
586 #endif
587 spin_unlock(&tb_lock);
588 }
589 }
590 tc_ptr = tb->tc_ptr;
591 env->current_tb = tb;
592 /* execute the generated code */
593 gen_func = (void *)tc_ptr;
594 #if defined(__sparc__)
595 __asm__ __volatile__("call %0\n\t"
596 "mov %%o7,%%i0"
597 : /* no outputs */
598 : "r" (gen_func)
599 : "i0", "i1", "i2", "i3", "i4", "i5",
600 "o0", "o1", "o2", "o3", "o4", "o5",
601 "l0", "l1", "l2", "l3", "l4", "l5",
602 "l6", "l7");
603 #elif defined(__arm__)
604 asm volatile ("mov pc, %0\n\t"
605 ".global exec_loop\n\t"
606 "exec_loop:\n\t"
607 : /* no outputs */
608 : "r" (gen_func)
609 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
610 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
611 {
612 if (!(tb->cflags & CF_CODE_COPY)) {
613 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
614 save_native_fp_state(env);
615 }
616 gen_func();
617 } else {
618 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
619 restore_native_fp_state(env);
620 }
621 /* we work with native eflags */
622 CC_SRC = cc_table[CC_OP].compute_all();
623 CC_OP = CC_OP_EFLAGS;
624 asm(".globl exec_loop\n"
625 "\n"
626 "debug1:\n"
627 " pushl %%ebp\n"
628 " fs movl %10, %9\n"
629 " fs movl %11, %%eax\n"
630 " andl $0x400, %%eax\n"
631 " fs orl %8, %%eax\n"
632 " pushl %%eax\n"
633 " popf\n"
634 " fs movl %%esp, %12\n"
635 " fs movl %0, %%eax\n"
636 " fs movl %1, %%ecx\n"
637 " fs movl %2, %%edx\n"
638 " fs movl %3, %%ebx\n"
639 " fs movl %4, %%esp\n"
640 " fs movl %5, %%ebp\n"
641 " fs movl %6, %%esi\n"
642 " fs movl %7, %%edi\n"
643 " fs jmp *%9\n"
644 "exec_loop:\n"
645 " fs movl %%esp, %4\n"
646 " fs movl %12, %%esp\n"
647 " fs movl %%eax, %0\n"
648 " fs movl %%ecx, %1\n"
649 " fs movl %%edx, %2\n"
650 " fs movl %%ebx, %3\n"
651 " fs movl %%ebp, %5\n"
652 " fs movl %%esi, %6\n"
653 " fs movl %%edi, %7\n"
654 " pushf\n"
655 " popl %%eax\n"
656 " movl %%eax, %%ecx\n"
657 " andl $0x400, %%ecx\n"
658 " shrl $9, %%ecx\n"
659 " andl $0x8d5, %%eax\n"
660 " fs movl %%eax, %8\n"
661 " movl $1, %%eax\n"
662 " subl %%ecx, %%eax\n"
663 " fs movl %%eax, %11\n"
664 " fs movl %9, %%ebx\n" /* get T0 value */
665 " popl %%ebp\n"
666 :
667 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
668 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
669 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
670 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
671 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
672 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
673 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
674 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
675 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
676 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
677 "a" (gen_func),
678 "m" (*(uint8_t *)offsetof(CPUState, df)),
679 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
680 : "%ecx", "%edx"
681 );
682 }
683 }
684 #elif defined(__ia64)
685 struct fptr {
686 void *ip;
687 void *gp;
688 } fp;
689
690 fp.ip = tc_ptr;
691 fp.gp = code_gen_buffer + 2 * (1 << 20);
692 (*(void (*)(void)) &fp)();
693 #else
694 gen_func();
695 #endif
696 env->current_tb = NULL;
697 /* reset soft MMU for next block (it can currently
698 only be set by a memory fault) */
699 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
700 if (env->hflags & HF_SOFTMMU_MASK) {
701 env->hflags &= ~HF_SOFTMMU_MASK;
702 /* do not allow linking to another block */
703 T0 = 0;
704 }
705 #endif
706 #if defined(USE_KQEMU)
707 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
708 if (kqemu_is_ok(env) &&
709 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
710 cpu_loop_exit();
711 }
712 #endif
713 } /* for(;;) */
714 } else {
715 env_to_regs();
716 }
717 } /* for(;;) */
718
719
720 #if defined(TARGET_I386)
721 #if defined(USE_CODE_COPY)
722 if (env->native_fp_regs) {
723 save_native_fp_state(env);
724 }
725 #endif
726 /* restore flags in standard format */
727 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
728 #elif defined(TARGET_ARM)
729 /* XXX: Save/restore host fpu exception state?. */
730 #elif defined(TARGET_SPARC)
731 #if defined(reg_REGWPTR)
732 REGWPTR = saved_regwptr;
733 #endif
734 #elif defined(TARGET_PPC)
735 #elif defined(TARGET_M68K)
736 cpu_m68k_flush_flags(env, env->cc_op);
737 env->cc_op = CC_OP_FLAGS;
738 env->sr = (env->sr & 0xffe0)
739 | env->cc_dest | (env->cc_x << 4);
740 #elif defined(TARGET_MIPS)
741 #elif defined(TARGET_SH4)
742 #elif defined(TARGET_ALPHA)
743 /* XXXXX */
744 #else
745 #error unsupported target CPU
746 #endif
747
748 /* restore global registers */
749 #if defined(__sparc__) && !defined(HOST_SOLARIS)
750 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
751 #endif
752 #include "hostregs_helper.h"
753
754 /* fail safe : never use cpu_single_env outside cpu_exec() */
755 cpu_single_env = NULL;
756 return ret;
757 }
758
759 /* must only be called from the generated code as an exception can be
760 generated */
761 void tb_invalidate_page_range(target_ulong start, target_ulong end)
762 {
763 /* XXX: cannot enable it yet because it yields to MMU exception
764 where NIP != read address on PowerPC */
765 #if 0
766 target_ulong phys_addr;
767 phys_addr = get_phys_addr_code(env, start);
768 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
769 #endif
770 }
771
772 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
773
774 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
775 {
776 CPUX86State *saved_env;
777
778 saved_env = env;
779 env = s;
780 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
781 selector &= 0xffff;
782 cpu_x86_load_seg_cache(env, seg_reg, selector,
783 (selector << 4), 0xffff, 0);
784 } else {
785 load_seg(seg_reg, selector);
786 }
787 env = saved_env;
788 }
789
790 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
791 {
792 CPUX86State *saved_env;
793
794 saved_env = env;
795 env = s;
796
797 helper_fsave((target_ulong)ptr, data32);
798
799 env = saved_env;
800 }
801
802 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
803 {
804 CPUX86State *saved_env;
805
806 saved_env = env;
807 env = s;
808
809 helper_frstor((target_ulong)ptr, data32);
810
811 env = saved_env;
812 }
813
814 #endif /* TARGET_I386 */
815
816 #if !defined(CONFIG_SOFTMMU)
817
818 #if defined(TARGET_I386)
819
820 /* 'pc' is the host PC at which the exception was raised. 'address' is
821 the effective address of the memory exception. 'is_write' is 1 if a
822 write caused the exception and otherwise 0'. 'old_set' is the
823 signal set which should be restored */
824 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
825 int is_write, sigset_t *old_set,
826 void *puc)
827 {
828 TranslationBlock *tb;
829 int ret;
830
831 if (cpu_single_env)
832 env = cpu_single_env; /* XXX: find a correct solution for multithread */
833 #if defined(DEBUG_SIGNAL)
834 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
835 pc, address, is_write, *(unsigned long *)old_set);
836 #endif
837 /* XXX: locking issue */
838 if (is_write && page_unprotect(h2g(address), pc, puc)) {
839 return 1;
840 }
841
842 /* see if it is an MMU fault */
843 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
844 ((env->hflags & HF_CPL_MASK) == 3), 0);
845 if (ret < 0)
846 return 0; /* not an MMU fault */
847 if (ret == 0)
848 return 1; /* the MMU fault was handled without causing real CPU fault */
849 /* now we have a real cpu fault */
850 tb = tb_find_pc(pc);
851 if (tb) {
852 /* the PC is inside the translated code. It means that we have
853 a virtual CPU fault */
854 cpu_restore_state(tb, env, pc, puc);
855 }
856 if (ret == 1) {
857 #if 0
858 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
859 env->eip, env->cr[2], env->error_code);
860 #endif
861 /* we restore the process signal mask as the sigreturn should
862 do it (XXX: use sigsetjmp) */
863 sigprocmask(SIG_SETMASK, old_set, NULL);
864 raise_exception_err(env->exception_index, env->error_code);
865 } else {
866 /* activate soft MMU for this block */
867 env->hflags |= HF_SOFTMMU_MASK;
868 cpu_resume_from_signal(env, puc);
869 }
870 /* never comes here */
871 return 1;
872 }
873
874 #elif defined(TARGET_ARM)
875 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
876 int is_write, sigset_t *old_set,
877 void *puc)
878 {
879 TranslationBlock *tb;
880 int ret;
881
882 if (cpu_single_env)
883 env = cpu_single_env; /* XXX: find a correct solution for multithread */
884 #if defined(DEBUG_SIGNAL)
885 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
886 pc, address, is_write, *(unsigned long *)old_set);
887 #endif
888 /* XXX: locking issue */
889 if (is_write && page_unprotect(h2g(address), pc, puc)) {
890 return 1;
891 }
892 /* see if it is an MMU fault */
893 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
894 if (ret < 0)
895 return 0; /* not an MMU fault */
896 if (ret == 0)
897 return 1; /* the MMU fault was handled without causing real CPU fault */
898 /* now we have a real cpu fault */
899 tb = tb_find_pc(pc);
900 if (tb) {
901 /* the PC is inside the translated code. It means that we have
902 a virtual CPU fault */
903 cpu_restore_state(tb, env, pc, puc);
904 }
905 /* we restore the process signal mask as the sigreturn should
906 do it (XXX: use sigsetjmp) */
907 sigprocmask(SIG_SETMASK, old_set, NULL);
908 cpu_loop_exit();
909 }
910 #elif defined(TARGET_SPARC)
911 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
912 int is_write, sigset_t *old_set,
913 void *puc)
914 {
915 TranslationBlock *tb;
916 int ret;
917
918 if (cpu_single_env)
919 env = cpu_single_env; /* XXX: find a correct solution for multithread */
920 #if defined(DEBUG_SIGNAL)
921 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
922 pc, address, is_write, *(unsigned long *)old_set);
923 #endif
924 /* XXX: locking issue */
925 if (is_write && page_unprotect(h2g(address), pc, puc)) {
926 return 1;
927 }
928 /* see if it is an MMU fault */
929 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
930 if (ret < 0)
931 return 0; /* not an MMU fault */
932 if (ret == 0)
933 return 1; /* the MMU fault was handled without causing real CPU fault */
934 /* now we have a real cpu fault */
935 tb = tb_find_pc(pc);
936 if (tb) {
937 /* the PC is inside the translated code. It means that we have
938 a virtual CPU fault */
939 cpu_restore_state(tb, env, pc, puc);
940 }
941 /* we restore the process signal mask as the sigreturn should
942 do it (XXX: use sigsetjmp) */
943 sigprocmask(SIG_SETMASK, old_set, NULL);
944 cpu_loop_exit();
945 }
946 #elif defined (TARGET_PPC)
947 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
948 int is_write, sigset_t *old_set,
949 void *puc)
950 {
951 TranslationBlock *tb;
952 int ret;
953
954 if (cpu_single_env)
955 env = cpu_single_env; /* XXX: find a correct solution for multithread */
956 #if defined(DEBUG_SIGNAL)
957 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
958 pc, address, is_write, *(unsigned long *)old_set);
959 #endif
960 /* XXX: locking issue */
961 if (is_write && page_unprotect(h2g(address), pc, puc)) {
962 return 1;
963 }
964
965 /* see if it is an MMU fault */
966 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
967 if (ret < 0)
968 return 0; /* not an MMU fault */
969 if (ret == 0)
970 return 1; /* the MMU fault was handled without causing real CPU fault */
971
972 /* now we have a real cpu fault */
973 tb = tb_find_pc(pc);
974 if (tb) {
975 /* the PC is inside the translated code. It means that we have
976 a virtual CPU fault */
977 cpu_restore_state(tb, env, pc, puc);
978 }
979 if (ret == 1) {
980 #if 0
981 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
982 env->nip, env->error_code, tb);
983 #endif
984 /* we restore the process signal mask as the sigreturn should
985 do it (XXX: use sigsetjmp) */
986 sigprocmask(SIG_SETMASK, old_set, NULL);
987 do_raise_exception_err(env->exception_index, env->error_code);
988 } else {
989 /* activate soft MMU for this block */
990 cpu_resume_from_signal(env, puc);
991 }
992 /* never comes here */
993 return 1;
994 }
995
996 #elif defined(TARGET_M68K)
997 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
998 int is_write, sigset_t *old_set,
999 void *puc)
1000 {
1001 TranslationBlock *tb;
1002 int ret;
1003
1004 if (cpu_single_env)
1005 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1006 #if defined(DEBUG_SIGNAL)
1007 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1008 pc, address, is_write, *(unsigned long *)old_set);
1009 #endif
1010 /* XXX: locking issue */
1011 if (is_write && page_unprotect(address, pc, puc)) {
1012 return 1;
1013 }
1014 /* see if it is an MMU fault */
1015 ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
1016 if (ret < 0)
1017 return 0; /* not an MMU fault */
1018 if (ret == 0)
1019 return 1; /* the MMU fault was handled without causing real CPU fault */
1020 /* now we have a real cpu fault */
1021 tb = tb_find_pc(pc);
1022 if (tb) {
1023 /* the PC is inside the translated code. It means that we have
1024 a virtual CPU fault */
1025 cpu_restore_state(tb, env, pc, puc);
1026 }
1027 /* we restore the process signal mask as the sigreturn should
1028 do it (XXX: use sigsetjmp) */
1029 sigprocmask(SIG_SETMASK, old_set, NULL);
1030 cpu_loop_exit();
1031 /* never comes here */
1032 return 1;
1033 }
1034
1035 #elif defined (TARGET_MIPS)
1036 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1037 int is_write, sigset_t *old_set,
1038 void *puc)
1039 {
1040 TranslationBlock *tb;
1041 int ret;
1042
1043 if (cpu_single_env)
1044 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1045 #if defined(DEBUG_SIGNAL)
1046 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1047 pc, address, is_write, *(unsigned long *)old_set);
1048 #endif
1049 /* XXX: locking issue */
1050 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1051 return 1;
1052 }
1053
1054 /* see if it is an MMU fault */
1055 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1056 if (ret < 0)
1057 return 0; /* not an MMU fault */
1058 if (ret == 0)
1059 return 1; /* the MMU fault was handled without causing real CPU fault */
1060
1061 /* now we have a real cpu fault */
1062 tb = tb_find_pc(pc);
1063 if (tb) {
1064 /* the PC is inside the translated code. It means that we have
1065 a virtual CPU fault */
1066 cpu_restore_state(tb, env, pc, puc);
1067 }
1068 if (ret == 1) {
1069 #if 0
1070 printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1071 env->PC, env->error_code, tb);
1072 #endif
1073 /* we restore the process signal mask as the sigreturn should
1074 do it (XXX: use sigsetjmp) */
1075 sigprocmask(SIG_SETMASK, old_set, NULL);
1076 do_raise_exception_err(env->exception_index, env->error_code);
1077 } else {
1078 /* activate soft MMU for this block */
1079 cpu_resume_from_signal(env, puc);
1080 }
1081 /* never comes here */
1082 return 1;
1083 }
1084
1085 #elif defined (TARGET_SH4)
1086 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1087 int is_write, sigset_t *old_set,
1088 void *puc)
1089 {
1090 TranslationBlock *tb;
1091 int ret;
1092
1093 if (cpu_single_env)
1094 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1095 #if defined(DEBUG_SIGNAL)
1096 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1097 pc, address, is_write, *(unsigned long *)old_set);
1098 #endif
1099 /* XXX: locking issue */
1100 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1101 return 1;
1102 }
1103
1104 /* see if it is an MMU fault */
1105 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1106 if (ret < 0)
1107 return 0; /* not an MMU fault */
1108 if (ret == 0)
1109 return 1; /* the MMU fault was handled without causing real CPU fault */
1110
1111 /* now we have a real cpu fault */
1112 tb = tb_find_pc(pc);
1113 if (tb) {
1114 /* the PC is inside the translated code. It means that we have
1115 a virtual CPU fault */
1116 cpu_restore_state(tb, env, pc, puc);
1117 }
1118 #if 0
1119 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1120 env->nip, env->error_code, tb);
1121 #endif
1122 /* we restore the process signal mask as the sigreturn should
1123 do it (XXX: use sigsetjmp) */
1124 sigprocmask(SIG_SETMASK, old_set, NULL);
1125 cpu_loop_exit();
1126 /* never comes here */
1127 return 1;
1128 }
1129
1130 #elif defined (TARGET_ALPHA)
1131 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1132 int is_write, sigset_t *old_set,
1133 void *puc)
1134 {
1135 TranslationBlock *tb;
1136 int ret;
1137
1138 if (cpu_single_env)
1139 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1140 #if defined(DEBUG_SIGNAL)
1141 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1142 pc, address, is_write, *(unsigned long *)old_set);
1143 #endif
1144 /* XXX: locking issue */
1145 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1146 return 1;
1147 }
1148
1149 /* see if it is an MMU fault */
1150 ret = cpu_alpha_handle_mmu_fault(env, address, is_write, 1, 0);
1151 if (ret < 0)
1152 return 0; /* not an MMU fault */
1153 if (ret == 0)
1154 return 1; /* the MMU fault was handled without causing real CPU fault */
1155
1156 /* now we have a real cpu fault */
1157 tb = tb_find_pc(pc);
1158 if (tb) {
1159 /* the PC is inside the translated code. It means that we have
1160 a virtual CPU fault */
1161 cpu_restore_state(tb, env, pc, puc);
1162 }
1163 #if 0
1164 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1165 env->nip, env->error_code, tb);
1166 #endif
1167 /* we restore the process signal mask as the sigreturn should
1168 do it (XXX: use sigsetjmp) */
1169 sigprocmask(SIG_SETMASK, old_set, NULL);
1170 cpu_loop_exit();
1171 /* never comes here */
1172 return 1;
1173 }
1174 #else
1175 #error unsupported target CPU
1176 #endif
1177
1178 #if defined(__i386__)
1179
1180 #if defined(__APPLE__)
1181 # include <sys/ucontext.h>
1182
1183 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1184 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1185 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1186 #else
1187 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1188 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1189 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1190 #endif
1191
1192 #if defined(USE_CODE_COPY)
1193 static void cpu_send_trap(unsigned long pc, int trap,
1194 struct ucontext *uc)
1195 {
1196 TranslationBlock *tb;
1197
1198 if (cpu_single_env)
1199 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1200 /* now we have a real cpu fault */
1201 tb = tb_find_pc(pc);
1202 if (tb) {
1203 /* the PC is inside the translated code. It means that we have
1204 a virtual CPU fault */
1205 cpu_restore_state(tb, env, pc, uc);
1206 }
1207 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1208 raise_exception_err(trap, env->error_code);
1209 }
1210 #endif
1211
1212 int cpu_signal_handler(int host_signum, void *pinfo,
1213 void *puc)
1214 {
1215 siginfo_t *info = pinfo;
1216 struct ucontext *uc = puc;
1217 unsigned long pc;
1218 int trapno;
1219
1220 #ifndef REG_EIP
1221 /* for glibc 2.1 */
1222 #define REG_EIP EIP
1223 #define REG_ERR ERR
1224 #define REG_TRAPNO TRAPNO
1225 #endif
1226 pc = EIP_sig(uc);
1227 trapno = TRAP_sig(uc);
1228 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1229 if (trapno == 0x00 || trapno == 0x05) {
1230 /* send division by zero or bound exception */
1231 cpu_send_trap(pc, trapno, uc);
1232 return 1;
1233 } else
1234 #endif
1235 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1236 trapno == 0xe ?
1237 (ERROR_sig(uc) >> 1) & 1 : 0,
1238 &uc->uc_sigmask, puc);
1239 }
1240
1241 #elif defined(__x86_64__)
1242
1243 int cpu_signal_handler(int host_signum, void *pinfo,
1244 void *puc)
1245 {
1246 siginfo_t *info = pinfo;
1247 struct ucontext *uc = puc;
1248 unsigned long pc;
1249
1250 pc = uc->uc_mcontext.gregs[REG_RIP];
1251 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1252 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1253 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1254 &uc->uc_sigmask, puc);
1255 }
1256
1257 #elif defined(__powerpc__)
1258
1259 /***********************************************************************
1260 * signal context platform-specific definitions
1261 * From Wine
1262 */
1263 #ifdef linux
1264 /* All Registers access - only for local access */
1265 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1266 /* Gpr Registers access */
1267 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1268 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1269 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1270 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1271 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1272 # define LR_sig(context) REG_sig(link, context) /* Link register */
1273 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1274 /* Float Registers access */
1275 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1276 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1277 /* Exception Registers access */
1278 # define DAR_sig(context) REG_sig(dar, context)
1279 # define DSISR_sig(context) REG_sig(dsisr, context)
1280 # define TRAP_sig(context) REG_sig(trap, context)
1281 #endif /* linux */
1282
1283 #ifdef __APPLE__
1284 # include <sys/ucontext.h>
1285 typedef struct ucontext SIGCONTEXT;
1286 /* All Registers access - only for local access */
1287 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1288 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1289 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1290 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1291 /* Gpr Registers access */
1292 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1293 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1294 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1295 # define CTR_sig(context) REG_sig(ctr, context)
1296 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1297 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1298 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1299 /* Float Registers access */
1300 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1301 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1302 /* Exception Registers access */
1303 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1304 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1305 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1306 #endif /* __APPLE__ */
1307
1308 int cpu_signal_handler(int host_signum, void *pinfo,
1309 void *puc)
1310 {
1311 siginfo_t *info = pinfo;
1312 struct ucontext *uc = puc;
1313 unsigned long pc;
1314 int is_write;
1315
1316 pc = IAR_sig(uc);
1317 is_write = 0;
1318 #if 0
1319 /* ppc 4xx case */
1320 if (DSISR_sig(uc) & 0x00800000)
1321 is_write = 1;
1322 #else
1323 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1324 is_write = 1;
1325 #endif
1326 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1327 is_write, &uc->uc_sigmask, puc);
1328 }
1329
1330 #elif defined(__alpha__)
1331
1332 int cpu_signal_handler(int host_signum, void *pinfo,
1333 void *puc)
1334 {
1335 siginfo_t *info = pinfo;
1336 struct ucontext *uc = puc;
1337 uint32_t *pc = uc->uc_mcontext.sc_pc;
1338 uint32_t insn = *pc;
1339 int is_write = 0;
1340
1341 /* XXX: need kernel patch to get write flag faster */
1342 switch (insn >> 26) {
1343 case 0x0d: // stw
1344 case 0x0e: // stb
1345 case 0x0f: // stq_u
1346 case 0x24: // stf
1347 case 0x25: // stg
1348 case 0x26: // sts
1349 case 0x27: // stt
1350 case 0x2c: // stl
1351 case 0x2d: // stq
1352 case 0x2e: // stl_c
1353 case 0x2f: // stq_c
1354 is_write = 1;
1355 }
1356
1357 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1358 is_write, &uc->uc_sigmask, puc);
1359 }
1360 #elif defined(__sparc__)
1361
1362 int cpu_signal_handler(int host_signum, void *pinfo,
1363 void *puc)
1364 {
1365 siginfo_t *info = pinfo;
1366 uint32_t *regs = (uint32_t *)(info + 1);
1367 void *sigmask = (regs + 20);
1368 unsigned long pc;
1369 int is_write;
1370 uint32_t insn;
1371
1372 /* XXX: is there a standard glibc define ? */
1373 pc = regs[1];
1374 /* XXX: need kernel patch to get write flag faster */
1375 is_write = 0;
1376 insn = *(uint32_t *)pc;
1377 if ((insn >> 30) == 3) {
1378 switch((insn >> 19) & 0x3f) {
1379 case 0x05: // stb
1380 case 0x06: // sth
1381 case 0x04: // st
1382 case 0x07: // std
1383 case 0x24: // stf
1384 case 0x27: // stdf
1385 case 0x25: // stfsr
1386 is_write = 1;
1387 break;
1388 }
1389 }
1390 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1391 is_write, sigmask, NULL);
1392 }
1393
1394 #elif defined(__arm__)
1395
1396 int cpu_signal_handler(int host_signum, void *pinfo,
1397 void *puc)
1398 {
1399 siginfo_t *info = pinfo;
1400 struct ucontext *uc = puc;
1401 unsigned long pc;
1402 int is_write;
1403
1404 pc = uc->uc_mcontext.gregs[R15];
1405 /* XXX: compute is_write */
1406 is_write = 0;
1407 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1408 is_write,
1409 &uc->uc_sigmask, puc);
1410 }
1411
1412 #elif defined(__mc68000)
1413
1414 int cpu_signal_handler(int host_signum, void *pinfo,
1415 void *puc)
1416 {
1417 siginfo_t *info = pinfo;
1418 struct ucontext *uc = puc;
1419 unsigned long pc;
1420 int is_write;
1421
1422 pc = uc->uc_mcontext.gregs[16];
1423 /* XXX: compute is_write */
1424 is_write = 0;
1425 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1426 is_write,
1427 &uc->uc_sigmask, puc);
1428 }
1429
1430 #elif defined(__ia64)
1431
1432 #ifndef __ISR_VALID
1433 /* This ought to be in <bits/siginfo.h>... */
1434 # define __ISR_VALID 1
1435 #endif
1436
1437 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1438 {
1439 siginfo_t *info = pinfo;
1440 struct ucontext *uc = puc;
1441 unsigned long ip;
1442 int is_write = 0;
1443
1444 ip = uc->uc_mcontext.sc_ip;
1445 switch (host_signum) {
1446 case SIGILL:
1447 case SIGFPE:
1448 case SIGSEGV:
1449 case SIGBUS:
1450 case SIGTRAP:
1451 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1452 /* ISR.W (write-access) is bit 33: */
1453 is_write = (info->si_isr >> 33) & 1;
1454 break;
1455
1456 default:
1457 break;
1458 }
1459 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1460 is_write,
1461 &uc->uc_sigmask, puc);
1462 }
1463
1464 #elif defined(__s390__)
1465
1466 int cpu_signal_handler(int host_signum, void *pinfo,
1467 void *puc)
1468 {
1469 siginfo_t *info = pinfo;
1470 struct ucontext *uc = puc;
1471 unsigned long pc;
1472 int is_write;
1473
1474 pc = uc->uc_mcontext.psw.addr;
1475 /* XXX: compute is_write */
1476 is_write = 0;
1477 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1478 is_write, &uc->uc_sigmask, puc);
1479 }
1480
1481 #elif defined(__mips__)
1482
1483 int cpu_signal_handler(int host_signum, void *pinfo,
1484 void *puc)
1485 {
1486 siginfo_t *info = pinfo;
1487 struct ucontext *uc = puc;
1488 greg_t pc = uc->uc_mcontext.pc;
1489 int is_write;
1490
1491 /* XXX: compute is_write */
1492 is_write = 0;
1493 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1494 is_write, &uc->uc_sigmask, puc);
1495 }
1496
1497 #else
1498
1499 #error host CPU specific signal handler needed
1500
1501 #endif
1502
1503 #endif /* !defined(CONFIG_SOFTMMU) */
Samsung s3c2440 and arm920t support for the mini2440 dev board