hw/sparc32_dma.c

   1 /*
   2  * QEMU Sparc32 DMA controller emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug DMA */
  27 //#define DEBUG_DMA
  28
  29 /*
  30  * This is the DMA controller part of chip STP2000 (Master I/O), also
  31  * produced as NCR89C100. See
  32  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  33  * and
  34  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
  35  */
  36
  37 #ifdef DEBUG_DMA
  38 #define DPRINTF(fmt, args...) \
  39 do { printf("DMA: " fmt , ##args); } while (0)
  40 #define pic_set_irq_new(ctl, irq, level)                                \
  41     do { printf("DMA: set_irq(%d): %d\n", (irq), (level));              \
  42         pic_set_irq_new((ctl), (irq),(level));} while (0)
  43 #else
  44 #define DPRINTF(fmt, args...)
  45 #endif
  46
  47 #define DMA_REGS 8
  48 #define DMA_MAXADDR (DMA_REGS * 4 - 1)
  49
  50 #define DMA_VER 0xa0000000
  51 #define DMA_INTR 1
  52 #define DMA_INTREN 0x10
  53 #define DMA_WRITE_MEM 0x100
  54 #define DMA_LOADED 0x04000000
  55 #define DMA_RESET 0x80
  56
  57 typedef struct DMAState DMAState;
  58
  59 struct DMAState {
  60     uint32_t dmaregs[DMA_REGS];
  61     int espirq, leirq;
  62     void *iommu, *esp_opaque, *lance_opaque, *intctl;
  63 };
  64
  65 void ledma_set_irq(void *opaque, int isr)
  66 {
  67     DMAState *s = opaque;
  68
  69     pic_set_irq_new(s->intctl, s->leirq, isr);
  70 }
  71
  72 /* Note: on sparc, the lance 16 bit bus is swapped */
  73 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
  74                        uint8_t *buf, int len, int do_bswap)
  75 {
  76     DMAState *s = opaque;
  77     int i;
  78
  79     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
  80             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  81     addr |= s->dmaregs[7];
  82     if (do_bswap) {
  83         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  84     } else {
  85         addr &= ~1;
  86         len &= ~1;
  87         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  88         for(i = 0; i < len; i += 2) {
  89             bswap16s((uint16_t *)(buf + i));
  90         }
  91     }
  92 }
  93
  94 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
  95                         uint8_t *buf, int len, int do_bswap)
  96 {
  97     DMAState *s = opaque;
  98     int l, i;
  99     uint16_t tmp_buf[32];
 100
 101     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
 102             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 103     addr |= s->dmaregs[7];
 104     if (do_bswap) {
 105         sparc_iommu_memory_write(s->iommu, addr, buf, len);
 106     } else {
 107         addr &= ~1;
 108         len &= ~1;
 109         while (len > 0) {
 110             l = len;
 111             if (l > sizeof(tmp_buf))
 112                 l = sizeof(tmp_buf);
 113             for(i = 0; i < l; i += 2) {
 114                 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
 115             }
 116             sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
 117             len -= l;
 118             buf += l;
 119             addr += l;
 120         }
 121     }
 122 }
 123
 124 void espdma_raise_irq(void *opaque)
 125 {
 126     DMAState *s = opaque;
 127
 128     s->dmaregs[0] |= DMA_INTR;
 129     pic_set_irq_new(s->intctl, s->espirq, 1);
 130 }
 131
 132 void espdma_clear_irq(void *opaque)
 133 {
 134     DMAState *s = opaque;
 135
 136     s->dmaregs[0] &= ~DMA_INTR;
 137     pic_set_irq_new(s->intctl, s->espirq, 0);
 138 }
 139
 140 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
 141 {
 142     DMAState *s = opaque;
 143
 144     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
 145             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 146     sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
 147     s->dmaregs[0] |= DMA_INTR;
 148     s->dmaregs[1] += len;
 149 }
 150
 151 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
 152 {
 153     DMAState *s = opaque;
 154
 155     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
 156             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 157     sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
 158     s->dmaregs[0] |= DMA_INTR;
 159     s->dmaregs[1] += len;
 160 }
 161
 162 static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
 163 {
 164     DMAState *s = opaque;
 165     uint32_t saddr;
 166
 167     saddr = (addr & DMA_MAXADDR) >> 2;
 168     DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->dmaregs[saddr]);
 169
 170     return s->dmaregs[saddr];
 171 }
 172
 173 static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 174 {
 175     DMAState *s = opaque;
 176     uint32_t saddr;
 177
 178     saddr = (addr & DMA_MAXADDR) >> 2;
 179     DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->dmaregs[saddr], val);
 180     switch (saddr) {
 181     case 0:
 182         if (!(val & DMA_INTREN))
 183             pic_set_irq_new(s->intctl, s->espirq, 0);
 184         if (val & DMA_RESET) {
 185             esp_reset(s->esp_opaque);
 186         } else if (val & 0x40) {
 187             val &= ~0x40;
 188         } else if (val == 0)
 189             val = 0x40;
 190         val &= 0x0fffffff;
 191         val |= DMA_VER;
 192         break;
 193     case 1:
 194         s->dmaregs[0] |= DMA_LOADED;
 195         break;
 196     case 4:
 197         if (!(val & DMA_INTREN))
 198             pic_set_irq_new(s->intctl, s->leirq, 0);
 199         if (val & DMA_RESET)
 200             pcnet_h_reset(s->lance_opaque);
 201         val &= 0x0fffffff;
 202         val |= DMA_VER;
 203         break;
 204     default:
 205         break;
 206     }
 207     s->dmaregs[saddr] = val;
 208 }
 209
 210 static CPUReadMemoryFunc *dma_mem_read[3] = {
 211     dma_mem_readl,
 212     dma_mem_readl,
 213     dma_mem_readl,
 214 };
 215
 216 static CPUWriteMemoryFunc *dma_mem_write[3] = {
 217     dma_mem_writel,
 218     dma_mem_writel,
 219     dma_mem_writel,
 220 };
 221
 222 static void dma_reset(void *opaque)
 223 {
 224     DMAState *s = opaque;
 225
 226     memset(s->dmaregs, 0, DMA_REGS * 4);
 227     s->dmaregs[0] = DMA_VER;
 228     s->dmaregs[4] = DMA_VER;
 229 }
 230
 231 static void dma_save(QEMUFile *f, void *opaque)
 232 {
 233     DMAState *s = opaque;
 234     unsigned int i;
 235
 236     for (i = 0; i < DMA_REGS; i++)
 237         qemu_put_be32s(f, &s->dmaregs[i]);
 238 }
 239
 240 static int dma_load(QEMUFile *f, void *opaque, int version_id)
 241 {
 242     DMAState *s = opaque;
 243     unsigned int i;
 244
 245     if (version_id != 1)
 246         return -EINVAL;
 247     for (i = 0; i < DMA_REGS; i++)
 248         qemu_get_be32s(f, &s->dmaregs[i]);
 249
 250     return 0;
 251 }
 252
 253 void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu, void *intctl)
 254 {
 255     DMAState *s;
 256     int dma_io_memory;
 257
 258     s = qemu_mallocz(sizeof(DMAState));
 259     if (!s)
 260         return NULL;
 261
 262     s->espirq = espirq;
 263     s->leirq = leirq;
 264     s->iommu = iommu;
 265     s->intctl = intctl;
 266
 267     dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
 268     cpu_register_physical_memory(daddr, 16 * 2, dma_io_memory);
 269
 270     register_savevm("sparc32_dma", daddr, 1, dma_save, dma_load, s);
 271     qemu_register_reset(dma_reset, s);
 272
 273     return s;
 274 }
 275
 276 void sparc32_dma_set_reset_data(void *opaque, void *esp_opaque,
 277                                 void *lance_opaque)
 278 {
 279     DMAState *s = opaque;
 280
 281     s->esp_opaque = esp_opaque;
 282     s->lance_opaque = lance_opaque;
 283 }