2 * QEMU Sparc32 DMA controller emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 * This is the DMA controller part of chip STP2000 (Master I/O), also
31 * produced as NCR89C100. See
32 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
38 #define DPRINTF(fmt, args...) \
39 do { printf("DMA: " fmt , ##args); } while (0)
40 #define pic_set_irq_new(ctl, irq, level) \
41 do { printf("DMA: set_irq(%d): %d\n", (irq), (level)); \
42 pic_set_irq_new((ctl), (irq),(level));} while (0)
44 #define DPRINTF(fmt, args...)
48 #define DMA_MAXADDR (DMA_REGS * 4 - 1)
50 #define DMA_VER 0xa0000000
52 #define DMA_INTREN 0x10
53 #define DMA_WRITE_MEM 0x100
54 #define DMA_LOADED 0x04000000
55 #define DMA_RESET 0x80
57 typedef struct DMAState DMAState
;
60 uint32_t dmaregs
[DMA_REGS
];
62 void *iommu
, *esp_opaque
, *lance_opaque
, *intctl
;
65 void ledma_set_irq(void *opaque
, int isr
)
69 pic_set_irq_new(s
->intctl
, s
->leirq
, isr
);
72 /* Note: on sparc, the lance 16 bit bus is swapped */
73 void ledma_memory_read(void *opaque
, target_phys_addr_t addr
,
74 uint8_t *buf
, int len
, int do_bswap
)
79 DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
80 s
->dmaregs
[0] & DMA_WRITE_MEM
? 'w': 'r', s
->dmaregs
[1]);
81 addr
|= s
->dmaregs
[7];
83 sparc_iommu_memory_read(s
->iommu
, addr
, buf
, len
);
87 sparc_iommu_memory_read(s
->iommu
, addr
, buf
, len
);
88 for(i
= 0; i
< len
; i
+= 2) {
89 bswap16s((uint16_t *)(buf
+ i
));
94 void ledma_memory_write(void *opaque
, target_phys_addr_t addr
,
95 uint8_t *buf
, int len
, int do_bswap
)
101 DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
102 s
->dmaregs
[0] & DMA_WRITE_MEM
? 'w': 'r', s
->dmaregs
[1]);
103 addr
|= s
->dmaregs
[7];
105 sparc_iommu_memory_write(s
->iommu
, addr
, buf
, len
);
111 if (l
> sizeof(tmp_buf
))
113 for(i
= 0; i
< l
; i
+= 2) {
114 tmp_buf
[i
>> 1] = bswap16(*(uint16_t *)(buf
+ i
));
116 sparc_iommu_memory_write(s
->iommu
, addr
, (uint8_t *)tmp_buf
, l
);
124 void espdma_raise_irq(void *opaque
)
126 DMAState
*s
= opaque
;
128 s
->dmaregs
[0] |= DMA_INTR
;
129 pic_set_irq_new(s
->intctl
, s
->espirq
, 1);
132 void espdma_clear_irq(void *opaque
)
134 DMAState
*s
= opaque
;
136 s
->dmaregs
[0] &= ~DMA_INTR
;
137 pic_set_irq_new(s
->intctl
, s
->espirq
, 0);
140 void espdma_memory_read(void *opaque
, uint8_t *buf
, int len
)
142 DMAState
*s
= opaque
;
144 DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
145 s
->dmaregs
[0] & DMA_WRITE_MEM
? 'w': 'r', s
->dmaregs
[1]);
146 sparc_iommu_memory_read(s
->iommu
, s
->dmaregs
[1], buf
, len
);
147 s
->dmaregs
[0] |= DMA_INTR
;
148 s
->dmaregs
[1] += len
;
151 void espdma_memory_write(void *opaque
, uint8_t *buf
, int len
)
153 DMAState
*s
= opaque
;
155 DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
156 s
->dmaregs
[0] & DMA_WRITE_MEM
? 'w': 'r', s
->dmaregs
[1]);
157 sparc_iommu_memory_write(s
->iommu
, s
->dmaregs
[1], buf
, len
);
158 s
->dmaregs
[0] |= DMA_INTR
;
159 s
->dmaregs
[1] += len
;
162 static uint32_t dma_mem_readl(void *opaque
, target_phys_addr_t addr
)
164 DMAState
*s
= opaque
;
167 saddr
= (addr
& DMA_MAXADDR
) >> 2;
168 DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr
, s
->dmaregs
[saddr
]);
170 return s
->dmaregs
[saddr
];
173 static void dma_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
175 DMAState
*s
= opaque
;
178 saddr
= (addr
& DMA_MAXADDR
) >> 2;
179 DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr
, s
->dmaregs
[saddr
], val
);
182 if (!(val
& DMA_INTREN
))
183 pic_set_irq_new(s
->intctl
, s
->espirq
, 0);
184 if (val
& DMA_RESET
) {
185 esp_reset(s
->esp_opaque
);
186 } else if (val
& 0x40) {
194 s
->dmaregs
[0] |= DMA_LOADED
;
197 if (!(val
& DMA_INTREN
))
198 pic_set_irq_new(s
->intctl
, s
->leirq
, 0);
200 pcnet_h_reset(s
->lance_opaque
);
207 s
->dmaregs
[saddr
] = val
;
210 static CPUReadMemoryFunc
*dma_mem_read
[3] = {
216 static CPUWriteMemoryFunc
*dma_mem_write
[3] = {
222 static void dma_reset(void *opaque
)
224 DMAState
*s
= opaque
;
226 memset(s
->dmaregs
, 0, DMA_REGS
* 4);
227 s
->dmaregs
[0] = DMA_VER
;
228 s
->dmaregs
[4] = DMA_VER
;
231 static void dma_save(QEMUFile
*f
, void *opaque
)
233 DMAState
*s
= opaque
;
236 for (i
= 0; i
< DMA_REGS
; i
++)
237 qemu_put_be32s(f
, &s
->dmaregs
[i
]);
240 static int dma_load(QEMUFile
*f
, void *opaque
, int version_id
)
242 DMAState
*s
= opaque
;
247 for (i
= 0; i
< DMA_REGS
; i
++)
248 qemu_get_be32s(f
, &s
->dmaregs
[i
]);
253 void *sparc32_dma_init(uint32_t daddr
, int espirq
, int leirq
, void *iommu
, void *intctl
)
258 s
= qemu_mallocz(sizeof(DMAState
));
267 dma_io_memory
= cpu_register_io_memory(0, dma_mem_read
, dma_mem_write
, s
);
268 cpu_register_physical_memory(daddr
, 16 * 2, dma_io_memory
);
270 register_savevm("sparc32_dma", daddr
, 1, dma_save
, dma_load
, s
);
271 qemu_register_reset(dma_reset
, s
);
276 void sparc32_dma_set_reset_data(void *opaque
, void *esp_opaque
,
279 DMAState
*s
= opaque
;
281 s
->esp_opaque
= esp_opaque
;
282 s
->lance_opaque
= lance_opaque
;