4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 /* i82731AB (PIIX4) compatible power management function */
24 #define PM_FREQ 3579545
26 #define ACPI_DBG_IO_ADDR 0xb044
28 typedef struct PIIX4PMState
{
36 int64_t tmr_overflow_time
;
39 #define RTC_EN (1 << 10)
40 #define PWRBTN_EN (1 << 8)
41 #define GBL_EN (1 << 5)
42 #define TMROF_EN (1 << 0)
44 #define SCI_EN (1 << 0)
46 #define SUS_EN (1 << 13)
48 static uint32_t get_pmtmr(PIIX4PMState
*s
)
51 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
55 static int get_pmsts(PIIX4PMState
*s
)
60 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
61 if (d
>= s
->tmr_overflow_time
)
66 static void pm_update_sci(PIIX4PMState
*s
)
72 sci_level
= (((pmsts
& s
->pmen
) &
73 (RTC_EN
| PWRBTN_EN
| GBL_EN
| TMROF_EN
)) != 0);
74 pci_set_irq(&s
->dev
, 0, sci_level
);
75 /* schedule a timer interruption if needed */
76 if ((s
->pmen
& TMROF_EN
) && !(pmsts
& TMROF_EN
)) {
77 expire_time
= muldiv64(s
->tmr_overflow_time
, ticks_per_sec
, PM_FREQ
);
78 qemu_mod_timer(s
->tmr_timer
, expire_time
);
80 qemu_del_timer(s
->tmr_timer
);
84 static void pm_tmr_timer(void *opaque
)
86 PIIX4PMState
*s
= opaque
;
90 static void pm_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
92 PIIX4PMState
*s
= opaque
;
100 if (pmsts
& val
& TMROF_EN
) {
101 /* if TMRSTS is reset, then compute the new overflow time */
102 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
103 s
->tmr_overflow_time
= (d
+ 0x800000LL
) & ~0x7fffffLL
;
116 s
->pmcntrl
= val
& ~(SUS_EN
);
118 /* change suspend type */
119 sus_typ
= (val
>> 10) & 3;
121 case 0: /* soft power off */
122 qemu_system_shutdown_request();
134 printf("PM writew port=0x%04x val=0x%04x\n", addr
, val
);
138 static uint32_t pm_ioport_readw(void *opaque
, uint32_t addr
)
140 PIIX4PMState
*s
= opaque
;
159 printf("PM readw port=0x%04x val=0x%04x\n", addr
, val
);
164 static void pm_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
166 // PIIX4PMState *s = opaque;
169 printf("PM writel port=0x%04x val=0x%08x\n", addr
, val
);
173 static uint32_t pm_ioport_readl(void *opaque
, uint32_t addr
)
175 PIIX4PMState
*s
= opaque
;
188 printf("PM readl port=0x%04x val=0x%08x\n", addr
, val
);
193 static void pm_smi_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
195 PIIX4PMState
*s
= opaque
;
198 printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr
, val
);
202 if (s
->dev
.config
[0x5b] & (1 << 1)) {
203 cpu_interrupt(first_cpu
, CPU_INTERRUPT_SMI
);
210 static uint32_t pm_smi_readb(void *opaque
, uint32_t addr
)
212 PIIX4PMState
*s
= opaque
;
222 printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr
, val
);
227 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
230 printf("ACPI: DBG: 0x%08x\n", val
);
234 static void pm_io_space_update(PIIX4PMState
*s
)
238 if (s
->dev
.config
[0x80] & 1) {
239 pm_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x40));
240 pm_io_base
&= 0xfffe;
242 /* XXX: need to improve memory and ioport allocation */
244 printf("PM: mapping to 0x%x\n", pm_io_base
);
246 register_ioport_write(pm_io_base
, 64, 2, pm_ioport_writew
, s
);
247 register_ioport_read(pm_io_base
, 64, 2, pm_ioport_readw
, s
);
248 register_ioport_write(pm_io_base
, 64, 4, pm_ioport_writel
, s
);
249 register_ioport_read(pm_io_base
, 64, 4, pm_ioport_readl
, s
);
253 static void pm_write_config(PCIDevice
*d
,
254 uint32_t address
, uint32_t val
, int len
)
256 pci_default_write_config(d
, address
, val
, len
);
258 pm_io_space_update((PIIX4PMState
*)d
);
261 static void pm_save(QEMUFile
* f
,void *opaque
)
263 PIIX4PMState
*s
= opaque
;
265 pci_device_save(&s
->dev
, f
);
267 qemu_put_be16s(f
, &s
->pmsts
);
268 qemu_put_be16s(f
, &s
->pmen
);
269 qemu_put_be16s(f
, &s
->pmcntrl
);
270 qemu_put_8s(f
, &s
->apmc
);
271 qemu_put_8s(f
, &s
->apms
);
272 qemu_put_timer(f
, s
->tmr_timer
);
273 qemu_put_be64s(f
, &s
->tmr_overflow_time
);
276 static int pm_load(QEMUFile
* f
,void* opaque
,int version_id
)
278 PIIX4PMState
*s
= opaque
;
284 ret
= pci_device_load(&s
->dev
, f
);
288 qemu_get_be16s(f
, &s
->pmsts
);
289 qemu_get_be16s(f
, &s
->pmen
);
290 qemu_get_be16s(f
, &s
->pmcntrl
);
291 qemu_get_8s(f
, &s
->apmc
);
292 qemu_get_8s(f
, &s
->apms
);
293 qemu_get_timer(f
, s
->tmr_timer
);
294 qemu_get_be64s(f
, &s
->tmr_overflow_time
);
296 pm_io_space_update(s
);
301 void piix4_pm_init(PCIBus
*bus
, int devfn
)
306 s
= (PIIX4PMState
*)pci_register_device(bus
,
307 "PM", sizeof(PIIX4PMState
),
308 devfn
, NULL
, pm_write_config
);
309 pci_conf
= s
->dev
.config
;
310 pci_conf
[0x00] = 0x86;
311 pci_conf
[0x01] = 0x80;
312 pci_conf
[0x02] = 0x13;
313 pci_conf
[0x03] = 0x71;
314 pci_conf
[0x08] = 0x00; // revision number
315 pci_conf
[0x09] = 0x00;
316 pci_conf
[0x0a] = 0x80; // other bridge device
317 pci_conf
[0x0b] = 0x06; // bridge device
318 pci_conf
[0x0e] = 0x00; // header_type
319 pci_conf
[0x3d] = 0x01; // interrupt pin 1
321 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
323 register_ioport_write(0xb2, 2, 1, pm_smi_writeb
, s
);
324 register_ioport_read(0xb2, 2, 1, pm_smi_readb
, s
);
326 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
328 /* XXX: which specification is used ? The i82731AB has different
330 pci_conf
[0x5f] = (parallel_hds
[0] != NULL
? 0x80 : 0) | 0x10;
331 pci_conf
[0x63] = 0x60;
332 pci_conf
[0x67] = (serial_hds
[0] != NULL
? 0x08 : 0) |
333 (serial_hds
[1] != NULL
? 0x90 : 0);
335 s
->tmr_timer
= qemu_new_timer(vm_clock
, pm_tmr_timer
, s
);
337 register_savevm("piix4_pm", 0, 1, pm_save
, pm_load
, s
);