hw/mips_timer.c

   1 #include "vl.h"
   2
   3 void cpu_mips_irqctrl_init (void)
   4 {
   5 }
   6
   7 /* XXX: do not use a global */
   8 uint32_t cpu_mips_get_random (CPUState *env)
   9 {
  10     static uint32_t seed = 0;
  11     uint32_t idx;
  12     seed = seed * 314159 + 1;
  13     idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
  14     return idx;
  15 }
  16
  17 /* MIPS R4K timer */
  18 uint32_t cpu_mips_get_count (CPUState *env)
  19 {
  20     return env->CP0_Count +
  21         (uint32_t)muldiv64(qemu_get_clock(vm_clock),
  22                            100 * 1000 * 1000, ticks_per_sec);
  23 }
  24
  25 static void cpu_mips_update_count (CPUState *env, uint32_t count,
  26                                    uint32_t compare)
  27 {
  28     uint64_t now, next;
  29     uint32_t tmp;
  30
  31     if (env->CP0_Cause & (1 << CP0Ca_DC))
  32         return;
  33
  34     tmp = count;
  35     if (count == compare)
  36         tmp++;
  37     now = qemu_get_clock(vm_clock);
  38     next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
  39     if (next == now)
  40         next++;
  41 #if 0
  42     if (logfile) {
  43         fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
  44                 __func__, now, count, compare, next - now);
  45     }
  46 #endif
  47     /* Store new count and compare registers */
  48     env->CP0_Compare = compare;
  49     env->CP0_Count =
  50         count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
  51     /* Adjust timer */
  52     qemu_mod_timer(env->timer, next);
  53 }
  54
  55 void cpu_mips_store_count (CPUState *env, uint32_t value)
  56 {
  57     cpu_mips_update_count(env, value, env->CP0_Compare);
  58 }
  59
  60 void cpu_mips_store_compare (CPUState *env, uint32_t value)
  61 {
  62     cpu_mips_update_count(env, cpu_mips_get_count(env), value);
  63     if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
  64         env->CP0_Cause &= ~(1 << CP0Ca_TI);
  65     cpu_mips_irq_request(env, 7, 0);
  66 }
  67
  68 static void mips_timer_cb (void *opaque)
  69 {
  70     CPUState *env;
  71
  72     env = opaque;
  73 #if 0
  74     if (logfile) {
  75         fprintf(logfile, "%s\n", __func__);
  76     }
  77 #endif
  78     cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
  79     if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
  80         env->CP0_Cause |= 1 << CP0Ca_TI;
  81     cpu_mips_irq_request(env, 7, 1);
  82 }
  83
  84 void cpu_mips_clock_init (CPUState *env)
  85 {
  86     env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
  87     env->CP0_Compare = 0;
  88     cpu_mips_update_count(env, 1, 0);
  89 }
  90