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Large kernel initrd fix (initial patch by Daniel Jacobowitz).
[qemu/mini2440.git] / hw / cirrus_vga.c
blobd8fb37a897465e3983f04a20e08e9bfd2f471668
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "vl.h"
30 #include "vga_int.h"
31
32 /*
33 * TODO:
34 * - destination write mask support not complete (bits 5..7)
35 * - optimize linear mappings
36 * - optimize bitblt functions
37 */
38
39 //#define DEBUG_CIRRUS
40 //#define DEBUG_BITBLT
41
42 /***************************************
43 *
44 * definitions
45 *
46 ***************************************/
47
48 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
49
50 // ID
51 #define CIRRUS_ID_CLGD5422 (0x23<<2)
52 #define CIRRUS_ID_CLGD5426 (0x24<<2)
53 #define CIRRUS_ID_CLGD5424 (0x25<<2)
54 #define CIRRUS_ID_CLGD5428 (0x26<<2)
55 #define CIRRUS_ID_CLGD5430 (0x28<<2)
56 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
57 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
58 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
59
60 // sequencer 0x07
61 #define CIRRUS_SR7_BPP_VGA 0x00
62 #define CIRRUS_SR7_BPP_SVGA 0x01
63 #define CIRRUS_SR7_BPP_MASK 0x0e
64 #define CIRRUS_SR7_BPP_8 0x00
65 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
66 #define CIRRUS_SR7_BPP_24 0x04
67 #define CIRRUS_SR7_BPP_16 0x06
68 #define CIRRUS_SR7_BPP_32 0x08
69 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
70
71 // sequencer 0x0f
72 #define CIRRUS_MEMSIZE_512k 0x08
73 #define CIRRUS_MEMSIZE_1M 0x10
74 #define CIRRUS_MEMSIZE_2M 0x18
75 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
76
77 // sequencer 0x12
78 #define CIRRUS_CURSOR_SHOW 0x01
79 #define CIRRUS_CURSOR_HIDDENPEL 0x02
80 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
81
82 // sequencer 0x17
83 #define CIRRUS_BUSTYPE_VLBFAST 0x10
84 #define CIRRUS_BUSTYPE_PCI 0x20
85 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
86 #define CIRRUS_BUSTYPE_ISA 0x38
87 #define CIRRUS_MMIO_ENABLE 0x04
88 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
89 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
90
91 // control 0x0b
92 #define CIRRUS_BANKING_DUAL 0x01
93 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
94
95 // control 0x30
96 #define CIRRUS_BLTMODE_BACKWARDS 0x01
97 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
98 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
99 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
100 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
101 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
102 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
103 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
104 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
105 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
106 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
107
108 // control 0x31
109 #define CIRRUS_BLT_BUSY 0x01
110 #define CIRRUS_BLT_START 0x02
111 #define CIRRUS_BLT_RESET 0x04
112 #define CIRRUS_BLT_FIFOUSED 0x10
113 #define CIRRUS_BLT_AUTOSTART 0x80
114
115 // control 0x32
116 #define CIRRUS_ROP_0 0x00
117 #define CIRRUS_ROP_SRC_AND_DST 0x05
118 #define CIRRUS_ROP_NOP 0x06
119 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
120 #define CIRRUS_ROP_NOTDST 0x0b
121 #define CIRRUS_ROP_SRC 0x0d
122 #define CIRRUS_ROP_1 0x0e
123 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
124 #define CIRRUS_ROP_SRC_XOR_DST 0x59
125 #define CIRRUS_ROP_SRC_OR_DST 0x6d
126 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
127 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
128 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
129 #define CIRRUS_ROP_NOTSRC 0xd0
130 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
131 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
132
133 #define CIRRUS_ROP_NOP_INDEX 2
134 #define CIRRUS_ROP_SRC_INDEX 5
135
136 // control 0x33
137 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
138 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
139 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
140
141 // memory-mapped IO
142 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
143 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
144 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
145 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
146 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
147 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
148 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
149 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
150 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
151 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
152 #define CIRRUS_MMIO_BLTROP 0x1a // byte
153 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
154 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
155 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
156 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
157 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
158 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
159 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
160 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
161 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
162 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
163 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
164 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
165 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
166 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
167 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
168 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
169 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
170 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
171
172 // PCI 0x00: vendor, 0x02: device
173 #define PCI_VENDOR_CIRRUS 0x1013
174 #define PCI_DEVICE_CLGD5462 0x00d0
175 #define PCI_DEVICE_CLGD5465 0x00d6
176
177 // PCI 0x04: command(word), 0x06(word): status
178 #define PCI_COMMAND_IOACCESS 0x0001
179 #define PCI_COMMAND_MEMACCESS 0x0002
180 #define PCI_COMMAND_BUSMASTER 0x0004
181 #define PCI_COMMAND_SPECIALCYCLE 0x0008
182 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
183 #define PCI_COMMAND_PALETTESNOOPING 0x0020
184 #define PCI_COMMAND_PARITYDETECTION 0x0040
185 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
186 #define PCI_COMMAND_SERR 0x0100
187 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
188 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
189 #define PCI_CLASS_BASE_DISPLAY 0x03
190 // PCI 0x08, 0x00ff0000
191 #define PCI_CLASS_SUB_VGA 0x00
192 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
193 #define PCI_CLASS_HEADERTYPE_00h 0x00
194 // 0x10-0x3f (headertype 00h)
195 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
196 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
197 #define PCI_MAP_MEM 0x0
198 #define PCI_MAP_IO 0x1
199 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
200 #define PCI_MAP_IO_ADDR_MASK (~0x3)
201 #define PCI_MAP_MEMFLAGS_32BIT 0x0
202 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
203 #define PCI_MAP_MEMFLAGS_64BIT 0x4
204 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
205 // PCI 0x28: cardbus CIS pointer
206 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
207 // PCI 0x30: expansion ROM base address
208 #define PCI_ROMBIOS_ENABLED 0x1
209 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
210 // PCI 0x38: reserved
211 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
212
213 #define CIRRUS_PNPMMIO_SIZE 0x1000
214
215
216 /* I/O and memory hook */
217 #define CIRRUS_HOOK_NOT_HANDLED 0
218 #define CIRRUS_HOOK_HANDLED 1
219
220 struct CirrusVGAState;
221 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
222 uint8_t * dst, const uint8_t * src,
223 int dstpitch, int srcpitch,
224 int bltwidth, int bltheight);
225 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
226 uint8_t *dst, int dst_pitch, int width, int height);
227
228 typedef struct CirrusVGAState {
229 VGA_STATE_COMMON
230
231 int cirrus_linear_io_addr;
232 int cirrus_linear_bitblt_io_addr;
233 int cirrus_mmio_io_addr;
234 uint32_t cirrus_addr_mask;
235 uint32_t linear_mmio_mask;
236 uint8_t cirrus_shadow_gr0;
237 uint8_t cirrus_shadow_gr1;
238 uint8_t cirrus_hidden_dac_lockindex;
239 uint8_t cirrus_hidden_dac_data;
240 uint32_t cirrus_bank_base[2];
241 uint32_t cirrus_bank_limit[2];
242 uint8_t cirrus_hidden_palette[48];
243 uint32_t hw_cursor_x;
244 uint32_t hw_cursor_y;
245 int cirrus_blt_pixelwidth;
246 int cirrus_blt_width;
247 int cirrus_blt_height;
248 int cirrus_blt_dstpitch;
249 int cirrus_blt_srcpitch;
250 uint32_t cirrus_blt_fgcol;
251 uint32_t cirrus_blt_bgcol;
252 uint32_t cirrus_blt_dstaddr;
253 uint32_t cirrus_blt_srcaddr;
254 uint8_t cirrus_blt_mode;
255 uint8_t cirrus_blt_modeext;
256 cirrus_bitblt_rop_t cirrus_rop;
257 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
258 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
259 uint8_t *cirrus_srcptr;
260 uint8_t *cirrus_srcptr_end;
261 uint32_t cirrus_srccounter;
262 /* hwcursor display state */
263 int last_hw_cursor_size;
264 int last_hw_cursor_x;
265 int last_hw_cursor_y;
266 int last_hw_cursor_y_start;
267 int last_hw_cursor_y_end;
268 int real_vram_size; /* XXX: suppress that */
269 CPUWriteMemoryFunc **cirrus_linear_write;
270 } CirrusVGAState;
271
272 typedef struct PCICirrusVGAState {
273 PCIDevice dev;
274 CirrusVGAState cirrus_vga;
275 } PCICirrusVGAState;
276
277 static uint8_t rop_to_index[256];
278
279 /***************************************
280 *
281 * prototypes.
282 *
283 ***************************************/
284
285
286 static void cirrus_bitblt_reset(CirrusVGAState *s);
287 static void cirrus_update_memory_access(CirrusVGAState *s);
288
289 /***************************************
290 *
291 * raster operations
292 *
293 ***************************************/
294
295 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
296 uint8_t *dst,const uint8_t *src,
297 int dstpitch,int srcpitch,
298 int bltwidth,int bltheight)
299 {
300 }
301
302 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
303 uint8_t *dst,
304 int dstpitch, int bltwidth,int bltheight)
305 {
306 }
307
308 #define ROP_NAME 0
309 #define ROP_OP(d, s) d = 0
310 #include "cirrus_vga_rop.h"
311
312 #define ROP_NAME src_and_dst
313 #define ROP_OP(d, s) d = (s) & (d)
314 #include "cirrus_vga_rop.h"
315
316 #define ROP_NAME src_and_notdst
317 #define ROP_OP(d, s) d = (s) & (~(d))
318 #include "cirrus_vga_rop.h"
319
320 #define ROP_NAME notdst
321 #define ROP_OP(d, s) d = ~(d)
322 #include "cirrus_vga_rop.h"
323
324 #define ROP_NAME src
325 #define ROP_OP(d, s) d = s
326 #include "cirrus_vga_rop.h"
327
328 #define ROP_NAME 1
329 #define ROP_OP(d, s) d = ~0
330 #include "cirrus_vga_rop.h"
331
332 #define ROP_NAME notsrc_and_dst
333 #define ROP_OP(d, s) d = (~(s)) & (d)
334 #include "cirrus_vga_rop.h"
335
336 #define ROP_NAME src_xor_dst
337 #define ROP_OP(d, s) d = (s) ^ (d)
338 #include "cirrus_vga_rop.h"
339
340 #define ROP_NAME src_or_dst
341 #define ROP_OP(d, s) d = (s) | (d)
342 #include "cirrus_vga_rop.h"
343
344 #define ROP_NAME notsrc_or_notdst
345 #define ROP_OP(d, s) d = (~(s)) | (~(d))
346 #include "cirrus_vga_rop.h"
347
348 #define ROP_NAME src_notxor_dst
349 #define ROP_OP(d, s) d = ~((s) ^ (d))
350 #include "cirrus_vga_rop.h"
351
352 #define ROP_NAME src_or_notdst
353 #define ROP_OP(d, s) d = (s) | (~(d))
354 #include "cirrus_vga_rop.h"
355
356 #define ROP_NAME notsrc
357 #define ROP_OP(d, s) d = (~(s))
358 #include "cirrus_vga_rop.h"
359
360 #define ROP_NAME notsrc_or_dst
361 #define ROP_OP(d, s) d = (~(s)) | (d)
362 #include "cirrus_vga_rop.h"
363
364 #define ROP_NAME notsrc_and_notdst
365 #define ROP_OP(d, s) d = (~(s)) & (~(d))
366 #include "cirrus_vga_rop.h"
367
368 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
369 cirrus_bitblt_rop_fwd_0,
370 cirrus_bitblt_rop_fwd_src_and_dst,
371 cirrus_bitblt_rop_nop,
372 cirrus_bitblt_rop_fwd_src_and_notdst,
373 cirrus_bitblt_rop_fwd_notdst,
374 cirrus_bitblt_rop_fwd_src,
375 cirrus_bitblt_rop_fwd_1,
376 cirrus_bitblt_rop_fwd_notsrc_and_dst,
377 cirrus_bitblt_rop_fwd_src_xor_dst,
378 cirrus_bitblt_rop_fwd_src_or_dst,
379 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
380 cirrus_bitblt_rop_fwd_src_notxor_dst,
381 cirrus_bitblt_rop_fwd_src_or_notdst,
382 cirrus_bitblt_rop_fwd_notsrc,
383 cirrus_bitblt_rop_fwd_notsrc_or_dst,
384 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
385 };
386
387 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
388 cirrus_bitblt_rop_bkwd_0,
389 cirrus_bitblt_rop_bkwd_src_and_dst,
390 cirrus_bitblt_rop_nop,
391 cirrus_bitblt_rop_bkwd_src_and_notdst,
392 cirrus_bitblt_rop_bkwd_notdst,
393 cirrus_bitblt_rop_bkwd_src,
394 cirrus_bitblt_rop_bkwd_1,
395 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
396 cirrus_bitblt_rop_bkwd_src_xor_dst,
397 cirrus_bitblt_rop_bkwd_src_or_dst,
398 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
399 cirrus_bitblt_rop_bkwd_src_notxor_dst,
400 cirrus_bitblt_rop_bkwd_src_or_notdst,
401 cirrus_bitblt_rop_bkwd_notsrc,
402 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
403 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
404 };
405
406 #define ROP2(name) {\
407 name ## _8,\
408 name ## _16,\
409 name ## _24,\
410 name ## _32,\
411 }
412
413 #define ROP_NOP2(func) {\
414 func,\
415 func,\
416 func,\
417 func,\
418 }
419
420 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
421 ROP2(cirrus_patternfill_0),
422 ROP2(cirrus_patternfill_src_and_dst),
423 ROP_NOP2(cirrus_bitblt_rop_nop),
424 ROP2(cirrus_patternfill_src_and_notdst),
425 ROP2(cirrus_patternfill_notdst),
426 ROP2(cirrus_patternfill_src),
427 ROP2(cirrus_patternfill_1),
428 ROP2(cirrus_patternfill_notsrc_and_dst),
429 ROP2(cirrus_patternfill_src_xor_dst),
430 ROP2(cirrus_patternfill_src_or_dst),
431 ROP2(cirrus_patternfill_notsrc_or_notdst),
432 ROP2(cirrus_patternfill_src_notxor_dst),
433 ROP2(cirrus_patternfill_src_or_notdst),
434 ROP2(cirrus_patternfill_notsrc),
435 ROP2(cirrus_patternfill_notsrc_or_dst),
436 ROP2(cirrus_patternfill_notsrc_and_notdst),
437 };
438
439 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
440 ROP2(cirrus_colorexpand_transp_0),
441 ROP2(cirrus_colorexpand_transp_src_and_dst),
442 ROP_NOP2(cirrus_bitblt_rop_nop),
443 ROP2(cirrus_colorexpand_transp_src_and_notdst),
444 ROP2(cirrus_colorexpand_transp_notdst),
445 ROP2(cirrus_colorexpand_transp_src),
446 ROP2(cirrus_colorexpand_transp_1),
447 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
448 ROP2(cirrus_colorexpand_transp_src_xor_dst),
449 ROP2(cirrus_colorexpand_transp_src_or_dst),
450 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
451 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
452 ROP2(cirrus_colorexpand_transp_src_or_notdst),
453 ROP2(cirrus_colorexpand_transp_notsrc),
454 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
455 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
456 };
457
458 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
459 ROP2(cirrus_colorexpand_0),
460 ROP2(cirrus_colorexpand_src_and_dst),
461 ROP_NOP2(cirrus_bitblt_rop_nop),
462 ROP2(cirrus_colorexpand_src_and_notdst),
463 ROP2(cirrus_colorexpand_notdst),
464 ROP2(cirrus_colorexpand_src),
465 ROP2(cirrus_colorexpand_1),
466 ROP2(cirrus_colorexpand_notsrc_and_dst),
467 ROP2(cirrus_colorexpand_src_xor_dst),
468 ROP2(cirrus_colorexpand_src_or_dst),
469 ROP2(cirrus_colorexpand_notsrc_or_notdst),
470 ROP2(cirrus_colorexpand_src_notxor_dst),
471 ROP2(cirrus_colorexpand_src_or_notdst),
472 ROP2(cirrus_colorexpand_notsrc),
473 ROP2(cirrus_colorexpand_notsrc_or_dst),
474 ROP2(cirrus_colorexpand_notsrc_and_notdst),
475 };
476
477 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
478 ROP2(cirrus_colorexpand_pattern_transp_0),
479 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
480 ROP_NOP2(cirrus_bitblt_rop_nop),
481 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
482 ROP2(cirrus_colorexpand_pattern_transp_notdst),
483 ROP2(cirrus_colorexpand_pattern_transp_src),
484 ROP2(cirrus_colorexpand_pattern_transp_1),
485 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
486 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
487 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
488 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
489 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
490 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
491 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
492 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
493 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
494 };
495
496 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
497 ROP2(cirrus_colorexpand_pattern_0),
498 ROP2(cirrus_colorexpand_pattern_src_and_dst),
499 ROP_NOP2(cirrus_bitblt_rop_nop),
500 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
501 ROP2(cirrus_colorexpand_pattern_notdst),
502 ROP2(cirrus_colorexpand_pattern_src),
503 ROP2(cirrus_colorexpand_pattern_1),
504 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
505 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
506 ROP2(cirrus_colorexpand_pattern_src_or_dst),
507 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
508 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
509 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
510 ROP2(cirrus_colorexpand_pattern_notsrc),
511 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
512 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
513 };
514
515 static const cirrus_fill_t cirrus_fill[16][4] = {
516 ROP2(cirrus_fill_0),
517 ROP2(cirrus_fill_src_and_dst),
518 ROP_NOP2(cirrus_bitblt_fill_nop),
519 ROP2(cirrus_fill_src_and_notdst),
520 ROP2(cirrus_fill_notdst),
521 ROP2(cirrus_fill_src),
522 ROP2(cirrus_fill_1),
523 ROP2(cirrus_fill_notsrc_and_dst),
524 ROP2(cirrus_fill_src_xor_dst),
525 ROP2(cirrus_fill_src_or_dst),
526 ROP2(cirrus_fill_notsrc_or_notdst),
527 ROP2(cirrus_fill_src_notxor_dst),
528 ROP2(cirrus_fill_src_or_notdst),
529 ROP2(cirrus_fill_notsrc),
530 ROP2(cirrus_fill_notsrc_or_dst),
531 ROP2(cirrus_fill_notsrc_and_notdst),
532 };
533
534 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
535 {
536 unsigned int color;
537 switch (s->cirrus_blt_pixelwidth) {
538 case 1:
539 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
540 break;
541 case 2:
542 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
543 s->cirrus_blt_fgcol = le16_to_cpu(color);
544 break;
545 case 3:
546 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
547 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
548 break;
549 default:
550 case 4:
551 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
552 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
553 s->cirrus_blt_fgcol = le32_to_cpu(color);
554 break;
555 }
556 }
557
558 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
559 {
560 unsigned int color;
561 switch (s->cirrus_blt_pixelwidth) {
562 case 1:
563 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
564 break;
565 case 2:
566 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
567 s->cirrus_blt_bgcol = le16_to_cpu(color);
568 break;
569 case 3:
570 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
571 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
572 break;
573 default:
574 case 4:
575 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
576 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
577 s->cirrus_blt_bgcol = le32_to_cpu(color);
578 break;
579 }
580 }
581
582 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
583 int off_pitch, int bytesperline,
584 int lines)
585 {
586 int y;
587 int off_cur;
588 int off_cur_end;
589
590 for (y = 0; y < lines; y++) {
591 off_cur = off_begin;
592 off_cur_end = off_cur + bytesperline;
593 off_cur &= TARGET_PAGE_MASK;
594 while (off_cur < off_cur_end) {
595 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
596 off_cur += TARGET_PAGE_SIZE;
597 }
598 off_begin += off_pitch;
599 }
600 }
601
602 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
603 const uint8_t * src)
604 {
605 uint8_t *dst;
606
607 dst = s->vram_ptr + s->cirrus_blt_dstaddr;
608 (*s->cirrus_rop) (s, dst, src,
609 s->cirrus_blt_dstpitch, 0,
610 s->cirrus_blt_width, s->cirrus_blt_height);
611 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
612 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
613 s->cirrus_blt_height);
614 return 1;
615 }
616
617 /* fill */
618
619 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
620 {
621 cirrus_fill_t rop_func;
622
623 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
624 rop_func(s, s->vram_ptr + s->cirrus_blt_dstaddr,
625 s->cirrus_blt_dstpitch,
626 s->cirrus_blt_width, s->cirrus_blt_height);
627 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
628 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
629 s->cirrus_blt_height);
630 cirrus_bitblt_reset(s);
631 return 1;
632 }
633
634 /***************************************
635 *
636 * bitblt (video-to-video)
637 *
638 ***************************************/
639
640 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
641 {
642 return cirrus_bitblt_common_patterncopy(s,
643 s->vram_ptr +
644 (s->cirrus_blt_srcaddr & ~7));
645 }
646
647 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
648 {
649 int sx, sy;
650 int dx, dy;
651 int width, height;
652 int depth;
653 int notify = 0;
654
655 depth = s->get_bpp((VGAState *)s) / 8;
656 s->get_resolution((VGAState *)s, &width, &height);
657
658 /* extra x, y */
659 sx = (src % (width * depth)) / depth;
660 sy = (src / (width * depth));
661 dx = (dst % (width *depth)) / depth;
662 dy = (dst / (width * depth));
663
664 /* normalize width */
665 w /= depth;
666
667 /* if we're doing a backward copy, we have to adjust
668 our x/y to be the upper left corner (instead of the lower
669 right corner) */
670 if (s->cirrus_blt_dstpitch < 0) {
671 sx -= (s->cirrus_blt_width / depth) - 1;
672 dx -= (s->cirrus_blt_width / depth) - 1;
673 sy -= s->cirrus_blt_height - 1;
674 dy -= s->cirrus_blt_height - 1;
675 }
676
677 /* are we in the visible portion of memory? */
678 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
679 (sx + w) <= width && (sy + h) <= height &&
680 (dx + w) <= width && (dy + h) <= height) {
681 notify = 1;
682 }
683
684 /* make to sure only copy if it's a plain copy ROP */
685 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
686 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
687 notify = 0;
688
689 /* we have to flush all pending changes so that the copy
690 is generated at the appropriate moment in time */
691 if (notify)
692 vga_hw_update();
693
694 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
695 s->vram_ptr + s->cirrus_blt_srcaddr,
696 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
697 s->cirrus_blt_width, s->cirrus_blt_height);
698
699 if (notify)
700 s->ds->dpy_copy(s->ds,
701 sx, sy, dx, dy,
702 s->cirrus_blt_width / depth,
703 s->cirrus_blt_height);
704
705 /* we don't have to notify the display that this portion has
706 changed since dpy_copy implies this */
707
708 if (!notify)
709 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
710 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
711 s->cirrus_blt_height);
712 }
713
714 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
715 {
716 if (s->ds->dpy_copy) {
717 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
718 s->cirrus_blt_srcaddr - s->start_addr,
719 s->cirrus_blt_width, s->cirrus_blt_height);
720 } else {
721 (*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
722 s->vram_ptr + s->cirrus_blt_srcaddr,
723 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
724 s->cirrus_blt_width, s->cirrus_blt_height);
725
726 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
727 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
728 s->cirrus_blt_height);
729 }
730
731 return 1;
732 }
733
734 /***************************************
735 *
736 * bitblt (cpu-to-video)
737 *
738 ***************************************/
739
740 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
741 {
742 int copy_count;
743 uint8_t *end_ptr;
744
745 if (s->cirrus_srccounter > 0) {
746 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
747 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
748 the_end:
749 s->cirrus_srccounter = 0;
750 cirrus_bitblt_reset(s);
751 } else {
752 /* at least one scan line */
753 do {
754 (*s->cirrus_rop)(s, s->vram_ptr + s->cirrus_blt_dstaddr,
755 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
756 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
757 s->cirrus_blt_width, 1);
758 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
759 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
760 if (s->cirrus_srccounter <= 0)
761 goto the_end;
762 /* more bytes than needed can be transfered because of
763 word alignment, so we keep them for the next line */
764 /* XXX: keep alignment to speed up transfer */
765 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
766 copy_count = s->cirrus_srcptr_end - end_ptr;
767 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
768 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
769 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
770 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
771 }
772 }
773 }
774
775 /***************************************
776 *
777 * bitblt wrapper
778 *
779 ***************************************/
780
781 static void cirrus_bitblt_reset(CirrusVGAState * s)
782 {
783 s->gr[0x31] &=
784 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
785 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
786 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
787 s->cirrus_srccounter = 0;
788 cirrus_update_memory_access(s);
789 }
790
791 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
792 {
793 int w;
794
795 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
796 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
797 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
798
799 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
800 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
801 s->cirrus_blt_srcpitch = 8;
802 } else {
803 /* XXX: check for 24 bpp */
804 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
805 }
806 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
807 } else {
808 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
809 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
810 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
811 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
812 else
813 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
814 } else {
815 /* always align input size to 32 bits */
816 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
817 }
818 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
819 }
820 s->cirrus_srcptr = s->cirrus_bltbuf;
821 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
822 cirrus_update_memory_access(s);
823 return 1;
824 }
825
826 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
827 {
828 /* XXX */
829 #ifdef DEBUG_BITBLT
830 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
831 #endif
832 return 0;
833 }
834
835 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
836 {
837 int ret;
838
839 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
840 ret = cirrus_bitblt_videotovideo_patterncopy(s);
841 } else {
842 ret = cirrus_bitblt_videotovideo_copy(s);
843 }
844 if (ret)
845 cirrus_bitblt_reset(s);
846 return ret;
847 }
848
849 static void cirrus_bitblt_start(CirrusVGAState * s)
850 {
851 uint8_t blt_rop;
852
853 s->gr[0x31] |= CIRRUS_BLT_BUSY;
854
855 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
856 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
857 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
858 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
859 s->cirrus_blt_dstaddr =
860 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
861 s->cirrus_blt_srcaddr =
862 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
863 s->cirrus_blt_mode = s->gr[0x30];
864 s->cirrus_blt_modeext = s->gr[0x33];
865 blt_rop = s->gr[0x32];
866
867 #ifdef DEBUG_BITBLT
868 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
869 blt_rop,
870 s->cirrus_blt_mode,
871 s->cirrus_blt_modeext,
872 s->cirrus_blt_width,
873 s->cirrus_blt_height,
874 s->cirrus_blt_dstpitch,
875 s->cirrus_blt_srcpitch,
876 s->cirrus_blt_dstaddr,
877 s->cirrus_blt_srcaddr,
878 s->gr[0x2f]);
879 #endif
880
881 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
882 case CIRRUS_BLTMODE_PIXELWIDTH8:
883 s->cirrus_blt_pixelwidth = 1;
884 break;
885 case CIRRUS_BLTMODE_PIXELWIDTH16:
886 s->cirrus_blt_pixelwidth = 2;
887 break;
888 case CIRRUS_BLTMODE_PIXELWIDTH24:
889 s->cirrus_blt_pixelwidth = 3;
890 break;
891 case CIRRUS_BLTMODE_PIXELWIDTH32:
892 s->cirrus_blt_pixelwidth = 4;
893 break;
894 default:
895 #ifdef DEBUG_BITBLT
896 printf("cirrus: bitblt - pixel width is unknown\n");
897 #endif
898 goto bitblt_ignore;
899 }
900 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
901
902 if ((s->
903 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
904 CIRRUS_BLTMODE_MEMSYSDEST))
905 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
906 #ifdef DEBUG_BITBLT
907 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
908 #endif
909 goto bitblt_ignore;
910 }
911
912 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
913 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
914 CIRRUS_BLTMODE_TRANSPARENTCOMP |
915 CIRRUS_BLTMODE_PATTERNCOPY |
916 CIRRUS_BLTMODE_COLOREXPAND)) ==
917 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
918 cirrus_bitblt_fgcol(s);
919 cirrus_bitblt_solidfill(s, blt_rop);
920 } else {
921 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
922 CIRRUS_BLTMODE_PATTERNCOPY)) ==
923 CIRRUS_BLTMODE_COLOREXPAND) {
924
925 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
926 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
927 cirrus_bitblt_bgcol(s);
928 else
929 cirrus_bitblt_fgcol(s);
930 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
931 } else {
932 cirrus_bitblt_fgcol(s);
933 cirrus_bitblt_bgcol(s);
934 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
935 }
936 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
937 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
938 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
939 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
940 cirrus_bitblt_bgcol(s);
941 else
942 cirrus_bitblt_fgcol(s);
943 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
944 } else {
945 cirrus_bitblt_fgcol(s);
946 cirrus_bitblt_bgcol(s);
947 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
948 }
949 } else {
950 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
951 }
952 } else {
953 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
954 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
955 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
956 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
957 } else {
958 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
959 }
960 }
961
962 // setup bitblt engine.
963 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
964 if (!cirrus_bitblt_cputovideo(s))
965 goto bitblt_ignore;
966 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
967 if (!cirrus_bitblt_videotocpu(s))
968 goto bitblt_ignore;
969 } else {
970 if (!cirrus_bitblt_videotovideo(s))
971 goto bitblt_ignore;
972 }
973 }
974 return;
975 bitblt_ignore:;
976 cirrus_bitblt_reset(s);
977 }
978
979 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
980 {
981 unsigned old_value;
982
983 old_value = s->gr[0x31];
984 s->gr[0x31] = reg_value;
985
986 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
987 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
988 cirrus_bitblt_reset(s);
989 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
990 ((reg_value & CIRRUS_BLT_START) != 0)) {
991 cirrus_bitblt_start(s);
992 }
993 }
994
995
996 /***************************************
997 *
998 * basic parameters
999 *
1000 ***************************************/
1001
1002 static void cirrus_get_offsets(VGAState *s1,
1003 uint32_t *pline_offset,
1004 uint32_t *pstart_addr,
1005 uint32_t *pline_compare)
1006 {
1007 CirrusVGAState * s = (CirrusVGAState *)s1;
1008 uint32_t start_addr, line_offset, line_compare;
1009
1010 line_offset = s->cr[0x13]
1011 | ((s->cr[0x1b] & 0x10) << 4);
1012 line_offset <<= 3;
1013 *pline_offset = line_offset;
1014
1015 start_addr = (s->cr[0x0c] << 8)
1016 | s->cr[0x0d]
1017 | ((s->cr[0x1b] & 0x01) << 16)
1018 | ((s->cr[0x1b] & 0x0c) << 15)
1019 | ((s->cr[0x1d] & 0x80) << 12);
1020 *pstart_addr = start_addr;
1021
1022 line_compare = s->cr[0x18] |
1023 ((s->cr[0x07] & 0x10) << 4) |
1024 ((s->cr[0x09] & 0x40) << 3);
1025 *pline_compare = line_compare;
1026 }
1027
1028 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1029 {
1030 uint32_t ret = 16;
1031
1032 switch (s->cirrus_hidden_dac_data & 0xf) {
1033 case 0:
1034 ret = 15;
1035 break; /* Sierra HiColor */
1036 case 1:
1037 ret = 16;
1038 break; /* XGA HiColor */
1039 default:
1040 #ifdef DEBUG_CIRRUS
1041 printf("cirrus: invalid DAC value %x in 16bpp\n",
1042 (s->cirrus_hidden_dac_data & 0xf));
1043 #endif
1044 ret = 15; /* XXX */
1045 break;
1046 }
1047 return ret;
1048 }
1049
1050 static int cirrus_get_bpp(VGAState *s1)
1051 {
1052 CirrusVGAState * s = (CirrusVGAState *)s1;
1053 uint32_t ret = 8;
1054
1055 if ((s->sr[0x07] & 0x01) != 0) {
1056 /* Cirrus SVGA */
1057 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1058 case CIRRUS_SR7_BPP_8:
1059 ret = 8;
1060 break;
1061 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1062 ret = cirrus_get_bpp16_depth(s);
1063 break;
1064 case CIRRUS_SR7_BPP_24:
1065 ret = 24;
1066 break;
1067 case CIRRUS_SR7_BPP_16:
1068 ret = cirrus_get_bpp16_depth(s);
1069 break;
1070 case CIRRUS_SR7_BPP_32:
1071 ret = 32;
1072 break;
1073 default:
1074 #ifdef DEBUG_CIRRUS
1075 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1076 #endif
1077 ret = 8;
1078 break;
1079 }
1080 } else {
1081 /* VGA */
1082 ret = 0;
1083 }
1084
1085 return ret;
1086 }
1087
1088 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1089 {
1090 int width, height;
1091
1092 width = (s->cr[0x01] + 1) * 8;
1093 height = s->cr[0x12] |
1094 ((s->cr[0x07] & 0x02) << 7) |
1095 ((s->cr[0x07] & 0x40) << 3);
1096 height = (height + 1);
1097 /* interlace support */
1098 if (s->cr[0x1a] & 0x01)
1099 height = height * 2;
1100 *pwidth = width;
1101 *pheight = height;
1102 }
1103
1104 /***************************************
1105 *
1106 * bank memory
1107 *
1108 ***************************************/
1109
1110 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1111 {
1112 unsigned offset;
1113 unsigned limit;
1114
1115 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1116 offset = s->gr[0x09 + bank_index];
1117 else /* single bank */
1118 offset = s->gr[0x09];
1119
1120 if ((s->gr[0x0b] & 0x20) != 0)
1121 offset <<= 14;
1122 else
1123 offset <<= 12;
1124
1125 if (s->real_vram_size <= offset)
1126 limit = 0;
1127 else
1128 limit = s->real_vram_size - offset;
1129
1130 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1131 if (limit > 0x8000) {
1132 offset += 0x8000;
1133 limit -= 0x8000;
1134 } else {
1135 limit = 0;
1136 }
1137 }
1138
1139 if (limit > 0) {
1140 s->cirrus_bank_base[bank_index] = offset;
1141 s->cirrus_bank_limit[bank_index] = limit;
1142 } else {
1143 s->cirrus_bank_base[bank_index] = 0;
1144 s->cirrus_bank_limit[bank_index] = 0;
1145 }
1146 }
1147
1148 /***************************************
1149 *
1150 * I/O access between 0x3c4-0x3c5
1151 *
1152 ***************************************/
1153
1154 static int
1155 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1156 {
1157 switch (reg_index) {
1158 case 0x00: // Standard VGA
1159 case 0x01: // Standard VGA
1160 case 0x02: // Standard VGA
1161 case 0x03: // Standard VGA
1162 case 0x04: // Standard VGA
1163 return CIRRUS_HOOK_NOT_HANDLED;
1164 case 0x06: // Unlock Cirrus extensions
1165 *reg_value = s->sr[reg_index];
1166 break;
1167 case 0x10:
1168 case 0x30:
1169 case 0x50:
1170 case 0x70: // Graphics Cursor X
1171 case 0x90:
1172 case 0xb0:
1173 case 0xd0:
1174 case 0xf0: // Graphics Cursor X
1175 *reg_value = s->sr[0x10];
1176 break;
1177 case 0x11:
1178 case 0x31:
1179 case 0x51:
1180 case 0x71: // Graphics Cursor Y
1181 case 0x91:
1182 case 0xb1:
1183 case 0xd1:
1184 case 0xf1: // Graphics Cursor Y
1185 *reg_value = s->sr[0x11];
1186 break;
1187 case 0x05: // ???
1188 case 0x07: // Extended Sequencer Mode
1189 case 0x08: // EEPROM Control
1190 case 0x09: // Scratch Register 0
1191 case 0x0a: // Scratch Register 1
1192 case 0x0b: // VCLK 0
1193 case 0x0c: // VCLK 1
1194 case 0x0d: // VCLK 2
1195 case 0x0e: // VCLK 3
1196 case 0x0f: // DRAM Control
1197 case 0x12: // Graphics Cursor Attribute
1198 case 0x13: // Graphics Cursor Pattern Address
1199 case 0x14: // Scratch Register 2
1200 case 0x15: // Scratch Register 3
1201 case 0x16: // Performance Tuning Register
1202 case 0x17: // Configuration Readback and Extended Control
1203 case 0x18: // Signature Generator Control
1204 case 0x19: // Signal Generator Result
1205 case 0x1a: // Signal Generator Result
1206 case 0x1b: // VCLK 0 Denominator & Post
1207 case 0x1c: // VCLK 1 Denominator & Post
1208 case 0x1d: // VCLK 2 Denominator & Post
1209 case 0x1e: // VCLK 3 Denominator & Post
1210 case 0x1f: // BIOS Write Enable and MCLK select
1211 #ifdef DEBUG_CIRRUS
1212 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1213 #endif
1214 *reg_value = s->sr[reg_index];
1215 break;
1216 default:
1217 #ifdef DEBUG_CIRRUS
1218 printf("cirrus: inport sr_index %02x\n", reg_index);
1219 #endif
1220 *reg_value = 0xff;
1221 break;
1222 }
1223
1224 return CIRRUS_HOOK_HANDLED;
1225 }
1226
1227 static int
1228 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1229 {
1230 switch (reg_index) {
1231 case 0x00: // Standard VGA
1232 case 0x01: // Standard VGA
1233 case 0x02: // Standard VGA
1234 case 0x03: // Standard VGA
1235 case 0x04: // Standard VGA
1236 return CIRRUS_HOOK_NOT_HANDLED;
1237 case 0x06: // Unlock Cirrus extensions
1238 reg_value &= 0x17;
1239 if (reg_value == 0x12) {
1240 s->sr[reg_index] = 0x12;
1241 } else {
1242 s->sr[reg_index] = 0x0f;
1243 }
1244 break;
1245 case 0x10:
1246 case 0x30:
1247 case 0x50:
1248 case 0x70: // Graphics Cursor X
1249 case 0x90:
1250 case 0xb0:
1251 case 0xd0:
1252 case 0xf0: // Graphics Cursor X
1253 s->sr[0x10] = reg_value;
1254 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1255 break;
1256 case 0x11:
1257 case 0x31:
1258 case 0x51:
1259 case 0x71: // Graphics Cursor Y
1260 case 0x91:
1261 case 0xb1:
1262 case 0xd1:
1263 case 0xf1: // Graphics Cursor Y
1264 s->sr[0x11] = reg_value;
1265 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1266 break;
1267 case 0x07: // Extended Sequencer Mode
1268 case 0x08: // EEPROM Control
1269 case 0x09: // Scratch Register 0
1270 case 0x0a: // Scratch Register 1
1271 case 0x0b: // VCLK 0
1272 case 0x0c: // VCLK 1
1273 case 0x0d: // VCLK 2
1274 case 0x0e: // VCLK 3
1275 case 0x0f: // DRAM Control
1276 case 0x12: // Graphics Cursor Attribute
1277 case 0x13: // Graphics Cursor Pattern Address
1278 case 0x14: // Scratch Register 2
1279 case 0x15: // Scratch Register 3
1280 case 0x16: // Performance Tuning Register
1281 case 0x18: // Signature Generator Control
1282 case 0x19: // Signature Generator Result
1283 case 0x1a: // Signature Generator Result
1284 case 0x1b: // VCLK 0 Denominator & Post
1285 case 0x1c: // VCLK 1 Denominator & Post
1286 case 0x1d: // VCLK 2 Denominator & Post
1287 case 0x1e: // VCLK 3 Denominator & Post
1288 case 0x1f: // BIOS Write Enable and MCLK select
1289 s->sr[reg_index] = reg_value;
1290 #ifdef DEBUG_CIRRUS
1291 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1292 reg_index, reg_value);
1293 #endif
1294 break;
1295 case 0x17: // Configuration Readback and Extended Control
1296 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1297 cirrus_update_memory_access(s);
1298 break;
1299 default:
1300 #ifdef DEBUG_CIRRUS
1301 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1302 reg_value);
1303 #endif
1304 break;
1305 }
1306
1307 return CIRRUS_HOOK_HANDLED;
1308 }
1309
1310 /***************************************
1311 *
1312 * I/O access at 0x3c6
1313 *
1314 ***************************************/
1315
1316 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1317 {
1318 *reg_value = 0xff;
1319 if (++s->cirrus_hidden_dac_lockindex == 5) {
1320 *reg_value = s->cirrus_hidden_dac_data;
1321 s->cirrus_hidden_dac_lockindex = 0;
1322 }
1323 }
1324
1325 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1326 {
1327 if (s->cirrus_hidden_dac_lockindex == 4) {
1328 s->cirrus_hidden_dac_data = reg_value;
1329 #if defined(DEBUG_CIRRUS)
1330 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1331 #endif
1332 }
1333 s->cirrus_hidden_dac_lockindex = 0;
1334 }
1335
1336 /***************************************
1337 *
1338 * I/O access at 0x3c9
1339 *
1340 ***************************************/
1341
1342 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1343 {
1344 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1345 return CIRRUS_HOOK_NOT_HANDLED;
1346 *reg_value =
1347 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1348 s->dac_sub_index];
1349 if (++s->dac_sub_index == 3) {
1350 s->dac_sub_index = 0;
1351 s->dac_read_index++;
1352 }
1353 return CIRRUS_HOOK_HANDLED;
1354 }
1355
1356 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1357 {
1358 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1359 return CIRRUS_HOOK_NOT_HANDLED;
1360 s->dac_cache[s->dac_sub_index] = reg_value;
1361 if (++s->dac_sub_index == 3) {
1362 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1363 s->dac_cache, 3);
1364 /* XXX update cursor */
1365 s->dac_sub_index = 0;
1366 s->dac_write_index++;
1367 }
1368 return CIRRUS_HOOK_HANDLED;
1369 }
1370
1371 /***************************************
1372 *
1373 * I/O access between 0x3ce-0x3cf
1374 *
1375 ***************************************/
1376
1377 static int
1378 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1379 {
1380 switch (reg_index) {
1381 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1382 *reg_value = s->cirrus_shadow_gr0;
1383 return CIRRUS_HOOK_HANDLED;
1384 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1385 *reg_value = s->cirrus_shadow_gr1;
1386 return CIRRUS_HOOK_HANDLED;
1387 case 0x02: // Standard VGA
1388 case 0x03: // Standard VGA
1389 case 0x04: // Standard VGA
1390 case 0x06: // Standard VGA
1391 case 0x07: // Standard VGA
1392 case 0x08: // Standard VGA
1393 return CIRRUS_HOOK_NOT_HANDLED;
1394 case 0x05: // Standard VGA, Cirrus extended mode
1395 default:
1396 break;
1397 }
1398
1399 if (reg_index < 0x3a) {
1400 *reg_value = s->gr[reg_index];
1401 } else {
1402 #ifdef DEBUG_CIRRUS
1403 printf("cirrus: inport gr_index %02x\n", reg_index);
1404 #endif
1405 *reg_value = 0xff;
1406 }
1407
1408 return CIRRUS_HOOK_HANDLED;
1409 }
1410
1411 static int
1412 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1413 {
1414 #if defined(DEBUG_BITBLT) && 0
1415 printf("gr%02x: %02x\n", reg_index, reg_value);
1416 #endif
1417 switch (reg_index) {
1418 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1419 s->cirrus_shadow_gr0 = reg_value;
1420 return CIRRUS_HOOK_NOT_HANDLED;
1421 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1422 s->cirrus_shadow_gr1 = reg_value;
1423 return CIRRUS_HOOK_NOT_HANDLED;
1424 case 0x02: // Standard VGA
1425 case 0x03: // Standard VGA
1426 case 0x04: // Standard VGA
1427 case 0x06: // Standard VGA
1428 case 0x07: // Standard VGA
1429 case 0x08: // Standard VGA
1430 return CIRRUS_HOOK_NOT_HANDLED;
1431 case 0x05: // Standard VGA, Cirrus extended mode
1432 s->gr[reg_index] = reg_value & 0x7f;
1433 cirrus_update_memory_access(s);
1434 break;
1435 case 0x09: // bank offset #0
1436 case 0x0A: // bank offset #1
1437 s->gr[reg_index] = reg_value;
1438 cirrus_update_bank_ptr(s, 0);
1439 cirrus_update_bank_ptr(s, 1);
1440 break;
1441 case 0x0B:
1442 s->gr[reg_index] = reg_value;
1443 cirrus_update_bank_ptr(s, 0);
1444 cirrus_update_bank_ptr(s, 1);
1445 cirrus_update_memory_access(s);
1446 break;
1447 case 0x10: // BGCOLOR 0x0000ff00
1448 case 0x11: // FGCOLOR 0x0000ff00
1449 case 0x12: // BGCOLOR 0x00ff0000
1450 case 0x13: // FGCOLOR 0x00ff0000
1451 case 0x14: // BGCOLOR 0xff000000
1452 case 0x15: // FGCOLOR 0xff000000
1453 case 0x20: // BLT WIDTH 0x0000ff
1454 case 0x22: // BLT HEIGHT 0x0000ff
1455 case 0x24: // BLT DEST PITCH 0x0000ff
1456 case 0x26: // BLT SRC PITCH 0x0000ff
1457 case 0x28: // BLT DEST ADDR 0x0000ff
1458 case 0x29: // BLT DEST ADDR 0x00ff00
1459 case 0x2c: // BLT SRC ADDR 0x0000ff
1460 case 0x2d: // BLT SRC ADDR 0x00ff00
1461 case 0x2f: // BLT WRITEMASK
1462 case 0x30: // BLT MODE
1463 case 0x32: // RASTER OP
1464 case 0x33: // BLT MODEEXT
1465 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1466 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1467 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1468 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1469 s->gr[reg_index] = reg_value;
1470 break;
1471 case 0x21: // BLT WIDTH 0x001f00
1472 case 0x23: // BLT HEIGHT 0x001f00
1473 case 0x25: // BLT DEST PITCH 0x001f00
1474 case 0x27: // BLT SRC PITCH 0x001f00
1475 s->gr[reg_index] = reg_value & 0x1f;
1476 break;
1477 case 0x2a: // BLT DEST ADDR 0x3f0000
1478 s->gr[reg_index] = reg_value & 0x3f;
1479 /* if auto start mode, starts bit blt now */
1480 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1481 cirrus_bitblt_start(s);
1482 }
1483 break;
1484 case 0x2e: // BLT SRC ADDR 0x3f0000
1485 s->gr[reg_index] = reg_value & 0x3f;
1486 break;
1487 case 0x31: // BLT STATUS/START
1488 cirrus_write_bitblt(s, reg_value);
1489 break;
1490 default:
1491 #ifdef DEBUG_CIRRUS
1492 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1493 reg_value);
1494 #endif
1495 break;
1496 }
1497
1498 return CIRRUS_HOOK_HANDLED;
1499 }
1500
1501 /***************************************
1502 *
1503 * I/O access between 0x3d4-0x3d5
1504 *
1505 ***************************************/
1506
1507 static int
1508 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1509 {
1510 switch (reg_index) {
1511 case 0x00: // Standard VGA
1512 case 0x01: // Standard VGA
1513 case 0x02: // Standard VGA
1514 case 0x03: // Standard VGA
1515 case 0x04: // Standard VGA
1516 case 0x05: // Standard VGA
1517 case 0x06: // Standard VGA
1518 case 0x07: // Standard VGA
1519 case 0x08: // Standard VGA
1520 case 0x09: // Standard VGA
1521 case 0x0a: // Standard VGA
1522 case 0x0b: // Standard VGA
1523 case 0x0c: // Standard VGA
1524 case 0x0d: // Standard VGA
1525 case 0x0e: // Standard VGA
1526 case 0x0f: // Standard VGA
1527 case 0x10: // Standard VGA
1528 case 0x11: // Standard VGA
1529 case 0x12: // Standard VGA
1530 case 0x13: // Standard VGA
1531 case 0x14: // Standard VGA
1532 case 0x15: // Standard VGA
1533 case 0x16: // Standard VGA
1534 case 0x17: // Standard VGA
1535 case 0x18: // Standard VGA
1536 return CIRRUS_HOOK_NOT_HANDLED;
1537 case 0x19: // Interlace End
1538 case 0x1a: // Miscellaneous Control
1539 case 0x1b: // Extended Display Control
1540 case 0x1c: // Sync Adjust and Genlock
1541 case 0x1d: // Overlay Extended Control
1542 case 0x22: // Graphics Data Latches Readback (R)
1543 case 0x24: // Attribute Controller Toggle Readback (R)
1544 case 0x25: // Part Status
1545 case 0x27: // Part ID (R)
1546 *reg_value = s->cr[reg_index];
1547 break;
1548 case 0x26: // Attribute Controller Index Readback (R)
1549 *reg_value = s->ar_index & 0x3f;
1550 break;
1551 default:
1552 #ifdef DEBUG_CIRRUS
1553 printf("cirrus: inport cr_index %02x\n", reg_index);
1554 *reg_value = 0xff;
1555 #endif
1556 break;
1557 }
1558
1559 return CIRRUS_HOOK_HANDLED;
1560 }
1561
1562 static int
1563 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1564 {
1565 switch (reg_index) {
1566 case 0x00: // Standard VGA
1567 case 0x01: // Standard VGA
1568 case 0x02: // Standard VGA
1569 case 0x03: // Standard VGA
1570 case 0x04: // Standard VGA
1571 case 0x05: // Standard VGA
1572 case 0x06: // Standard VGA
1573 case 0x07: // Standard VGA
1574 case 0x08: // Standard VGA
1575 case 0x09: // Standard VGA
1576 case 0x0a: // Standard VGA
1577 case 0x0b: // Standard VGA
1578 case 0x0c: // Standard VGA
1579 case 0x0d: // Standard VGA
1580 case 0x0e: // Standard VGA
1581 case 0x0f: // Standard VGA
1582 case 0x10: // Standard VGA
1583 case 0x11: // Standard VGA
1584 case 0x12: // Standard VGA
1585 case 0x13: // Standard VGA
1586 case 0x14: // Standard VGA
1587 case 0x15: // Standard VGA
1588 case 0x16: // Standard VGA
1589 case 0x17: // Standard VGA
1590 case 0x18: // Standard VGA
1591 return CIRRUS_HOOK_NOT_HANDLED;
1592 case 0x19: // Interlace End
1593 case 0x1a: // Miscellaneous Control
1594 case 0x1b: // Extended Display Control
1595 case 0x1c: // Sync Adjust and Genlock
1596 case 0x1d: // Overlay Extended Control
1597 s->cr[reg_index] = reg_value;
1598 #ifdef DEBUG_CIRRUS
1599 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1600 reg_index, reg_value);
1601 #endif
1602 break;
1603 case 0x22: // Graphics Data Latches Readback (R)
1604 case 0x24: // Attribute Controller Toggle Readback (R)
1605 case 0x26: // Attribute Controller Index Readback (R)
1606 case 0x27: // Part ID (R)
1607 break;
1608 case 0x25: // Part Status
1609 default:
1610 #ifdef DEBUG_CIRRUS
1611 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1612 reg_value);
1613 #endif
1614 break;
1615 }
1616
1617 return CIRRUS_HOOK_HANDLED;
1618 }
1619
1620 /***************************************
1621 *
1622 * memory-mapped I/O (bitblt)
1623 *
1624 ***************************************/
1625
1626 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1627 {
1628 int value = 0xff;
1629
1630 switch (address) {
1631 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1632 cirrus_hook_read_gr(s, 0x00, &value);
1633 break;
1634 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1635 cirrus_hook_read_gr(s, 0x10, &value);
1636 break;
1637 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1638 cirrus_hook_read_gr(s, 0x12, &value);
1639 break;
1640 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1641 cirrus_hook_read_gr(s, 0x14, &value);
1642 break;
1643 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1644 cirrus_hook_read_gr(s, 0x01, &value);
1645 break;
1646 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1647 cirrus_hook_read_gr(s, 0x11, &value);
1648 break;
1649 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1650 cirrus_hook_read_gr(s, 0x13, &value);
1651 break;
1652 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1653 cirrus_hook_read_gr(s, 0x15, &value);
1654 break;
1655 case (CIRRUS_MMIO_BLTWIDTH + 0):
1656 cirrus_hook_read_gr(s, 0x20, &value);
1657 break;
1658 case (CIRRUS_MMIO_BLTWIDTH + 1):
1659 cirrus_hook_read_gr(s, 0x21, &value);
1660 break;
1661 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1662 cirrus_hook_read_gr(s, 0x22, &value);
1663 break;
1664 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1665 cirrus_hook_read_gr(s, 0x23, &value);
1666 break;
1667 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1668 cirrus_hook_read_gr(s, 0x24, &value);
1669 break;
1670 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1671 cirrus_hook_read_gr(s, 0x25, &value);
1672 break;
1673 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1674 cirrus_hook_read_gr(s, 0x26, &value);
1675 break;
1676 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1677 cirrus_hook_read_gr(s, 0x27, &value);
1678 break;
1679 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1680 cirrus_hook_read_gr(s, 0x28, &value);
1681 break;
1682 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1683 cirrus_hook_read_gr(s, 0x29, &value);
1684 break;
1685 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1686 cirrus_hook_read_gr(s, 0x2a, &value);
1687 break;
1688 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1689 cirrus_hook_read_gr(s, 0x2c, &value);
1690 break;
1691 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1692 cirrus_hook_read_gr(s, 0x2d, &value);
1693 break;
1694 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1695 cirrus_hook_read_gr(s, 0x2e, &value);
1696 break;
1697 case CIRRUS_MMIO_BLTWRITEMASK:
1698 cirrus_hook_read_gr(s, 0x2f, &value);
1699 break;
1700 case CIRRUS_MMIO_BLTMODE:
1701 cirrus_hook_read_gr(s, 0x30, &value);
1702 break;
1703 case CIRRUS_MMIO_BLTROP:
1704 cirrus_hook_read_gr(s, 0x32, &value);
1705 break;
1706 case CIRRUS_MMIO_BLTMODEEXT:
1707 cirrus_hook_read_gr(s, 0x33, &value);
1708 break;
1709 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1710 cirrus_hook_read_gr(s, 0x34, &value);
1711 break;
1712 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1713 cirrus_hook_read_gr(s, 0x35, &value);
1714 break;
1715 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1716 cirrus_hook_read_gr(s, 0x38, &value);
1717 break;
1718 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1719 cirrus_hook_read_gr(s, 0x39, &value);
1720 break;
1721 case CIRRUS_MMIO_BLTSTATUS:
1722 cirrus_hook_read_gr(s, 0x31, &value);
1723 break;
1724 default:
1725 #ifdef DEBUG_CIRRUS
1726 printf("cirrus: mmio read - address 0x%04x\n", address);
1727 #endif
1728 break;
1729 }
1730
1731 return (uint8_t) value;
1732 }
1733
1734 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1735 uint8_t value)
1736 {
1737 switch (address) {
1738 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1739 cirrus_hook_write_gr(s, 0x00, value);
1740 break;
1741 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1742 cirrus_hook_write_gr(s, 0x10, value);
1743 break;
1744 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1745 cirrus_hook_write_gr(s, 0x12, value);
1746 break;
1747 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1748 cirrus_hook_write_gr(s, 0x14, value);
1749 break;
1750 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1751 cirrus_hook_write_gr(s, 0x01, value);
1752 break;
1753 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1754 cirrus_hook_write_gr(s, 0x11, value);
1755 break;
1756 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1757 cirrus_hook_write_gr(s, 0x13, value);
1758 break;
1759 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1760 cirrus_hook_write_gr(s, 0x15, value);
1761 break;
1762 case (CIRRUS_MMIO_BLTWIDTH + 0):
1763 cirrus_hook_write_gr(s, 0x20, value);
1764 break;
1765 case (CIRRUS_MMIO_BLTWIDTH + 1):
1766 cirrus_hook_write_gr(s, 0x21, value);
1767 break;
1768 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1769 cirrus_hook_write_gr(s, 0x22, value);
1770 break;
1771 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1772 cirrus_hook_write_gr(s, 0x23, value);
1773 break;
1774 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1775 cirrus_hook_write_gr(s, 0x24, value);
1776 break;
1777 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1778 cirrus_hook_write_gr(s, 0x25, value);
1779 break;
1780 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1781 cirrus_hook_write_gr(s, 0x26, value);
1782 break;
1783 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1784 cirrus_hook_write_gr(s, 0x27, value);
1785 break;
1786 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1787 cirrus_hook_write_gr(s, 0x28, value);
1788 break;
1789 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1790 cirrus_hook_write_gr(s, 0x29, value);
1791 break;
1792 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1793 cirrus_hook_write_gr(s, 0x2a, value);
1794 break;
1795 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1796 /* ignored */
1797 break;
1798 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1799 cirrus_hook_write_gr(s, 0x2c, value);
1800 break;
1801 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1802 cirrus_hook_write_gr(s, 0x2d, value);
1803 break;
1804 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1805 cirrus_hook_write_gr(s, 0x2e, value);
1806 break;
1807 case CIRRUS_MMIO_BLTWRITEMASK:
1808 cirrus_hook_write_gr(s, 0x2f, value);
1809 break;
1810 case CIRRUS_MMIO_BLTMODE:
1811 cirrus_hook_write_gr(s, 0x30, value);
1812 break;
1813 case CIRRUS_MMIO_BLTROP:
1814 cirrus_hook_write_gr(s, 0x32, value);
1815 break;
1816 case CIRRUS_MMIO_BLTMODEEXT:
1817 cirrus_hook_write_gr(s, 0x33, value);
1818 break;
1819 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1820 cirrus_hook_write_gr(s, 0x34, value);
1821 break;
1822 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1823 cirrus_hook_write_gr(s, 0x35, value);
1824 break;
1825 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1826 cirrus_hook_write_gr(s, 0x38, value);
1827 break;
1828 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1829 cirrus_hook_write_gr(s, 0x39, value);
1830 break;
1831 case CIRRUS_MMIO_BLTSTATUS:
1832 cirrus_hook_write_gr(s, 0x31, value);
1833 break;
1834 default:
1835 #ifdef DEBUG_CIRRUS
1836 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1837 address, value);
1838 #endif
1839 break;
1840 }
1841 }
1842
1843 /***************************************
1844 *
1845 * write mode 4/5
1846 *
1847 * assume TARGET_PAGE_SIZE >= 16
1848 *
1849 ***************************************/
1850
1851 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1852 unsigned mode,
1853 unsigned offset,
1854 uint32_t mem_value)
1855 {
1856 int x;
1857 unsigned val = mem_value;
1858 uint8_t *dst;
1859
1860 dst = s->vram_ptr + offset;
1861 for (x = 0; x < 8; x++) {
1862 if (val & 0x80) {
1863 *dst = s->cirrus_shadow_gr1;
1864 } else if (mode == 5) {
1865 *dst = s->cirrus_shadow_gr0;
1866 }
1867 val <<= 1;
1868 dst++;
1869 }
1870 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1871 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1872 }
1873
1874 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1875 unsigned mode,
1876 unsigned offset,
1877 uint32_t mem_value)
1878 {
1879 int x;
1880 unsigned val = mem_value;
1881 uint8_t *dst;
1882
1883 dst = s->vram_ptr + offset;
1884 for (x = 0; x < 8; x++) {
1885 if (val & 0x80) {
1886 *dst = s->cirrus_shadow_gr1;
1887 *(dst + 1) = s->gr[0x11];
1888 } else if (mode == 5) {
1889 *dst = s->cirrus_shadow_gr0;
1890 *(dst + 1) = s->gr[0x10];
1891 }
1892 val <<= 1;
1893 dst += 2;
1894 }
1895 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1896 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1897 }
1898
1899 /***************************************
1900 *
1901 * memory access between 0xa0000-0xbffff
1902 *
1903 ***************************************/
1904
1905 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
1906 {
1907 CirrusVGAState *s = opaque;
1908 unsigned bank_index;
1909 unsigned bank_offset;
1910 uint32_t val;
1911
1912 if ((s->sr[0x07] & 0x01) == 0) {
1913 return vga_mem_readb(s, addr);
1914 }
1915
1916 addr &= 0x1ffff;
1917
1918 if (addr < 0x10000) {
1919 /* XXX handle bitblt */
1920 /* video memory */
1921 bank_index = addr >> 15;
1922 bank_offset = addr & 0x7fff;
1923 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
1924 bank_offset += s->cirrus_bank_base[bank_index];
1925 if ((s->gr[0x0B] & 0x14) == 0x14) {
1926 bank_offset <<= 4;
1927 } else if (s->gr[0x0B] & 0x02) {
1928 bank_offset <<= 3;
1929 }
1930 bank_offset &= s->cirrus_addr_mask;
1931 val = *(s->vram_ptr + bank_offset);
1932 } else
1933 val = 0xff;
1934 } else if (addr >= 0x18000 && addr < 0x18100) {
1935 /* memory-mapped I/O */
1936 val = 0xff;
1937 if ((s->sr[0x17] & 0x44) == 0x04) {
1938 val = cirrus_mmio_blt_read(s, addr & 0xff);
1939 }
1940 } else {
1941 val = 0xff;
1942 #ifdef DEBUG_CIRRUS
1943 printf("cirrus: mem_readb %06x\n", addr);
1944 #endif
1945 }
1946 return val;
1947 }
1948
1949 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
1950 {
1951 uint32_t v;
1952 #ifdef TARGET_WORDS_BIGENDIAN
1953 v = cirrus_vga_mem_readb(opaque, addr) << 8;
1954 v |= cirrus_vga_mem_readb(opaque, addr + 1);
1955 #else
1956 v = cirrus_vga_mem_readb(opaque, addr);
1957 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
1958 #endif
1959 return v;
1960 }
1961
1962 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
1963 {
1964 uint32_t v;
1965 #ifdef TARGET_WORDS_BIGENDIAN
1966 v = cirrus_vga_mem_readb(opaque, addr) << 24;
1967 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
1968 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
1969 v |= cirrus_vga_mem_readb(opaque, addr + 3);
1970 #else
1971 v = cirrus_vga_mem_readb(opaque, addr);
1972 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
1973 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
1974 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
1975 #endif
1976 return v;
1977 }
1978
1979 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
1980 uint32_t mem_value)
1981 {
1982 CirrusVGAState *s = opaque;
1983 unsigned bank_index;
1984 unsigned bank_offset;
1985 unsigned mode;
1986
1987 if ((s->sr[0x07] & 0x01) == 0) {
1988 vga_mem_writeb(s, addr, mem_value);
1989 return;
1990 }
1991
1992 addr &= 0x1ffff;
1993
1994 if (addr < 0x10000) {
1995 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
1996 /* bitblt */
1997 *s->cirrus_srcptr++ = (uint8_t) mem_value;
1998 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
1999 cirrus_bitblt_cputovideo_next(s);
2000 }
2001 } else {
2002 /* video memory */
2003 bank_index = addr >> 15;
2004 bank_offset = addr & 0x7fff;
2005 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2006 bank_offset += s->cirrus_bank_base[bank_index];
2007 if ((s->gr[0x0B] & 0x14) == 0x14) {
2008 bank_offset <<= 4;
2009 } else if (s->gr[0x0B] & 0x02) {
2010 bank_offset <<= 3;
2011 }
2012 bank_offset &= s->cirrus_addr_mask;
2013 mode = s->gr[0x05] & 0x7;
2014 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2015 *(s->vram_ptr + bank_offset) = mem_value;
2016 cpu_physical_memory_set_dirty(s->vram_offset +
2017 bank_offset);
2018 } else {
2019 if ((s->gr[0x0B] & 0x14) != 0x14) {
2020 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2021 bank_offset,
2022 mem_value);
2023 } else {
2024 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2025 bank_offset,
2026 mem_value);
2027 }
2028 }
2029 }
2030 }
2031 } else if (addr >= 0x18000 && addr < 0x18100) {
2032 /* memory-mapped I/O */
2033 if ((s->sr[0x17] & 0x44) == 0x04) {
2034 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2035 }
2036 } else {
2037 #ifdef DEBUG_CIRRUS
2038 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2039 #endif
2040 }
2041 }
2042
2043 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2044 {
2045 #ifdef TARGET_WORDS_BIGENDIAN
2046 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2047 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2048 #else
2049 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2050 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2051 #endif
2052 }
2053
2054 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2055 {
2056 #ifdef TARGET_WORDS_BIGENDIAN
2057 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2058 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2059 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2060 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2061 #else
2062 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2063 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2064 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2065 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2066 #endif
2067 }
2068
2069 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2070 cirrus_vga_mem_readb,
2071 cirrus_vga_mem_readw,
2072 cirrus_vga_mem_readl,
2073 };
2074
2075 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2076 cirrus_vga_mem_writeb,
2077 cirrus_vga_mem_writew,
2078 cirrus_vga_mem_writel,
2079 };
2080
2081 /***************************************
2082 *
2083 * hardware cursor
2084 *
2085 ***************************************/
2086
2087 static inline void invalidate_cursor1(CirrusVGAState *s)
2088 {
2089 if (s->last_hw_cursor_size) {
2090 vga_invalidate_scanlines((VGAState *)s,
2091 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2092 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2093 }
2094 }
2095
2096 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2097 {
2098 const uint8_t *src;
2099 uint32_t content;
2100 int y, y_min, y_max;
2101
2102 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2103 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2104 src += (s->sr[0x13] & 0x3c) * 256;
2105 y_min = 64;
2106 y_max = -1;
2107 for(y = 0; y < 64; y++) {
2108 content = ((uint32_t *)src)[0] |
2109 ((uint32_t *)src)[1] |
2110 ((uint32_t *)src)[2] |
2111 ((uint32_t *)src)[3];
2112 if (content) {
2113 if (y < y_min)
2114 y_min = y;
2115 if (y > y_max)
2116 y_max = y;
2117 }
2118 src += 16;
2119 }
2120 } else {
2121 src += (s->sr[0x13] & 0x3f) * 256;
2122 y_min = 32;
2123 y_max = -1;
2124 for(y = 0; y < 32; y++) {
2125 content = ((uint32_t *)src)[0] |
2126 ((uint32_t *)(src + 128))[0];
2127 if (content) {
2128 if (y < y_min)
2129 y_min = y;
2130 if (y > y_max)
2131 y_max = y;
2132 }
2133 src += 4;
2134 }
2135 }
2136 if (y_min > y_max) {
2137 s->last_hw_cursor_y_start = 0;
2138 s->last_hw_cursor_y_end = 0;
2139 } else {
2140 s->last_hw_cursor_y_start = y_min;
2141 s->last_hw_cursor_y_end = y_max + 1;
2142 }
2143 }
2144
2145 /* NOTE: we do not currently handle the cursor bitmap change, so we
2146 update the cursor only if it moves. */
2147 static void cirrus_cursor_invalidate(VGAState *s1)
2148 {
2149 CirrusVGAState *s = (CirrusVGAState *)s1;
2150 int size;
2151
2152 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2153 size = 0;
2154 } else {
2155 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2156 size = 64;
2157 else
2158 size = 32;
2159 }
2160 /* invalidate last cursor and new cursor if any change */
2161 if (s->last_hw_cursor_size != size ||
2162 s->last_hw_cursor_x != s->hw_cursor_x ||
2163 s->last_hw_cursor_y != s->hw_cursor_y) {
2164
2165 invalidate_cursor1(s);
2166
2167 s->last_hw_cursor_size = size;
2168 s->last_hw_cursor_x = s->hw_cursor_x;
2169 s->last_hw_cursor_y = s->hw_cursor_y;
2170 /* compute the real cursor min and max y */
2171 cirrus_cursor_compute_yrange(s);
2172 invalidate_cursor1(s);
2173 }
2174 }
2175
2176 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2177 {
2178 CirrusVGAState *s = (CirrusVGAState *)s1;
2179 int w, h, bpp, x1, x2, poffset;
2180 unsigned int color0, color1;
2181 const uint8_t *palette, *src;
2182 uint32_t content;
2183
2184 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2185 return;
2186 /* fast test to see if the cursor intersects with the scan line */
2187 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2188 h = 64;
2189 } else {
2190 h = 32;
2191 }
2192 if (scr_y < s->hw_cursor_y ||
2193 scr_y >= (s->hw_cursor_y + h))
2194 return;
2195
2196 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2197 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2198 src += (s->sr[0x13] & 0x3c) * 256;
2199 src += (scr_y - s->hw_cursor_y) * 16;
2200 poffset = 8;
2201 content = ((uint32_t *)src)[0] |
2202 ((uint32_t *)src)[1] |
2203 ((uint32_t *)src)[2] |
2204 ((uint32_t *)src)[3];
2205 } else {
2206 src += (s->sr[0x13] & 0x3f) * 256;
2207 src += (scr_y - s->hw_cursor_y) * 4;
2208 poffset = 128;
2209 content = ((uint32_t *)src)[0] |
2210 ((uint32_t *)(src + 128))[0];
2211 }
2212 /* if nothing to draw, no need to continue */
2213 if (!content)
2214 return;
2215 w = h;
2216
2217 x1 = s->hw_cursor_x;
2218 if (x1 >= s->last_scr_width)
2219 return;
2220 x2 = s->hw_cursor_x + w;
2221 if (x2 > s->last_scr_width)
2222 x2 = s->last_scr_width;
2223 w = x2 - x1;
2224 palette = s->cirrus_hidden_palette;
2225 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2226 c6_to_8(palette[0x0 * 3 + 1]),
2227 c6_to_8(palette[0x0 * 3 + 2]));
2228 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2229 c6_to_8(palette[0xf * 3 + 1]),
2230 c6_to_8(palette[0xf * 3 + 2]));
2231 bpp = ((s->ds->depth + 7) >> 3);
2232 d1 += x1 * bpp;
2233 switch(s->ds->depth) {
2234 default:
2235 break;
2236 case 8:
2237 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2238 break;
2239 case 15:
2240 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2241 break;
2242 case 16:
2243 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2244 break;
2245 case 32:
2246 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2247 break;
2248 }
2249 }
2250
2251 /***************************************
2252 *
2253 * LFB memory access
2254 *
2255 ***************************************/
2256
2257 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2258 {
2259 CirrusVGAState *s = (CirrusVGAState *) opaque;
2260 uint32_t ret;
2261
2262 addr &= s->cirrus_addr_mask;
2263
2264 if (((s->sr[0x17] & 0x44) == 0x44) &&
2265 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2266 /* memory-mapped I/O */
2267 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2268 } else if (0) {
2269 /* XXX handle bitblt */
2270 ret = 0xff;
2271 } else {
2272 /* video memory */
2273 if ((s->gr[0x0B] & 0x14) == 0x14) {
2274 addr <<= 4;
2275 } else if (s->gr[0x0B] & 0x02) {
2276 addr <<= 3;
2277 }
2278 addr &= s->cirrus_addr_mask;
2279 ret = *(s->vram_ptr + addr);
2280 }
2281
2282 return ret;
2283 }
2284
2285 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2286 {
2287 uint32_t v;
2288 #ifdef TARGET_WORDS_BIGENDIAN
2289 v = cirrus_linear_readb(opaque, addr) << 8;
2290 v |= cirrus_linear_readb(opaque, addr + 1);
2291 #else
2292 v = cirrus_linear_readb(opaque, addr);
2293 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2294 #endif
2295 return v;
2296 }
2297
2298 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2299 {
2300 uint32_t v;
2301 #ifdef TARGET_WORDS_BIGENDIAN
2302 v = cirrus_linear_readb(opaque, addr) << 24;
2303 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2304 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2305 v |= cirrus_linear_readb(opaque, addr + 3);
2306 #else
2307 v = cirrus_linear_readb(opaque, addr);
2308 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2309 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2310 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2311 #endif
2312 return v;
2313 }
2314
2315 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2316 uint32_t val)
2317 {
2318 CirrusVGAState *s = (CirrusVGAState *) opaque;
2319 unsigned mode;
2320
2321 addr &= s->cirrus_addr_mask;
2322
2323 if (((s->sr[0x17] & 0x44) == 0x44) &&
2324 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2325 /* memory-mapped I/O */
2326 cirrus_mmio_blt_write(s, addr & 0xff, val);
2327 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2328 /* bitblt */
2329 *s->cirrus_srcptr++ = (uint8_t) val;
2330 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2331 cirrus_bitblt_cputovideo_next(s);
2332 }
2333 } else {
2334 /* video memory */
2335 if ((s->gr[0x0B] & 0x14) == 0x14) {
2336 addr <<= 4;
2337 } else if (s->gr[0x0B] & 0x02) {
2338 addr <<= 3;
2339 }
2340 addr &= s->cirrus_addr_mask;
2341
2342 mode = s->gr[0x05] & 0x7;
2343 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2344 *(s->vram_ptr + addr) = (uint8_t) val;
2345 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2346 } else {
2347 if ((s->gr[0x0B] & 0x14) != 0x14) {
2348 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2349 } else {
2350 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2351 }
2352 }
2353 }
2354 }
2355
2356 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2357 uint32_t val)
2358 {
2359 #ifdef TARGET_WORDS_BIGENDIAN
2360 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2361 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2362 #else
2363 cirrus_linear_writeb(opaque, addr, val & 0xff);
2364 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2365 #endif
2366 }
2367
2368 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2369 uint32_t val)
2370 {
2371 #ifdef TARGET_WORDS_BIGENDIAN
2372 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2373 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2374 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2375 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2376 #else
2377 cirrus_linear_writeb(opaque, addr, val & 0xff);
2378 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2379 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2380 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2381 #endif
2382 }
2383
2384
2385 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2386 cirrus_linear_readb,
2387 cirrus_linear_readw,
2388 cirrus_linear_readl,
2389 };
2390
2391 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2392 cirrus_linear_writeb,
2393 cirrus_linear_writew,
2394 cirrus_linear_writel,
2395 };
2396
2397 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2398 uint32_t val)
2399 {
2400 CirrusVGAState *s = (CirrusVGAState *) opaque;
2401
2402 addr &= s->cirrus_addr_mask;
2403 *(s->vram_ptr + addr) = val;
2404 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2405 }
2406
2407 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2408 uint32_t val)
2409 {
2410 CirrusVGAState *s = (CirrusVGAState *) opaque;
2411
2412 addr &= s->cirrus_addr_mask;
2413 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2414 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2415 }
2416
2417 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2418 uint32_t val)
2419 {
2420 CirrusVGAState *s = (CirrusVGAState *) opaque;
2421
2422 addr &= s->cirrus_addr_mask;
2423 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2424 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2425 }
2426
2427 /***************************************
2428 *
2429 * system to screen memory access
2430 *
2431 ***************************************/
2432
2433
2434 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2435 {
2436 uint32_t ret;
2437
2438 /* XXX handle bitblt */
2439 ret = 0xff;
2440 return ret;
2441 }
2442
2443 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2444 {
2445 uint32_t v;
2446 #ifdef TARGET_WORDS_BIGENDIAN
2447 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2448 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2449 #else
2450 v = cirrus_linear_bitblt_readb(opaque, addr);
2451 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2452 #endif
2453 return v;
2454 }
2455
2456 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2457 {
2458 uint32_t v;
2459 #ifdef TARGET_WORDS_BIGENDIAN
2460 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2461 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2462 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2463 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2464 #else
2465 v = cirrus_linear_bitblt_readb(opaque, addr);
2466 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2467 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2468 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2469 #endif
2470 return v;
2471 }
2472
2473 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2474 uint32_t val)
2475 {
2476 CirrusVGAState *s = (CirrusVGAState *) opaque;
2477
2478 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2479 /* bitblt */
2480 *s->cirrus_srcptr++ = (uint8_t) val;
2481 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2482 cirrus_bitblt_cputovideo_next(s);
2483 }
2484 }
2485 }
2486
2487 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2488 uint32_t val)
2489 {
2490 #ifdef TARGET_WORDS_BIGENDIAN
2491 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2492 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2493 #else
2494 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2495 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2496 #endif
2497 }
2498
2499 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2500 uint32_t val)
2501 {
2502 #ifdef TARGET_WORDS_BIGENDIAN
2503 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2504 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2505 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2506 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2507 #else
2508 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2509 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2510 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2511 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2512 #endif
2513 }
2514
2515
2516 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2517 cirrus_linear_bitblt_readb,
2518 cirrus_linear_bitblt_readw,
2519 cirrus_linear_bitblt_readl,
2520 };
2521
2522 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2523 cirrus_linear_bitblt_writeb,
2524 cirrus_linear_bitblt_writew,
2525 cirrus_linear_bitblt_writel,
2526 };
2527
2528 /* Compute the memory access functions */
2529 static void cirrus_update_memory_access(CirrusVGAState *s)
2530 {
2531 unsigned mode;
2532
2533 if ((s->sr[0x17] & 0x44) == 0x44) {
2534 goto generic_io;
2535 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2536 goto generic_io;
2537 } else {
2538 if ((s->gr[0x0B] & 0x14) == 0x14) {
2539 goto generic_io;
2540 } else if (s->gr[0x0B] & 0x02) {
2541 goto generic_io;
2542 }
2543
2544 mode = s->gr[0x05] & 0x7;
2545 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2546 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2547 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2548 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2549 } else {
2550 generic_io:
2551 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2552 s->cirrus_linear_write[1] = cirrus_linear_writew;
2553 s->cirrus_linear_write[2] = cirrus_linear_writel;
2554 }
2555 }
2556 }
2557
2558
2559 /* I/O ports */
2560
2561 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2562 {
2563 CirrusVGAState *s = opaque;
2564 int val, index;
2565
2566 /* check port range access depending on color/monochrome mode */
2567 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2568 || (addr >= 0x3d0 && addr <= 0x3df
2569 && !(s->msr & MSR_COLOR_EMULATION))) {
2570 val = 0xff;
2571 } else {
2572 switch (addr) {
2573 case 0x3c0:
2574 if (s->ar_flip_flop == 0) {
2575 val = s->ar_index;
2576 } else {
2577 val = 0;
2578 }
2579 break;
2580 case 0x3c1:
2581 index = s->ar_index & 0x1f;
2582 if (index < 21)
2583 val = s->ar[index];
2584 else
2585 val = 0;
2586 break;
2587 case 0x3c2:
2588 val = s->st00;
2589 break;
2590 case 0x3c4:
2591 val = s->sr_index;
2592 break;
2593 case 0x3c5:
2594 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2595 break;
2596 val = s->sr[s->sr_index];
2597 #ifdef DEBUG_VGA_REG
2598 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2599 #endif
2600 break;
2601 case 0x3c6:
2602 cirrus_read_hidden_dac(s, &val);
2603 break;
2604 case 0x3c7:
2605 val = s->dac_state;
2606 break;
2607 case 0x3c8:
2608 val = s->dac_write_index;
2609 s->cirrus_hidden_dac_lockindex = 0;
2610 break;
2611 case 0x3c9:
2612 if (cirrus_hook_read_palette(s, &val))
2613 break;
2614 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2615 if (++s->dac_sub_index == 3) {
2616 s->dac_sub_index = 0;
2617 s->dac_read_index++;
2618 }
2619 break;
2620 case 0x3ca:
2621 val = s->fcr;
2622 break;
2623 case 0x3cc:
2624 val = s->msr;
2625 break;
2626 case 0x3ce:
2627 val = s->gr_index;
2628 break;
2629 case 0x3cf:
2630 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2631 break;
2632 val = s->gr[s->gr_index];
2633 #ifdef DEBUG_VGA_REG
2634 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2635 #endif
2636 break;
2637 case 0x3b4:
2638 case 0x3d4:
2639 val = s->cr_index;
2640 break;
2641 case 0x3b5:
2642 case 0x3d5:
2643 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2644 break;
2645 val = s->cr[s->cr_index];
2646 #ifdef DEBUG_VGA_REG
2647 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2648 #endif
2649 break;
2650 case 0x3ba:
2651 case 0x3da:
2652 /* just toggle to fool polling */
2653 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
2654 val = s->st01;
2655 s->ar_flip_flop = 0;
2656 break;
2657 default:
2658 val = 0x00;
2659 break;
2660 }
2661 }
2662 #if defined(DEBUG_VGA)
2663 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2664 #endif
2665 return val;
2666 }
2667
2668 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2669 {
2670 CirrusVGAState *s = opaque;
2671 int index;
2672
2673 /* check port range access depending on color/monochrome mode */
2674 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2675 || (addr >= 0x3d0 && addr <= 0x3df
2676 && !(s->msr & MSR_COLOR_EMULATION)))
2677 return;
2678
2679 #ifdef DEBUG_VGA
2680 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2681 #endif
2682
2683 switch (addr) {
2684 case 0x3c0:
2685 if (s->ar_flip_flop == 0) {
2686 val &= 0x3f;
2687 s->ar_index = val;
2688 } else {
2689 index = s->ar_index & 0x1f;
2690 switch (index) {
2691 case 0x00 ... 0x0f:
2692 s->ar[index] = val & 0x3f;
2693 break;
2694 case 0x10:
2695 s->ar[index] = val & ~0x10;
2696 break;
2697 case 0x11:
2698 s->ar[index] = val;
2699 break;
2700 case 0x12:
2701 s->ar[index] = val & ~0xc0;
2702 break;
2703 case 0x13:
2704 s->ar[index] = val & ~0xf0;
2705 break;
2706 case 0x14:
2707 s->ar[index] = val & ~0xf0;
2708 break;
2709 default:
2710 break;
2711 }
2712 }
2713 s->ar_flip_flop ^= 1;
2714 break;
2715 case 0x3c2:
2716 s->msr = val & ~0x10;
2717 break;
2718 case 0x3c4:
2719 s->sr_index = val;
2720 break;
2721 case 0x3c5:
2722 if (cirrus_hook_write_sr(s, s->sr_index, val))
2723 break;
2724 #ifdef DEBUG_VGA_REG
2725 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2726 #endif
2727 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2728 break;
2729 case 0x3c6:
2730 cirrus_write_hidden_dac(s, val);
2731 break;
2732 case 0x3c7:
2733 s->dac_read_index = val;
2734 s->dac_sub_index = 0;
2735 s->dac_state = 3;
2736 break;
2737 case 0x3c8:
2738 s->dac_write_index = val;
2739 s->dac_sub_index = 0;
2740 s->dac_state = 0;
2741 break;
2742 case 0x3c9:
2743 if (cirrus_hook_write_palette(s, val))
2744 break;
2745 s->dac_cache[s->dac_sub_index] = val;
2746 if (++s->dac_sub_index == 3) {
2747 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2748 s->dac_sub_index = 0;
2749 s->dac_write_index++;
2750 }
2751 break;
2752 case 0x3ce:
2753 s->gr_index = val;
2754 break;
2755 case 0x3cf:
2756 if (cirrus_hook_write_gr(s, s->gr_index, val))
2757 break;
2758 #ifdef DEBUG_VGA_REG
2759 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2760 #endif
2761 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2762 break;
2763 case 0x3b4:
2764 case 0x3d4:
2765 s->cr_index = val;
2766 break;
2767 case 0x3b5:
2768 case 0x3d5:
2769 if (cirrus_hook_write_cr(s, s->cr_index, val))
2770 break;
2771 #ifdef DEBUG_VGA_REG
2772 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2773 #endif
2774 /* handle CR0-7 protection */
2775 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2776 /* can always write bit 4 of CR7 */
2777 if (s->cr_index == 7)
2778 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2779 return;
2780 }
2781 switch (s->cr_index) {
2782 case 0x01: /* horizontal display end */
2783 case 0x07:
2784 case 0x09:
2785 case 0x0c:
2786 case 0x0d:
2787 case 0x12: /* veritcal display end */
2788 s->cr[s->cr_index] = val;
2789 break;
2790
2791 default:
2792 s->cr[s->cr_index] = val;
2793 break;
2794 }
2795 break;
2796 case 0x3ba:
2797 case 0x3da:
2798 s->fcr = val & 0x10;
2799 break;
2800 }
2801 }
2802
2803 /***************************************
2804 *
2805 * memory-mapped I/O access
2806 *
2807 ***************************************/
2808
2809 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2810 {
2811 CirrusVGAState *s = (CirrusVGAState *) opaque;
2812
2813 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2814
2815 if (addr >= 0x100) {
2816 return cirrus_mmio_blt_read(s, addr - 0x100);
2817 } else {
2818 return vga_ioport_read(s, addr + 0x3c0);
2819 }
2820 }
2821
2822 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2823 {
2824 uint32_t v;
2825 #ifdef TARGET_WORDS_BIGENDIAN
2826 v = cirrus_mmio_readb(opaque, addr) << 8;
2827 v |= cirrus_mmio_readb(opaque, addr + 1);
2828 #else
2829 v = cirrus_mmio_readb(opaque, addr);
2830 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2831 #endif
2832 return v;
2833 }
2834
2835 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2836 {
2837 uint32_t v;
2838 #ifdef TARGET_WORDS_BIGENDIAN
2839 v = cirrus_mmio_readb(opaque, addr) << 24;
2840 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
2841 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
2842 v |= cirrus_mmio_readb(opaque, addr + 3);
2843 #else
2844 v = cirrus_mmio_readb(opaque, addr);
2845 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2846 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
2847 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
2848 #endif
2849 return v;
2850 }
2851
2852 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
2853 uint32_t val)
2854 {
2855 CirrusVGAState *s = (CirrusVGAState *) opaque;
2856
2857 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2858
2859 if (addr >= 0x100) {
2860 cirrus_mmio_blt_write(s, addr - 0x100, val);
2861 } else {
2862 vga_ioport_write(s, addr + 0x3c0, val);
2863 }
2864 }
2865
2866 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
2867 uint32_t val)
2868 {
2869 #ifdef TARGET_WORDS_BIGENDIAN
2870 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
2871 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
2872 #else
2873 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2874 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2875 #endif
2876 }
2877
2878 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
2879 uint32_t val)
2880 {
2881 #ifdef TARGET_WORDS_BIGENDIAN
2882 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
2883 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2884 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2885 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
2886 #else
2887 cirrus_mmio_writeb(opaque, addr, val & 0xff);
2888 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2889 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2890 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2891 #endif
2892 }
2893
2894
2895 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
2896 cirrus_mmio_readb,
2897 cirrus_mmio_readw,
2898 cirrus_mmio_readl,
2899 };
2900
2901 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
2902 cirrus_mmio_writeb,
2903 cirrus_mmio_writew,
2904 cirrus_mmio_writel,
2905 };
2906
2907 /* load/save state */
2908
2909 static void cirrus_vga_save(QEMUFile *f, void *opaque)
2910 {
2911 CirrusVGAState *s = opaque;
2912
2913 if (s->pci_dev)
2914 pci_device_save(s->pci_dev, f);
2915
2916 qemu_put_be32s(f, &s->latch);
2917 qemu_put_8s(f, &s->sr_index);
2918 qemu_put_buffer(f, s->sr, 256);
2919 qemu_put_8s(f, &s->gr_index);
2920 qemu_put_8s(f, &s->cirrus_shadow_gr0);
2921 qemu_put_8s(f, &s->cirrus_shadow_gr1);
2922 qemu_put_buffer(f, s->gr + 2, 254);
2923 qemu_put_8s(f, &s->ar_index);
2924 qemu_put_buffer(f, s->ar, 21);
2925 qemu_put_be32s(f, &s->ar_flip_flop);
2926 qemu_put_8s(f, &s->cr_index);
2927 qemu_put_buffer(f, s->cr, 256);
2928 qemu_put_8s(f, &s->msr);
2929 qemu_put_8s(f, &s->fcr);
2930 qemu_put_8s(f, &s->st00);
2931 qemu_put_8s(f, &s->st01);
2932
2933 qemu_put_8s(f, &s->dac_state);
2934 qemu_put_8s(f, &s->dac_sub_index);
2935 qemu_put_8s(f, &s->dac_read_index);
2936 qemu_put_8s(f, &s->dac_write_index);
2937 qemu_put_buffer(f, s->dac_cache, 3);
2938 qemu_put_buffer(f, s->palette, 768);
2939
2940 qemu_put_be32s(f, &s->bank_offset);
2941
2942 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
2943 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
2944
2945 qemu_put_be32s(f, &s->hw_cursor_x);
2946 qemu_put_be32s(f, &s->hw_cursor_y);
2947 /* XXX: we do not save the bitblt state - we assume we do not save
2948 the state when the blitter is active */
2949 }
2950
2951 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
2952 {
2953 CirrusVGAState *s = opaque;
2954 int ret;
2955
2956 if (version_id > 2)
2957 return -EINVAL;
2958
2959 if (s->pci_dev && version_id >= 2) {
2960 ret = pci_device_load(s->pci_dev, f);
2961 if (ret < 0)
2962 return ret;
2963 }
2964
2965 qemu_get_be32s(f, &s->latch);
2966 qemu_get_8s(f, &s->sr_index);
2967 qemu_get_buffer(f, s->sr, 256);
2968 qemu_get_8s(f, &s->gr_index);
2969 qemu_get_8s(f, &s->cirrus_shadow_gr0);
2970 qemu_get_8s(f, &s->cirrus_shadow_gr1);
2971 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2972 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2973 qemu_get_buffer(f, s->gr + 2, 254);
2974 qemu_get_8s(f, &s->ar_index);
2975 qemu_get_buffer(f, s->ar, 21);
2976 qemu_get_be32s(f, &s->ar_flip_flop);
2977 qemu_get_8s(f, &s->cr_index);
2978 qemu_get_buffer(f, s->cr, 256);
2979 qemu_get_8s(f, &s->msr);
2980 qemu_get_8s(f, &s->fcr);
2981 qemu_get_8s(f, &s->st00);
2982 qemu_get_8s(f, &s->st01);
2983
2984 qemu_get_8s(f, &s->dac_state);
2985 qemu_get_8s(f, &s->dac_sub_index);
2986 qemu_get_8s(f, &s->dac_read_index);
2987 qemu_get_8s(f, &s->dac_write_index);
2988 qemu_get_buffer(f, s->dac_cache, 3);
2989 qemu_get_buffer(f, s->palette, 768);
2990
2991 qemu_get_be32s(f, &s->bank_offset);
2992
2993 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
2994 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
2995
2996 qemu_get_be32s(f, &s->hw_cursor_x);
2997 qemu_get_be32s(f, &s->hw_cursor_y);
2998
2999 /* force refresh */
3000 s->graphic_mode = -1;
3001 cirrus_update_bank_ptr(s, 0);
3002 cirrus_update_bank_ptr(s, 1);
3003 return 0;
3004 }
3005
3006 /***************************************
3007 *
3008 * initialize
3009 *
3010 ***************************************/
3011
3012 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3013 {
3014 int vga_io_memory, i;
3015 static int inited;
3016
3017 if (!inited) {
3018 inited = 1;
3019 for(i = 0;i < 256; i++)
3020 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3021 rop_to_index[CIRRUS_ROP_0] = 0;
3022 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3023 rop_to_index[CIRRUS_ROP_NOP] = 2;
3024 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3025 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3026 rop_to_index[CIRRUS_ROP_SRC] = 5;
3027 rop_to_index[CIRRUS_ROP_1] = 6;
3028 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3029 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3030 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3031 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3032 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3033 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3034 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3035 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3036 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3037 }
3038
3039 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3040
3041 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3042 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3043 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3044 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3045
3046 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3047
3048 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3049 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3050 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3051 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3052
3053 vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3054 cirrus_vga_mem_write, s);
3055 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3056 vga_io_memory);
3057
3058 s->sr[0x06] = 0x0f;
3059 if (device_id == CIRRUS_ID_CLGD5446) {
3060 /* 4MB 64 bit memory config, always PCI */
3061 s->sr[0x1F] = 0x2d; // MemClock
3062 s->gr[0x18] = 0x0f; // fastest memory configuration
3063 #if 1
3064 s->sr[0x0f] = 0x98;
3065 s->sr[0x17] = 0x20;
3066 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3067 s->real_vram_size = 4096 * 1024;
3068 #else
3069 s->sr[0x0f] = 0x18;
3070 s->sr[0x17] = 0x20;
3071 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3072 s->real_vram_size = 2048 * 1024;
3073 #endif
3074 } else {
3075 s->sr[0x1F] = 0x22; // MemClock
3076 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3077 if (is_pci)
3078 s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3079 else
3080 s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3081 s->real_vram_size = 2048 * 1024;
3082 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3083 }
3084 s->cr[0x27] = device_id;
3085
3086 /* Win2K seems to assume that the pattern buffer is at 0xff
3087 initially ! */
3088 memset(s->vram_ptr, 0xff, s->real_vram_size);
3089
3090 s->cirrus_hidden_dac_lockindex = 5;
3091 s->cirrus_hidden_dac_data = 0;
3092
3093 /* I/O handler for LFB */
3094 s->cirrus_linear_io_addr =
3095 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3096 s);
3097 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3098
3099 /* I/O handler for LFB */
3100 s->cirrus_linear_bitblt_io_addr =
3101 cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3102 s);
3103
3104 /* I/O handler for memory-mapped I/O */
3105 s->cirrus_mmio_io_addr =
3106 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3107
3108 /* XXX: s->vram_size must be a power of two */
3109 s->cirrus_addr_mask = s->real_vram_size - 1;
3110 s->linear_mmio_mask = s->real_vram_size - 256;
3111
3112 s->get_bpp = cirrus_get_bpp;
3113 s->get_offsets = cirrus_get_offsets;
3114 s->get_resolution = cirrus_get_resolution;
3115 s->cursor_invalidate = cirrus_cursor_invalidate;
3116 s->cursor_draw_line = cirrus_cursor_draw_line;
3117
3118 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3119 }
3120
3121 /***************************************
3122 *
3123 * ISA bus support
3124 *
3125 ***************************************/
3126
3127 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3128 unsigned long vga_ram_offset, int vga_ram_size)
3129 {
3130 CirrusVGAState *s;
3131
3132 s = qemu_mallocz(sizeof(CirrusVGAState));
3133
3134 vga_common_init((VGAState *)s,
3135 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3136 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3137 /* XXX ISA-LFB support */
3138 }
3139
3140 /***************************************
3141 *
3142 * PCI bus support
3143 *
3144 ***************************************/
3145
3146 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3147 uint32_t addr, uint32_t size, int type)
3148 {
3149 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3150
3151 /* XXX: add byte swapping apertures */
3152 cpu_register_physical_memory(addr, s->vram_size,
3153 s->cirrus_linear_io_addr);
3154 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3155 s->cirrus_linear_bitblt_io_addr);
3156 }
3157
3158 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3159 uint32_t addr, uint32_t size, int type)
3160 {
3161 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3162
3163 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3164 s->cirrus_mmio_io_addr);
3165 }
3166
3167 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3168 unsigned long vga_ram_offset, int vga_ram_size)
3169 {
3170 PCICirrusVGAState *d;
3171 uint8_t *pci_conf;
3172 CirrusVGAState *s;
3173 int device_id;
3174
3175 device_id = CIRRUS_ID_CLGD5446;
3176
3177 /* setup PCI configuration registers */
3178 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3179 sizeof(PCICirrusVGAState),
3180 -1, NULL, NULL);
3181 pci_conf = d->dev.config;
3182 pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3183 pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3184 pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3185 pci_conf[0x03] = (uint8_t) (device_id >> 8);
3186 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3187 pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3188 pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3189 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3190
3191 /* setup VGA */
3192 s = &d->cirrus_vga;
3193 vga_common_init((VGAState *)s,
3194 ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3195 cirrus_init_common(s, device_id, 1);
3196 s->pci_dev = (PCIDevice *)d;
3197
3198 /* setup memory space */
3199 /* memory #0 LFB */
3200 /* memory #1 memory-mapped I/O */
3201 /* XXX: s->vram_size must be a power of two */
3202 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3203 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3204 if (device_id == CIRRUS_ID_CLGD5446) {
3205 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3206 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3207 }
3208 /* XXX: ROM BIOS */
3209 }
Samsung s3c2440 and arm920t support for the mini2440 dev board