hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19 #include "vl.h"
  20
  21 //#define DEBUG
  22
  23 /* i82731AB (PIIX4) compatible power management function */
  24 #define PM_FREQ 3579545
  25
  26 #define ACPI_DBG_IO_ADDR  0xb044
  27 #define SMB_IO_BASE       0xb100
  28
  29 typedef struct PIIX4PMState {
  30     PCIDevice dev;
  31     uint16_t pmsts;
  32     uint16_t pmen;
  33     uint16_t pmcntrl;
  34     uint8_t apmc;
  35     uint8_t apms;
  36     QEMUTimer *tmr_timer;
  37     int64_t tmr_overflow_time;
  38     SMBusDevice *smb_dev[128];
  39     uint8_t smb_stat;
  40     uint8_t smb_ctl;
  41     uint8_t smb_cmd;
  42     uint8_t smb_addr;
  43     uint8_t smb_data0;
  44     uint8_t smb_data1;
  45     uint8_t smb_data[32];
  46     uint8_t smb_index;
  47 } PIIX4PMState;
  48
  49 #define RTC_EN (1 << 10)
  50 #define PWRBTN_EN (1 << 8)
  51 #define GBL_EN (1 << 5)
  52 #define TMROF_EN (1 << 0)
  53
  54 #define SCI_EN (1 << 0)
  55
  56 #define SUS_EN (1 << 13)
  57
  58 #define SMBHSTSTS 0x00
  59 #define SMBHSTCNT 0x02
  60 #define SMBHSTCMD 0x03
  61 #define SMBHSTADD 0x04
  62 #define SMBHSTDAT0 0x05
  63 #define SMBHSTDAT1 0x06
  64 #define SMBBLKDAT 0x07
  65
  66 /* Note: only used for piix4_smbus_register_device */
  67 static PIIX4PMState *piix4_pm_state;
  68
  69 static uint32_t get_pmtmr(PIIX4PMState *s)
  70 {
  71     uint32_t d;
  72     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  73     return d & 0xffffff;
  74 }
  75
  76 static int get_pmsts(PIIX4PMState *s)
  77 {
  78     int64_t d;
  79     int pmsts;
  80     pmsts = s->pmsts;
  81     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  82     if (d >= s->tmr_overflow_time)
  83         s->pmsts |= TMROF_EN;
  84     return pmsts;
  85 }
  86
  87 static void pm_update_sci(PIIX4PMState *s)
  88 {
  89     int sci_level, pmsts;
  90     int64_t expire_time;
  91
  92     pmsts = get_pmsts(s);
  93     sci_level = (((pmsts & s->pmen) &
  94                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
  95     pci_set_irq(&s->dev, 0, sci_level);
  96     /* schedule a timer interruption if needed */
  97     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
  98         expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
  99         qemu_mod_timer(s->tmr_timer, expire_time);
 100     } else {
 101         qemu_del_timer(s->tmr_timer);
 102     }
 103 }
 104
 105 static void pm_tmr_timer(void *opaque)
 106 {
 107     PIIX4PMState *s = opaque;
 108     pm_update_sci(s);
 109 }
 110
 111 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 112 {
 113     PIIX4PMState *s = opaque;
 114     addr &= 0x3f;
 115     switch(addr) {
 116     case 0x00:
 117         {
 118             int64_t d;
 119             int pmsts;
 120             pmsts = get_pmsts(s);
 121             if (pmsts & val & TMROF_EN) {
 122                 /* if TMRSTS is reset, then compute the new overflow time */
 123                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
 124                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 125             }
 126             s->pmsts &= ~val;
 127             pm_update_sci(s);
 128         }
 129         break;
 130     case 0x02:
 131         s->pmen = val;
 132         pm_update_sci(s);
 133         break;
 134     case 0x04:
 135         {
 136             int sus_typ;
 137             s->pmcntrl = val & ~(SUS_EN);
 138             if (val & SUS_EN) {
 139                 /* change suspend type */
 140                 sus_typ = (val >> 10) & 3;
 141                 switch(sus_typ) {
 142                 case 0: /* soft power off */
 143                     qemu_system_shutdown_request();
 144                     break;
 145                 default:
 146                     break;
 147                 }
 148             }
 149         }
 150         break;
 151     default:
 152         break;
 153     }
 154 #ifdef DEBUG
 155     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 156 #endif
 157 }
 158
 159 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 160 {
 161     PIIX4PMState *s = opaque;
 162     uint32_t val;
 163
 164     addr &= 0x3f;
 165     switch(addr) {
 166     case 0x00:
 167         val = get_pmsts(s);
 168         break;
 169     case 0x02:
 170         val = s->pmen;
 171         break;
 172     case 0x04:
 173         val = s->pmcntrl;
 174         break;
 175     default:
 176         val = 0;
 177         break;
 178     }
 179 #ifdef DEBUG
 180     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 181 #endif
 182     return val;
 183 }
 184
 185 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 186 {
 187     //    PIIX4PMState *s = opaque;
 188     addr &= 0x3f;
 189 #ifdef DEBUG
 190     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 191 #endif
 192 }
 193
 194 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 195 {
 196     PIIX4PMState *s = opaque;
 197     uint32_t val;
 198
 199     addr &= 0x3f;
 200     switch(addr) {
 201     case 0x08:
 202         val = get_pmtmr(s);
 203         break;
 204     default:
 205         val = 0;
 206         break;
 207     }
 208 #ifdef DEBUG
 209     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 210 #endif
 211     return val;
 212 }
 213
 214 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 215 {
 216     PIIX4PMState *s = opaque;
 217     addr &= 1;
 218 #ifdef DEBUG
 219     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 220 #endif
 221     if (addr == 0) {
 222         s->apmc = val;
 223         if (s->dev.config[0x5b] & (1 << 1)) {
 224             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 225         }
 226     } else {
 227         s->apms = val;
 228     }
 229 }
 230
 231 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 232 {
 233     PIIX4PMState *s = opaque;
 234     uint32_t val;
 235
 236     addr &= 1;
 237     if (addr == 0) {
 238         val = s->apmc;
 239     } else {
 240         val = s->apms;
 241     }
 242 #ifdef DEBUG
 243     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 244 #endif
 245     return val;
 246 }
 247
 248 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 249 {
 250 #if defined(DEBUG)
 251     printf("ACPI: DBG: 0x%08x\n", val);
 252 #endif
 253 }
 254
 255 static void smb_transaction(PIIX4PMState *s)
 256 {
 257     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 258     uint8_t read = s->smb_addr & 0x01;
 259     uint8_t cmd = s->smb_cmd;
 260     uint8_t addr = s->smb_addr >> 1;
 261     SMBusDevice *dev = s->smb_dev[addr];
 262
 263 #ifdef DEBUG
 264     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 265 #endif
 266     if (!dev) goto error;
 267
 268     switch(prot) {
 269     case 0x0:
 270         if (!dev->quick_cmd) goto error;
 271         (*dev->quick_cmd)(dev, read);
 272         break;
 273     case 0x1:
 274         if (read) {
 275             if (!dev->receive_byte) goto error;
 276             s->smb_data0 = (*dev->receive_byte)(dev);
 277         }
 278         else {
 279             if (!dev->send_byte) goto error;
 280             (*dev->send_byte)(dev, cmd);
 281         }
 282         break;
 283     case 0x2:
 284         if (read) {
 285             if (!dev->read_byte) goto error;
 286             s->smb_data0 = (*dev->read_byte)(dev, cmd);
 287         }
 288         else {
 289             if (!dev->write_byte) goto error;
 290             (*dev->write_byte)(dev, cmd, s->smb_data0);
 291         }
 292         break;
 293     case 0x3:
 294         if (read) {
 295             uint16_t val;
 296             if (!dev->read_word) goto error;
 297             val = (*dev->read_word)(dev, cmd);
 298             s->smb_data0 = val;
 299             s->smb_data1 = val >> 8;
 300         }
 301         else {
 302             if (!dev->write_word) goto error;
 303             (*dev->write_word)(dev, cmd, (s->smb_data1 << 8) | s->smb_data0);
 304         }
 305         break;
 306     case 0x5:
 307         if (read) {
 308             if (!dev->read_block) goto error;
 309             s->smb_data0 = (*dev->read_block)(dev, cmd, s->smb_data);
 310         }
 311         else {
 312             if (!dev->write_block) goto error;
 313             (*dev->write_block)(dev, cmd, s->smb_data0, s->smb_data);
 314         }
 315         break;
 316     default:
 317         goto error;
 318     }
 319     return;
 320
 321   error:
 322     s->smb_stat |= 0x04;
 323 }
 324
 325 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 326 {
 327     PIIX4PMState *s = opaque;
 328     addr &= 0x3f;
 329 #ifdef DEBUG
 330     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 331 #endif
 332     switch(addr) {
 333     case SMBHSTSTS:
 334         s->smb_stat = 0;
 335         s->smb_index = 0;
 336         break;
 337     case SMBHSTCNT:
 338         s->smb_ctl = val;
 339         if (val & 0x40)
 340             smb_transaction(s);
 341         break;
 342     case SMBHSTCMD:
 343         s->smb_cmd = val;
 344         break;
 345     case SMBHSTADD:
 346         s->smb_addr = val;
 347         break;
 348     case SMBHSTDAT0:
 349         s->smb_data0 = val;
 350         break;
 351     case SMBHSTDAT1:
 352         s->smb_data1 = val;
 353         break;
 354     case SMBBLKDAT:
 355         s->smb_data[s->smb_index++] = val;
 356         if (s->smb_index > 31)
 357             s->smb_index = 0;
 358         break;
 359     default:
 360         break;
 361     }
 362 }
 363
 364 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 365 {
 366     PIIX4PMState *s = opaque;
 367     uint32_t val;
 368
 369     addr &= 0x3f;
 370     switch(addr) {
 371     case SMBHSTSTS:
 372         val = s->smb_stat;
 373         break;
 374     case SMBHSTCNT:
 375         s->smb_index = 0;
 376         val = s->smb_ctl & 0x1f;
 377         break;
 378     case SMBHSTCMD:
 379         val = s->smb_cmd;
 380         break;
 381     case SMBHSTADD:
 382         val = s->smb_addr;
 383         break;
 384     case SMBHSTDAT0:
 385         val = s->smb_data0;
 386         break;
 387     case SMBHSTDAT1:
 388         val = s->smb_data1;
 389         break;
 390     case SMBBLKDAT:
 391         val = s->smb_data[s->smb_index++];
 392         if (s->smb_index > 31)
 393             s->smb_index = 0;
 394         break;
 395     default:
 396         val = 0;
 397         break;
 398     }
 399 #ifdef DEBUG
 400     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 401 #endif
 402     return val;
 403 }
 404
 405 static void pm_io_space_update(PIIX4PMState *s)
 406 {
 407     uint32_t pm_io_base;
 408
 409     if (s->dev.config[0x80] & 1) {
 410         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 411         pm_io_base &= 0xfffe;
 412
 413         /* XXX: need to improve memory and ioport allocation */
 414 #if defined(DEBUG)
 415         printf("PM: mapping to 0x%x\n", pm_io_base);
 416 #endif
 417         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 418         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 419         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 420         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 421     }
 422 }
 423
 424 static void pm_write_config(PCIDevice *d,
 425                             uint32_t address, uint32_t val, int len)
 426 {
 427     pci_default_write_config(d, address, val, len);
 428     if (address == 0x80)
 429         pm_io_space_update((PIIX4PMState *)d);
 430 }
 431
 432 static void pm_save(QEMUFile* f,void *opaque)
 433 {
 434     PIIX4PMState *s = opaque;
 435
 436     pci_device_save(&s->dev, f);
 437
 438     qemu_put_be16s(f, &s->pmsts);
 439     qemu_put_be16s(f, &s->pmen);
 440     qemu_put_be16s(f, &s->pmcntrl);
 441     qemu_put_8s(f, &s->apmc);
 442     qemu_put_8s(f, &s->apms);
 443     qemu_put_timer(f, s->tmr_timer);
 444     qemu_put_be64s(f, &s->tmr_overflow_time);
 445 }
 446
 447 static int pm_load(QEMUFile* f,void* opaque,int version_id)
 448 {
 449     PIIX4PMState *s = opaque;
 450     int ret;
 451
 452     if (version_id > 1)
 453         return -EINVAL;
 454
 455     ret = pci_device_load(&s->dev, f);
 456     if (ret < 0)
 457         return ret;
 458
 459     qemu_get_be16s(f, &s->pmsts);
 460     qemu_get_be16s(f, &s->pmen);
 461     qemu_get_be16s(f, &s->pmcntrl);
 462     qemu_get_8s(f, &s->apmc);
 463     qemu_get_8s(f, &s->apms);
 464     qemu_get_timer(f, s->tmr_timer);
 465     qemu_get_be64s(f, &s->tmr_overflow_time);
 466
 467     pm_io_space_update(s);
 468
 469     return 0;
 470 }
 471
 472 void piix4_pm_init(PCIBus *bus, int devfn)
 473 {
 474     PIIX4PMState *s;
 475     uint8_t *pci_conf;
 476     uint32_t pm_io_base, smb_io_base;
 477
 478     s = (PIIX4PMState *)pci_register_device(bus,
 479                                          "PM", sizeof(PIIX4PMState),
 480                                          devfn, NULL, pm_write_config);
 481     pci_conf = s->dev.config;
 482     pci_conf[0x00] = 0x86;
 483     pci_conf[0x01] = 0x80;
 484     pci_conf[0x02] = 0x13;
 485     pci_conf[0x03] = 0x71;
 486     pci_conf[0x08] = 0x00; // revision number
 487     pci_conf[0x09] = 0x00;
 488     pci_conf[0x0a] = 0x80; // other bridge device
 489     pci_conf[0x0b] = 0x06; // bridge device
 490     pci_conf[0x0e] = 0x00; // header_type
 491     pci_conf[0x3d] = 0x01; // interrupt pin 1
 492
 493     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 494
 495     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 496     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 497
 498     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 499
 500     /* XXX: which specification is used ? The i82731AB has different
 501        mappings */
 502     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 503     pci_conf[0x63] = 0x60;
 504     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 505         (serial_hds[1] != NULL ? 0x90 : 0);
 506
 507     smb_io_base = SMB_IO_BASE;
 508     pci_conf[0x90] = smb_io_base | 1;
 509     pci_conf[0x91] = smb_io_base >> 8;
 510     pci_conf[0xd2] = 0x09;
 511     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 512     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 513
 514     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 515
 516     register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
 517     piix4_pm_state = s;
 518 }
 519
 520 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr)
 521 {
 522     piix4_pm_state->smb_dev[addr] = dev;
 523 }