2 * QEMU Sun4u/Sun4v System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "qemu-timer.h"
33 #include "firmware_abi.h"
39 #define DPRINTF(fmt, args...) \
40 do { printf("CPUIRQ: " fmt , ##args); } while (0)
42 #define DPRINTF(fmt, args...)
45 #define KERNEL_LOAD_ADDR 0x00404000
46 #define CMDLINE_ADDR 0x003ff000
47 #define INITRD_LOAD_ADDR 0x00300000
48 #define PROM_SIZE_MAX (4 * 1024 * 1024)
49 #define PROM_VADDR 0x000ffd00000ULL
50 #define APB_SPECIAL_BASE 0x1fe00000000ULL
51 #define APB_MEM_BASE 0x1ff00000000ULL
52 #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
53 #define PROM_FILENAME "openbios-sparc64"
54 #define NVRAM_SIZE 0x2000
56 #define BIOS_CFG_IOPORT 0x510
61 const char * const default_cpu_model
;
64 uint64_t console_serial_base
;
67 int DMA_get_channel_mode (int nchan
)
71 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
75 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
79 void DMA_hold_DREQ (int nchan
) {}
80 void DMA_release_DREQ (int nchan
) {}
81 void DMA_schedule(int nchan
) {}
82 void DMA_init (int high_page_enable
) {}
83 void DMA_register_channel (int nchan
,
84 DMA_transfer_handler transfer_handler
,
89 static int nvram_boot_set(void *opaque
, const char *boot_device
)
92 uint8_t image
[sizeof(ohwcfg_v3_t
)];
93 ohwcfg_v3_t
*header
= (ohwcfg_v3_t
*)&image
;
94 m48t59_t
*nvram
= (m48t59_t
*)opaque
;
96 for (i
= 0; i
< sizeof(image
); i
++)
97 image
[i
] = m48t59_read(nvram
, i
) & 0xff;
99 pstrcpy((char *)header
->boot_devices
, sizeof(header
->boot_devices
),
101 header
->nboot_devices
= strlen(boot_device
) & 0xff;
102 header
->crc
= cpu_to_be16(OHW_compute_crc(header
, 0x00, 0xF8));
104 for (i
= 0; i
< sizeof(image
); i
++)
105 m48t59_write(nvram
, i
, image
[i
]);
110 static int sun4u_NVRAM_set_params (m48t59_t
*nvram
, uint16_t NVRAM_size
,
113 const char *boot_devices
,
114 uint32_t kernel_image
, uint32_t kernel_size
,
116 uint32_t initrd_image
, uint32_t initrd_size
,
117 uint32_t NVRAM_image
,
118 int width
, int height
, int depth
,
119 const uint8_t *macaddr
)
123 uint8_t image
[0x1ff0];
124 ohwcfg_v3_t
*header
= (ohwcfg_v3_t
*)&image
;
125 struct sparc_arch_cfg
*sparc_header
;
126 struct OpenBIOS_nvpart_v1
*part_header
;
128 memset(image
, '\0', sizeof(image
));
130 // Try to match PPC NVRAM
131 pstrcpy((char *)header
->struct_ident
, sizeof(header
->struct_ident
),
133 header
->struct_version
= cpu_to_be32(3); /* structure v3 */
135 header
->nvram_size
= cpu_to_be16(NVRAM_size
);
136 header
->nvram_arch_ptr
= cpu_to_be16(sizeof(ohwcfg_v3_t
));
137 header
->nvram_arch_size
= cpu_to_be16(sizeof(struct sparc_arch_cfg
));
138 pstrcpy((char *)header
->arch
, sizeof(header
->arch
), arch
);
139 header
->nb_cpus
= smp_cpus
& 0xff;
140 header
->RAM0_base
= 0;
141 header
->RAM0_size
= cpu_to_be64((uint64_t)RAM_size
);
142 pstrcpy((char *)header
->boot_devices
, sizeof(header
->boot_devices
),
144 header
->nboot_devices
= strlen(boot_devices
) & 0xff;
145 header
->kernel_image
= cpu_to_be64((uint64_t)kernel_image
);
146 header
->kernel_size
= cpu_to_be64((uint64_t)kernel_size
);
148 pstrcpy_targphys(CMDLINE_ADDR
, TARGET_PAGE_SIZE
, cmdline
);
149 header
->cmdline
= cpu_to_be64((uint64_t)CMDLINE_ADDR
);
150 header
->cmdline_size
= cpu_to_be64((uint64_t)strlen(cmdline
));
152 header
->initrd_image
= cpu_to_be64((uint64_t)initrd_image
);
153 header
->initrd_size
= cpu_to_be64((uint64_t)initrd_size
);
154 header
->NVRAM_image
= cpu_to_be64((uint64_t)NVRAM_image
);
156 header
->width
= cpu_to_be16(width
);
157 header
->height
= cpu_to_be16(height
);
158 header
->depth
= cpu_to_be16(depth
);
160 header
->graphic_flags
= cpu_to_be16(OHW_GF_NOGRAPHICS
);
162 header
->crc
= cpu_to_be16(OHW_compute_crc(header
, 0x00, 0xF8));
164 // Architecture specific header
165 start
= sizeof(ohwcfg_v3_t
);
166 sparc_header
= (struct sparc_arch_cfg
*)&image
[start
];
167 sparc_header
->valid
= 0;
168 start
+= sizeof(struct sparc_arch_cfg
);
170 // OpenBIOS nvram variables
171 // Variable partition
172 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
173 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
174 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
176 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
177 for (i
= 0; i
< nb_prom_envs
; i
++)
178 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
183 end
= start
+ ((end
- start
+ 15) & ~15);
184 OpenBIOS_finish_partition(part_header
, end
- start
);
188 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
189 part_header
->signature
= OPENBIOS_PART_FREE
;
190 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
193 OpenBIOS_finish_partition(part_header
, end
- start
);
195 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
, 0x80);
197 for (i
= 0; i
< sizeof(image
); i
++)
198 m48t59_write(nvram
, i
, image
[i
]);
200 qemu_register_boot_set(nvram_boot_set
, nvram
);
213 void cpu_check_irqs(CPUState
*env
)
215 uint32_t pil
= env
->pil_in
| (env
->softint
& ~SOFTINT_TIMER
) |
216 ((env
->softint
& SOFTINT_TIMER
) << 14);
218 if (pil
&& (env
->interrupt_index
== 0 ||
219 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
222 for (i
= 15; i
> 0; i
--) {
223 if (pil
& (1 << i
)) {
224 int old_interrupt
= env
->interrupt_index
;
226 env
->interrupt_index
= TT_EXTINT
| i
;
227 if (old_interrupt
!= env
->interrupt_index
) {
228 DPRINTF("Set CPU IRQ %d\n", i
);
229 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
234 } else if (!pil
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
235 DPRINTF("Reset CPU IRQ %d\n", env
->interrupt_index
& 15);
236 env
->interrupt_index
= 0;
237 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
241 static void cpu_set_irq(void *opaque
, int irq
, int level
)
243 CPUState
*env
= opaque
;
246 DPRINTF("Raise CPU IRQ %d\n", irq
);
248 env
->pil_in
|= 1 << irq
;
251 DPRINTF("Lower CPU IRQ %d\n", irq
);
252 env
->pil_in
&= ~(1 << irq
);
257 void qemu_system_powerdown(void)
261 typedef struct ResetData
{
266 static void main_cpu_reset(void *opaque
)
268 ResetData
*s
= (ResetData
*)opaque
;
269 CPUState
*env
= s
->env
;
272 ptimer_set_limit(env
->tick
, 0x7fffffffffffffffULL
, 1);
273 ptimer_run(env
->tick
, 0);
274 ptimer_set_limit(env
->stick
, 0x7fffffffffffffffULL
, 1);
275 ptimer_run(env
->stick
, 0);
276 ptimer_set_limit(env
->hstick
, 0x7fffffffffffffffULL
, 1);
277 ptimer_run(env
->hstick
, 0);
278 env
->gregs
[1] = 0; // Memory start
279 env
->gregs
[2] = ram_size
; // Memory size
280 env
->gregs
[3] = 0; // Machine description XXX
281 env
->pc
= s
->reset_addr
;
282 env
->npc
= env
->pc
+ 4;
285 static void tick_irq(void *opaque
)
287 CPUState
*env
= opaque
;
289 env
->softint
|= SOFTINT_TIMER
;
290 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
293 static void stick_irq(void *opaque
)
295 CPUState
*env
= opaque
;
297 env
->softint
|= SOFTINT_TIMER
;
298 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
301 static void hstick_irq(void *opaque
)
303 CPUState
*env
= opaque
;
305 env
->softint
|= SOFTINT_TIMER
;
306 cpu_interrupt(env
, CPU_INTERRUPT_TIMER
);
309 void cpu_tick_set_count(void *opaque
, uint64_t count
)
311 ptimer_set_count(opaque
, -count
);
314 uint64_t cpu_tick_get_count(void *opaque
)
316 return -ptimer_get_count(opaque
);
319 void cpu_tick_set_limit(void *opaque
, uint64_t limit
)
321 ptimer_set_limit(opaque
, -limit
, 0);
324 static const int ide_iobase
[2] = { 0x1f0, 0x170 };
325 static const int ide_iobase2
[2] = { 0x3f6, 0x376 };
326 static const int ide_irq
[2] = { 14, 15 };
328 static const int serial_io
[MAX_SERIAL_PORTS
] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
329 static const int serial_irq
[MAX_SERIAL_PORTS
] = { 4, 3, 4, 3 };
331 static const int parallel_io
[MAX_PARALLEL_PORTS
] = { 0x378, 0x278, 0x3bc };
332 static const int parallel_irq
[MAX_PARALLEL_PORTS
] = { 7, 7, 7 };
334 static fdctrl_t
*floppy_controller
;
336 static void sun4uv_init(ram_addr_t RAM_size
, int vga_ram_size
,
337 const char *boot_devices
, DisplayState
*ds
,
338 const char *kernel_filename
, const char *kernel_cmdline
,
339 const char *initrd_filename
, const char *cpu_model
,
340 const struct hwdef
*hwdef
)
347 long prom_offset
, initrd_size
, kernel_size
;
352 BlockDriverState
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
353 BlockDriverState
*fd
[MAX_FD
];
355 ResetData
*reset_info
;
357 linux_boot
= (kernel_filename
!= NULL
);
361 cpu_model
= hwdef
->default_cpu_model
;
363 env
= cpu_init(cpu_model
);
365 fprintf(stderr
, "Unable to find Sparc CPU definition\n");
368 bh
= qemu_bh_new(tick_irq
, env
);
369 env
->tick
= ptimer_init(bh
);
370 ptimer_set_period(env
->tick
, 1ULL);
372 bh
= qemu_bh_new(stick_irq
, env
);
373 env
->stick
= ptimer_init(bh
);
374 ptimer_set_period(env
->stick
, 1ULL);
376 bh
= qemu_bh_new(hstick_irq
, env
);
377 env
->hstick
= ptimer_init(bh
);
378 ptimer_set_period(env
->hstick
, 1ULL);
380 reset_info
= qemu_mallocz(sizeof(ResetData
));
381 reset_info
->env
= env
;
382 reset_info
->reset_addr
= hwdef
->prom_addr
+ 0x40ULL
;
383 qemu_register_reset(main_cpu_reset
, reset_info
);
384 main_cpu_reset(reset_info
);
385 // Override warm reset address with cold start address
386 env
->pc
= hwdef
->prom_addr
+ 0x20ULL
;
387 env
->npc
= env
->pc
+ 4;
390 cpu_register_physical_memory(0, RAM_size
, 0);
392 prom_offset
= RAM_size
+ vga_ram_size
;
393 cpu_register_physical_memory(hwdef
->prom_addr
,
394 (PROM_SIZE_MAX
+ TARGET_PAGE_SIZE
) &
396 prom_offset
| IO_MEM_ROM
);
398 if (bios_name
== NULL
)
399 bios_name
= PROM_FILENAME
;
400 snprintf(buf
, sizeof(buf
), "%s/%s", bios_dir
, bios_name
);
401 ret
= load_elf(buf
, hwdef
->prom_addr
- PROM_VADDR
, NULL
, NULL
, NULL
);
403 ret
= load_image_targphys(buf
, hwdef
->prom_addr
,
404 (PROM_SIZE_MAX
+ TARGET_PAGE_SIZE
) &
407 fprintf(stderr
, "qemu: could not load prom '%s'\n",
416 /* XXX: put correct offset */
417 kernel_size
= load_elf(kernel_filename
, 0, NULL
, NULL
, NULL
);
419 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
420 ram_size
- KERNEL_LOAD_ADDR
);
422 kernel_size
= load_image_targphys(kernel_filename
,
424 ram_size
- KERNEL_LOAD_ADDR
);
425 if (kernel_size
< 0) {
426 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
432 if (initrd_filename
) {
433 initrd_size
= load_image_targphys(initrd_filename
,
435 ram_size
- INITRD_LOAD_ADDR
);
436 if (initrd_size
< 0) {
437 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
442 if (initrd_size
> 0) {
443 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
444 if (ldl_phys(KERNEL_LOAD_ADDR
+ i
) == 0x48647253) { // HdrS
445 stl_phys(KERNEL_LOAD_ADDR
+ i
+ 16, INITRD_LOAD_ADDR
);
446 stl_phys(KERNEL_LOAD_ADDR
+ i
+ 20, initrd_size
);
452 pci_bus
= pci_apb_init(APB_SPECIAL_BASE
, APB_MEM_BASE
, NULL
);
453 isa_mem_base
= VGA_BASE
;
454 pci_cirrus_vga_init(pci_bus
, ds
, phys_ram_base
+ RAM_size
, RAM_size
,
458 if (hwdef
->console_serial_base
) {
459 serial_mm_init(hwdef
->console_serial_base
, 0, NULL
, 115200,
463 for(; i
< MAX_SERIAL_PORTS
; i
++) {
465 serial_init(serial_io
[i
], NULL
/*serial_irq[i]*/, 115200,
470 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
471 if (parallel_hds
[i
]) {
472 parallel_init(parallel_io
[i
], NULL
/*parallel_irq[i]*/,
477 for(i
= 0; i
< nb_nics
; i
++) {
478 if (!nd_table
[i
].model
)
479 nd_table
[i
].model
= "ne2k_pci";
480 pci_nic_init(pci_bus
, &nd_table
[i
], -1);
483 irq
= qemu_allocate_irqs(cpu_set_irq
, env
, MAX_PILS
);
484 if (drive_get_max_bus(IF_IDE
) >= MAX_IDE_BUS
) {
485 fprintf(stderr
, "qemu: too many IDE bus\n");
488 for(i
= 0; i
< MAX_IDE_BUS
* MAX_IDE_DEVS
; i
++) {
489 drive_index
= drive_get_index(IF_IDE
, i
/ MAX_IDE_DEVS
,
491 if (drive_index
!= -1)
492 hd
[i
] = drives_table
[drive_index
].bdrv
;
497 // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
498 pci_piix3_ide_init(pci_bus
, hd
, -1, irq
);
499 /* FIXME: wire up interrupts. */
500 i8042_init(NULL
/*1*/, NULL
/*12*/, 0x60);
501 for(i
= 0; i
< MAX_FD
; i
++) {
502 drive_index
= drive_get_index(IF_FLOPPY
, 0, i
);
503 if (drive_index
!= -1)
504 fd
[i
] = drives_table
[drive_index
].bdrv
;
508 floppy_controller
= fdctrl_init(NULL
/*6*/, 2, 0, 0x3f0, fd
);
509 nvram
= m48t59_init(NULL
/*8*/, 0, 0x0074, NVRAM_SIZE
, 59);
510 sun4u_NVRAM_set_params(nvram
, NVRAM_SIZE
, "Sun4u", RAM_size
, boot_devices
,
511 KERNEL_LOAD_ADDR
, kernel_size
,
513 INITRD_LOAD_ADDR
, initrd_size
,
514 /* XXX: need an option to load a NVRAM image */
516 graphic_width
, graphic_height
, graphic_depth
,
517 (uint8_t *)&nd_table
[0].macaddr
);
519 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
520 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
521 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
522 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
531 static const struct hwdef hwdefs
[] = {
532 /* Sun4u generic PC-like machine */
534 .default_cpu_model
= "TI UltraSparc II",
535 .machine_id
= sun4u_id
,
536 .prom_addr
= 0x1fff0000000ULL
,
537 .console_serial_base
= 0,
539 /* Sun4v generic PC-like machine */
541 .default_cpu_model
= "Sun UltraSparc T1",
542 .machine_id
= sun4v_id
,
543 .prom_addr
= 0x1fff0000000ULL
,
544 .console_serial_base
= 0,
546 /* Sun4v generic Niagara machine */
548 .default_cpu_model
= "Sun UltraSparc T1",
549 .machine_id
= niagara_id
,
550 .prom_addr
= 0xfff0000000ULL
,
551 .console_serial_base
= 0xfff0c2c000ULL
,
555 /* Sun4u hardware initialisation */
556 static void sun4u_init(ram_addr_t RAM_size
, int vga_ram_size
,
557 const char *boot_devices
, DisplayState
*ds
,
558 const char *kernel_filename
, const char *kernel_cmdline
,
559 const char *initrd_filename
, const char *cpu_model
)
561 sun4uv_init(RAM_size
, vga_ram_size
, boot_devices
, ds
, kernel_filename
,
562 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[0]);
565 /* Sun4v hardware initialisation */
566 static void sun4v_init(ram_addr_t RAM_size
, int vga_ram_size
,
567 const char *boot_devices
, DisplayState
*ds
,
568 const char *kernel_filename
, const char *kernel_cmdline
,
569 const char *initrd_filename
, const char *cpu_model
)
571 sun4uv_init(RAM_size
, vga_ram_size
, boot_devices
, ds
, kernel_filename
,
572 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[1]);
575 /* Niagara hardware initialisation */
576 static void niagara_init(ram_addr_t RAM_size
, int vga_ram_size
,
577 const char *boot_devices
, DisplayState
*ds
,
578 const char *kernel_filename
, const char *kernel_cmdline
,
579 const char *initrd_filename
, const char *cpu_model
)
581 sun4uv_init(RAM_size
, vga_ram_size
, boot_devices
, ds
, kernel_filename
,
582 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[2]);
585 QEMUMachine sun4u_machine
= {
587 .desc
= "Sun4u platform",
589 .ram_require
= PROM_SIZE_MAX
+ VGA_RAM_SIZE
,
591 .max_cpus
= 1, // XXX for now
594 QEMUMachine sun4v_machine
= {
596 .desc
= "Sun4v platform",
598 .ram_require
= PROM_SIZE_MAX
+ VGA_RAM_SIZE
,
600 .max_cpus
= 1, // XXX for now
603 QEMUMachine niagara_machine
= {
605 .desc
= "Sun4v platform, Niagara",
606 .init
= niagara_init
,
607 .ram_require
= PROM_SIZE_MAX
+ VGA_RAM_SIZE
,
609 .max_cpus
= 1, // XXX for now