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Attached patch contains warning fixes.
[qemu/mini2440.git] / hw / ppc405_uc.c
blob25bcfd82fca6efaa54bdd7830fbca607a7749b55
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30 #include "qemu-log.h"
31
32 #define DEBUG_OPBA
33 #define DEBUG_SDRAM
34 #define DEBUG_GPIO
35 #define DEBUG_SERIAL
36 #define DEBUG_OCM
37 //#define DEBUG_I2C
38 #define DEBUG_GPT
39 #define DEBUG_MAL
40 #define DEBUG_CLOCKS
41 //#define DEBUG_CLOCKS_LL
42
43 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
44 uint32_t flags)
45 {
46 ram_addr_t bdloc;
47 int i, n;
48
49 /* We put the bd structure at the top of memory */
50 if (bd->bi_memsize >= 0x01000000UL)
51 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
52 else
53 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
54 stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);
55 stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);
56 stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);
57 stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);
58 stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);
59 stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);
60 stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);
61 stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);
62 stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);
63 for (i = 0; i < 6; i++)
64 stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);
65 stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);
66 stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);
67 stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);
68 stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);
69 for (i = 0; i < 4; i++)
70 stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);
71 for (i = 0; i < 32; i++)
72 stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);
73 stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);
74 stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);
75 for (i = 0; i < 6; i++)
76 stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
77 n = 0x6A;
78 if (flags & 0x00000001) {
79 for (i = 0; i < 6; i++)
80 stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);
81 }
82 stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);
83 n += 4;
84 for (i = 0; i < 2; i++) {
85 stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);
86 n += 4;
87 }
88
89 return bdloc;
90 }
91
92 /*****************************************************************************/
93 /* Shared peripherals */
94
95 /*****************************************************************************/
96 /* Peripheral local bus arbitrer */
97 enum {
98 PLB0_BESR = 0x084,
99 PLB0_BEAR = 0x086,
100 PLB0_ACR = 0x087,
101 };
102
103 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
104 struct ppc4xx_plb_t {
105 uint32_t acr;
106 uint32_t bear;
107 uint32_t besr;
108 };
109
110 static target_ulong dcr_read_plb (void *opaque, int dcrn)
111 {
112 ppc4xx_plb_t *plb;
113 target_ulong ret;
114
115 plb = opaque;
116 switch (dcrn) {
117 case PLB0_ACR:
118 ret = plb->acr;
119 break;
120 case PLB0_BEAR:
121 ret = plb->bear;
122 break;
123 case PLB0_BESR:
124 ret = plb->besr;
125 break;
126 default:
127 /* Avoid gcc warning */
128 ret = 0;
129 break;
130 }
131
132 return ret;
133 }
134
135 static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
136 {
137 ppc4xx_plb_t *plb;
138
139 plb = opaque;
140 switch (dcrn) {
141 case PLB0_ACR:
142 /* We don't care about the actual parameters written as
143 * we don't manage any priorities on the bus
144 */
145 plb->acr = val & 0xF8000000;
146 break;
147 case PLB0_BEAR:
148 /* Read only */
149 break;
150 case PLB0_BESR:
151 /* Write-clear */
152 plb->besr &= ~val;
153 break;
154 }
155 }
156
157 static void ppc4xx_plb_reset (void *opaque)
158 {
159 ppc4xx_plb_t *plb;
160
161 plb = opaque;
162 plb->acr = 0x00000000;
163 plb->bear = 0x00000000;
164 plb->besr = 0x00000000;
165 }
166
167 void ppc4xx_plb_init (CPUState *env)
168 {
169 ppc4xx_plb_t *plb;
170
171 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
172 if (plb != NULL) {
173 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
174 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
175 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
176 ppc4xx_plb_reset(plb);
177 qemu_register_reset(ppc4xx_plb_reset, plb);
178 }
179 }
180
181 /*****************************************************************************/
182 /* PLB to OPB bridge */
183 enum {
184 POB0_BESR0 = 0x0A0,
185 POB0_BESR1 = 0x0A2,
186 POB0_BEAR = 0x0A4,
187 };
188
189 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
190 struct ppc4xx_pob_t {
191 uint32_t bear;
192 uint32_t besr[2];
193 };
194
195 static target_ulong dcr_read_pob (void *opaque, int dcrn)
196 {
197 ppc4xx_pob_t *pob;
198 target_ulong ret;
199
200 pob = opaque;
201 switch (dcrn) {
202 case POB0_BEAR:
203 ret = pob->bear;
204 break;
205 case POB0_BESR0:
206 case POB0_BESR1:
207 ret = pob->besr[dcrn - POB0_BESR0];
208 break;
209 default:
210 /* Avoid gcc warning */
211 ret = 0;
212 break;
213 }
214
215 return ret;
216 }
217
218 static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
219 {
220 ppc4xx_pob_t *pob;
221
222 pob = opaque;
223 switch (dcrn) {
224 case POB0_BEAR:
225 /* Read only */
226 break;
227 case POB0_BESR0:
228 case POB0_BESR1:
229 /* Write-clear */
230 pob->besr[dcrn - POB0_BESR0] &= ~val;
231 break;
232 }
233 }
234
235 static void ppc4xx_pob_reset (void *opaque)
236 {
237 ppc4xx_pob_t *pob;
238
239 pob = opaque;
240 /* No error */
241 pob->bear = 0x00000000;
242 pob->besr[0] = 0x0000000;
243 pob->besr[1] = 0x0000000;
244 }
245
246 void ppc4xx_pob_init (CPUState *env)
247 {
248 ppc4xx_pob_t *pob;
249
250 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
251 if (pob != NULL) {
252 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
253 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
254 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
255 qemu_register_reset(ppc4xx_pob_reset, pob);
256 ppc4xx_pob_reset(env);
257 }
258 }
259
260 /*****************************************************************************/
261 /* OPB arbitrer */
262 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
263 struct ppc4xx_opba_t {
264 target_phys_addr_t base;
265 uint8_t cr;
266 uint8_t pr;
267 };
268
269 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
270 {
271 ppc4xx_opba_t *opba;
272 uint32_t ret;
273
274 #ifdef DEBUG_OPBA
275 printf("%s: addr " PADDRX "\n", __func__, addr);
276 #endif
277 opba = opaque;
278 switch (addr - opba->base) {
279 case 0x00:
280 ret = opba->cr;
281 break;
282 case 0x01:
283 ret = opba->pr;
284 break;
285 default:
286 ret = 0x00;
287 break;
288 }
289
290 return ret;
291 }
292
293 static void opba_writeb (void *opaque,
294 target_phys_addr_t addr, uint32_t value)
295 {
296 ppc4xx_opba_t *opba;
297
298 #ifdef DEBUG_OPBA
299 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
300 #endif
301 opba = opaque;
302 switch (addr - opba->base) {
303 case 0x00:
304 opba->cr = value & 0xF8;
305 break;
306 case 0x01:
307 opba->pr = value & 0xFF;
308 break;
309 default:
310 break;
311 }
312 }
313
314 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
315 {
316 uint32_t ret;
317
318 #ifdef DEBUG_OPBA
319 printf("%s: addr " PADDRX "\n", __func__, addr);
320 #endif
321 ret = opba_readb(opaque, addr) << 8;
322 ret |= opba_readb(opaque, addr + 1);
323
324 return ret;
325 }
326
327 static void opba_writew (void *opaque,
328 target_phys_addr_t addr, uint32_t value)
329 {
330 #ifdef DEBUG_OPBA
331 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
332 #endif
333 opba_writeb(opaque, addr, value >> 8);
334 opba_writeb(opaque, addr + 1, value);
335 }
336
337 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
338 {
339 uint32_t ret;
340
341 #ifdef DEBUG_OPBA
342 printf("%s: addr " PADDRX "\n", __func__, addr);
343 #endif
344 ret = opba_readb(opaque, addr) << 24;
345 ret |= opba_readb(opaque, addr + 1) << 16;
346
347 return ret;
348 }
349
350 static void opba_writel (void *opaque,
351 target_phys_addr_t addr, uint32_t value)
352 {
353 #ifdef DEBUG_OPBA
354 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
355 #endif
356 opba_writeb(opaque, addr, value >> 24);
357 opba_writeb(opaque, addr + 1, value >> 16);
358 }
359
360 static CPUReadMemoryFunc *opba_read[] = {
361 &opba_readb,
362 &opba_readw,
363 &opba_readl,
364 };
365
366 static CPUWriteMemoryFunc *opba_write[] = {
367 &opba_writeb,
368 &opba_writew,
369 &opba_writel,
370 };
371
372 static void ppc4xx_opba_reset (void *opaque)
373 {
374 ppc4xx_opba_t *opba;
375
376 opba = opaque;
377 opba->cr = 0x00; /* No dynamic priorities - park disabled */
378 opba->pr = 0x11;
379 }
380
381 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
382 target_phys_addr_t offset)
383 {
384 ppc4xx_opba_t *opba;
385
386 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
387 if (opba != NULL) {
388 opba->base = offset;
389 #ifdef DEBUG_OPBA
390 printf("%s: offset " PADDRX "\n", __func__, offset);
391 #endif
392 ppc4xx_mmio_register(env, mmio, offset, 0x002,
393 opba_read, opba_write, opba);
394 qemu_register_reset(ppc4xx_opba_reset, opba);
395 ppc4xx_opba_reset(opba);
396 }
397 }
398
399 /*****************************************************************************/
400 /* Code decompression controller */
401 /* XXX: TODO */
402
403 /*****************************************************************************/
404 /* SDRAM controller */
405 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
406 struct ppc4xx_sdram_t {
407 uint32_t addr;
408 int nbanks;
409 target_phys_addr_t ram_bases[4];
410 target_phys_addr_t ram_sizes[4];
411 uint32_t besr0;
412 uint32_t besr1;
413 uint32_t bear;
414 uint32_t cfg;
415 uint32_t status;
416 uint32_t rtr;
417 uint32_t pmit;
418 uint32_t bcr[4];
419 uint32_t tr;
420 uint32_t ecccfg;
421 uint32_t eccesr;
422 qemu_irq irq;
423 };
424
425 enum {
426 SDRAM0_CFGADDR = 0x010,
427 SDRAM0_CFGDATA = 0x011,
428 };
429
430 /* XXX: TOFIX: some patches have made this code become inconsistent:
431 * there are type inconsistencies, mixing target_phys_addr_t, target_ulong
432 * and uint32_t
433 */
434 static uint32_t sdram_bcr (target_phys_addr_t ram_base,
435 target_phys_addr_t ram_size)
436 {
437 uint32_t bcr;
438
439 switch (ram_size) {
440 case (4 * 1024 * 1024):
441 bcr = 0x00000000;
442 break;
443 case (8 * 1024 * 1024):
444 bcr = 0x00020000;
445 break;
446 case (16 * 1024 * 1024):
447 bcr = 0x00040000;
448 break;
449 case (32 * 1024 * 1024):
450 bcr = 0x00060000;
451 break;
452 case (64 * 1024 * 1024):
453 bcr = 0x00080000;
454 break;
455 case (128 * 1024 * 1024):
456 bcr = 0x000A0000;
457 break;
458 case (256 * 1024 * 1024):
459 bcr = 0x000C0000;
460 break;
461 default:
462 printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
463 return 0x00000000;
464 }
465 bcr |= ram_base & 0xFF800000;
466 bcr |= 1;
467
468 return bcr;
469 }
470
471 static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
472 {
473 return bcr & 0xFF800000;
474 }
475
476 static target_ulong sdram_size (uint32_t bcr)
477 {
478 target_ulong size;
479 int sh;
480
481 sh = (bcr >> 17) & 0x7;
482 if (sh == 7)
483 size = -1;
484 else
485 size = (4 * 1024 * 1024) << sh;
486
487 return size;
488 }
489
490 static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
491 {
492 if (*bcrp & 0x00000001) {
493 /* Unmap RAM */
494 #ifdef DEBUG_SDRAM
495 printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
496 __func__, sdram_base(*bcrp), sdram_size(*bcrp));
497 #endif
498 cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
499 IO_MEM_UNASSIGNED);
500 }
501 *bcrp = bcr & 0xFFDEE001;
502 if (enabled && (bcr & 0x00000001)) {
503 #ifdef DEBUG_SDRAM
504 printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
505 __func__, sdram_base(bcr), sdram_size(bcr));
506 #endif
507 cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
508 sdram_base(bcr) | IO_MEM_RAM);
509 }
510 }
511
512 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
513 {
514 int i;
515
516 for (i = 0; i < sdram->nbanks; i++) {
517 if (sdram->ram_sizes[i] != 0) {
518 sdram_set_bcr(&sdram->bcr[i],
519 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
520 1);
521 } else {
522 sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
523 }
524 }
525 }
526
527 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
528 {
529 int i;
530
531 for (i = 0; i < sdram->nbanks; i++) {
532 #ifdef DEBUG_SDRAM
533 printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
534 __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
535 #endif
536 cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
537 sdram_size(sdram->bcr[i]),
538 IO_MEM_UNASSIGNED);
539 }
540 }
541
542 static target_ulong dcr_read_sdram (void *opaque, int dcrn)
543 {
544 ppc4xx_sdram_t *sdram;
545 target_ulong ret;
546
547 sdram = opaque;
548 switch (dcrn) {
549 case SDRAM0_CFGADDR:
550 ret = sdram->addr;
551 break;
552 case SDRAM0_CFGDATA:
553 switch (sdram->addr) {
554 case 0x00: /* SDRAM_BESR0 */
555 ret = sdram->besr0;
556 break;
557 case 0x08: /* SDRAM_BESR1 */
558 ret = sdram->besr1;
559 break;
560 case 0x10: /* SDRAM_BEAR */
561 ret = sdram->bear;
562 break;
563 case 0x20: /* SDRAM_CFG */
564 ret = sdram->cfg;
565 break;
566 case 0x24: /* SDRAM_STATUS */
567 ret = sdram->status;
568 break;
569 case 0x30: /* SDRAM_RTR */
570 ret = sdram->rtr;
571 break;
572 case 0x34: /* SDRAM_PMIT */
573 ret = sdram->pmit;
574 break;
575 case 0x40: /* SDRAM_B0CR */
576 ret = sdram->bcr[0];
577 break;
578 case 0x44: /* SDRAM_B1CR */
579 ret = sdram->bcr[1];
580 break;
581 case 0x48: /* SDRAM_B2CR */
582 ret = sdram->bcr[2];
583 break;
584 case 0x4C: /* SDRAM_B3CR */
585 ret = sdram->bcr[3];
586 break;
587 case 0x80: /* SDRAM_TR */
588 ret = -1; /* ? */
589 break;
590 case 0x94: /* SDRAM_ECCCFG */
591 ret = sdram->ecccfg;
592 break;
593 case 0x98: /* SDRAM_ECCESR */
594 ret = sdram->eccesr;
595 break;
596 default: /* Error */
597 ret = -1;
598 break;
599 }
600 break;
601 default:
602 /* Avoid gcc warning */
603 ret = 0x00000000;
604 break;
605 }
606
607 return ret;
608 }
609
610 static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
611 {
612 ppc4xx_sdram_t *sdram;
613
614 sdram = opaque;
615 switch (dcrn) {
616 case SDRAM0_CFGADDR:
617 sdram->addr = val;
618 break;
619 case SDRAM0_CFGDATA:
620 switch (sdram->addr) {
621 case 0x00: /* SDRAM_BESR0 */
622 sdram->besr0 &= ~val;
623 break;
624 case 0x08: /* SDRAM_BESR1 */
625 sdram->besr1 &= ~val;
626 break;
627 case 0x10: /* SDRAM_BEAR */
628 sdram->bear = val;
629 break;
630 case 0x20: /* SDRAM_CFG */
631 val &= 0xFFE00000;
632 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
633 #ifdef DEBUG_SDRAM
634 printf("%s: enable SDRAM controller\n", __func__);
635 #endif
636 /* validate all RAM mappings */
637 sdram_map_bcr(sdram);
638 sdram->status &= ~0x80000000;
639 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
640 #ifdef DEBUG_SDRAM
641 printf("%s: disable SDRAM controller\n", __func__);
642 #endif
643 /* invalidate all RAM mappings */
644 sdram_unmap_bcr(sdram);
645 sdram->status |= 0x80000000;
646 }
647 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
648 sdram->status |= 0x40000000;
649 else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
650 sdram->status &= ~0x40000000;
651 sdram->cfg = val;
652 break;
653 case 0x24: /* SDRAM_STATUS */
654 /* Read-only register */
655 break;
656 case 0x30: /* SDRAM_RTR */
657 sdram->rtr = val & 0x3FF80000;
658 break;
659 case 0x34: /* SDRAM_PMIT */
660 sdram->pmit = (val & 0xF8000000) | 0x07C00000;
661 break;
662 case 0x40: /* SDRAM_B0CR */
663 sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
664 break;
665 case 0x44: /* SDRAM_B1CR */
666 sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
667 break;
668 case 0x48: /* SDRAM_B2CR */
669 sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
670 break;
671 case 0x4C: /* SDRAM_B3CR */
672 sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
673 break;
674 case 0x80: /* SDRAM_TR */
675 sdram->tr = val & 0x018FC01F;
676 break;
677 case 0x94: /* SDRAM_ECCCFG */
678 sdram->ecccfg = val & 0x00F00000;
679 break;
680 case 0x98: /* SDRAM_ECCESR */
681 val &= 0xFFF0F000;
682 if (sdram->eccesr == 0 && val != 0)
683 qemu_irq_raise(sdram->irq);
684 else if (sdram->eccesr != 0 && val == 0)
685 qemu_irq_lower(sdram->irq);
686 sdram->eccesr = val;
687 break;
688 default: /* Error */
689 break;
690 }
691 break;
692 }
693 }
694
695 static void sdram_reset (void *opaque)
696 {
697 ppc4xx_sdram_t *sdram;
698
699 sdram = opaque;
700 sdram->addr = 0x00000000;
701 sdram->bear = 0x00000000;
702 sdram->besr0 = 0x00000000; /* No error */
703 sdram->besr1 = 0x00000000; /* No error */
704 sdram->cfg = 0x00000000;
705 sdram->ecccfg = 0x00000000; /* No ECC */
706 sdram->eccesr = 0x00000000; /* No error */
707 sdram->pmit = 0x07C00000;
708 sdram->rtr = 0x05F00000;
709 sdram->tr = 0x00854009;
710 /* We pre-initialize RAM banks */
711 sdram->status = 0x00000000;
712 sdram->cfg = 0x00800000;
713 sdram_unmap_bcr(sdram);
714 }
715
716 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
717 target_phys_addr_t *ram_bases,
718 target_phys_addr_t *ram_sizes,
719 int do_init)
720 {
721 ppc4xx_sdram_t *sdram;
722
723 sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
724 if (sdram != NULL) {
725 sdram->irq = irq;
726 sdram->nbanks = nbanks;
727 memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
728 memcpy(sdram->ram_bases, ram_bases,
729 nbanks * sizeof(target_phys_addr_t));
730 memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
731 memcpy(sdram->ram_sizes, ram_sizes,
732 nbanks * sizeof(target_phys_addr_t));
733 sdram_reset(sdram);
734 qemu_register_reset(&sdram_reset, sdram);
735 ppc_dcr_register(env, SDRAM0_CFGADDR,
736 sdram, &dcr_read_sdram, &dcr_write_sdram);
737 ppc_dcr_register(env, SDRAM0_CFGDATA,
738 sdram, &dcr_read_sdram, &dcr_write_sdram);
739 if (do_init)
740 sdram_map_bcr(sdram);
741 }
742 }
743
744 /*****************************************************************************/
745 /* Peripheral controller */
746 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
747 struct ppc4xx_ebc_t {
748 uint32_t addr;
749 uint32_t bcr[8];
750 uint32_t bap[8];
751 uint32_t bear;
752 uint32_t besr0;
753 uint32_t besr1;
754 uint32_t cfg;
755 };
756
757 enum {
758 EBC0_CFGADDR = 0x012,
759 EBC0_CFGDATA = 0x013,
760 };
761
762 static target_ulong dcr_read_ebc (void *opaque, int dcrn)
763 {
764 ppc4xx_ebc_t *ebc;
765 target_ulong ret;
766
767 ebc = opaque;
768 switch (dcrn) {
769 case EBC0_CFGADDR:
770 ret = ebc->addr;
771 break;
772 case EBC0_CFGDATA:
773 switch (ebc->addr) {
774 case 0x00: /* B0CR */
775 ret = ebc->bcr[0];
776 break;
777 case 0x01: /* B1CR */
778 ret = ebc->bcr[1];
779 break;
780 case 0x02: /* B2CR */
781 ret = ebc->bcr[2];
782 break;
783 case 0x03: /* B3CR */
784 ret = ebc->bcr[3];
785 break;
786 case 0x04: /* B4CR */
787 ret = ebc->bcr[4];
788 break;
789 case 0x05: /* B5CR */
790 ret = ebc->bcr[5];
791 break;
792 case 0x06: /* B6CR */
793 ret = ebc->bcr[6];
794 break;
795 case 0x07: /* B7CR */
796 ret = ebc->bcr[7];
797 break;
798 case 0x10: /* B0AP */
799 ret = ebc->bap[0];
800 break;
801 case 0x11: /* B1AP */
802 ret = ebc->bap[1];
803 break;
804 case 0x12: /* B2AP */
805 ret = ebc->bap[2];
806 break;
807 case 0x13: /* B3AP */
808 ret = ebc->bap[3];
809 break;
810 case 0x14: /* B4AP */
811 ret = ebc->bap[4];
812 break;
813 case 0x15: /* B5AP */
814 ret = ebc->bap[5];
815 break;
816 case 0x16: /* B6AP */
817 ret = ebc->bap[6];
818 break;
819 case 0x17: /* B7AP */
820 ret = ebc->bap[7];
821 break;
822 case 0x20: /* BEAR */
823 ret = ebc->bear;
824 break;
825 case 0x21: /* BESR0 */
826 ret = ebc->besr0;
827 break;
828 case 0x22: /* BESR1 */
829 ret = ebc->besr1;
830 break;
831 case 0x23: /* CFG */
832 ret = ebc->cfg;
833 break;
834 default:
835 ret = 0x00000000;
836 break;
837 }
838 default:
839 ret = 0x00000000;
840 break;
841 }
842
843 return ret;
844 }
845
846 static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
847 {
848 ppc4xx_ebc_t *ebc;
849
850 ebc = opaque;
851 switch (dcrn) {
852 case EBC0_CFGADDR:
853 ebc->addr = val;
854 break;
855 case EBC0_CFGDATA:
856 switch (ebc->addr) {
857 case 0x00: /* B0CR */
858 break;
859 case 0x01: /* B1CR */
860 break;
861 case 0x02: /* B2CR */
862 break;
863 case 0x03: /* B3CR */
864 break;
865 case 0x04: /* B4CR */
866 break;
867 case 0x05: /* B5CR */
868 break;
869 case 0x06: /* B6CR */
870 break;
871 case 0x07: /* B7CR */
872 break;
873 case 0x10: /* B0AP */
874 break;
875 case 0x11: /* B1AP */
876 break;
877 case 0x12: /* B2AP */
878 break;
879 case 0x13: /* B3AP */
880 break;
881 case 0x14: /* B4AP */
882 break;
883 case 0x15: /* B5AP */
884 break;
885 case 0x16: /* B6AP */
886 break;
887 case 0x17: /* B7AP */
888 break;
889 case 0x20: /* BEAR */
890 break;
891 case 0x21: /* BESR0 */
892 break;
893 case 0x22: /* BESR1 */
894 break;
895 case 0x23: /* CFG */
896 break;
897 default:
898 break;
899 }
900 break;
901 default:
902 break;
903 }
904 }
905
906 static void ebc_reset (void *opaque)
907 {
908 ppc4xx_ebc_t *ebc;
909 int i;
910
911 ebc = opaque;
912 ebc->addr = 0x00000000;
913 ebc->bap[0] = 0x7F8FFE80;
914 ebc->bcr[0] = 0xFFE28000;
915 for (i = 0; i < 8; i++) {
916 ebc->bap[i] = 0x00000000;
917 ebc->bcr[i] = 0x00000000;
918 }
919 ebc->besr0 = 0x00000000;
920 ebc->besr1 = 0x00000000;
921 ebc->cfg = 0x80400000;
922 }
923
924 void ppc405_ebc_init (CPUState *env)
925 {
926 ppc4xx_ebc_t *ebc;
927
928 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
929 if (ebc != NULL) {
930 ebc_reset(ebc);
931 qemu_register_reset(&ebc_reset, ebc);
932 ppc_dcr_register(env, EBC0_CFGADDR,
933 ebc, &dcr_read_ebc, &dcr_write_ebc);
934 ppc_dcr_register(env, EBC0_CFGDATA,
935 ebc, &dcr_read_ebc, &dcr_write_ebc);
936 }
937 }
938
939 /*****************************************************************************/
940 /* DMA controller */
941 enum {
942 DMA0_CR0 = 0x100,
943 DMA0_CT0 = 0x101,
944 DMA0_DA0 = 0x102,
945 DMA0_SA0 = 0x103,
946 DMA0_SG0 = 0x104,
947 DMA0_CR1 = 0x108,
948 DMA0_CT1 = 0x109,
949 DMA0_DA1 = 0x10A,
950 DMA0_SA1 = 0x10B,
951 DMA0_SG1 = 0x10C,
952 DMA0_CR2 = 0x110,
953 DMA0_CT2 = 0x111,
954 DMA0_DA2 = 0x112,
955 DMA0_SA2 = 0x113,
956 DMA0_SG2 = 0x114,
957 DMA0_CR3 = 0x118,
958 DMA0_CT3 = 0x119,
959 DMA0_DA3 = 0x11A,
960 DMA0_SA3 = 0x11B,
961 DMA0_SG3 = 0x11C,
962 DMA0_SR = 0x120,
963 DMA0_SGC = 0x123,
964 DMA0_SLP = 0x125,
965 DMA0_POL = 0x126,
966 };
967
968 typedef struct ppc405_dma_t ppc405_dma_t;
969 struct ppc405_dma_t {
970 qemu_irq irqs[4];
971 uint32_t cr[4];
972 uint32_t ct[4];
973 uint32_t da[4];
974 uint32_t sa[4];
975 uint32_t sg[4];
976 uint32_t sr;
977 uint32_t sgc;
978 uint32_t slp;
979 uint32_t pol;
980 };
981
982 static target_ulong dcr_read_dma (void *opaque, int dcrn)
983 {
984 ppc405_dma_t *dma;
985
986 dma = opaque;
987
988 return 0;
989 }
990
991 static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
992 {
993 ppc405_dma_t *dma;
994
995 dma = opaque;
996 }
997
998 static void ppc405_dma_reset (void *opaque)
999 {
1000 ppc405_dma_t *dma;
1001 int i;
1002
1003 dma = opaque;
1004 for (i = 0; i < 4; i++) {
1005 dma->cr[i] = 0x00000000;
1006 dma->ct[i] = 0x00000000;
1007 dma->da[i] = 0x00000000;
1008 dma->sa[i] = 0x00000000;
1009 dma->sg[i] = 0x00000000;
1010 }
1011 dma->sr = 0x00000000;
1012 dma->sgc = 0x00000000;
1013 dma->slp = 0x7C000000;
1014 dma->pol = 0x00000000;
1015 }
1016
1017 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
1018 {
1019 ppc405_dma_t *dma;
1020
1021 dma = qemu_mallocz(sizeof(ppc405_dma_t));
1022 if (dma != NULL) {
1023 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
1024 ppc405_dma_reset(dma);
1025 qemu_register_reset(&ppc405_dma_reset, dma);
1026 ppc_dcr_register(env, DMA0_CR0,
1027 dma, &dcr_read_dma, &dcr_write_dma);
1028 ppc_dcr_register(env, DMA0_CT0,
1029 dma, &dcr_read_dma, &dcr_write_dma);
1030 ppc_dcr_register(env, DMA0_DA0,
1031 dma, &dcr_read_dma, &dcr_write_dma);
1032 ppc_dcr_register(env, DMA0_SA0,
1033 dma, &dcr_read_dma, &dcr_write_dma);
1034 ppc_dcr_register(env, DMA0_SG0,
1035 dma, &dcr_read_dma, &dcr_write_dma);
1036 ppc_dcr_register(env, DMA0_CR1,
1037 dma, &dcr_read_dma, &dcr_write_dma);
1038 ppc_dcr_register(env, DMA0_CT1,
1039 dma, &dcr_read_dma, &dcr_write_dma);
1040 ppc_dcr_register(env, DMA0_DA1,
1041 dma, &dcr_read_dma, &dcr_write_dma);
1042 ppc_dcr_register(env, DMA0_SA1,
1043 dma, &dcr_read_dma, &dcr_write_dma);
1044 ppc_dcr_register(env, DMA0_SG1,
1045 dma, &dcr_read_dma, &dcr_write_dma);
1046 ppc_dcr_register(env, DMA0_CR2,
1047 dma, &dcr_read_dma, &dcr_write_dma);
1048 ppc_dcr_register(env, DMA0_CT2,
1049 dma, &dcr_read_dma, &dcr_write_dma);
1050 ppc_dcr_register(env, DMA0_DA2,
1051 dma, &dcr_read_dma, &dcr_write_dma);
1052 ppc_dcr_register(env, DMA0_SA2,
1053 dma, &dcr_read_dma, &dcr_write_dma);
1054 ppc_dcr_register(env, DMA0_SG2,
1055 dma, &dcr_read_dma, &dcr_write_dma);
1056 ppc_dcr_register(env, DMA0_CR3,
1057 dma, &dcr_read_dma, &dcr_write_dma);
1058 ppc_dcr_register(env, DMA0_CT3,
1059 dma, &dcr_read_dma, &dcr_write_dma);
1060 ppc_dcr_register(env, DMA0_DA3,
1061 dma, &dcr_read_dma, &dcr_write_dma);
1062 ppc_dcr_register(env, DMA0_SA3,
1063 dma, &dcr_read_dma, &dcr_write_dma);
1064 ppc_dcr_register(env, DMA0_SG3,
1065 dma, &dcr_read_dma, &dcr_write_dma);
1066 ppc_dcr_register(env, DMA0_SR,
1067 dma, &dcr_read_dma, &dcr_write_dma);
1068 ppc_dcr_register(env, DMA0_SGC,
1069 dma, &dcr_read_dma, &dcr_write_dma);
1070 ppc_dcr_register(env, DMA0_SLP,
1071 dma, &dcr_read_dma, &dcr_write_dma);
1072 ppc_dcr_register(env, DMA0_POL,
1073 dma, &dcr_read_dma, &dcr_write_dma);
1074 }
1075 }
1076
1077 /*****************************************************************************/
1078 /* GPIO */
1079 typedef struct ppc405_gpio_t ppc405_gpio_t;
1080 struct ppc405_gpio_t {
1081 target_phys_addr_t base;
1082 uint32_t or;
1083 uint32_t tcr;
1084 uint32_t osrh;
1085 uint32_t osrl;
1086 uint32_t tsrh;
1087 uint32_t tsrl;
1088 uint32_t odr;
1089 uint32_t ir;
1090 uint32_t rr1;
1091 uint32_t isr1h;
1092 uint32_t isr1l;
1093 };
1094
1095 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
1096 {
1097 ppc405_gpio_t *gpio;
1098
1099 gpio = opaque;
1100 #ifdef DEBUG_GPIO
1101 printf("%s: addr " PADDRX "\n", __func__, addr);
1102 #endif
1103
1104 return 0;
1105 }
1106
1107 static void ppc405_gpio_writeb (void *opaque,
1108 target_phys_addr_t addr, uint32_t value)
1109 {
1110 ppc405_gpio_t *gpio;
1111
1112 gpio = opaque;
1113 #ifdef DEBUG_GPIO
1114 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1115 #endif
1116 }
1117
1118 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
1119 {
1120 ppc405_gpio_t *gpio;
1121
1122 gpio = opaque;
1123 #ifdef DEBUG_GPIO
1124 printf("%s: addr " PADDRX "\n", __func__, addr);
1125 #endif
1126
1127 return 0;
1128 }
1129
1130 static void ppc405_gpio_writew (void *opaque,
1131 target_phys_addr_t addr, uint32_t value)
1132 {
1133 ppc405_gpio_t *gpio;
1134
1135 gpio = opaque;
1136 #ifdef DEBUG_GPIO
1137 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1138 #endif
1139 }
1140
1141 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
1142 {
1143 ppc405_gpio_t *gpio;
1144
1145 gpio = opaque;
1146 #ifdef DEBUG_GPIO
1147 printf("%s: addr " PADDRX "\n", __func__, addr);
1148 #endif
1149
1150 return 0;
1151 }
1152
1153 static void ppc405_gpio_writel (void *opaque,
1154 target_phys_addr_t addr, uint32_t value)
1155 {
1156 ppc405_gpio_t *gpio;
1157
1158 gpio = opaque;
1159 #ifdef DEBUG_GPIO
1160 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1161 #endif
1162 }
1163
1164 static CPUReadMemoryFunc *ppc405_gpio_read[] = {
1165 &ppc405_gpio_readb,
1166 &ppc405_gpio_readw,
1167 &ppc405_gpio_readl,
1168 };
1169
1170 static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
1171 &ppc405_gpio_writeb,
1172 &ppc405_gpio_writew,
1173 &ppc405_gpio_writel,
1174 };
1175
1176 static void ppc405_gpio_reset (void *opaque)
1177 {
1178 ppc405_gpio_t *gpio;
1179
1180 gpio = opaque;
1181 }
1182
1183 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
1184 target_phys_addr_t offset)
1185 {
1186 ppc405_gpio_t *gpio;
1187
1188 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
1189 if (gpio != NULL) {
1190 gpio->base = offset;
1191 ppc405_gpio_reset(gpio);
1192 qemu_register_reset(&ppc405_gpio_reset, gpio);
1193 #ifdef DEBUG_GPIO
1194 printf("%s: offset " PADDRX "\n", __func__, offset);
1195 #endif
1196 ppc4xx_mmio_register(env, mmio, offset, 0x038,
1197 ppc405_gpio_read, ppc405_gpio_write, gpio);
1198 }
1199 }
1200
1201 /*****************************************************************************/
1202 /* Serial ports */
1203 static CPUReadMemoryFunc *serial_mm_read[] = {
1204 &serial_mm_readb,
1205 &serial_mm_readw,
1206 &serial_mm_readl,
1207 };
1208
1209 static CPUWriteMemoryFunc *serial_mm_write[] = {
1210 &serial_mm_writeb,
1211 &serial_mm_writew,
1212 &serial_mm_writel,
1213 };
1214
1215 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
1216 target_phys_addr_t offset, qemu_irq irq,
1217 CharDriverState *chr)
1218 {
1219 void *serial;
1220
1221 #ifdef DEBUG_SERIAL
1222 printf("%s: offset " PADDRX "\n", __func__, offset);
1223 #endif
1224 serial = serial_mm_init(offset, 0, irq, 399193, chr, 0);
1225 ppc4xx_mmio_register(env, mmio, offset, 0x008,
1226 serial_mm_read, serial_mm_write, serial);
1227 }
1228
1229 /*****************************************************************************/
1230 /* On Chip Memory */
1231 enum {
1232 OCM0_ISARC = 0x018,
1233 OCM0_ISACNTL = 0x019,
1234 OCM0_DSARC = 0x01A,
1235 OCM0_DSACNTL = 0x01B,
1236 };
1237
1238 typedef struct ppc405_ocm_t ppc405_ocm_t;
1239 struct ppc405_ocm_t {
1240 target_ulong offset;
1241 uint32_t isarc;
1242 uint32_t isacntl;
1243 uint32_t dsarc;
1244 uint32_t dsacntl;
1245 };
1246
1247 static void ocm_update_mappings (ppc405_ocm_t *ocm,
1248 uint32_t isarc, uint32_t isacntl,
1249 uint32_t dsarc, uint32_t dsacntl)
1250 {
1251 #ifdef DEBUG_OCM
1252 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
1253 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
1254 " (%08" PRIx32 " %08" PRIx32 ")\n",
1255 isarc, isacntl, dsarc, dsacntl,
1256 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
1257 #endif
1258 if (ocm->isarc != isarc ||
1259 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
1260 if (ocm->isacntl & 0x80000000) {
1261 /* Unmap previously assigned memory region */
1262 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
1263 cpu_register_physical_memory(ocm->isarc, 0x04000000,
1264 IO_MEM_UNASSIGNED);
1265 }
1266 if (isacntl & 0x80000000) {
1267 /* Map new instruction memory region */
1268 #ifdef DEBUG_OCM
1269 printf("OCM map ISA %08" PRIx32 "\n", isarc);
1270 #endif
1271 cpu_register_physical_memory(isarc, 0x04000000,
1272 ocm->offset | IO_MEM_RAM);
1273 }
1274 }
1275 if (ocm->dsarc != dsarc ||
1276 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
1277 if (ocm->dsacntl & 0x80000000) {
1278 /* Beware not to unmap the region we just mapped */
1279 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
1280 /* Unmap previously assigned memory region */
1281 #ifdef DEBUG_OCM
1282 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
1283 #endif
1284 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
1285 IO_MEM_UNASSIGNED);
1286 }
1287 }
1288 if (dsacntl & 0x80000000) {
1289 /* Beware not to remap the region we just mapped */
1290 if (!(isacntl & 0x80000000) || dsarc != isarc) {
1291 /* Map new data memory region */
1292 #ifdef DEBUG_OCM
1293 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
1294 #endif
1295 cpu_register_physical_memory(dsarc, 0x04000000,
1296 ocm->offset | IO_MEM_RAM);
1297 }
1298 }
1299 }
1300 }
1301
1302 static target_ulong dcr_read_ocm (void *opaque, int dcrn)
1303 {
1304 ppc405_ocm_t *ocm;
1305 target_ulong ret;
1306
1307 ocm = opaque;
1308 switch (dcrn) {
1309 case OCM0_ISARC:
1310 ret = ocm->isarc;
1311 break;
1312 case OCM0_ISACNTL:
1313 ret = ocm->isacntl;
1314 break;
1315 case OCM0_DSARC:
1316 ret = ocm->dsarc;
1317 break;
1318 case OCM0_DSACNTL:
1319 ret = ocm->dsacntl;
1320 break;
1321 default:
1322 ret = 0;
1323 break;
1324 }
1325
1326 return ret;
1327 }
1328
1329 static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
1330 {
1331 ppc405_ocm_t *ocm;
1332 uint32_t isarc, dsarc, isacntl, dsacntl;
1333
1334 ocm = opaque;
1335 isarc = ocm->isarc;
1336 dsarc = ocm->dsarc;
1337 isacntl = ocm->isacntl;
1338 dsacntl = ocm->dsacntl;
1339 switch (dcrn) {
1340 case OCM0_ISARC:
1341 isarc = val & 0xFC000000;
1342 break;
1343 case OCM0_ISACNTL:
1344 isacntl = val & 0xC0000000;
1345 break;
1346 case OCM0_DSARC:
1347 isarc = val & 0xFC000000;
1348 break;
1349 case OCM0_DSACNTL:
1350 isacntl = val & 0xC0000000;
1351 break;
1352 }
1353 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1354 ocm->isarc = isarc;
1355 ocm->dsarc = dsarc;
1356 ocm->isacntl = isacntl;
1357 ocm->dsacntl = dsacntl;
1358 }
1359
1360 static void ocm_reset (void *opaque)
1361 {
1362 ppc405_ocm_t *ocm;
1363 uint32_t isarc, dsarc, isacntl, dsacntl;
1364
1365 ocm = opaque;
1366 isarc = 0x00000000;
1367 isacntl = 0x00000000;
1368 dsarc = 0x00000000;
1369 dsacntl = 0x00000000;
1370 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1371 ocm->isarc = isarc;
1372 ocm->dsarc = dsarc;
1373 ocm->isacntl = isacntl;
1374 ocm->dsacntl = dsacntl;
1375 }
1376
1377 void ppc405_ocm_init (CPUState *env, unsigned long offset)
1378 {
1379 ppc405_ocm_t *ocm;
1380
1381 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
1382 if (ocm != NULL) {
1383 ocm->offset = offset;
1384 ocm_reset(ocm);
1385 qemu_register_reset(&ocm_reset, ocm);
1386 ppc_dcr_register(env, OCM0_ISARC,
1387 ocm, &dcr_read_ocm, &dcr_write_ocm);
1388 ppc_dcr_register(env, OCM0_ISACNTL,
1389 ocm, &dcr_read_ocm, &dcr_write_ocm);
1390 ppc_dcr_register(env, OCM0_DSARC,
1391 ocm, &dcr_read_ocm, &dcr_write_ocm);
1392 ppc_dcr_register(env, OCM0_DSACNTL,
1393 ocm, &dcr_read_ocm, &dcr_write_ocm);
1394 }
1395 }
1396
1397 /*****************************************************************************/
1398 /* I2C controller */
1399 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
1400 struct ppc4xx_i2c_t {
1401 target_phys_addr_t base;
1402 qemu_irq irq;
1403 uint8_t mdata;
1404 uint8_t lmadr;
1405 uint8_t hmadr;
1406 uint8_t cntl;
1407 uint8_t mdcntl;
1408 uint8_t sts;
1409 uint8_t extsts;
1410 uint8_t sdata;
1411 uint8_t lsadr;
1412 uint8_t hsadr;
1413 uint8_t clkdiv;
1414 uint8_t intrmsk;
1415 uint8_t xfrcnt;
1416 uint8_t xtcntlss;
1417 uint8_t directcntl;
1418 };
1419
1420 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1421 {
1422 ppc4xx_i2c_t *i2c;
1423 uint32_t ret;
1424
1425 #ifdef DEBUG_I2C
1426 printf("%s: addr " PADDRX "\n", __func__, addr);
1427 #endif
1428 i2c = opaque;
1429 switch (addr - i2c->base) {
1430 case 0x00:
1431 // i2c_readbyte(&i2c->mdata);
1432 ret = i2c->mdata;
1433 break;
1434 case 0x02:
1435 ret = i2c->sdata;
1436 break;
1437 case 0x04:
1438 ret = i2c->lmadr;
1439 break;
1440 case 0x05:
1441 ret = i2c->hmadr;
1442 break;
1443 case 0x06:
1444 ret = i2c->cntl;
1445 break;
1446 case 0x07:
1447 ret = i2c->mdcntl;
1448 break;
1449 case 0x08:
1450 ret = i2c->sts;
1451 break;
1452 case 0x09:
1453 ret = i2c->extsts;
1454 break;
1455 case 0x0A:
1456 ret = i2c->lsadr;
1457 break;
1458 case 0x0B:
1459 ret = i2c->hsadr;
1460 break;
1461 case 0x0C:
1462 ret = i2c->clkdiv;
1463 break;
1464 case 0x0D:
1465 ret = i2c->intrmsk;
1466 break;
1467 case 0x0E:
1468 ret = i2c->xfrcnt;
1469 break;
1470 case 0x0F:
1471 ret = i2c->xtcntlss;
1472 break;
1473 case 0x10:
1474 ret = i2c->directcntl;
1475 break;
1476 default:
1477 ret = 0x00;
1478 break;
1479 }
1480 #ifdef DEBUG_I2C
1481 printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
1482 #endif
1483
1484 return ret;
1485 }
1486
1487 static void ppc4xx_i2c_writeb (void *opaque,
1488 target_phys_addr_t addr, uint32_t value)
1489 {
1490 ppc4xx_i2c_t *i2c;
1491
1492 #ifdef DEBUG_I2C
1493 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1494 #endif
1495 i2c = opaque;
1496 switch (addr - i2c->base) {
1497 case 0x00:
1498 i2c->mdata = value;
1499 // i2c_sendbyte(&i2c->mdata);
1500 break;
1501 case 0x02:
1502 i2c->sdata = value;
1503 break;
1504 case 0x04:
1505 i2c->lmadr = value;
1506 break;
1507 case 0x05:
1508 i2c->hmadr = value;
1509 break;
1510 case 0x06:
1511 i2c->cntl = value;
1512 break;
1513 case 0x07:
1514 i2c->mdcntl = value & 0xDF;
1515 break;
1516 case 0x08:
1517 i2c->sts &= ~(value & 0x0A);
1518 break;
1519 case 0x09:
1520 i2c->extsts &= ~(value & 0x8F);
1521 break;
1522 case 0x0A:
1523 i2c->lsadr = value;
1524 break;
1525 case 0x0B:
1526 i2c->hsadr = value;
1527 break;
1528 case 0x0C:
1529 i2c->clkdiv = value;
1530 break;
1531 case 0x0D:
1532 i2c->intrmsk = value;
1533 break;
1534 case 0x0E:
1535 i2c->xfrcnt = value & 0x77;
1536 break;
1537 case 0x0F:
1538 i2c->xtcntlss = value;
1539 break;
1540 case 0x10:
1541 i2c->directcntl = value & 0x7;
1542 break;
1543 }
1544 }
1545
1546 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1547 {
1548 uint32_t ret;
1549
1550 #ifdef DEBUG_I2C
1551 printf("%s: addr " PADDRX "\n", __func__, addr);
1552 #endif
1553 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1554 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1555
1556 return ret;
1557 }
1558
1559 static void ppc4xx_i2c_writew (void *opaque,
1560 target_phys_addr_t addr, uint32_t value)
1561 {
1562 #ifdef DEBUG_I2C
1563 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1564 #endif
1565 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1566 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1567 }
1568
1569 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1570 {
1571 uint32_t ret;
1572
1573 #ifdef DEBUG_I2C
1574 printf("%s: addr " PADDRX "\n", __func__, addr);
1575 #endif
1576 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1577 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1578 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1579 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1580
1581 return ret;
1582 }
1583
1584 static void ppc4xx_i2c_writel (void *opaque,
1585 target_phys_addr_t addr, uint32_t value)
1586 {
1587 #ifdef DEBUG_I2C
1588 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1589 #endif
1590 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1591 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1592 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1593 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1594 }
1595
1596 static CPUReadMemoryFunc *i2c_read[] = {
1597 &ppc4xx_i2c_readb,
1598 &ppc4xx_i2c_readw,
1599 &ppc4xx_i2c_readl,
1600 };
1601
1602 static CPUWriteMemoryFunc *i2c_write[] = {
1603 &ppc4xx_i2c_writeb,
1604 &ppc4xx_i2c_writew,
1605 &ppc4xx_i2c_writel,
1606 };
1607
1608 static void ppc4xx_i2c_reset (void *opaque)
1609 {
1610 ppc4xx_i2c_t *i2c;
1611
1612 i2c = opaque;
1613 i2c->mdata = 0x00;
1614 i2c->sdata = 0x00;
1615 i2c->cntl = 0x00;
1616 i2c->mdcntl = 0x00;
1617 i2c->sts = 0x00;
1618 i2c->extsts = 0x00;
1619 i2c->clkdiv = 0x00;
1620 i2c->xfrcnt = 0x00;
1621 i2c->directcntl = 0x0F;
1622 }
1623
1624 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
1625 target_phys_addr_t offset, qemu_irq irq)
1626 {
1627 ppc4xx_i2c_t *i2c;
1628
1629 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
1630 if (i2c != NULL) {
1631 i2c->base = offset;
1632 i2c->irq = irq;
1633 ppc4xx_i2c_reset(i2c);
1634 #ifdef DEBUG_I2C
1635 printf("%s: offset " PADDRX "\n", __func__, offset);
1636 #endif
1637 ppc4xx_mmio_register(env, mmio, offset, 0x011,
1638 i2c_read, i2c_write, i2c);
1639 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1640 }
1641 }
1642
1643 /*****************************************************************************/
1644 /* General purpose timers */
1645 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1646 struct ppc4xx_gpt_t {
1647 target_phys_addr_t base;
1648 int64_t tb_offset;
1649 uint32_t tb_freq;
1650 struct QEMUTimer *timer;
1651 qemu_irq irqs[5];
1652 uint32_t oe;
1653 uint32_t ol;
1654 uint32_t im;
1655 uint32_t is;
1656 uint32_t ie;
1657 uint32_t comp[5];
1658 uint32_t mask[5];
1659 };
1660
1661 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1662 {
1663 #ifdef DEBUG_GPT
1664 printf("%s: addr " PADDRX "\n", __func__, addr);
1665 #endif
1666 /* XXX: generate a bus fault */
1667 return -1;
1668 }
1669
1670 static void ppc4xx_gpt_writeb (void *opaque,
1671 target_phys_addr_t addr, uint32_t value)
1672 {
1673 #ifdef DEBUG_I2C
1674 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1675 #endif
1676 /* XXX: generate a bus fault */
1677 }
1678
1679 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1680 {
1681 #ifdef DEBUG_GPT
1682 printf("%s: addr " PADDRX "\n", __func__, addr);
1683 #endif
1684 /* XXX: generate a bus fault */
1685 return -1;
1686 }
1687
1688 static void ppc4xx_gpt_writew (void *opaque,
1689 target_phys_addr_t addr, uint32_t value)
1690 {
1691 #ifdef DEBUG_I2C
1692 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1693 #endif
1694 /* XXX: generate a bus fault */
1695 }
1696
1697 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1698 {
1699 /* XXX: TODO */
1700 return 0;
1701 }
1702
1703 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1704 {
1705 /* XXX: TODO */
1706 }
1707
1708 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1709 {
1710 uint32_t mask;
1711 int i;
1712
1713 mask = 0x80000000;
1714 for (i = 0; i < 5; i++) {
1715 if (gpt->oe & mask) {
1716 /* Output is enabled */
1717 if (ppc4xx_gpt_compare(gpt, i)) {
1718 /* Comparison is OK */
1719 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1720 } else {
1721 /* Comparison is KO */
1722 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1723 }
1724 }
1725 mask = mask >> 1;
1726 }
1727 }
1728
1729 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1730 {
1731 uint32_t mask;
1732 int i;
1733
1734 mask = 0x00008000;
1735 for (i = 0; i < 5; i++) {
1736 if (gpt->is & gpt->im & mask)
1737 qemu_irq_raise(gpt->irqs[i]);
1738 else
1739 qemu_irq_lower(gpt->irqs[i]);
1740 mask = mask >> 1;
1741 }
1742 }
1743
1744 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1745 {
1746 /* XXX: TODO */
1747 }
1748
1749 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1750 {
1751 ppc4xx_gpt_t *gpt;
1752 uint32_t ret;
1753 int idx;
1754
1755 #ifdef DEBUG_GPT
1756 printf("%s: addr " PADDRX "\n", __func__, addr);
1757 #endif
1758 gpt = opaque;
1759 switch (addr - gpt->base) {
1760 case 0x00:
1761 /* Time base counter */
1762 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
1763 gpt->tb_freq, ticks_per_sec);
1764 break;
1765 case 0x10:
1766 /* Output enable */
1767 ret = gpt->oe;
1768 break;
1769 case 0x14:
1770 /* Output level */
1771 ret = gpt->ol;
1772 break;
1773 case 0x18:
1774 /* Interrupt mask */
1775 ret = gpt->im;
1776 break;
1777 case 0x1C:
1778 case 0x20:
1779 /* Interrupt status */
1780 ret = gpt->is;
1781 break;
1782 case 0x24:
1783 /* Interrupt enable */
1784 ret = gpt->ie;
1785 break;
1786 case 0x80 ... 0x90:
1787 /* Compare timer */
1788 idx = ((addr - gpt->base) - 0x80) >> 2;
1789 ret = gpt->comp[idx];
1790 break;
1791 case 0xC0 ... 0xD0:
1792 /* Compare mask */
1793 idx = ((addr - gpt->base) - 0xC0) >> 2;
1794 ret = gpt->mask[idx];
1795 break;
1796 default:
1797 ret = -1;
1798 break;
1799 }
1800
1801 return ret;
1802 }
1803
1804 static void ppc4xx_gpt_writel (void *opaque,
1805 target_phys_addr_t addr, uint32_t value)
1806 {
1807 ppc4xx_gpt_t *gpt;
1808 int idx;
1809
1810 #ifdef DEBUG_I2C
1811 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1812 #endif
1813 gpt = opaque;
1814 switch (addr - gpt->base) {
1815 case 0x00:
1816 /* Time base counter */
1817 gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
1818 - qemu_get_clock(vm_clock);
1819 ppc4xx_gpt_compute_timer(gpt);
1820 break;
1821 case 0x10:
1822 /* Output enable */
1823 gpt->oe = value & 0xF8000000;
1824 ppc4xx_gpt_set_outputs(gpt);
1825 break;
1826 case 0x14:
1827 /* Output level */
1828 gpt->ol = value & 0xF8000000;
1829 ppc4xx_gpt_set_outputs(gpt);
1830 break;
1831 case 0x18:
1832 /* Interrupt mask */
1833 gpt->im = value & 0x0000F800;
1834 break;
1835 case 0x1C:
1836 /* Interrupt status set */
1837 gpt->is |= value & 0x0000F800;
1838 ppc4xx_gpt_set_irqs(gpt);
1839 break;
1840 case 0x20:
1841 /* Interrupt status clear */
1842 gpt->is &= ~(value & 0x0000F800);
1843 ppc4xx_gpt_set_irqs(gpt);
1844 break;
1845 case 0x24:
1846 /* Interrupt enable */
1847 gpt->ie = value & 0x0000F800;
1848 ppc4xx_gpt_set_irqs(gpt);
1849 break;
1850 case 0x80 ... 0x90:
1851 /* Compare timer */
1852 idx = ((addr - gpt->base) - 0x80) >> 2;
1853 gpt->comp[idx] = value & 0xF8000000;
1854 ppc4xx_gpt_compute_timer(gpt);
1855 break;
1856 case 0xC0 ... 0xD0:
1857 /* Compare mask */
1858 idx = ((addr - gpt->base) - 0xC0) >> 2;
1859 gpt->mask[idx] = value & 0xF8000000;
1860 ppc4xx_gpt_compute_timer(gpt);
1861 break;
1862 }
1863 }
1864
1865 static CPUReadMemoryFunc *gpt_read[] = {
1866 &ppc4xx_gpt_readb,
1867 &ppc4xx_gpt_readw,
1868 &ppc4xx_gpt_readl,
1869 };
1870
1871 static CPUWriteMemoryFunc *gpt_write[] = {
1872 &ppc4xx_gpt_writeb,
1873 &ppc4xx_gpt_writew,
1874 &ppc4xx_gpt_writel,
1875 };
1876
1877 static void ppc4xx_gpt_cb (void *opaque)
1878 {
1879 ppc4xx_gpt_t *gpt;
1880
1881 gpt = opaque;
1882 ppc4xx_gpt_set_irqs(gpt);
1883 ppc4xx_gpt_set_outputs(gpt);
1884 ppc4xx_gpt_compute_timer(gpt);
1885 }
1886
1887 static void ppc4xx_gpt_reset (void *opaque)
1888 {
1889 ppc4xx_gpt_t *gpt;
1890 int i;
1891
1892 gpt = opaque;
1893 qemu_del_timer(gpt->timer);
1894 gpt->oe = 0x00000000;
1895 gpt->ol = 0x00000000;
1896 gpt->im = 0x00000000;
1897 gpt->is = 0x00000000;
1898 gpt->ie = 0x00000000;
1899 for (i = 0; i < 5; i++) {
1900 gpt->comp[i] = 0x00000000;
1901 gpt->mask[i] = 0x00000000;
1902 }
1903 }
1904
1905 void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
1906 target_phys_addr_t offset, qemu_irq irqs[5])
1907 {
1908 ppc4xx_gpt_t *gpt;
1909 int i;
1910
1911 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
1912 if (gpt != NULL) {
1913 gpt->base = offset;
1914 for (i = 0; i < 5; i++)
1915 gpt->irqs[i] = irqs[i];
1916 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
1917 ppc4xx_gpt_reset(gpt);
1918 #ifdef DEBUG_GPT
1919 printf("%s: offset " PADDRX "\n", __func__, offset);
1920 #endif
1921 ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
1922 gpt_read, gpt_write, gpt);
1923 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1924 }
1925 }
1926
1927 /*****************************************************************************/
1928 /* MAL */
1929 enum {
1930 MAL0_CFG = 0x180,
1931 MAL0_ESR = 0x181,
1932 MAL0_IER = 0x182,
1933 MAL0_TXCASR = 0x184,
1934 MAL0_TXCARR = 0x185,
1935 MAL0_TXEOBISR = 0x186,
1936 MAL0_TXDEIR = 0x187,
1937 MAL0_RXCASR = 0x190,
1938 MAL0_RXCARR = 0x191,
1939 MAL0_RXEOBISR = 0x192,
1940 MAL0_RXDEIR = 0x193,
1941 MAL0_TXCTP0R = 0x1A0,
1942 MAL0_TXCTP1R = 0x1A1,
1943 MAL0_TXCTP2R = 0x1A2,
1944 MAL0_TXCTP3R = 0x1A3,
1945 MAL0_RXCTP0R = 0x1C0,
1946 MAL0_RXCTP1R = 0x1C1,
1947 MAL0_RCBS0 = 0x1E0,
1948 MAL0_RCBS1 = 0x1E1,
1949 };
1950
1951 typedef struct ppc40x_mal_t ppc40x_mal_t;
1952 struct ppc40x_mal_t {
1953 qemu_irq irqs[4];
1954 uint32_t cfg;
1955 uint32_t esr;
1956 uint32_t ier;
1957 uint32_t txcasr;
1958 uint32_t txcarr;
1959 uint32_t txeobisr;
1960 uint32_t txdeir;
1961 uint32_t rxcasr;
1962 uint32_t rxcarr;
1963 uint32_t rxeobisr;
1964 uint32_t rxdeir;
1965 uint32_t txctpr[4];
1966 uint32_t rxctpr[2];
1967 uint32_t rcbs[2];
1968 };
1969
1970 static void ppc40x_mal_reset (void *opaque);
1971
1972 static target_ulong dcr_read_mal (void *opaque, int dcrn)
1973 {
1974 ppc40x_mal_t *mal;
1975 target_ulong ret;
1976
1977 mal = opaque;
1978 switch (dcrn) {
1979 case MAL0_CFG:
1980 ret = mal->cfg;
1981 break;
1982 case MAL0_ESR:
1983 ret = mal->esr;
1984 break;
1985 case MAL0_IER:
1986 ret = mal->ier;
1987 break;
1988 case MAL0_TXCASR:
1989 ret = mal->txcasr;
1990 break;
1991 case MAL0_TXCARR:
1992 ret = mal->txcarr;
1993 break;
1994 case MAL0_TXEOBISR:
1995 ret = mal->txeobisr;
1996 break;
1997 case MAL0_TXDEIR:
1998 ret = mal->txdeir;
1999 break;
2000 case MAL0_RXCASR:
2001 ret = mal->rxcasr;
2002 break;
2003 case MAL0_RXCARR:
2004 ret = mal->rxcarr;
2005 break;
2006 case MAL0_RXEOBISR:
2007 ret = mal->rxeobisr;
2008 break;
2009 case MAL0_RXDEIR:
2010 ret = mal->rxdeir;
2011 break;
2012 case MAL0_TXCTP0R:
2013 ret = mal->txctpr[0];
2014 break;
2015 case MAL0_TXCTP1R:
2016 ret = mal->txctpr[1];
2017 break;
2018 case MAL0_TXCTP2R:
2019 ret = mal->txctpr[2];
2020 break;
2021 case MAL0_TXCTP3R:
2022 ret = mal->txctpr[3];
2023 break;
2024 case MAL0_RXCTP0R:
2025 ret = mal->rxctpr[0];
2026 break;
2027 case MAL0_RXCTP1R:
2028 ret = mal->rxctpr[1];
2029 break;
2030 case MAL0_RCBS0:
2031 ret = mal->rcbs[0];
2032 break;
2033 case MAL0_RCBS1:
2034 ret = mal->rcbs[1];
2035 break;
2036 default:
2037 ret = 0;
2038 break;
2039 }
2040
2041 return ret;
2042 }
2043
2044 static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
2045 {
2046 ppc40x_mal_t *mal;
2047 int idx;
2048
2049 mal = opaque;
2050 switch (dcrn) {
2051 case MAL0_CFG:
2052 if (val & 0x80000000)
2053 ppc40x_mal_reset(mal);
2054 mal->cfg = val & 0x00FFC087;
2055 break;
2056 case MAL0_ESR:
2057 /* Read/clear */
2058 mal->esr &= ~val;
2059 break;
2060 case MAL0_IER:
2061 mal->ier = val & 0x0000001F;
2062 break;
2063 case MAL0_TXCASR:
2064 mal->txcasr = val & 0xF0000000;
2065 break;
2066 case MAL0_TXCARR:
2067 mal->txcarr = val & 0xF0000000;
2068 break;
2069 case MAL0_TXEOBISR:
2070 /* Read/clear */
2071 mal->txeobisr &= ~val;
2072 break;
2073 case MAL0_TXDEIR:
2074 /* Read/clear */
2075 mal->txdeir &= ~val;
2076 break;
2077 case MAL0_RXCASR:
2078 mal->rxcasr = val & 0xC0000000;
2079 break;
2080 case MAL0_RXCARR:
2081 mal->rxcarr = val & 0xC0000000;
2082 break;
2083 case MAL0_RXEOBISR:
2084 /* Read/clear */
2085 mal->rxeobisr &= ~val;
2086 break;
2087 case MAL0_RXDEIR:
2088 /* Read/clear */
2089 mal->rxdeir &= ~val;
2090 break;
2091 case MAL0_TXCTP0R:
2092 idx = 0;
2093 goto update_tx_ptr;
2094 case MAL0_TXCTP1R:
2095 idx = 1;
2096 goto update_tx_ptr;
2097 case MAL0_TXCTP2R:
2098 idx = 2;
2099 goto update_tx_ptr;
2100 case MAL0_TXCTP3R:
2101 idx = 3;
2102 update_tx_ptr:
2103 mal->txctpr[idx] = val;
2104 break;
2105 case MAL0_RXCTP0R:
2106 idx = 0;
2107 goto update_rx_ptr;
2108 case MAL0_RXCTP1R:
2109 idx = 1;
2110 update_rx_ptr:
2111 mal->rxctpr[idx] = val;
2112 break;
2113 case MAL0_RCBS0:
2114 idx = 0;
2115 goto update_rx_size;
2116 case MAL0_RCBS1:
2117 idx = 1;
2118 update_rx_size:
2119 mal->rcbs[idx] = val & 0x000000FF;
2120 break;
2121 }
2122 }
2123
2124 static void ppc40x_mal_reset (void *opaque)
2125 {
2126 ppc40x_mal_t *mal;
2127
2128 mal = opaque;
2129 mal->cfg = 0x0007C000;
2130 mal->esr = 0x00000000;
2131 mal->ier = 0x00000000;
2132 mal->rxcasr = 0x00000000;
2133 mal->rxdeir = 0x00000000;
2134 mal->rxeobisr = 0x00000000;
2135 mal->txcasr = 0x00000000;
2136 mal->txdeir = 0x00000000;
2137 mal->txeobisr = 0x00000000;
2138 }
2139
2140 void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
2141 {
2142 ppc40x_mal_t *mal;
2143 int i;
2144
2145 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
2146 if (mal != NULL) {
2147 for (i = 0; i < 4; i++)
2148 mal->irqs[i] = irqs[i];
2149 ppc40x_mal_reset(mal);
2150 qemu_register_reset(&ppc40x_mal_reset, mal);
2151 ppc_dcr_register(env, MAL0_CFG,
2152 mal, &dcr_read_mal, &dcr_write_mal);
2153 ppc_dcr_register(env, MAL0_ESR,
2154 mal, &dcr_read_mal, &dcr_write_mal);
2155 ppc_dcr_register(env, MAL0_IER,
2156 mal, &dcr_read_mal, &dcr_write_mal);
2157 ppc_dcr_register(env, MAL0_TXCASR,
2158 mal, &dcr_read_mal, &dcr_write_mal);
2159 ppc_dcr_register(env, MAL0_TXCARR,
2160 mal, &dcr_read_mal, &dcr_write_mal);
2161 ppc_dcr_register(env, MAL0_TXEOBISR,
2162 mal, &dcr_read_mal, &dcr_write_mal);
2163 ppc_dcr_register(env, MAL0_TXDEIR,
2164 mal, &dcr_read_mal, &dcr_write_mal);
2165 ppc_dcr_register(env, MAL0_RXCASR,
2166 mal, &dcr_read_mal, &dcr_write_mal);
2167 ppc_dcr_register(env, MAL0_RXCARR,
2168 mal, &dcr_read_mal, &dcr_write_mal);
2169 ppc_dcr_register(env, MAL0_RXEOBISR,
2170 mal, &dcr_read_mal, &dcr_write_mal);
2171 ppc_dcr_register(env, MAL0_RXDEIR,
2172 mal, &dcr_read_mal, &dcr_write_mal);
2173 ppc_dcr_register(env, MAL0_TXCTP0R,
2174 mal, &dcr_read_mal, &dcr_write_mal);
2175 ppc_dcr_register(env, MAL0_TXCTP1R,
2176 mal, &dcr_read_mal, &dcr_write_mal);
2177 ppc_dcr_register(env, MAL0_TXCTP2R,
2178 mal, &dcr_read_mal, &dcr_write_mal);
2179 ppc_dcr_register(env, MAL0_TXCTP3R,
2180 mal, &dcr_read_mal, &dcr_write_mal);
2181 ppc_dcr_register(env, MAL0_RXCTP0R,
2182 mal, &dcr_read_mal, &dcr_write_mal);
2183 ppc_dcr_register(env, MAL0_RXCTP1R,
2184 mal, &dcr_read_mal, &dcr_write_mal);
2185 ppc_dcr_register(env, MAL0_RCBS0,
2186 mal, &dcr_read_mal, &dcr_write_mal);
2187 ppc_dcr_register(env, MAL0_RCBS1,
2188 mal, &dcr_read_mal, &dcr_write_mal);
2189 }
2190 }
2191
2192 /*****************************************************************************/
2193 /* SPR */
2194 void ppc40x_core_reset (CPUState *env)
2195 {
2196 target_ulong dbsr;
2197
2198 printf("Reset PowerPC core\n");
2199 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2200 /* XXX: TOFIX */
2201 #if 0
2202 cpu_ppc_reset(env);
2203 #else
2204 qemu_system_reset_request();
2205 #endif
2206 dbsr = env->spr[SPR_40x_DBSR];
2207 dbsr &= ~0x00000300;
2208 dbsr |= 0x00000100;
2209 env->spr[SPR_40x_DBSR] = dbsr;
2210 }
2211
2212 void ppc40x_chip_reset (CPUState *env)
2213 {
2214 target_ulong dbsr;
2215
2216 printf("Reset PowerPC chip\n");
2217 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2218 /* XXX: TOFIX */
2219 #if 0
2220 cpu_ppc_reset(env);
2221 #else
2222 qemu_system_reset_request();
2223 #endif
2224 /* XXX: TODO reset all internal peripherals */
2225 dbsr = env->spr[SPR_40x_DBSR];
2226 dbsr &= ~0x00000300;
2227 dbsr |= 0x00000200;
2228 env->spr[SPR_40x_DBSR] = dbsr;
2229 }
2230
2231 void ppc40x_system_reset (CPUState *env)
2232 {
2233 printf("Reset PowerPC system\n");
2234 qemu_system_reset_request();
2235 }
2236
2237 void store_40x_dbcr0 (CPUState *env, uint32_t val)
2238 {
2239 switch ((val >> 28) & 0x3) {
2240 case 0x0:
2241 /* No action */
2242 break;
2243 case 0x1:
2244 /* Core reset */
2245 ppc40x_core_reset(env);
2246 break;
2247 case 0x2:
2248 /* Chip reset */
2249 ppc40x_chip_reset(env);
2250 break;
2251 case 0x3:
2252 /* System reset */
2253 ppc40x_system_reset(env);
2254 break;
2255 }
2256 }
2257
2258 /*****************************************************************************/
2259 /* PowerPC 405CR */
2260 enum {
2261 PPC405CR_CPC0_PLLMR = 0x0B0,
2262 PPC405CR_CPC0_CR0 = 0x0B1,
2263 PPC405CR_CPC0_CR1 = 0x0B2,
2264 PPC405CR_CPC0_PSR = 0x0B4,
2265 PPC405CR_CPC0_JTAGID = 0x0B5,
2266 PPC405CR_CPC0_ER = 0x0B9,
2267 PPC405CR_CPC0_FR = 0x0BA,
2268 PPC405CR_CPC0_SR = 0x0BB,
2269 };
2270
2271 enum {
2272 PPC405CR_CPU_CLK = 0,
2273 PPC405CR_TMR_CLK = 1,
2274 PPC405CR_PLB_CLK = 2,
2275 PPC405CR_SDRAM_CLK = 3,
2276 PPC405CR_OPB_CLK = 4,
2277 PPC405CR_EXT_CLK = 5,
2278 PPC405CR_UART_CLK = 6,
2279 PPC405CR_CLK_NB = 7,
2280 };
2281
2282 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
2283 struct ppc405cr_cpc_t {
2284 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2285 uint32_t sysclk;
2286 uint32_t psr;
2287 uint32_t cr0;
2288 uint32_t cr1;
2289 uint32_t jtagid;
2290 uint32_t pllmr;
2291 uint32_t er;
2292 uint32_t fr;
2293 };
2294
2295 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
2296 {
2297 uint64_t VCO_out, PLL_out;
2298 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
2299 int M, D0, D1, D2;
2300
2301 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
2302 if (cpc->pllmr & 0x80000000) {
2303 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
2304 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
2305 M = D0 * D1 * D2;
2306 VCO_out = cpc->sysclk * M;
2307 if (VCO_out < 400000000 || VCO_out > 800000000) {
2308 /* PLL cannot lock */
2309 cpc->pllmr &= ~0x80000000;
2310 goto bypass_pll;
2311 }
2312 PLL_out = VCO_out / D2;
2313 } else {
2314 /* Bypass PLL */
2315 bypass_pll:
2316 M = D0;
2317 PLL_out = cpc->sysclk * M;
2318 }
2319 CPU_clk = PLL_out;
2320 if (cpc->cr1 & 0x00800000)
2321 TMR_clk = cpc->sysclk; /* Should have a separate clock */
2322 else
2323 TMR_clk = CPU_clk;
2324 PLB_clk = CPU_clk / D0;
2325 SDRAM_clk = PLB_clk;
2326 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
2327 OPB_clk = PLB_clk / D0;
2328 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
2329 EXT_clk = PLB_clk / D0;
2330 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
2331 UART_clk = CPU_clk / D0;
2332 /* Setup CPU clocks */
2333 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
2334 /* Setup time-base clock */
2335 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
2336 /* Setup PLB clock */
2337 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
2338 /* Setup SDRAM clock */
2339 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
2340 /* Setup OPB clock */
2341 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
2342 /* Setup external clock */
2343 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
2344 /* Setup UART clock */
2345 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
2346 }
2347
2348 static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
2349 {
2350 ppc405cr_cpc_t *cpc;
2351 target_ulong ret;
2352
2353 cpc = opaque;
2354 switch (dcrn) {
2355 case PPC405CR_CPC0_PLLMR:
2356 ret = cpc->pllmr;
2357 break;
2358 case PPC405CR_CPC0_CR0:
2359 ret = cpc->cr0;
2360 break;
2361 case PPC405CR_CPC0_CR1:
2362 ret = cpc->cr1;
2363 break;
2364 case PPC405CR_CPC0_PSR:
2365 ret = cpc->psr;
2366 break;
2367 case PPC405CR_CPC0_JTAGID:
2368 ret = cpc->jtagid;
2369 break;
2370 case PPC405CR_CPC0_ER:
2371 ret = cpc->er;
2372 break;
2373 case PPC405CR_CPC0_FR:
2374 ret = cpc->fr;
2375 break;
2376 case PPC405CR_CPC0_SR:
2377 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
2378 break;
2379 default:
2380 /* Avoid gcc warning */
2381 ret = 0;
2382 break;
2383 }
2384
2385 return ret;
2386 }
2387
2388 static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
2389 {
2390 ppc405cr_cpc_t *cpc;
2391
2392 cpc = opaque;
2393 switch (dcrn) {
2394 case PPC405CR_CPC0_PLLMR:
2395 cpc->pllmr = val & 0xFFF77C3F;
2396 break;
2397 case PPC405CR_CPC0_CR0:
2398 cpc->cr0 = val & 0x0FFFFFFE;
2399 break;
2400 case PPC405CR_CPC0_CR1:
2401 cpc->cr1 = val & 0x00800000;
2402 break;
2403 case PPC405CR_CPC0_PSR:
2404 /* Read-only */
2405 break;
2406 case PPC405CR_CPC0_JTAGID:
2407 /* Read-only */
2408 break;
2409 case PPC405CR_CPC0_ER:
2410 cpc->er = val & 0xBFFC0000;
2411 break;
2412 case PPC405CR_CPC0_FR:
2413 cpc->fr = val & 0xBFFC0000;
2414 break;
2415 case PPC405CR_CPC0_SR:
2416 /* Read-only */
2417 break;
2418 }
2419 }
2420
2421 static void ppc405cr_cpc_reset (void *opaque)
2422 {
2423 ppc405cr_cpc_t *cpc;
2424 int D;
2425
2426 cpc = opaque;
2427 /* Compute PLLMR value from PSR settings */
2428 cpc->pllmr = 0x80000000;
2429 /* PFWD */
2430 switch ((cpc->psr >> 30) & 3) {
2431 case 0:
2432 /* Bypass */
2433 cpc->pllmr &= ~0x80000000;
2434 break;
2435 case 1:
2436 /* Divide by 3 */
2437 cpc->pllmr |= 5 << 16;
2438 break;
2439 case 2:
2440 /* Divide by 4 */
2441 cpc->pllmr |= 4 << 16;
2442 break;
2443 case 3:
2444 /* Divide by 6 */
2445 cpc->pllmr |= 2 << 16;
2446 break;
2447 }
2448 /* PFBD */
2449 D = (cpc->psr >> 28) & 3;
2450 cpc->pllmr |= (D + 1) << 20;
2451 /* PT */
2452 D = (cpc->psr >> 25) & 7;
2453 switch (D) {
2454 case 0x2:
2455 cpc->pllmr |= 0x13;
2456 break;
2457 case 0x4:
2458 cpc->pllmr |= 0x15;
2459 break;
2460 case 0x5:
2461 cpc->pllmr |= 0x16;
2462 break;
2463 default:
2464 break;
2465 }
2466 /* PDC */
2467 D = (cpc->psr >> 23) & 3;
2468 cpc->pllmr |= D << 26;
2469 /* ODP */
2470 D = (cpc->psr >> 21) & 3;
2471 cpc->pllmr |= D << 10;
2472 /* EBPD */
2473 D = (cpc->psr >> 17) & 3;
2474 cpc->pllmr |= D << 24;
2475 cpc->cr0 = 0x0000003C;
2476 cpc->cr1 = 0x2B0D8800;
2477 cpc->er = 0x00000000;
2478 cpc->fr = 0x00000000;
2479 ppc405cr_clk_setup(cpc);
2480 }
2481
2482 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2483 {
2484 int D;
2485
2486 /* XXX: this should be read from IO pins */
2487 cpc->psr = 0x00000000; /* 8 bits ROM */
2488 /* PFWD */
2489 D = 0x2; /* Divide by 4 */
2490 cpc->psr |= D << 30;
2491 /* PFBD */
2492 D = 0x1; /* Divide by 2 */
2493 cpc->psr |= D << 28;
2494 /* PDC */
2495 D = 0x1; /* Divide by 2 */
2496 cpc->psr |= D << 23;
2497 /* PT */
2498 D = 0x5; /* M = 16 */
2499 cpc->psr |= D << 25;
2500 /* ODP */
2501 D = 0x1; /* Divide by 2 */
2502 cpc->psr |= D << 21;
2503 /* EBDP */
2504 D = 0x2; /* Divide by 4 */
2505 cpc->psr |= D << 17;
2506 }
2507
2508 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2509 uint32_t sysclk)
2510 {
2511 ppc405cr_cpc_t *cpc;
2512
2513 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2514 if (cpc != NULL) {
2515 memcpy(cpc->clk_setup, clk_setup,
2516 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2517 cpc->sysclk = sysclk;
2518 cpc->jtagid = 0x42051049;
2519 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2520 &dcr_read_crcpc, &dcr_write_crcpc);
2521 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2522 &dcr_read_crcpc, &dcr_write_crcpc);
2523 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2524 &dcr_read_crcpc, &dcr_write_crcpc);
2525 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2526 &dcr_read_crcpc, &dcr_write_crcpc);
2527 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2528 &dcr_read_crcpc, &dcr_write_crcpc);
2529 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2530 &dcr_read_crcpc, &dcr_write_crcpc);
2531 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2532 &dcr_read_crcpc, &dcr_write_crcpc);
2533 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2534 &dcr_read_crcpc, &dcr_write_crcpc);
2535 ppc405cr_clk_init(cpc);
2536 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2537 ppc405cr_cpc_reset(cpc);
2538 }
2539 }
2540
2541 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
2542 target_phys_addr_t ram_sizes[4],
2543 uint32_t sysclk, qemu_irq **picp,
2544 ram_addr_t *offsetp, int do_init)
2545 {
2546 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2547 qemu_irq dma_irqs[4];
2548 CPUState *env;
2549 ppc4xx_mmio_t *mmio;
2550 qemu_irq *pic, *irqs;
2551 ram_addr_t offset;
2552 int i;
2553
2554 memset(clk_setup, 0, sizeof(clk_setup));
2555 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2556 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2557 /* Memory mapped devices registers */
2558 mmio = ppc4xx_mmio_init(env, 0xEF600000);
2559 /* PLB arbitrer */
2560 ppc4xx_plb_init(env);
2561 /* PLB to OPB bridge */
2562 ppc4xx_pob_init(env);
2563 /* OBP arbitrer */
2564 ppc4xx_opba_init(env, mmio, 0x600);
2565 /* Universal interrupt controller */
2566 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2567 irqs[PPCUIC_OUTPUT_INT] =
2568 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2569 irqs[PPCUIC_OUTPUT_CINT] =
2570 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2571 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2572 *picp = pic;
2573 /* SDRAM controller */
2574 ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
2575 offset = 0;
2576 for (i = 0; i < 4; i++)
2577 offset += ram_sizes[i];
2578 /* External bus controller */
2579 ppc405_ebc_init(env);
2580 /* DMA controller */
2581 dma_irqs[0] = pic[26];
2582 dma_irqs[1] = pic[25];
2583 dma_irqs[2] = pic[24];
2584 dma_irqs[3] = pic[23];
2585 ppc405_dma_init(env, dma_irqs);
2586 /* Serial ports */
2587 if (serial_hds[0] != NULL) {
2588 ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
2589 }
2590 if (serial_hds[1] != NULL) {
2591 ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
2592 }
2593 /* IIC controller */
2594 ppc405_i2c_init(env, mmio, 0x500, pic[2]);
2595 /* GPIO */
2596 ppc405_gpio_init(env, mmio, 0x700);
2597 /* CPU control */
2598 ppc405cr_cpc_init(env, clk_setup, sysclk);
2599 *offsetp = offset;
2600
2601 return env;
2602 }
2603
2604 /*****************************************************************************/
2605 /* PowerPC 405EP */
2606 /* CPU control */
2607 enum {
2608 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2609 PPC405EP_CPC0_BOOT = 0x0F1,
2610 PPC405EP_CPC0_EPCTL = 0x0F3,
2611 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2612 PPC405EP_CPC0_UCR = 0x0F5,
2613 PPC405EP_CPC0_SRR = 0x0F6,
2614 PPC405EP_CPC0_JTAGID = 0x0F7,
2615 PPC405EP_CPC0_PCI = 0x0F9,
2616 #if 0
2617 PPC405EP_CPC0_ER = xxx,
2618 PPC405EP_CPC0_FR = xxx,
2619 PPC405EP_CPC0_SR = xxx,
2620 #endif
2621 };
2622
2623 enum {
2624 PPC405EP_CPU_CLK = 0,
2625 PPC405EP_PLB_CLK = 1,
2626 PPC405EP_OPB_CLK = 2,
2627 PPC405EP_EBC_CLK = 3,
2628 PPC405EP_MAL_CLK = 4,
2629 PPC405EP_PCI_CLK = 5,
2630 PPC405EP_UART0_CLK = 6,
2631 PPC405EP_UART1_CLK = 7,
2632 PPC405EP_CLK_NB = 8,
2633 };
2634
2635 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2636 struct ppc405ep_cpc_t {
2637 uint32_t sysclk;
2638 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2639 uint32_t boot;
2640 uint32_t epctl;
2641 uint32_t pllmr[2];
2642 uint32_t ucr;
2643 uint32_t srr;
2644 uint32_t jtagid;
2645 uint32_t pci;
2646 /* Clock and power management */
2647 uint32_t er;
2648 uint32_t fr;
2649 uint32_t sr;
2650 };
2651
2652 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2653 {
2654 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2655 uint32_t UART0_clk, UART1_clk;
2656 uint64_t VCO_out, PLL_out;
2657 int M, D;
2658
2659 VCO_out = 0;
2660 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2661 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2662 #ifdef DEBUG_CLOCKS_LL
2663 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2664 #endif
2665 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2666 #ifdef DEBUG_CLOCKS_LL
2667 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2668 #endif
2669 VCO_out = cpc->sysclk * M * D;
2670 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2671 /* Error - unlock the PLL */
2672 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2673 #if 0
2674 cpc->pllmr[1] &= ~0x80000000;
2675 goto pll_bypass;
2676 #endif
2677 }
2678 PLL_out = VCO_out / D;
2679 /* Pretend the PLL is locked */
2680 cpc->boot |= 0x00000001;
2681 } else {
2682 #if 0
2683 pll_bypass:
2684 #endif
2685 PLL_out = cpc->sysclk;
2686 if (cpc->pllmr[1] & 0x40000000) {
2687 /* Pretend the PLL is not locked */
2688 cpc->boot &= ~0x00000001;
2689 }
2690 }
2691 /* Now, compute all other clocks */
2692 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2693 #ifdef DEBUG_CLOCKS_LL
2694 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2695 #endif
2696 CPU_clk = PLL_out / D;
2697 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2698 #ifdef DEBUG_CLOCKS_LL
2699 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2700 #endif
2701 PLB_clk = CPU_clk / D;
2702 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2703 #ifdef DEBUG_CLOCKS_LL
2704 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2705 #endif
2706 OPB_clk = PLB_clk / D;
2707 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2708 #ifdef DEBUG_CLOCKS_LL
2709 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2710 #endif
2711 EBC_clk = PLB_clk / D;
2712 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2713 #ifdef DEBUG_CLOCKS_LL
2714 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2715 #endif
2716 MAL_clk = PLB_clk / D;
2717 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2718 #ifdef DEBUG_CLOCKS_LL
2719 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2720 #endif
2721 PCI_clk = PLB_clk / D;
2722 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2723 #ifdef DEBUG_CLOCKS_LL
2724 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2725 #endif
2726 UART0_clk = PLL_out / D;
2727 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2728 #ifdef DEBUG_CLOCKS_LL
2729 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2730 #endif
2731 UART1_clk = PLL_out / D;
2732 #ifdef DEBUG_CLOCKS
2733 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2734 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2735 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2736 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2737 " UART1 %" PRIu32 "\n",
2738 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2739 UART0_clk, UART1_clk);
2740 #endif
2741 /* Setup CPU clocks */
2742 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2743 /* Setup PLB clock */
2744 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2745 /* Setup OPB clock */
2746 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2747 /* Setup external clock */
2748 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2749 /* Setup MAL clock */
2750 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2751 /* Setup PCI clock */
2752 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2753 /* Setup UART0 clock */
2754 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2755 /* Setup UART1 clock */
2756 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2757 }
2758
2759 static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
2760 {
2761 ppc405ep_cpc_t *cpc;
2762 target_ulong ret;
2763
2764 cpc = opaque;
2765 switch (dcrn) {
2766 case PPC405EP_CPC0_BOOT:
2767 ret = cpc->boot;
2768 break;
2769 case PPC405EP_CPC0_EPCTL:
2770 ret = cpc->epctl;
2771 break;
2772 case PPC405EP_CPC0_PLLMR0:
2773 ret = cpc->pllmr[0];
2774 break;
2775 case PPC405EP_CPC0_PLLMR1:
2776 ret = cpc->pllmr[1];
2777 break;
2778 case PPC405EP_CPC0_UCR:
2779 ret = cpc->ucr;
2780 break;
2781 case PPC405EP_CPC0_SRR:
2782 ret = cpc->srr;
2783 break;
2784 case PPC405EP_CPC0_JTAGID:
2785 ret = cpc->jtagid;
2786 break;
2787 case PPC405EP_CPC0_PCI:
2788 ret = cpc->pci;
2789 break;
2790 default:
2791 /* Avoid gcc warning */
2792 ret = 0;
2793 break;
2794 }
2795
2796 return ret;
2797 }
2798
2799 static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
2800 {
2801 ppc405ep_cpc_t *cpc;
2802
2803 cpc = opaque;
2804 switch (dcrn) {
2805 case PPC405EP_CPC0_BOOT:
2806 /* Read-only register */
2807 break;
2808 case PPC405EP_CPC0_EPCTL:
2809 /* Don't care for now */
2810 cpc->epctl = val & 0xC00000F3;
2811 break;
2812 case PPC405EP_CPC0_PLLMR0:
2813 cpc->pllmr[0] = val & 0x00633333;
2814 ppc405ep_compute_clocks(cpc);
2815 break;
2816 case PPC405EP_CPC0_PLLMR1:
2817 cpc->pllmr[1] = val & 0xC0F73FFF;
2818 ppc405ep_compute_clocks(cpc);
2819 break;
2820 case PPC405EP_CPC0_UCR:
2821 /* UART control - don't care for now */
2822 cpc->ucr = val & 0x003F7F7F;
2823 break;
2824 case PPC405EP_CPC0_SRR:
2825 cpc->srr = val;
2826 break;
2827 case PPC405EP_CPC0_JTAGID:
2828 /* Read-only */
2829 break;
2830 case PPC405EP_CPC0_PCI:
2831 cpc->pci = val;
2832 break;
2833 }
2834 }
2835
2836 static void ppc405ep_cpc_reset (void *opaque)
2837 {
2838 ppc405ep_cpc_t *cpc = opaque;
2839
2840 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2841 cpc->epctl = 0x00000000;
2842 cpc->pllmr[0] = 0x00011010;
2843 cpc->pllmr[1] = 0x40000000;
2844 cpc->ucr = 0x00000000;
2845 cpc->srr = 0x00040000;
2846 cpc->pci = 0x00000000;
2847 cpc->er = 0x00000000;
2848 cpc->fr = 0x00000000;
2849 cpc->sr = 0x00000000;
2850 ppc405ep_compute_clocks(cpc);
2851 }
2852
2853 /* XXX: sysclk should be between 25 and 100 MHz */
2854 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2855 uint32_t sysclk)
2856 {
2857 ppc405ep_cpc_t *cpc;
2858
2859 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
2860 if (cpc != NULL) {
2861 memcpy(cpc->clk_setup, clk_setup,
2862 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2863 cpc->jtagid = 0x20267049;
2864 cpc->sysclk = sysclk;
2865 ppc405ep_cpc_reset(cpc);
2866 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2867 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2868 &dcr_read_epcpc, &dcr_write_epcpc);
2869 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2870 &dcr_read_epcpc, &dcr_write_epcpc);
2871 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2872 &dcr_read_epcpc, &dcr_write_epcpc);
2873 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2874 &dcr_read_epcpc, &dcr_write_epcpc);
2875 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2876 &dcr_read_epcpc, &dcr_write_epcpc);
2877 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2878 &dcr_read_epcpc, &dcr_write_epcpc);
2879 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2880 &dcr_read_epcpc, &dcr_write_epcpc);
2881 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2882 &dcr_read_epcpc, &dcr_write_epcpc);
2883 #if 0
2884 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2885 &dcr_read_epcpc, &dcr_write_epcpc);
2886 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2887 &dcr_read_epcpc, &dcr_write_epcpc);
2888 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2889 &dcr_read_epcpc, &dcr_write_epcpc);
2890 #endif
2891 }
2892 }
2893
2894 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
2895 target_phys_addr_t ram_sizes[2],
2896 uint32_t sysclk, qemu_irq **picp,
2897 ram_addr_t *offsetp, int do_init)
2898 {
2899 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2900 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2901 CPUState *env;
2902 ppc4xx_mmio_t *mmio;
2903 qemu_irq *pic, *irqs;
2904 ram_addr_t offset;
2905 int i;
2906
2907 memset(clk_setup, 0, sizeof(clk_setup));
2908 /* init CPUs */
2909 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2910 &tlb_clk_setup, sysclk);
2911 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2912 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2913 /* Internal devices init */
2914 /* Memory mapped devices registers */
2915 mmio = ppc4xx_mmio_init(env, 0xEF600000);
2916 /* PLB arbitrer */
2917 ppc4xx_plb_init(env);
2918 /* PLB to OPB bridge */
2919 ppc4xx_pob_init(env);
2920 /* OBP arbitrer */
2921 ppc4xx_opba_init(env, mmio, 0x600);
2922 /* Universal interrupt controller */
2923 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2924 irqs[PPCUIC_OUTPUT_INT] =
2925 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2926 irqs[PPCUIC_OUTPUT_CINT] =
2927 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2928 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2929 *picp = pic;
2930 /* SDRAM controller */
2931 /* XXX 405EP has no ECC interrupt */
2932 ppc405_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
2933 offset = 0;
2934 for (i = 0; i < 2; i++)
2935 offset += ram_sizes[i];
2936 /* External bus controller */
2937 ppc405_ebc_init(env);
2938 /* DMA controller */
2939 dma_irqs[0] = pic[5];
2940 dma_irqs[1] = pic[6];
2941 dma_irqs[2] = pic[7];
2942 dma_irqs[3] = pic[8];
2943 ppc405_dma_init(env, dma_irqs);
2944 /* IIC controller */
2945 ppc405_i2c_init(env, mmio, 0x500, pic[2]);
2946 /* GPIO */
2947 ppc405_gpio_init(env, mmio, 0x700);
2948 /* Serial ports */
2949 if (serial_hds[0] != NULL) {
2950 ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
2951 }
2952 if (serial_hds[1] != NULL) {
2953 ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
2954 }
2955 /* OCM */
2956 ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]);
2957 offset += 4096;
2958 /* GPT */
2959 gpt_irqs[0] = pic[19];
2960 gpt_irqs[1] = pic[20];
2961 gpt_irqs[2] = pic[21];
2962 gpt_irqs[3] = pic[22];
2963 gpt_irqs[4] = pic[23];
2964 ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
2965 /* PCI */
2966 /* Uses pic[3], pic[16], pic[18] */
2967 /* MAL */
2968 mal_irqs[0] = pic[11];
2969 mal_irqs[1] = pic[12];
2970 mal_irqs[2] = pic[13];
2971 mal_irqs[3] = pic[14];
2972 ppc405_mal_init(env, mal_irqs);
2973 /* Ethernet */
2974 /* Uses pic[9], pic[15], pic[17] */
2975 /* CPU control */
2976 ppc405ep_cpc_init(env, clk_setup, sysclk);
2977 *offsetp = offset;
2978
2979 return env;
2980 }
Samsung s3c2440 and arm920t support for the mini2440 dev board