2 * TI OMAP DMA gigacell.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Lauro Ramos Venancio <lauro.venancio@indt.org.br>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include "qemu-common.h"
23 #include "qemu-timer.h"
27 struct omap_dma_channel_s
{
34 enum omap_dma_port port
[2];
35 target_phys_addr_t addr
[2];
36 omap_dma_addressing_t mode
[2];
39 int32_t frame_index
[2];
40 int16_t element_index
[2];
49 /* auto init and linked channel data */
56 /* interruption data */
75 int omap_3_1_compatible_disable
;
78 struct omap_dma_channel_s
*sibling
;
80 struct omap_dma_reg_set_s
{
81 target_phys_addr_t src
, dest
;
92 /* unused parameters */
95 int interleave_disabled
;
103 struct omap_mpu_state_s
*mpu
;
104 target_phys_addr_t base
;
109 void (*intr_update
)(struct omap_dma_s
*s
);
110 enum omap_dma_model model
;
111 int omap_3_1_mapping_disabled
;
121 struct omap_dma_channel_s ch
[32];
122 struct omap_dma_lcd_channel_s lcd_ch
;
126 #define TIMEOUT_INTR (1 << 0)
127 #define EVENT_DROP_INTR (1 << 1)
128 #define HALF_FRAME_INTR (1 << 2)
129 #define END_FRAME_INTR (1 << 3)
130 #define LAST_FRAME_INTR (1 << 4)
131 #define END_BLOCK_INTR (1 << 5)
132 #define SYNC (1 << 6)
133 #define END_PKT_INTR (1 << 7)
134 #define TRANS_ERR_INTR (1 << 8)
135 #define MISALIGN_INTR (1 << 11)
137 static inline void omap_dma_interrupts_update(struct omap_dma_s
*s
)
139 return s
->intr_update(s
);
142 static void omap_dma_channel_load(struct omap_dma_s
*s
,
143 struct omap_dma_channel_s
*ch
)
145 struct omap_dma_reg_set_s
*a
= &ch
->active_set
;
147 int omap_3_1
= !ch
->omap_3_1_compatible_disable
;
150 * TODO: verify address ranges and alignment
151 * TODO: port endianness
154 a
->src
= ch
->addr
[0];
155 a
->dest
= ch
->addr
[1];
156 a
->frames
= ch
->frames
;
157 a
->elements
= ch
->elements
;
158 a
->pck_elements
= ch
->frame_index
[!ch
->src_sync
];
163 if (unlikely(!ch
->elements
|| !ch
->frames
)) {
164 printf("%s: bad DMA request\n", __FUNCTION__
);
168 for (i
= 0; i
< 2; i
++)
169 switch (ch
->mode
[i
]) {
171 a
->elem_delta
[i
] = 0;
172 a
->frame_delta
[i
] = 0;
174 case post_incremented
:
175 a
->elem_delta
[i
] = ch
->data_type
;
176 a
->frame_delta
[i
] = 0;
179 a
->elem_delta
[i
] = ch
->data_type
+
180 ch
->element_index
[omap_3_1
? 0 : i
] - 1;
181 a
->frame_delta
[i
] = 0;
184 a
->elem_delta
[i
] = ch
->data_type
+
185 ch
->element_index
[omap_3_1
? 0 : i
] - 1;
186 a
->frame_delta
[i
] = ch
->frame_index
[omap_3_1
? 0 : i
] -
187 ch
->element_index
[omap_3_1
? 0 : i
];
194 static void omap_dma_activate_channel(struct omap_dma_s
*s
,
195 struct omap_dma_channel_s
*ch
)
204 if (s
->delay
&& !qemu_timer_pending(s
->tm
))
205 qemu_mod_timer(s
->tm
, qemu_get_clock(vm_clock
) + s
->delay
);
208 static void omap_dma_deactivate_channel(struct omap_dma_s
*s
,
209 struct omap_dma_channel_s
*ch
)
212 ch
->cpc
= ch
->active_set
.dest
& 0xffff;
214 if (ch
->pending_request
&& !ch
->waiting_end_prog
&& ch
->enable
) {
215 /* Don't deactivate the channel */
216 ch
->pending_request
= 0;
220 /* Don't deactive the channel if it is synchronized and the DMA request is
222 if (ch
->sync
&& ch
->enable
&& (s
->drq
& (1 << ch
->sync
)))
232 qemu_del_timer(s
->tm
);
235 static void omap_dma_enable_channel(struct omap_dma_s
*s
,
236 struct omap_dma_channel_s
*ch
)
240 ch
->waiting_end_prog
= 0;
241 omap_dma_channel_load(s
, ch
);
242 /* TODO: theoretically if ch->sync && ch->prefetch &&
243 * !s->drq[ch->sync], we should also activate and fetch from source
244 * and then stall until signalled. */
245 if ((!ch
->sync
) || (s
->drq
& (1 << ch
->sync
)))
246 omap_dma_activate_channel(s
, ch
);
250 static void omap_dma_disable_channel(struct omap_dma_s
*s
,
251 struct omap_dma_channel_s
*ch
)
255 /* Discard any pending request */
256 ch
->pending_request
= 0;
257 omap_dma_deactivate_channel(s
, ch
);
261 static void omap_dma_channel_end_prog(struct omap_dma_s
*s
,
262 struct omap_dma_channel_s
*ch
)
264 if (ch
->waiting_end_prog
) {
265 ch
->waiting_end_prog
= 0;
266 if (!ch
->sync
|| ch
->pending_request
) {
267 ch
->pending_request
= 0;
268 omap_dma_activate_channel(s
, ch
);
273 static void omap_dma_interrupts_3_1_update(struct omap_dma_s
*s
)
275 struct omap_dma_channel_s
*ch
= s
->ch
;
277 /* First three interrupts are shared between two channels each. */
278 if (ch
[0].status
| ch
[6].status
)
279 qemu_irq_raise(ch
[0].irq
);
280 if (ch
[1].status
| ch
[7].status
)
281 qemu_irq_raise(ch
[1].irq
);
282 if (ch
[2].status
| ch
[8].status
)
283 qemu_irq_raise(ch
[2].irq
);
285 qemu_irq_raise(ch
[3].irq
);
287 qemu_irq_raise(ch
[4].irq
);
289 qemu_irq_raise(ch
[5].irq
);
292 static void omap_dma_interrupts_3_2_update(struct omap_dma_s
*s
)
294 struct omap_dma_channel_s
*ch
= s
->ch
;
297 for (i
= s
->chans
; i
; ch
++, i
--)
299 qemu_irq_raise(ch
->irq
);
302 static void omap_dma_enable_3_1_mapping(struct omap_dma_s
*s
)
304 s
->omap_3_1_mapping_disabled
= 0;
306 s
->intr_update
= omap_dma_interrupts_3_1_update
;
309 static void omap_dma_disable_3_1_mapping(struct omap_dma_s
*s
)
311 s
->omap_3_1_mapping_disabled
= 1;
313 s
->intr_update
= omap_dma_interrupts_3_2_update
;
316 static void omap_dma_process_request(struct omap_dma_s
*s
, int request
)
320 struct omap_dma_channel_s
*ch
= s
->ch
;
322 for (channel
= 0; channel
< s
->chans
; channel
++, ch
++) {
323 if (ch
->enable
&& ch
->sync
== request
) {
325 omap_dma_activate_channel(s
, ch
);
326 else if (!ch
->pending_request
)
327 ch
->pending_request
= 1;
329 /* Request collision */
330 /* Second request received while processing other request */
331 ch
->status
|= EVENT_DROP_INTR
;
338 omap_dma_interrupts_update(s
);
341 static void omap_dma_channel_run(struct omap_dma_s
*s
)
346 struct omap_dma_port_if_s
*src_p
, *dest_p
;
347 struct omap_dma_reg_set_s
*a
;
348 struct omap_dma_channel_s
*ch
;
350 for (ch
= s
->ch
; n
; n
--, ch
++) {
356 src_p
= &s
->mpu
->port
[ch
->port
[0]];
357 dest_p
= &s
->mpu
->port
[ch
->port
[1]];
358 if ((!ch
->constant_fill
&& !src_p
->addr_valid(s
->mpu
, a
->src
)) ||
359 (!dest_p
->addr_valid(s
->mpu
, a
->dest
))) {
362 if (ch
->interrupts
& TIMEOUT_INTR
)
363 ch
->status
|= TIMEOUT_INTR
;
364 omap_dma_deactivate_channel(s
, ch
);
367 printf("%s: Bus time-out in DMA%i operation\n",
368 __FUNCTION__
, s
->chans
- n
);
372 while (status
== ch
->status
&& ch
->active
) {
373 /* Transfer a single element */
374 /* FIXME: check the endianness */
375 if (!ch
->constant_fill
)
376 cpu_physical_memory_read(a
->src
, value
, ch
->data_type
);
378 *(uint32_t *) value
= ch
->color
;
380 if (!ch
->transparent_copy
||
381 *(uint32_t *) value
!= ch
->color
)
382 cpu_physical_memory_write(a
->dest
, value
, ch
->data_type
);
384 a
->src
+= a
->elem_delta
[0];
385 a
->dest
+= a
->elem_delta
[1];
388 /* If the channel is element synchronized, deactivate it */
389 if (ch
->sync
&& !ch
->fs
&& !ch
->bs
)
390 omap_dma_deactivate_channel(s
, ch
);
392 /* If it is the last frame, set the LAST_FRAME interrupt */
393 if (a
->element
== 1 && a
->frame
== a
->frames
- 1)
394 if (ch
->interrupts
& LAST_FRAME_INTR
)
395 ch
->status
|= LAST_FRAME_INTR
;
397 /* If the half of the frame was reached, set the HALF_FRAME
399 if (a
->element
== (a
->elements
>> 1))
400 if (ch
->interrupts
& HALF_FRAME_INTR
)
401 ch
->status
|= HALF_FRAME_INTR
;
403 if (ch
->fs
&& ch
->bs
) {
405 /* Check if a full packet has beed transferred. */
406 if (a
->pck_element
== a
->pck_elements
) {
409 /* Set the END_PKT interrupt */
410 if ((ch
->interrupts
& END_PKT_INTR
) && !ch
->src_sync
)
411 ch
->status
|= END_PKT_INTR
;
413 /* If the channel is packet-synchronized, deactivate it */
415 omap_dma_deactivate_channel(s
, ch
);
419 if (a
->element
== a
->elements
) {
422 a
->src
+= a
->frame_delta
[0];
423 a
->dest
+= a
->frame_delta
[1];
426 /* If the channel is frame synchronized, deactivate it */
427 if (ch
->sync
&& ch
->fs
&& !ch
->bs
)
428 omap_dma_deactivate_channel(s
, ch
);
430 /* If the channel is async, update cpc */
432 ch
->cpc
= a
->dest
& 0xffff;
434 /* Set the END_FRAME interrupt */
435 if (ch
->interrupts
& END_FRAME_INTR
)
436 ch
->status
|= END_FRAME_INTR
;
438 if (a
->frame
== a
->frames
) {
440 /* Disable the channel */
442 if (ch
->omap_3_1_compatible_disable
) {
443 omap_dma_disable_channel(s
, ch
);
444 if (ch
->link_enabled
)
445 omap_dma_enable_channel(s
,
446 &s
->ch
[ch
->link_next_ch
]);
449 omap_dma_disable_channel(s
, ch
);
450 else if (ch
->repeat
|| ch
->end_prog
)
451 omap_dma_channel_load(s
, ch
);
453 ch
->waiting_end_prog
= 1;
454 omap_dma_deactivate_channel(s
, ch
);
458 if (ch
->interrupts
& END_BLOCK_INTR
)
459 ch
->status
|= END_BLOCK_INTR
;
465 omap_dma_interrupts_update(s
);
466 if (s
->run_count
&& s
->delay
)
467 qemu_mod_timer(s
->tm
, qemu_get_clock(vm_clock
) + s
->delay
);
470 void omap_dma_reset(struct omap_dma_s
*s
)
474 qemu_del_timer(s
->tm
);
475 if (s
->model
< omap_dma_4
)
480 memset(&s
->irqstat
, 0, sizeof(s
->irqstat
));
481 memset(&s
->irqen
, 0, sizeof(s
->irqen
));
484 s
->lcd_ch
.src
= emiff
;
485 s
->lcd_ch
.condition
= 0;
486 s
->lcd_ch
.interrupts
= 0;
488 if (s
->model
< omap_dma_4
)
489 omap_dma_enable_3_1_mapping(s
);
490 for (i
= 0; i
< s
->chans
; i
++) {
491 s
->ch
[i
].suspend
= 0;
492 s
->ch
[i
].prefetch
= 0;
493 s
->ch
[i
].buf_disable
= 0;
494 s
->ch
[i
].src_sync
= 0;
495 memset(&s
->ch
[i
].burst
, 0, sizeof(s
->ch
[i
].burst
));
496 memset(&s
->ch
[i
].port
, 0, sizeof(s
->ch
[i
].port
));
497 memset(&s
->ch
[i
].mode
, 0, sizeof(s
->ch
[i
].mode
));
498 memset(&s
->ch
[i
].frame_index
, 0, sizeof(s
->ch
[i
].frame_index
));
499 memset(&s
->ch
[i
].element_index
, 0, sizeof(s
->ch
[i
].element_index
));
500 memset(&s
->ch
[i
].endian
, 0, sizeof(s
->ch
[i
].endian
));
501 memset(&s
->ch
[i
].endian_lock
, 0, sizeof(s
->ch
[i
].endian_lock
));
502 memset(&s
->ch
[i
].translate
, 0, sizeof(s
->ch
[i
].translate
));
503 s
->ch
[i
].write_mode
= 0;
504 s
->ch
[i
].data_type
= 0;
505 s
->ch
[i
].transparent_copy
= 0;
506 s
->ch
[i
].constant_fill
= 0;
507 s
->ch
[i
].color
= 0x00000000;
508 s
->ch
[i
].end_prog
= 0;
510 s
->ch
[i
].auto_init
= 0;
511 s
->ch
[i
].link_enabled
= 0;
512 if (s
->model
< omap_dma_4
)
513 s
->ch
[i
].interrupts
= 0x0003;
515 s
->ch
[i
].interrupts
= 0x0000;
517 s
->ch
[i
].cstatus
= 0;
521 s
->ch
[i
].pending_request
= 0;
522 s
->ch
[i
].waiting_end_prog
= 0;
523 s
->ch
[i
].cpc
= 0x0000;
526 s
->ch
[i
].omap_3_1_compatible_disable
= 0;
527 memset(&s
->ch
[i
].active_set
, 0, sizeof(s
->ch
[i
].active_set
));
528 s
->ch
[i
].priority
= 0;
529 s
->ch
[i
].interleave_disabled
= 0;
534 static int omap_dma_ch_reg_read(struct omap_dma_s
*s
,
535 struct omap_dma_channel_s
*ch
, int reg
, uint16_t *value
)
538 case 0x00: /* SYS_DMA_CSDP_CH0 */
539 *value
= (ch
->burst
[1] << 14) |
540 (ch
->pack
[1] << 13) |
542 (ch
->burst
[0] << 7) |
545 (ch
->data_type
>> 1);
548 case 0x02: /* SYS_DMA_CCR_CH0 */
549 if (s
->model
<= omap_dma_3_1
)
550 *value
= 0 << 10; /* FIFO_FLUSH reads as 0 */
552 *value
= ch
->omap_3_1_compatible_disable
<< 10;
553 *value
|= (ch
->mode
[1] << 14) |
554 (ch
->mode
[0] << 12) |
555 (ch
->end_prog
<< 11) |
557 (ch
->auto_init
<< 8) |
559 (ch
->priority
<< 6) |
560 (ch
->fs
<< 5) | ch
->sync
;
563 case 0x04: /* SYS_DMA_CICR_CH0 */
564 *value
= ch
->interrupts
;
567 case 0x06: /* SYS_DMA_CSR_CH0 */
570 if (!ch
->omap_3_1_compatible_disable
&& ch
->sibling
) {
571 *value
|= (ch
->sibling
->status
& 0x3f) << 6;
572 ch
->sibling
->status
&= SYNC
;
574 qemu_irq_lower(ch
->irq
);
577 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
578 *value
= ch
->addr
[0] & 0x0000ffff;
581 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
582 *value
= ch
->addr
[0] >> 16;
585 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
586 *value
= ch
->addr
[1] & 0x0000ffff;
589 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
590 *value
= ch
->addr
[1] >> 16;
593 case 0x10: /* SYS_DMA_CEN_CH0 */
594 *value
= ch
->elements
;
597 case 0x12: /* SYS_DMA_CFN_CH0 */
601 case 0x14: /* SYS_DMA_CFI_CH0 */
602 *value
= ch
->frame_index
[0];
605 case 0x16: /* SYS_DMA_CEI_CH0 */
606 *value
= ch
->element_index
[0];
609 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
610 if (ch
->omap_3_1_compatible_disable
)
611 *value
= ch
->active_set
.src
& 0xffff; /* CSAC */
616 case 0x1a: /* DMA_CDAC */
617 *value
= ch
->active_set
.dest
& 0xffff; /* CDAC */
620 case 0x1c: /* DMA_CDEI */
621 *value
= ch
->element_index
[1];
624 case 0x1e: /* DMA_CDFI */
625 *value
= ch
->frame_index
[1];
628 case 0x20: /* DMA_COLOR_L */
629 *value
= ch
->color
& 0xffff;
632 case 0x22: /* DMA_COLOR_U */
633 *value
= ch
->color
>> 16;
636 case 0x24: /* DMA_CCR2 */
637 *value
= (ch
->bs
<< 2) |
638 (ch
->transparent_copy
<< 1) |
642 case 0x28: /* DMA_CLNK_CTRL */
643 *value
= (ch
->link_enabled
<< 15) |
644 (ch
->link_next_ch
& 0xf);
647 case 0x2a: /* DMA_LCH_CTRL */
648 *value
= (ch
->interleave_disabled
<< 15) |
658 static int omap_dma_ch_reg_write(struct omap_dma_s
*s
,
659 struct omap_dma_channel_s
*ch
, int reg
, uint16_t value
)
662 case 0x00: /* SYS_DMA_CSDP_CH0 */
663 ch
->burst
[1] = (value
& 0xc000) >> 14;
664 ch
->pack
[1] = (value
& 0x2000) >> 13;
665 ch
->port
[1] = (enum omap_dma_port
) ((value
& 0x1e00) >> 9);
666 ch
->burst
[0] = (value
& 0x0180) >> 7;
667 ch
->pack
[0] = (value
& 0x0040) >> 6;
668 ch
->port
[0] = (enum omap_dma_port
) ((value
& 0x003c) >> 2);
669 ch
->data_type
= 1 << (value
& 3);
670 if (ch
->port
[0] >= __omap_dma_port_last
)
671 printf("%s: invalid DMA port %i\n", __FUNCTION__
,
673 if (ch
->port
[1] >= __omap_dma_port_last
)
674 printf("%s: invalid DMA port %i\n", __FUNCTION__
,
676 if ((value
& 3) == 3)
677 printf("%s: bad data_type for DMA channel\n", __FUNCTION__
);
680 case 0x02: /* SYS_DMA_CCR_CH0 */
681 ch
->mode
[1] = (omap_dma_addressing_t
) ((value
& 0xc000) >> 14);
682 ch
->mode
[0] = (omap_dma_addressing_t
) ((value
& 0x3000) >> 12);
683 ch
->end_prog
= (value
& 0x0800) >> 11;
684 if (s
->model
>= omap_dma_3_2
)
685 ch
->omap_3_1_compatible_disable
= (value
>> 10) & 0x1;
686 ch
->repeat
= (value
& 0x0200) >> 9;
687 ch
->auto_init
= (value
& 0x0100) >> 8;
688 ch
->priority
= (value
& 0x0040) >> 6;
689 ch
->fs
= (value
& 0x0020) >> 5;
690 ch
->sync
= value
& 0x001f;
693 omap_dma_enable_channel(s
, ch
);
695 omap_dma_disable_channel(s
, ch
);
698 omap_dma_channel_end_prog(s
, ch
);
702 case 0x04: /* SYS_DMA_CICR_CH0 */
703 ch
->interrupts
= value
& 0x3f;
706 case 0x06: /* SYS_DMA_CSR_CH0 */
707 OMAP_RO_REG((target_phys_addr_t
) reg
);
710 case 0x08: /* SYS_DMA_CSSA_L_CH0 */
711 ch
->addr
[0] &= 0xffff0000;
712 ch
->addr
[0] |= value
;
715 case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
716 ch
->addr
[0] &= 0x0000ffff;
717 ch
->addr
[0] |= (uint32_t) value
<< 16;
720 case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
721 ch
->addr
[1] &= 0xffff0000;
722 ch
->addr
[1] |= value
;
725 case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
726 ch
->addr
[1] &= 0x0000ffff;
727 ch
->addr
[1] |= (uint32_t) value
<< 16;
730 case 0x10: /* SYS_DMA_CEN_CH0 */
731 ch
->elements
= value
;
734 case 0x12: /* SYS_DMA_CFN_CH0 */
738 case 0x14: /* SYS_DMA_CFI_CH0 */
739 ch
->frame_index
[0] = (int16_t) value
;
742 case 0x16: /* SYS_DMA_CEI_CH0 */
743 ch
->element_index
[0] = (int16_t) value
;
746 case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
747 OMAP_RO_REG((target_phys_addr_t
) reg
);
750 case 0x1c: /* DMA_CDEI */
751 ch
->element_index
[1] = (int16_t) value
;
754 case 0x1e: /* DMA_CDFI */
755 ch
->frame_index
[1] = (int16_t) value
;
758 case 0x20: /* DMA_COLOR_L */
759 ch
->color
&= 0xffff0000;
763 case 0x22: /* DMA_COLOR_U */
765 ch
->color
|= value
<< 16;
768 case 0x24: /* DMA_CCR2 */
769 ch
->bs
= (value
>> 2) & 0x1;
770 ch
->transparent_copy
= (value
>> 1) & 0x1;
771 ch
->constant_fill
= value
& 0x1;
774 case 0x28: /* DMA_CLNK_CTRL */
775 ch
->link_enabled
= (value
>> 15) & 0x1;
776 if (value
& (1 << 14)) { /* Stop_Lnk */
777 ch
->link_enabled
= 0;
778 omap_dma_disable_channel(s
, ch
);
780 ch
->link_next_ch
= value
& 0x1f;
783 case 0x2a: /* DMA_LCH_CTRL */
784 ch
->interleave_disabled
= (value
>> 15) & 0x1;
785 ch
->type
= value
& 0xf;
794 static int omap_dma_3_2_lcd_write(struct omap_dma_lcd_channel_s
*s
, int offset
,
798 case 0xbc0: /* DMA_LCD_CSDP */
799 s
->brust_f2
= (value
>> 14) & 0x3;
800 s
->pack_f2
= (value
>> 13) & 0x1;
801 s
->data_type_f2
= (1 << ((value
>> 11) & 0x3));
802 s
->brust_f1
= (value
>> 7) & 0x3;
803 s
->pack_f1
= (value
>> 6) & 0x1;
804 s
->data_type_f1
= (1 << ((value
>> 0) & 0x3));
807 case 0xbc2: /* DMA_LCD_CCR */
808 s
->mode_f2
= (value
>> 14) & 0x3;
809 s
->mode_f1
= (value
>> 12) & 0x3;
810 s
->end_prog
= (value
>> 11) & 0x1;
811 s
->omap_3_1_compatible_disable
= (value
>> 10) & 0x1;
812 s
->repeat
= (value
>> 9) & 0x1;
813 s
->auto_init
= (value
>> 8) & 0x1;
814 s
->running
= (value
>> 7) & 0x1;
815 s
->priority
= (value
>> 6) & 0x1;
816 s
->bs
= (value
>> 4) & 0x1;
819 case 0xbc4: /* DMA_LCD_CTRL */
820 s
->dst
= (value
>> 8) & 0x1;
821 s
->src
= ((value
>> 6) & 0x3) << 1;
823 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
824 s
->interrupts
= (value
>> 1) & 1;
828 case 0xbc8: /* TOP_B1_L */
829 s
->src_f1_top
&= 0xffff0000;
830 s
->src_f1_top
|= 0x0000ffff & value
;
833 case 0xbca: /* TOP_B1_U */
834 s
->src_f1_top
&= 0x0000ffff;
835 s
->src_f1_top
|= value
<< 16;
838 case 0xbcc: /* BOT_B1_L */
839 s
->src_f1_bottom
&= 0xffff0000;
840 s
->src_f1_bottom
|= 0x0000ffff & value
;
843 case 0xbce: /* BOT_B1_U */
844 s
->src_f1_bottom
&= 0x0000ffff;
845 s
->src_f1_bottom
|= (uint32_t) value
<< 16;
848 case 0xbd0: /* TOP_B2_L */
849 s
->src_f2_top
&= 0xffff0000;
850 s
->src_f2_top
|= 0x0000ffff & value
;
853 case 0xbd2: /* TOP_B2_U */
854 s
->src_f2_top
&= 0x0000ffff;
855 s
->src_f2_top
|= (uint32_t) value
<< 16;
858 case 0xbd4: /* BOT_B2_L */
859 s
->src_f2_bottom
&= 0xffff0000;
860 s
->src_f2_bottom
|= 0x0000ffff & value
;
863 case 0xbd6: /* BOT_B2_U */
864 s
->src_f2_bottom
&= 0x0000ffff;
865 s
->src_f2_bottom
|= (uint32_t) value
<< 16;
868 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
869 s
->element_index_f1
= value
;
872 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
873 s
->frame_index_f1
&= 0xffff0000;
874 s
->frame_index_f1
|= 0x0000ffff & value
;
877 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
878 s
->frame_index_f1
&= 0x0000ffff;
879 s
->frame_index_f1
|= (uint32_t) value
<< 16;
882 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
883 s
->element_index_f2
= value
;
886 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
887 s
->frame_index_f2
&= 0xffff0000;
888 s
->frame_index_f2
|= 0x0000ffff & value
;
891 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
892 s
->frame_index_f2
&= 0x0000ffff;
893 s
->frame_index_f2
|= (uint32_t) value
<< 16;
896 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
897 s
->elements_f1
= value
;
900 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
901 s
->frames_f1
= value
;
904 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
905 s
->elements_f2
= value
;
908 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
909 s
->frames_f2
= value
;
912 case 0xbea: /* DMA_LCD_LCH_CTRL */
913 s
->lch_type
= value
& 0xf;
922 static int omap_dma_3_2_lcd_read(struct omap_dma_lcd_channel_s
*s
, int offset
,
926 case 0xbc0: /* DMA_LCD_CSDP */
927 *ret
= (s
->brust_f2
<< 14) |
929 ((s
->data_type_f2
>> 1) << 11) |
932 ((s
->data_type_f1
>> 1) << 0);
935 case 0xbc2: /* DMA_LCD_CCR */
936 *ret
= (s
->mode_f2
<< 14) |
938 (s
->end_prog
<< 11) |
939 (s
->omap_3_1_compatible_disable
<< 10) |
941 (s
->auto_init
<< 8) |
947 case 0xbc4: /* DMA_LCD_CTRL */
948 qemu_irq_lower(s
->irq
);
949 *ret
= (s
->dst
<< 8) |
950 ((s
->src
& 0x6) << 5) |
951 (s
->condition
<< 3) |
952 (s
->interrupts
<< 1) |
956 case 0xbc8: /* TOP_B1_L */
957 *ret
= s
->src_f1_top
& 0xffff;
960 case 0xbca: /* TOP_B1_U */
961 *ret
= s
->src_f1_top
>> 16;
964 case 0xbcc: /* BOT_B1_L */
965 *ret
= s
->src_f1_bottom
& 0xffff;
968 case 0xbce: /* BOT_B1_U */
969 *ret
= s
->src_f1_bottom
>> 16;
972 case 0xbd0: /* TOP_B2_L */
973 *ret
= s
->src_f2_top
& 0xffff;
976 case 0xbd2: /* TOP_B2_U */
977 *ret
= s
->src_f2_top
>> 16;
980 case 0xbd4: /* BOT_B2_L */
981 *ret
= s
->src_f2_bottom
& 0xffff;
984 case 0xbd6: /* BOT_B2_U */
985 *ret
= s
->src_f2_bottom
>> 16;
988 case 0xbd8: /* DMA_LCD_SRC_EI_B1 */
989 *ret
= s
->element_index_f1
;
992 case 0xbda: /* DMA_LCD_SRC_FI_B1_L */
993 *ret
= s
->frame_index_f1
& 0xffff;
996 case 0xbf4: /* DMA_LCD_SRC_FI_B1_U */
997 *ret
= s
->frame_index_f1
>> 16;
1000 case 0xbdc: /* DMA_LCD_SRC_EI_B2 */
1001 *ret
= s
->element_index_f2
;
1004 case 0xbde: /* DMA_LCD_SRC_FI_B2_L */
1005 *ret
= s
->frame_index_f2
& 0xffff;
1008 case 0xbf6: /* DMA_LCD_SRC_FI_B2_U */
1009 *ret
= s
->frame_index_f2
>> 16;
1012 case 0xbe0: /* DMA_LCD_SRC_EN_B1 */
1013 *ret
= s
->elements_f1
;
1016 case 0xbe4: /* DMA_LCD_SRC_FN_B1 */
1017 *ret
= s
->frames_f1
;
1020 case 0xbe2: /* DMA_LCD_SRC_EN_B2 */
1021 *ret
= s
->elements_f2
;
1024 case 0xbe6: /* DMA_LCD_SRC_FN_B2 */
1025 *ret
= s
->frames_f2
;
1028 case 0xbea: /* DMA_LCD_LCH_CTRL */
1038 static int omap_dma_3_1_lcd_write(struct omap_dma_lcd_channel_s
*s
, int offset
,
1042 case 0x300: /* SYS_DMA_LCD_CTRL */
1043 s
->src
= (value
& 0x40) ? imif
: emiff
;
1045 /* Assume no bus errors and thus no BUS_ERROR irq bits. */
1046 s
->interrupts
= (value
>> 1) & 1;
1047 s
->dual
= value
& 1;
1050 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1051 s
->src_f1_top
&= 0xffff0000;
1052 s
->src_f1_top
|= 0x0000ffff & value
;
1055 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1056 s
->src_f1_top
&= 0x0000ffff;
1057 s
->src_f1_top
|= value
<< 16;
1060 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1061 s
->src_f1_bottom
&= 0xffff0000;
1062 s
->src_f1_bottom
|= 0x0000ffff & value
;
1065 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1066 s
->src_f1_bottom
&= 0x0000ffff;
1067 s
->src_f1_bottom
|= value
<< 16;
1070 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1071 s
->src_f2_top
&= 0xffff0000;
1072 s
->src_f2_top
|= 0x0000ffff & value
;
1075 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1076 s
->src_f2_top
&= 0x0000ffff;
1077 s
->src_f2_top
|= value
<< 16;
1080 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1081 s
->src_f2_bottom
&= 0xffff0000;
1082 s
->src_f2_bottom
|= 0x0000ffff & value
;
1085 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1086 s
->src_f2_bottom
&= 0x0000ffff;
1087 s
->src_f2_bottom
|= value
<< 16;
1096 static int omap_dma_3_1_lcd_read(struct omap_dma_lcd_channel_s
*s
, int offset
,
1102 case 0x300: /* SYS_DMA_LCD_CTRL */
1105 qemu_irq_lower(s
->irq
);
1106 *ret
= ((s
->src
== imif
) << 6) | (i
<< 3) |
1107 (s
->interrupts
<< 1) | s
->dual
;
1110 case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
1111 *ret
= s
->src_f1_top
& 0xffff;
1114 case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
1115 *ret
= s
->src_f1_top
>> 16;
1118 case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
1119 *ret
= s
->src_f1_bottom
& 0xffff;
1122 case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
1123 *ret
= s
->src_f1_bottom
>> 16;
1126 case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
1127 *ret
= s
->src_f2_top
& 0xffff;
1130 case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
1131 *ret
= s
->src_f2_top
>> 16;
1134 case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
1135 *ret
= s
->src_f2_bottom
& 0xffff;
1138 case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
1139 *ret
= s
->src_f2_bottom
>> 16;
1148 static int omap_dma_sys_write(struct omap_dma_s
*s
, int offset
, uint16_t value
)
1151 case 0x400: /* SYS_DMA_GCR */
1155 case 0x404: /* DMA_GSCR */
1157 omap_dma_disable_3_1_mapping(s
);
1159 omap_dma_enable_3_1_mapping(s
);
1162 case 0x408: /* DMA_GRST */
1173 static int omap_dma_sys_read(struct omap_dma_s
*s
, int offset
,
1177 case 0x400: /* SYS_DMA_GCR */
1181 case 0x404: /* DMA_GSCR */
1182 *ret
= s
->omap_3_1_mapping_disabled
<< 3;
1185 case 0x408: /* DMA_GRST */
1189 case 0x442: /* DMA_HW_ID */
1190 case 0x444: /* DMA_PCh2_ID */
1191 case 0x446: /* DMA_PCh0_ID */
1192 case 0x448: /* DMA_PCh1_ID */
1193 case 0x44a: /* DMA_PChG_ID */
1194 case 0x44c: /* DMA_PChD_ID */
1198 case 0x44e: /* DMA_CAPS_0_U */
1199 *ret
= (s
->caps
[0] >> 16) & 0xffff;
1201 case 0x450: /* DMA_CAPS_0_L */
1202 *ret
= (s
->caps
[0] >> 0) & 0xffff;
1205 case 0x452: /* DMA_CAPS_1_U */
1206 *ret
= (s
->caps
[1] >> 16) & 0xffff;
1208 case 0x454: /* DMA_CAPS_1_L */
1209 *ret
= (s
->caps
[1] >> 0) & 0xffff;
1212 case 0x456: /* DMA_CAPS_2 */
1216 case 0x458: /* DMA_CAPS_3 */
1220 case 0x45a: /* DMA_CAPS_4 */
1224 case 0x460: /* DMA_PCh2_SR */
1225 case 0x480: /* DMA_PCh0_SR */
1226 case 0x482: /* DMA_PCh1_SR */
1227 case 0x4c0: /* DMA_PChD_SR_0 */
1228 printf("%s: Physical Channel Status Registers not implemented.\n",
1239 static uint32_t omap_dma_read(void *opaque
, target_phys_addr_t addr
)
1241 struct omap_dma_s
*s
= (struct omap_dma_s
*) opaque
;
1242 int reg
, ch
, offset
= addr
- s
->base
;
1246 case 0x300 ... 0x3fe:
1247 if (s
->model
<= omap_dma_3_1
|| !s
->omap_3_1_mapping_disabled
) {
1248 if (omap_dma_3_1_lcd_read(&s
->lcd_ch
, offset
, &ret
))
1253 case 0x000 ... 0x2fe:
1254 reg
= offset
& 0x3f;
1255 ch
= (offset
>> 6) & 0x0f;
1256 if (omap_dma_ch_reg_read(s
, &s
->ch
[ch
], reg
, &ret
))
1260 case 0x404 ... 0x4fe:
1261 if (s
->model
<= omap_dma_3_1
)
1265 if (omap_dma_sys_read(s
, offset
, &ret
))
1269 case 0xb00 ... 0xbfe:
1270 if (s
->model
== omap_dma_3_2
&& s
->omap_3_1_mapping_disabled
) {
1271 if (omap_dma_3_2_lcd_read(&s
->lcd_ch
, offset
, &ret
))
1282 static void omap_dma_write(void *opaque
, target_phys_addr_t addr
,
1285 struct omap_dma_s
*s
= (struct omap_dma_s
*) opaque
;
1286 int reg
, ch
, offset
= addr
- s
->base
;
1289 case 0x300 ... 0x3fe:
1290 if (s
->model
<= omap_dma_3_1
|| !s
->omap_3_1_mapping_disabled
) {
1291 if (omap_dma_3_1_lcd_write(&s
->lcd_ch
, offset
, value
))
1296 case 0x000 ... 0x2fe:
1297 reg
= offset
& 0x3f;
1298 ch
= (offset
>> 6) & 0x0f;
1299 if (omap_dma_ch_reg_write(s
, &s
->ch
[ch
], reg
, value
))
1303 case 0x404 ... 0x4fe:
1304 if (s
->model
<= omap_dma_3_1
)
1308 if (omap_dma_sys_write(s
, offset
, value
))
1312 case 0xb00 ... 0xbfe:
1313 if (s
->model
== omap_dma_3_2
&& s
->omap_3_1_mapping_disabled
) {
1314 if (omap_dma_3_2_lcd_write(&s
->lcd_ch
, offset
, value
))
1324 static CPUReadMemoryFunc
*omap_dma_readfn
[] = {
1325 omap_badwidth_read16
,
1327 omap_badwidth_read16
,
1330 static CPUWriteMemoryFunc
*omap_dma_writefn
[] = {
1331 omap_badwidth_write16
,
1333 omap_badwidth_write16
,
1336 static void omap_dma_request(void *opaque
, int drq
, int req
)
1338 struct omap_dma_s
*s
= (struct omap_dma_s
*) opaque
;
1339 /* The request pins are level triggered in QEMU. */
1341 if (~s
->drq
& (1 << drq
)) {
1343 omap_dma_process_request(s
, drq
);
1346 s
->drq
&= ~(1 << drq
);
1349 static void omap_dma_clk_update(void *opaque
, int line
, int on
)
1351 struct omap_dma_s
*s
= (struct omap_dma_s
*) opaque
;
1354 /* TODO: make a clever calculation */
1355 s
->delay
= ticks_per_sec
>> 8;
1357 qemu_mod_timer(s
->tm
, qemu_get_clock(vm_clock
) + s
->delay
);
1360 qemu_del_timer(s
->tm
);
1364 static void omap_dma_setcaps(struct omap_dma_s
*s
)
1372 /* XXX Only available for sDMA */
1374 (1 << 19) | /* Constant Fill Capability */
1375 (1 << 18); /* Transparent BLT Capability */
1377 (1 << 1); /* 1-bit palettized capability (DMA 3.2 only) */
1379 (1 << 8) | /* SEPARATE_SRC_AND_DST_INDEX_CPBLTY */
1380 (1 << 7) | /* DST_DOUBLE_INDEX_ADRS_CPBLTY */
1381 (1 << 6) | /* DST_SINGLE_INDEX_ADRS_CPBLTY */
1382 (1 << 5) | /* DST_POST_INCRMNT_ADRS_CPBLTY */
1383 (1 << 4) | /* DST_CONST_ADRS_CPBLTY */
1384 (1 << 3) | /* SRC_DOUBLE_INDEX_ADRS_CPBLTY */
1385 (1 << 2) | /* SRC_SINGLE_INDEX_ADRS_CPBLTY */
1386 (1 << 1) | /* SRC_POST_INCRMNT_ADRS_CPBLTY */
1387 (1 << 0); /* SRC_CONST_ADRS_CPBLTY */
1389 (1 << 6) | /* BLOCK_SYNCHR_CPBLTY (DMA 4 only) */
1390 (1 << 7) | /* PKT_SYNCHR_CPBLTY (DMA 4 only) */
1391 (1 << 5) | /* CHANNEL_CHAINING_CPBLTY */
1392 (1 << 4) | /* LCh_INTERLEAVE_CPBLTY */
1393 (1 << 3) | /* AUTOINIT_REPEAT_CPBLTY (DMA 3.2 only) */
1394 (1 << 2) | /* AUTOINIT_ENDPROG_CPBLTY (DMA 3.2 only) */
1395 (1 << 1) | /* FRAME_SYNCHR_CPBLTY */
1396 (1 << 0); /* ELMNT_SYNCHR_CPBLTY */
1398 (1 << 7) | /* PKT_INTERRUPT_CPBLTY (DMA 4 only) */
1399 (1 << 6) | /* SYNC_STATUS_CPBLTY */
1400 (1 << 5) | /* BLOCK_INTERRUPT_CPBLTY */
1401 (1 << 4) | /* LAST_FRAME_INTERRUPT_CPBLTY */
1402 (1 << 3) | /* FRAME_INTERRUPT_CPBLTY */
1403 (1 << 2) | /* HALF_FRAME_INTERRUPT_CPBLTY */
1404 (1 << 1) | /* EVENT_DROP_INTERRUPT_CPBLTY */
1405 (1 << 0); /* TIMEOUT_INTERRUPT_CPBLTY (DMA 3.2 only) */
1410 struct omap_dma_s
*omap_dma_init(target_phys_addr_t base
, qemu_irq
*irqs
,
1411 qemu_irq lcd_irq
, struct omap_mpu_state_s
*mpu
, omap_clk clk
,
1412 enum omap_dma_model model
)
1414 int iomemtype
, num_irqs
, memsize
, i
;
1415 struct omap_dma_s
*s
= (struct omap_dma_s
*)
1416 qemu_mallocz(sizeof(struct omap_dma_s
));
1418 if (model
<= omap_dma_3_1
) {
1429 s
->lcd_ch
.irq
= lcd_irq
;
1430 s
->lcd_ch
.mpu
= mpu
;
1431 omap_dma_setcaps(s
);
1433 s
->ch
[num_irqs
].irq
= irqs
[num_irqs
];
1434 for (i
= 0; i
< 3; i
++) {
1435 s
->ch
[i
].sibling
= &s
->ch
[i
+ 6];
1436 s
->ch
[i
+ 6].sibling
= &s
->ch
[i
];
1438 s
->tm
= qemu_new_timer(vm_clock
, (QEMUTimerCB
*) omap_dma_channel_run
, s
);
1439 omap_clk_adduser(s
->clk
, qemu_allocate_irqs(omap_dma_clk_update
, s
, 1)[0]);
1440 mpu
->drq
= qemu_allocate_irqs(omap_dma_request
, s
, 32);
1442 omap_dma_clk_update(s
, 0, 1);
1444 iomemtype
= cpu_register_io_memory(0, omap_dma_readfn
,
1445 omap_dma_writefn
, s
);
1446 cpu_register_physical_memory(s
->base
, memsize
, iomemtype
);
1451 static void omap_dma_interrupts_4_update(struct omap_dma_s
*s
)
1453 struct omap_dma_channel_s
*ch
= s
->ch
;
1456 for (bmp
= 0, bit
= 1; bit
; ch
++, bit
<<= 1)
1459 ch
->cstatus
|= ch
->status
;
1462 if ((s
->irqstat
[0] |= s
->irqen
[0] & bmp
))
1463 qemu_irq_raise(s
->irq
[0]);
1464 if ((s
->irqstat
[1] |= s
->irqen
[1] & bmp
))
1465 qemu_irq_raise(s
->irq
[1]);
1466 if ((s
->irqstat
[2] |= s
->irqen
[2] & bmp
))
1467 qemu_irq_raise(s
->irq
[2]);
1468 if ((s
->irqstat
[3] |= s
->irqen
[3] & bmp
))
1469 qemu_irq_raise(s
->irq
[3]);
1472 static uint32_t omap_dma4_read(void *opaque
, target_phys_addr_t addr
)
1474 struct omap_dma_s
*s
= (struct omap_dma_s
*) opaque
;
1475 int irqn
= 0, chnum
, offset
= addr
- s
->base
;
1476 struct omap_dma_channel_s
*ch
;
1479 case 0x00: /* DMA4_REVISION */
1482 case 0x14: /* DMA4_IRQSTATUS_L3 */
1484 case 0x10: /* DMA4_IRQSTATUS_L2 */
1486 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1488 case 0x08: /* DMA4_IRQSTATUS_L0 */
1489 return s
->irqstat
[irqn
];
1491 case 0x24: /* DMA4_IRQENABLE_L3 */
1493 case 0x20: /* DMA4_IRQENABLE_L2 */
1495 case 0x1c: /* DMA4_IRQENABLE_L1 */
1497 case 0x18: /* DMA4_IRQENABLE_L0 */
1498 return s
->irqen
[irqn
];
1500 case 0x28: /* DMA4_SYSSTATUS */
1501 return 1; /* RESETDONE */
1503 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1506 case 0x64: /* DMA4_CAPS_0 */
1508 case 0x6c: /* DMA4_CAPS_2 */
1510 case 0x70: /* DMA4_CAPS_3 */
1512 case 0x74: /* DMA4_CAPS_4 */
1515 case 0x78: /* DMA4_GCR */
1518 case 0x80 ... 0xfff:
1520 chnum
= offset
/ 0x60;
1522 offset
-= chnum
* 0x60;
1530 /* Per-channel registers */
1532 case 0x00: /* DMA4_CCR */
1533 return (ch
->buf_disable
<< 25) |
1534 (ch
->src_sync
<< 24) |
1535 (ch
->prefetch
<< 23) |
1536 ((ch
->sync
& 0x60) << 14) |
1538 (ch
->transparent_copy
<< 17) |
1539 (ch
->constant_fill
<< 16) |
1540 (ch
->mode
[1] << 14) |
1541 (ch
->mode
[0] << 12) |
1542 (0 << 10) | (0 << 9) |
1543 (ch
->suspend
<< 8) |
1545 (ch
->priority
<< 6) |
1546 (ch
->fs
<< 5) | (ch
->sync
& 0x1f);
1548 case 0x04: /* DMA4_CLNK_CTRL */
1549 return (ch
->link_enabled
<< 15) | ch
->link_next_ch
;
1551 case 0x08: /* DMA4_CICR */
1552 return ch
->interrupts
;
1554 case 0x0c: /* DMA4_CSR */
1557 case 0x10: /* DMA4_CSDP */
1558 return (ch
->endian
[0] << 21) |
1559 (ch
->endian_lock
[0] << 20) |
1560 (ch
->endian
[1] << 19) |
1561 (ch
->endian_lock
[1] << 18) |
1562 (ch
->write_mode
<< 16) |
1563 (ch
->burst
[1] << 14) |
1564 (ch
->pack
[1] << 13) |
1565 (ch
->translate
[1] << 9) |
1566 (ch
->burst
[0] << 7) |
1567 (ch
->pack
[0] << 6) |
1568 (ch
->translate
[0] << 2) |
1569 (ch
->data_type
>> 1);
1571 case 0x14: /* DMA4_CEN */
1572 return ch
->elements
;
1574 case 0x18: /* DMA4_CFN */
1577 case 0x1c: /* DMA4_CSSA */
1580 case 0x20: /* DMA4_CDSA */
1583 case 0x24: /* DMA4_CSEI */
1584 return ch
->element_index
[0];
1586 case 0x28: /* DMA4_CSFI */
1587 return ch
->frame_index
[0];
1589 case 0x2c: /* DMA4_CDEI */
1590 return ch
->element_index
[1];
1592 case 0x30: /* DMA4_CDFI */
1593 return ch
->frame_index
[1];
1595 case 0x34: /* DMA4_CSAC */
1596 return ch
->active_set
.src
& 0xffff;
1598 case 0x38: /* DMA4_CDAC */
1599 return ch
->active_set
.dest
& 0xffff;
1601 case 0x3c: /* DMA4_CCEN */
1602 return ch
->active_set
.element
;
1604 case 0x40: /* DMA4_CCFN */
1605 return ch
->active_set
.frame
;
1607 case 0x44: /* DMA4_COLOR */
1608 /* XXX only in sDMA */
1617 static void omap_dma4_write(void *opaque
, target_phys_addr_t addr
,
1620 struct omap_dma_s
*s
= (struct omap_dma_s
*) opaque
;
1621 int chnum
, irqn
= 0, offset
= addr
- s
->base
;
1622 struct omap_dma_channel_s
*ch
;
1625 case 0x14: /* DMA4_IRQSTATUS_L3 */
1627 case 0x10: /* DMA4_IRQSTATUS_L2 */
1629 case 0x0c: /* DMA4_IRQSTATUS_L1 */
1631 case 0x08: /* DMA4_IRQSTATUS_L0 */
1632 s
->irqstat
[irqn
] &= ~value
;
1633 if (!s
->irqstat
[irqn
])
1634 qemu_irq_lower(s
->irq
[irqn
]);
1637 case 0x24: /* DMA4_IRQENABLE_L3 */
1639 case 0x20: /* DMA4_IRQENABLE_L2 */
1641 case 0x1c: /* DMA4_IRQENABLE_L1 */
1643 case 0x18: /* DMA4_IRQENABLE_L0 */
1644 s
->irqen
[irqn
] = value
;
1647 case 0x2c: /* DMA4_OCP_SYSCONFIG */
1648 if (value
& 2) /* SOFTRESET */
1650 s
->ocp
= value
& 0x3321;
1651 if (((s
->ocp
>> 12) & 3) == 3) /* MIDLEMODE */
1652 fprintf(stderr
, "%s: invalid DMA power mode\n", __FUNCTION__
);
1655 case 0x78: /* DMA4_GCR */
1656 s
->gcr
= value
& 0x00ff00ff;
1657 if ((value
& 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */
1658 fprintf(stderr
, "%s: wrong FIFO depth in GCR\n", __FUNCTION__
);
1661 case 0x80 ... 0xfff:
1663 chnum
= offset
/ 0x60;
1665 offset
-= chnum
* 0x60;
1668 case 0x00: /* DMA4_REVISION */
1669 case 0x28: /* DMA4_SYSSTATUS */
1670 case 0x64: /* DMA4_CAPS_0 */
1671 case 0x6c: /* DMA4_CAPS_2 */
1672 case 0x70: /* DMA4_CAPS_3 */
1673 case 0x74: /* DMA4_CAPS_4 */
1682 /* Per-channel registers */
1684 case 0x00: /* DMA4_CCR */
1685 ch
->buf_disable
= (value
>> 25) & 1;
1686 ch
->src_sync
= (value
>> 24) & 1; /* XXX For CamDMA must be 1 */
1687 if (ch
->buf_disable
&& !ch
->src_sync
)
1688 fprintf(stderr
, "%s: Buffering disable is not allowed in "
1689 "destination synchronised mode\n", __FUNCTION__
);
1690 ch
->prefetch
= (value
>> 23) & 1;
1691 ch
->bs
= (value
>> 18) & 1;
1692 ch
->transparent_copy
= (value
>> 17) & 1;
1693 ch
->constant_fill
= (value
>> 16) & 1;
1694 ch
->mode
[1] = (omap_dma_addressing_t
) ((value
& 0xc000) >> 14);
1695 ch
->mode
[0] = (omap_dma_addressing_t
) ((value
& 0x3000) >> 12);
1696 ch
->suspend
= (value
& 0x0100) >> 8;
1697 ch
->priority
= (value
& 0x0040) >> 6;
1698 ch
->fs
= (value
& 0x0020) >> 5;
1699 if (ch
->fs
&& ch
->bs
&& ch
->mode
[0] && ch
->mode
[1])
1700 fprintf(stderr
, "%s: For a packet transfer at least one port "
1701 "must be constant-addressed\n", __FUNCTION__
);
1702 ch
->sync
= (value
& 0x001f) | ((value
>> 14) & 0x0060);
1703 /* XXX must be 0x01 for CamDMA */
1706 omap_dma_enable_channel(s
, ch
);
1708 omap_dma_disable_channel(s
, ch
);
1712 case 0x04: /* DMA4_CLNK_CTRL */
1713 ch
->link_enabled
= (value
>> 15) & 0x1;
1714 ch
->link_next_ch
= value
& 0x1f;
1717 case 0x08: /* DMA4_CICR */
1718 ch
->interrupts
= value
& 0x09be;
1721 case 0x0c: /* DMA4_CSR */
1722 ch
->cstatus
&= ~value
;
1725 case 0x10: /* DMA4_CSDP */
1726 ch
->endian
[0] =(value
>> 21) & 1;
1727 ch
->endian_lock
[0] =(value
>> 20) & 1;
1728 ch
->endian
[1] =(value
>> 19) & 1;
1729 ch
->endian_lock
[1] =(value
>> 18) & 1;
1730 if (ch
->endian
[0] != ch
->endian
[1])
1731 fprintf(stderr
, "%s: DMA endianned conversion enable attempt\n",
1733 ch
->write_mode
= (value
>> 16) & 3;
1734 ch
->burst
[1] = (value
& 0xc000) >> 14;
1735 ch
->pack
[1] = (value
& 0x2000) >> 13;
1736 ch
->translate
[1] = (value
& 0x1e00) >> 9;
1737 ch
->burst
[0] = (value
& 0x0180) >> 7;
1738 ch
->pack
[0] = (value
& 0x0040) >> 6;
1739 ch
->translate
[0] = (value
& 0x003c) >> 2;
1740 if (ch
->translate
[0] | ch
->translate
[1])
1741 fprintf(stderr
, "%s: bad MReqAddressTranslate sideband signal\n",
1743 ch
->data_type
= 1 << (value
& 3);
1744 if ((value
& 3) == 3)
1745 printf("%s: bad data_type for DMA channel\n", __FUNCTION__
);
1748 case 0x14: /* DMA4_CEN */
1749 ch
->elements
= value
& 0xffffff;
1752 case 0x18: /* DMA4_CFN */
1753 ch
->frames
= value
& 0xffff;
1756 case 0x1c: /* DMA4_CSSA */
1757 ch
->addr
[0] = (target_phys_addr_t
) (uint32_t) value
;
1760 case 0x20: /* DMA4_CDSA */
1761 ch
->addr
[1] = (target_phys_addr_t
) (uint32_t) value
;
1764 case 0x24: /* DMA4_CSEI */
1765 ch
->element_index
[0] = (int16_t) value
;
1768 case 0x28: /* DMA4_CSFI */
1769 ch
->frame_index
[0] = (int32_t) value
;
1772 case 0x2c: /* DMA4_CDEI */
1773 ch
->element_index
[1] = (int16_t) value
;
1776 case 0x30: /* DMA4_CDFI */
1777 ch
->frame_index
[1] = (int32_t) value
;
1780 case 0x44: /* DMA4_COLOR */
1781 /* XXX only in sDMA */
1785 case 0x34: /* DMA4_CSAC */
1786 case 0x38: /* DMA4_CDAC */
1787 case 0x3c: /* DMA4_CCEN */
1788 case 0x40: /* DMA4_CCFN */
1797 static CPUReadMemoryFunc
*omap_dma4_readfn
[] = {
1798 omap_badwidth_read16
,
1803 static CPUWriteMemoryFunc
*omap_dma4_writefn
[] = {
1804 omap_badwidth_write16
,
1809 struct omap_dma_s
*omap_dma4_init(target_phys_addr_t base
, qemu_irq
*irqs
,
1810 struct omap_mpu_state_s
*mpu
, int fifo
,
1811 int chans
, omap_clk iclk
, omap_clk fclk
)
1814 struct omap_dma_s
*s
= (struct omap_dma_s
*)
1815 qemu_mallocz(sizeof(struct omap_dma_s
));
1818 s
->model
= omap_dma_4
;
1822 memcpy(&s
->irq
, irqs
, sizeof(s
->irq
));
1823 s
->intr_update
= omap_dma_interrupts_4_update
;
1824 omap_dma_setcaps(s
);
1825 s
->tm
= qemu_new_timer(vm_clock
, (QEMUTimerCB
*) omap_dma_channel_run
, s
);
1826 omap_clk_adduser(s
->clk
, qemu_allocate_irqs(omap_dma_clk_update
, s
, 1)[0]);
1827 mpu
->drq
= qemu_allocate_irqs(omap_dma_request
, s
, 64);
1829 omap_dma_clk_update(s
, 0, 1);
1831 iomemtype
= cpu_register_io_memory(0, omap_dma4_readfn
,
1832 omap_dma4_writefn
, s
);
1833 cpu_register_physical_memory(s
->base
, 0x1000, iomemtype
);
1838 struct omap_dma_lcd_channel_s
*omap_dma_get_lcdch(struct omap_dma_s
*s
)