hw/parallel.c

   1 /*
   2  * QEMU Parallel PORT emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2007 Marko Kohtala
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "qemu-char.h"
  27 #include "isa.h"
  28 #include "pc.h"
  29
  30 //#define DEBUG_PARALLEL
  31
  32 #ifdef DEBUG_PARALLEL
  33 #define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
  34 #else
  35 #define pdebug(fmt, arg...) ((void)0)
  36 #endif
  37
  38 #define PARA_REG_DATA 0
  39 #define PARA_REG_STS 1
  40 #define PARA_REG_CTR 2
  41 #define PARA_REG_EPP_ADDR 3
  42 #define PARA_REG_EPP_DATA 4
  43
  44 /*
  45  * These are the definitions for the Printer Status Register
  46  */
  47 #define PARA_STS_BUSY   0x80    /* Busy complement */
  48 #define PARA_STS_ACK    0x40    /* Acknowledge */
  49 #define PARA_STS_PAPER  0x20    /* Out of paper */
  50 #define PARA_STS_ONLINE 0x10    /* Online */
  51 #define PARA_STS_ERROR  0x08    /* Error complement */
  52 #define PARA_STS_TMOUT  0x01    /* EPP timeout */
  53
  54 /*
  55  * These are the definitions for the Printer Control Register
  56  */
  57 #define PARA_CTR_DIR    0x20    /* Direction (1=read, 0=write) */
  58 #define PARA_CTR_INTEN  0x10    /* IRQ Enable */
  59 #define PARA_CTR_SELECT 0x08    /* Select In complement */
  60 #define PARA_CTR_INIT   0x04    /* Initialize Printer complement */
  61 #define PARA_CTR_AUTOLF 0x02    /* Auto linefeed complement */
  62 #define PARA_CTR_STROBE 0x01    /* Strobe complement */
  63
  64 #define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
  65
  66 struct ParallelState {
  67     uint8_t dataw;
  68     uint8_t datar;
  69     uint8_t status;
  70     uint8_t control;
  71     qemu_irq irq;
  72     int irq_pending;
  73     CharDriverState *chr;
  74     int hw_driver;
  75     int epp_timeout;
  76     uint32_t last_read_offset; /* For debugging */
  77     /* Memory-mapped interface */
  78     target_phys_addr_t base;
  79     int it_shift;
  80 };
  81
  82 static void parallel_update_irq(ParallelState *s)
  83 {
  84     if (s->irq_pending)
  85         qemu_irq_raise(s->irq);
  86     else
  87         qemu_irq_lower(s->irq);
  88 }
  89
  90 static void
  91 parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
  92 {
  93     ParallelState *s = opaque;
  94
  95     pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
  96
  97     addr &= 7;
  98     switch(addr) {
  99     case PARA_REG_DATA:
 100         s->dataw = val;
 101         parallel_update_irq(s);
 102         break;
 103     case PARA_REG_CTR:
 104         val |= 0xc0;
 105         if ((val & PARA_CTR_INIT) == 0 ) {
 106             s->status = PARA_STS_BUSY;
 107             s->status |= PARA_STS_ACK;
 108             s->status |= PARA_STS_ONLINE;
 109             s->status |= PARA_STS_ERROR;
 110         }
 111         else if (val & PARA_CTR_SELECT) {
 112             if (val & PARA_CTR_STROBE) {
 113                 s->status &= ~PARA_STS_BUSY;
 114                 if ((s->control & PARA_CTR_STROBE) == 0)
 115                     qemu_chr_write(s->chr, &s->dataw, 1);
 116             } else {
 117                 if (s->control & PARA_CTR_INTEN) {
 118                     s->irq_pending = 1;
 119                 }
 120             }
 121         }
 122         parallel_update_irq(s);
 123         s->control = val;
 124         break;
 125     }
 126 }
 127
 128 static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
 129 {
 130     ParallelState *s = opaque;
 131     uint8_t parm = val;
 132     int dir;
 133
 134     /* Sometimes programs do several writes for timing purposes on old
 135        HW. Take care not to waste time on writes that do nothing. */
 136
 137     s->last_read_offset = ~0U;
 138
 139     addr &= 7;
 140     switch(addr) {
 141     case PARA_REG_DATA:
 142         if (s->dataw == val)
 143             return;
 144         pdebug("wd%02x\n", val);
 145         qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
 146         s->dataw = val;
 147         break;
 148     case PARA_REG_STS:
 149         pdebug("ws%02x\n", val);
 150         if (val & PARA_STS_TMOUT)
 151             s->epp_timeout = 0;
 152         break;
 153     case PARA_REG_CTR:
 154         val |= 0xc0;
 155         if (s->control == val)
 156             return;
 157         pdebug("wc%02x\n", val);
 158
 159         if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
 160             if (val & PARA_CTR_DIR) {
 161                 dir = 1;
 162             } else {
 163                 dir = 0;
 164             }
 165             qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
 166             parm &= ~PARA_CTR_DIR;
 167         }
 168
 169         qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
 170         s->control = val;
 171         break;
 172     case PARA_REG_EPP_ADDR:
 173         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
 174             /* Controls not correct for EPP address cycle, so do nothing */
 175             pdebug("wa%02x s\n", val);
 176         else {
 177             struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
 178             if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
 179                 s->epp_timeout = 1;
 180                 pdebug("wa%02x t\n", val);
 181             }
 182             else
 183                 pdebug("wa%02x\n", val);
 184         }
 185         break;
 186     case PARA_REG_EPP_DATA:
 187         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
 188             /* Controls not correct for EPP data cycle, so do nothing */
 189             pdebug("we%02x s\n", val);
 190         else {
 191             struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
 192             if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
 193                 s->epp_timeout = 1;
 194                 pdebug("we%02x t\n", val);
 195             }
 196             else
 197                 pdebug("we%02x\n", val);
 198         }
 199         break;
 200     }
 201 }
 202
 203 static void
 204 parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
 205 {
 206     ParallelState *s = opaque;
 207     uint16_t eppdata = cpu_to_le16(val);
 208     int err;
 209     struct ParallelIOArg ioarg = {
 210         .buffer = &eppdata, .count = sizeof(eppdata)
 211     };
 212     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
 213         /* Controls not correct for EPP data cycle, so do nothing */
 214         pdebug("we%04x s\n", val);
 215         return;
 216     }
 217     err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
 218     if (err) {
 219         s->epp_timeout = 1;
 220         pdebug("we%04x t\n", val);
 221     }
 222     else
 223         pdebug("we%04x\n", val);
 224 }
 225
 226 static void
 227 parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
 228 {
 229     ParallelState *s = opaque;
 230     uint32_t eppdata = cpu_to_le32(val);
 231     int err;
 232     struct ParallelIOArg ioarg = {
 233         .buffer = &eppdata, .count = sizeof(eppdata)
 234     };
 235     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
 236         /* Controls not correct for EPP data cycle, so do nothing */
 237         pdebug("we%08x s\n", val);
 238         return;
 239     }
 240     err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
 241     if (err) {
 242         s->epp_timeout = 1;
 243         pdebug("we%08x t\n", val);
 244     }
 245     else
 246         pdebug("we%08x\n", val);
 247 }
 248
 249 static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
 250 {
 251     ParallelState *s = opaque;
 252     uint32_t ret = 0xff;
 253
 254     addr &= 7;
 255     switch(addr) {
 256     case PARA_REG_DATA:
 257         if (s->control & PARA_CTR_DIR)
 258             ret = s->datar;
 259         else
 260             ret = s->dataw;
 261         break;
 262     case PARA_REG_STS:
 263         ret = s->status;
 264         s->irq_pending = 0;
 265         if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
 266             /* XXX Fixme: wait 5 microseconds */
 267             if (s->status & PARA_STS_ACK)
 268                 s->status &= ~PARA_STS_ACK;
 269             else {
 270                 /* XXX Fixme: wait 5 microseconds */
 271                 s->status |= PARA_STS_ACK;
 272                 s->status |= PARA_STS_BUSY;
 273             }
 274         }
 275         parallel_update_irq(s);
 276         break;
 277     case PARA_REG_CTR:
 278         ret = s->control;
 279         break;
 280     }
 281     pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
 282     return ret;
 283 }
 284
 285 static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
 286 {
 287     ParallelState *s = opaque;
 288     uint8_t ret = 0xff;
 289     addr &= 7;
 290     switch(addr) {
 291     case PARA_REG_DATA:
 292         qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
 293         if (s->last_read_offset != addr || s->datar != ret)
 294             pdebug("rd%02x\n", ret);
 295         s->datar = ret;
 296         break;
 297     case PARA_REG_STS:
 298         qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
 299         ret &= ~PARA_STS_TMOUT;
 300         if (s->epp_timeout)
 301             ret |= PARA_STS_TMOUT;
 302         if (s->last_read_offset != addr || s->status != ret)
 303             pdebug("rs%02x\n", ret);
 304         s->status = ret;
 305         break;
 306     case PARA_REG_CTR:
 307         /* s->control has some bits fixed to 1. It is zero only when
 308            it has not been yet written to.  */
 309         if (s->control == 0) {
 310             qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
 311             if (s->last_read_offset != addr)
 312                 pdebug("rc%02x\n", ret);
 313             s->control = ret;
 314         }
 315         else {
 316             ret = s->control;
 317             if (s->last_read_offset != addr)
 318                 pdebug("rc%02x\n", ret);
 319         }
 320         break;
 321     case PARA_REG_EPP_ADDR:
 322         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
 323             /* Controls not correct for EPP addr cycle, so do nothing */
 324             pdebug("ra%02x s\n", ret);
 325         else {
 326             struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
 327             if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
 328                 s->epp_timeout = 1;
 329                 pdebug("ra%02x t\n", ret);
 330             }
 331             else
 332                 pdebug("ra%02x\n", ret);
 333         }
 334         break;
 335     case PARA_REG_EPP_DATA:
 336         if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
 337             /* Controls not correct for EPP data cycle, so do nothing */
 338             pdebug("re%02x s\n", ret);
 339         else {
 340             struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
 341             if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
 342                 s->epp_timeout = 1;
 343                 pdebug("re%02x t\n", ret);
 344             }
 345             else
 346                 pdebug("re%02x\n", ret);
 347         }
 348         break;
 349     }
 350     s->last_read_offset = addr;
 351     return ret;
 352 }
 353
 354 static uint32_t
 355 parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
 356 {
 357     ParallelState *s = opaque;
 358     uint32_t ret;
 359     uint16_t eppdata = ~0;
 360     int err;
 361     struct ParallelIOArg ioarg = {
 362         .buffer = &eppdata, .count = sizeof(eppdata)
 363     };
 364     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
 365         /* Controls not correct for EPP data cycle, so do nothing */
 366         pdebug("re%04x s\n", eppdata);
 367         return eppdata;
 368     }
 369     err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
 370     ret = le16_to_cpu(eppdata);
 371
 372     if (err) {
 373         s->epp_timeout = 1;
 374         pdebug("re%04x t\n", ret);
 375     }
 376     else
 377         pdebug("re%04x\n", ret);
 378     return ret;
 379 }
 380
 381 static uint32_t
 382 parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
 383 {
 384     ParallelState *s = opaque;
 385     uint32_t ret;
 386     uint32_t eppdata = ~0U;
 387     int err;
 388     struct ParallelIOArg ioarg = {
 389         .buffer = &eppdata, .count = sizeof(eppdata)
 390     };
 391     if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
 392         /* Controls not correct for EPP data cycle, so do nothing */
 393         pdebug("re%08x s\n", eppdata);
 394         return eppdata;
 395     }
 396     err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
 397     ret = le32_to_cpu(eppdata);
 398
 399     if (err) {
 400         s->epp_timeout = 1;
 401         pdebug("re%08x t\n", ret);
 402     }
 403     else
 404         pdebug("re%08x\n", ret);
 405     return ret;
 406 }
 407
 408 static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
 409 {
 410     addr &= 7;
 411     pdebug("wecp%d=%02x\n", addr, val);
 412 }
 413
 414 static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
 415 {
 416     uint8_t ret = 0xff;
 417     addr &= 7;
 418     pdebug("recp%d:%02x\n", addr, ret);
 419     return ret;
 420 }
 421
 422 static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
 423 {
 424     s->datar = ~0;
 425     s->dataw = ~0;
 426     s->status = PARA_STS_BUSY;
 427     s->status |= PARA_STS_ACK;
 428     s->status |= PARA_STS_ONLINE;
 429     s->status |= PARA_STS_ERROR;
 430     s->status |= PARA_STS_TMOUT;
 431     s->control = PARA_CTR_SELECT;
 432     s->control |= PARA_CTR_INIT;
 433     s->control |= 0xc0;
 434     s->irq = irq;
 435     s->irq_pending = 0;
 436     s->chr = chr;
 437     s->hw_driver = 0;
 438     s->epp_timeout = 0;
 439     s->last_read_offset = ~0U;
 440 }
 441
 442 /* If fd is zero, it means that the parallel device uses the console */
 443 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
 444 {
 445     ParallelState *s;
 446     uint8_t dummy;
 447
 448     s = qemu_mallocz(sizeof(ParallelState));
 449     if (!s)
 450         return NULL;
 451     parallel_reset(s, irq, chr);
 452
 453     if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
 454         s->hw_driver = 1;
 455         s->status = dummy;
 456     }
 457
 458     if (s->hw_driver) {
 459         register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
 460         register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
 461         register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
 462         register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
 463         register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
 464         register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
 465         register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
 466         register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
 467     }
 468     else {
 469         register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
 470         register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
 471     }
 472     return s;
 473 }
 474
 475 /* Memory mapped interface */
 476 static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
 477 {
 478     ParallelState *s = opaque;
 479
 480     return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
 481 }
 482
 483 static void parallel_mm_writeb (void *opaque,
 484                                 target_phys_addr_t addr, uint32_t value)
 485 {
 486     ParallelState *s = opaque;
 487
 488     parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
 489 }
 490
 491 static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
 492 {
 493     ParallelState *s = opaque;
 494
 495     return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
 496 }
 497
 498 static void parallel_mm_writew (void *opaque,
 499                                 target_phys_addr_t addr, uint32_t value)
 500 {
 501     ParallelState *s = opaque;
 502
 503     parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
 504 }
 505
 506 static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
 507 {
 508     ParallelState *s = opaque;
 509
 510     return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
 511 }
 512
 513 static void parallel_mm_writel (void *opaque,
 514                                 target_phys_addr_t addr, uint32_t value)
 515 {
 516     ParallelState *s = opaque;
 517
 518     parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
 519 }
 520
 521 static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
 522     &parallel_mm_readb,
 523     &parallel_mm_readw,
 524     &parallel_mm_readl,
 525 };
 526
 527 static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
 528     &parallel_mm_writeb,
 529     &parallel_mm_writew,
 530     &parallel_mm_writel,
 531 };
 532
 533 /* If fd is zero, it means that the parallel device uses the console */
 534 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
 535 {
 536     ParallelState *s;
 537     int io_sw;
 538
 539     s = qemu_mallocz(sizeof(ParallelState));
 540     if (!s)
 541         return NULL;
 542     parallel_reset(s, irq, chr);
 543     s->base = base;
 544     s->it_shift = it_shift;
 545
 546     io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
 547     cpu_register_physical_memory(base, 8 << it_shift, io_sw);
 548     return s;
 549 }