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Fix typo in softfloat code.
[qemu/mini2440.git] / target-ppc / translate_init.c
blob40b59105bd398018647c545b4bd8131227414475
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* A lot of PowerPC definition have been included here.
22 * Most of them are not usable for now but have been kept
23 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24 */
25
26 #include "dis-asm.h"
27 #include "host-utils.h"
28
29 //#define PPC_DUMP_CPU
30 //#define PPC_DEBUG_SPR
31 //#define PPC_DUMP_SPR_ACCESSES
32 #if defined(CONFIG_USER_ONLY)
33 #define TODO_USER_ONLY 1
34 #endif
35
36 struct ppc_def_t {
37 const unsigned char *name;
38 uint32_t pvr;
39 uint32_t svr;
40 uint64_t insns_flags;
41 uint64_t msr_mask;
42 powerpc_mmu_t mmu_model;
43 powerpc_excp_t excp_model;
44 powerpc_input_t bus_model;
45 uint32_t flags;
46 int bfd_mach;
47 void (*init_proc)(CPUPPCState *env);
48 int (*check_pow)(CPUPPCState *env);
49 };
50
51 /* For user-mode emulation, we don't emulate any IRQ controller */
52 #if defined(CONFIG_USER_ONLY)
53 #define PPC_IRQ_INIT_FN(name) \
54 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
55 { \
56 }
57 #else
58 #define PPC_IRQ_INIT_FN(name) \
59 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
60 #endif
61
62 PPC_IRQ_INIT_FN(40x);
63 PPC_IRQ_INIT_FN(6xx);
64 PPC_IRQ_INIT_FN(970);
65
66 /* Generic callbacks:
67 * do nothing but store/retrieve spr value
68 */
69 #ifdef PPC_DUMP_SPR_ACCESSES
70 static void spr_read_generic (void *opaque, int sprn)
71 {
72 gen_op_load_dump_spr(sprn);
73 }
74
75 static void spr_write_generic (void *opaque, int sprn)
76 {
77 gen_op_store_dump_spr(sprn);
78 }
79 #else
80 static void spr_read_generic (void *opaque, int sprn)
81 {
82 gen_op_load_spr(sprn);
83 }
84
85 static void spr_write_generic (void *opaque, int sprn)
86 {
87 gen_op_store_spr(sprn);
88 }
89 #endif
90
91 #if !defined(CONFIG_USER_ONLY)
92 static void spr_write_clear (void *opaque, int sprn)
93 {
94 gen_op_mask_spr(sprn);
95 }
96 #endif
97
98 /* SPR common to all PowerPC */
99 /* XER */
100 static void spr_read_xer (void *opaque, int sprn)
101 {
102 gen_op_load_xer();
103 }
104
105 static void spr_write_xer (void *opaque, int sprn)
106 {
107 gen_op_store_xer();
108 }
109
110 /* LR */
111 static void spr_read_lr (void *opaque, int sprn)
112 {
113 gen_op_load_lr();
114 }
115
116 static void spr_write_lr (void *opaque, int sprn)
117 {
118 gen_op_store_lr();
119 }
120
121 /* CTR */
122 static void spr_read_ctr (void *opaque, int sprn)
123 {
124 gen_op_load_ctr();
125 }
126
127 static void spr_write_ctr (void *opaque, int sprn)
128 {
129 gen_op_store_ctr();
130 }
131
132 /* User read access to SPR */
133 /* USPRx */
134 /* UMMCRx */
135 /* UPMCx */
136 /* USIA */
137 /* UDECR */
138 static void spr_read_ureg (void *opaque, int sprn)
139 {
140 gen_op_load_spr(sprn + 0x10);
141 }
142
143 /* SPR common to all non-embedded PowerPC */
144 /* DECR */
145 #if !defined(CONFIG_USER_ONLY)
146 static void spr_read_decr (void *opaque, int sprn)
147 {
148 gen_op_load_decr();
149 }
150
151 static void spr_write_decr (void *opaque, int sprn)
152 {
153 gen_op_store_decr();
154 }
155 #endif
156
157 /* SPR common to all non-embedded PowerPC, except 601 */
158 /* Time base */
159 static void spr_read_tbl (void *opaque, int sprn)
160 {
161 gen_op_load_tbl();
162 }
163
164 static void spr_read_tbu (void *opaque, int sprn)
165 {
166 gen_op_load_tbu();
167 }
168
169 __attribute__ (( unused ))
170 static void spr_read_atbl (void *opaque, int sprn)
171 {
172 gen_op_load_atbl();
173 }
174
175 __attribute__ (( unused ))
176 static void spr_read_atbu (void *opaque, int sprn)
177 {
178 gen_op_load_atbu();
179 }
180
181 #if !defined(CONFIG_USER_ONLY)
182 static void spr_write_tbl (void *opaque, int sprn)
183 {
184 gen_op_store_tbl();
185 }
186
187 static void spr_write_tbu (void *opaque, int sprn)
188 {
189 gen_op_store_tbu();
190 }
191
192 __attribute__ (( unused ))
193 static void spr_write_atbl (void *opaque, int sprn)
194 {
195 gen_op_store_atbl();
196 }
197
198 __attribute__ (( unused ))
199 static void spr_write_atbu (void *opaque, int sprn)
200 {
201 gen_op_store_atbu();
202 }
203 #endif
204
205 #if !defined(CONFIG_USER_ONLY)
206 /* IBAT0U...IBAT0U */
207 /* IBAT0L...IBAT7L */
208 static void spr_read_ibat (void *opaque, int sprn)
209 {
210 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
211 }
212
213 static void spr_read_ibat_h (void *opaque, int sprn)
214 {
215 gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
216 }
217
218 static void spr_write_ibatu (void *opaque, int sprn)
219 {
220 gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
221 }
222
223 static void spr_write_ibatu_h (void *opaque, int sprn)
224 {
225 gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
226 }
227
228 static void spr_write_ibatl (void *opaque, int sprn)
229 {
230 gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
231 }
232
233 static void spr_write_ibatl_h (void *opaque, int sprn)
234 {
235 gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
236 }
237
238 /* DBAT0U...DBAT7U */
239 /* DBAT0L...DBAT7L */
240 static void spr_read_dbat (void *opaque, int sprn)
241 {
242 gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
243 }
244
245 static void spr_read_dbat_h (void *opaque, int sprn)
246 {
247 gen_op_load_dbat(sprn & 1, ((sprn - SPR_DBAT4U) / 2) + 4);
248 }
249
250 static void spr_write_dbatu (void *opaque, int sprn)
251 {
252 gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
253 }
254
255 static void spr_write_dbatu_h (void *opaque, int sprn)
256 {
257 gen_op_store_dbatu(((sprn - SPR_DBAT4U) / 2) + 4);
258 }
259
260 static void spr_write_dbatl (void *opaque, int sprn)
261 {
262 gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
263 }
264
265 static void spr_write_dbatl_h (void *opaque, int sprn)
266 {
267 gen_op_store_dbatl(((sprn - SPR_DBAT4L) / 2) + 4);
268 }
269
270 /* SDR1 */
271 static void spr_read_sdr1 (void *opaque, int sprn)
272 {
273 gen_op_load_sdr1();
274 }
275
276 static void spr_write_sdr1 (void *opaque, int sprn)
277 {
278 gen_op_store_sdr1();
279 }
280
281 /* 64 bits PowerPC specific SPRs */
282 /* ASR */
283 #if defined(TARGET_PPC64)
284 static void spr_read_asr (void *opaque, int sprn)
285 {
286 gen_op_load_asr();
287 }
288
289 static void spr_write_asr (void *opaque, int sprn)
290 {
291 gen_op_store_asr();
292 }
293 #endif
294 #endif
295
296 /* PowerPC 601 specific registers */
297 /* RTC */
298 static void spr_read_601_rtcl (void *opaque, int sprn)
299 {
300 gen_op_load_601_rtcl();
301 }
302
303 static void spr_read_601_rtcu (void *opaque, int sprn)
304 {
305 gen_op_load_601_rtcu();
306 }
307
308 #if !defined(CONFIG_USER_ONLY)
309 static void spr_write_601_rtcu (void *opaque, int sprn)
310 {
311 gen_op_store_601_rtcu();
312 }
313
314 static void spr_write_601_rtcl (void *opaque, int sprn)
315 {
316 gen_op_store_601_rtcl();
317 }
318
319 static void spr_write_hid0_601 (void *opaque, int sprn)
320 {
321 DisasContext *ctx = opaque;
322
323 gen_op_store_hid0_601();
324 /* Must stop the translation as endianness may have changed */
325 GEN_STOP(ctx);
326 }
327 #endif
328
329 /* Unified bats */
330 #if !defined(CONFIG_USER_ONLY)
331 static void spr_read_601_ubat (void *opaque, int sprn)
332 {
333 gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
334 }
335
336 static void spr_write_601_ubatu (void *opaque, int sprn)
337 {
338 gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
339 }
340
341 static void spr_write_601_ubatl (void *opaque, int sprn)
342 {
343 gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
344 }
345 #endif
346
347 /* PowerPC 40x specific registers */
348 #if !defined(CONFIG_USER_ONLY)
349 static void spr_read_40x_pit (void *opaque, int sprn)
350 {
351 gen_op_load_40x_pit();
352 }
353
354 static void spr_write_40x_pit (void *opaque, int sprn)
355 {
356 gen_op_store_40x_pit();
357 }
358
359 static void spr_write_40x_dbcr0 (void *opaque, int sprn)
360 {
361 DisasContext *ctx = opaque;
362
363 gen_op_store_40x_dbcr0();
364 /* We must stop translation as we may have rebooted */
365 GEN_STOP(ctx);
366 }
367
368 static void spr_write_40x_sler (void *opaque, int sprn)
369 {
370 gen_op_store_40x_sler();
371 }
372
373 static void spr_write_booke_tcr (void *opaque, int sprn)
374 {
375 gen_op_store_booke_tcr();
376 }
377
378 static void spr_write_booke_tsr (void *opaque, int sprn)
379 {
380 gen_op_store_booke_tsr();
381 }
382 #endif
383
384 /* PowerPC 403 specific registers */
385 /* PBL1 / PBU1 / PBL2 / PBU2 */
386 #if !defined(CONFIG_USER_ONLY)
387 static void spr_read_403_pbr (void *opaque, int sprn)
388 {
389 gen_op_load_403_pb(sprn - SPR_403_PBL1);
390 }
391
392 static void spr_write_403_pbr (void *opaque, int sprn)
393 {
394 gen_op_store_403_pb(sprn - SPR_403_PBL1);
395 }
396
397 static void spr_write_pir (void *opaque, int sprn)
398 {
399 gen_op_store_pir();
400 }
401 #endif
402
403 #if !defined(CONFIG_USER_ONLY)
404 /* Callback used to write the exception vector base */
405 static void spr_write_excp_prefix (void *opaque, int sprn)
406 {
407 gen_op_store_excp_prefix();
408 gen_op_store_spr(sprn);
409 }
410
411 static void spr_write_excp_vector (void *opaque, int sprn)
412 {
413 DisasContext *ctx = opaque;
414
415 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
416 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR0);
417 gen_op_store_spr(sprn);
418 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
419 gen_op_store_excp_vector(sprn - SPR_BOOKE_IVOR32 + 32);
420 gen_op_store_spr(sprn);
421 } else {
422 printf("Trying to write an unknown exception vector %d %03x\n",
423 sprn, sprn);
424 GEN_EXCP_PRIVREG(ctx);
425 }
426 }
427 #endif
428
429 #if defined(CONFIG_USER_ONLY)
430 #define spr_register(env, num, name, uea_read, uea_write, \
431 oea_read, oea_write, initial_value) \
432 do { \
433 _spr_register(env, num, name, uea_read, uea_write, initial_value); \
434 } while (0)
435 static inline void _spr_register (CPUPPCState *env, int num,
436 const unsigned char *name,
437 void (*uea_read)(void *opaque, int sprn),
438 void (*uea_write)(void *opaque, int sprn),
439 target_ulong initial_value)
440 #else
441 static inline void spr_register (CPUPPCState *env, int num,
442 const unsigned char *name,
443 void (*uea_read)(void *opaque, int sprn),
444 void (*uea_write)(void *opaque, int sprn),
445 void (*oea_read)(void *opaque, int sprn),
446 void (*oea_write)(void *opaque, int sprn),
447 target_ulong initial_value)
448 #endif
449 {
450 ppc_spr_t *spr;
451
452 spr = &env->spr_cb[num];
453 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
454 #if !defined(CONFIG_USER_ONLY)
455 spr->oea_read != NULL || spr->oea_write != NULL ||
456 #endif
457 spr->uea_read != NULL || spr->uea_write != NULL) {
458 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
459 exit(1);
460 }
461 #if defined(PPC_DEBUG_SPR)
462 printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
463 initial_value);
464 #endif
465 spr->name = name;
466 spr->uea_read = uea_read;
467 spr->uea_write = uea_write;
468 #if !defined(CONFIG_USER_ONLY)
469 spr->oea_read = oea_read;
470 spr->oea_write = oea_write;
471 #endif
472 env->spr[num] = initial_value;
473 }
474
475 /* Generic PowerPC SPRs */
476 static void gen_spr_generic (CPUPPCState *env)
477 {
478 /* Integer processing */
479 spr_register(env, SPR_XER, "XER",
480 &spr_read_xer, &spr_write_xer,
481 &spr_read_xer, &spr_write_xer,
482 0x00000000);
483 /* Branch contol */
484 spr_register(env, SPR_LR, "LR",
485 &spr_read_lr, &spr_write_lr,
486 &spr_read_lr, &spr_write_lr,
487 0x00000000);
488 spr_register(env, SPR_CTR, "CTR",
489 &spr_read_ctr, &spr_write_ctr,
490 &spr_read_ctr, &spr_write_ctr,
491 0x00000000);
492 /* Interrupt processing */
493 spr_register(env, SPR_SRR0, "SRR0",
494 SPR_NOACCESS, SPR_NOACCESS,
495 &spr_read_generic, &spr_write_generic,
496 0x00000000);
497 spr_register(env, SPR_SRR1, "SRR1",
498 SPR_NOACCESS, SPR_NOACCESS,
499 &spr_read_generic, &spr_write_generic,
500 0x00000000);
501 /* Processor control */
502 spr_register(env, SPR_SPRG0, "SPRG0",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_generic, &spr_write_generic,
505 0x00000000);
506 spr_register(env, SPR_SPRG1, "SPRG1",
507 SPR_NOACCESS, SPR_NOACCESS,
508 &spr_read_generic, &spr_write_generic,
509 0x00000000);
510 spr_register(env, SPR_SPRG2, "SPRG2",
511 SPR_NOACCESS, SPR_NOACCESS,
512 &spr_read_generic, &spr_write_generic,
513 0x00000000);
514 spr_register(env, SPR_SPRG3, "SPRG3",
515 SPR_NOACCESS, SPR_NOACCESS,
516 &spr_read_generic, &spr_write_generic,
517 0x00000000);
518 }
519
520 /* SPR common to all non-embedded PowerPC, including 601 */
521 static void gen_spr_ne_601 (CPUPPCState *env)
522 {
523 /* Exception processing */
524 spr_register(env, SPR_DSISR, "DSISR",
525 SPR_NOACCESS, SPR_NOACCESS,
526 &spr_read_generic, &spr_write_generic,
527 0x00000000);
528 spr_register(env, SPR_DAR, "DAR",
529 SPR_NOACCESS, SPR_NOACCESS,
530 &spr_read_generic, &spr_write_generic,
531 0x00000000);
532 /* Timer */
533 spr_register(env, SPR_DECR, "DECR",
534 SPR_NOACCESS, SPR_NOACCESS,
535 &spr_read_decr, &spr_write_decr,
536 0x00000000);
537 /* Memory management */
538 spr_register(env, SPR_SDR1, "SDR1",
539 SPR_NOACCESS, SPR_NOACCESS,
540 &spr_read_sdr1, &spr_write_sdr1,
541 0x00000000);
542 }
543
544 /* BATs 0-3 */
545 static void gen_low_BATs (CPUPPCState *env)
546 {
547 #if !defined(CONFIG_USER_ONLY)
548 spr_register(env, SPR_IBAT0U, "IBAT0U",
549 SPR_NOACCESS, SPR_NOACCESS,
550 &spr_read_ibat, &spr_write_ibatu,
551 0x00000000);
552 spr_register(env, SPR_IBAT0L, "IBAT0L",
553 SPR_NOACCESS, SPR_NOACCESS,
554 &spr_read_ibat, &spr_write_ibatl,
555 0x00000000);
556 spr_register(env, SPR_IBAT1U, "IBAT1U",
557 SPR_NOACCESS, SPR_NOACCESS,
558 &spr_read_ibat, &spr_write_ibatu,
559 0x00000000);
560 spr_register(env, SPR_IBAT1L, "IBAT1L",
561 SPR_NOACCESS, SPR_NOACCESS,
562 &spr_read_ibat, &spr_write_ibatl,
563 0x00000000);
564 spr_register(env, SPR_IBAT2U, "IBAT2U",
565 SPR_NOACCESS, SPR_NOACCESS,
566 &spr_read_ibat, &spr_write_ibatu,
567 0x00000000);
568 spr_register(env, SPR_IBAT2L, "IBAT2L",
569 SPR_NOACCESS, SPR_NOACCESS,
570 &spr_read_ibat, &spr_write_ibatl,
571 0x00000000);
572 spr_register(env, SPR_IBAT3U, "IBAT3U",
573 SPR_NOACCESS, SPR_NOACCESS,
574 &spr_read_ibat, &spr_write_ibatu,
575 0x00000000);
576 spr_register(env, SPR_IBAT3L, "IBAT3L",
577 SPR_NOACCESS, SPR_NOACCESS,
578 &spr_read_ibat, &spr_write_ibatl,
579 0x00000000);
580 spr_register(env, SPR_DBAT0U, "DBAT0U",
581 SPR_NOACCESS, SPR_NOACCESS,
582 &spr_read_dbat, &spr_write_dbatu,
583 0x00000000);
584 spr_register(env, SPR_DBAT0L, "DBAT0L",
585 SPR_NOACCESS, SPR_NOACCESS,
586 &spr_read_dbat, &spr_write_dbatl,
587 0x00000000);
588 spr_register(env, SPR_DBAT1U, "DBAT1U",
589 SPR_NOACCESS, SPR_NOACCESS,
590 &spr_read_dbat, &spr_write_dbatu,
591 0x00000000);
592 spr_register(env, SPR_DBAT1L, "DBAT1L",
593 SPR_NOACCESS, SPR_NOACCESS,
594 &spr_read_dbat, &spr_write_dbatl,
595 0x00000000);
596 spr_register(env, SPR_DBAT2U, "DBAT2U",
597 SPR_NOACCESS, SPR_NOACCESS,
598 &spr_read_dbat, &spr_write_dbatu,
599 0x00000000);
600 spr_register(env, SPR_DBAT2L, "DBAT2L",
601 SPR_NOACCESS, SPR_NOACCESS,
602 &spr_read_dbat, &spr_write_dbatl,
603 0x00000000);
604 spr_register(env, SPR_DBAT3U, "DBAT3U",
605 SPR_NOACCESS, SPR_NOACCESS,
606 &spr_read_dbat, &spr_write_dbatu,
607 0x00000000);
608 spr_register(env, SPR_DBAT3L, "DBAT3L",
609 SPR_NOACCESS, SPR_NOACCESS,
610 &spr_read_dbat, &spr_write_dbatl,
611 0x00000000);
612 env->nb_BATs += 4;
613 #endif
614 }
615
616 /* BATs 4-7 */
617 static void gen_high_BATs (CPUPPCState *env)
618 {
619 #if !defined(CONFIG_USER_ONLY)
620 spr_register(env, SPR_IBAT4U, "IBAT4U",
621 SPR_NOACCESS, SPR_NOACCESS,
622 &spr_read_ibat_h, &spr_write_ibatu_h,
623 0x00000000);
624 spr_register(env, SPR_IBAT4L, "IBAT4L",
625 SPR_NOACCESS, SPR_NOACCESS,
626 &spr_read_ibat_h, &spr_write_ibatl_h,
627 0x00000000);
628 spr_register(env, SPR_IBAT5U, "IBAT5U",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_ibat_h, &spr_write_ibatu_h,
631 0x00000000);
632 spr_register(env, SPR_IBAT5L, "IBAT5L",
633 SPR_NOACCESS, SPR_NOACCESS,
634 &spr_read_ibat_h, &spr_write_ibatl_h,
635 0x00000000);
636 spr_register(env, SPR_IBAT6U, "IBAT6U",
637 SPR_NOACCESS, SPR_NOACCESS,
638 &spr_read_ibat_h, &spr_write_ibatu_h,
639 0x00000000);
640 spr_register(env, SPR_IBAT6L, "IBAT6L",
641 SPR_NOACCESS, SPR_NOACCESS,
642 &spr_read_ibat_h, &spr_write_ibatl_h,
643 0x00000000);
644 spr_register(env, SPR_IBAT7U, "IBAT7U",
645 SPR_NOACCESS, SPR_NOACCESS,
646 &spr_read_ibat_h, &spr_write_ibatu_h,
647 0x00000000);
648 spr_register(env, SPR_IBAT7L, "IBAT7L",
649 SPR_NOACCESS, SPR_NOACCESS,
650 &spr_read_ibat_h, &spr_write_ibatl_h,
651 0x00000000);
652 spr_register(env, SPR_DBAT4U, "DBAT4U",
653 SPR_NOACCESS, SPR_NOACCESS,
654 &spr_read_dbat_h, &spr_write_dbatu_h,
655 0x00000000);
656 spr_register(env, SPR_DBAT4L, "DBAT4L",
657 SPR_NOACCESS, SPR_NOACCESS,
658 &spr_read_dbat_h, &spr_write_dbatl_h,
659 0x00000000);
660 spr_register(env, SPR_DBAT5U, "DBAT5U",
661 SPR_NOACCESS, SPR_NOACCESS,
662 &spr_read_dbat_h, &spr_write_dbatu_h,
663 0x00000000);
664 spr_register(env, SPR_DBAT5L, "DBAT5L",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_dbat_h, &spr_write_dbatl_h,
667 0x00000000);
668 spr_register(env, SPR_DBAT6U, "DBAT6U",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_dbat_h, &spr_write_dbatu_h,
671 0x00000000);
672 spr_register(env, SPR_DBAT6L, "DBAT6L",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_dbat_h, &spr_write_dbatl_h,
675 0x00000000);
676 spr_register(env, SPR_DBAT7U, "DBAT7U",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_dbat_h, &spr_write_dbatu_h,
679 0x00000000);
680 spr_register(env, SPR_DBAT7L, "DBAT7L",
681 SPR_NOACCESS, SPR_NOACCESS,
682 &spr_read_dbat_h, &spr_write_dbatl_h,
683 0x00000000);
684 env->nb_BATs += 4;
685 #endif
686 }
687
688 /* Generic PowerPC time base */
689 static void gen_tbl (CPUPPCState *env)
690 {
691 spr_register(env, SPR_VTBL, "TBL",
692 &spr_read_tbl, SPR_NOACCESS,
693 &spr_read_tbl, SPR_NOACCESS,
694 0x00000000);
695 spr_register(env, SPR_TBL, "TBL",
696 SPR_NOACCESS, SPR_NOACCESS,
697 SPR_NOACCESS, &spr_write_tbl,
698 0x00000000);
699 spr_register(env, SPR_VTBU, "TBU",
700 &spr_read_tbu, SPR_NOACCESS,
701 &spr_read_tbu, SPR_NOACCESS,
702 0x00000000);
703 spr_register(env, SPR_TBU, "TBU",
704 SPR_NOACCESS, SPR_NOACCESS,
705 SPR_NOACCESS, &spr_write_tbu,
706 0x00000000);
707 }
708
709 /* Softare table search registers */
710 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
711 {
712 #if !defined(CONFIG_USER_ONLY)
713 env->nb_tlb = nb_tlbs;
714 env->nb_ways = nb_ways;
715 env->id_tlbs = 1;
716 spr_register(env, SPR_DMISS, "DMISS",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_generic, SPR_NOACCESS,
719 0x00000000);
720 spr_register(env, SPR_DCMP, "DCMP",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, SPR_NOACCESS,
723 0x00000000);
724 spr_register(env, SPR_HASH1, "HASH1",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_generic, SPR_NOACCESS,
727 0x00000000);
728 spr_register(env, SPR_HASH2, "HASH2",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_generic, SPR_NOACCESS,
731 0x00000000);
732 spr_register(env, SPR_IMISS, "IMISS",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_generic, SPR_NOACCESS,
735 0x00000000);
736 spr_register(env, SPR_ICMP, "ICMP",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, SPR_NOACCESS,
739 0x00000000);
740 spr_register(env, SPR_RPA, "RPA",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 #endif
745 }
746
747 /* SPR common to MPC755 and G2 */
748 static void gen_spr_G2_755 (CPUPPCState *env)
749 {
750 /* SGPRs */
751 spr_register(env, SPR_SPRG4, "SPRG4",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_generic, &spr_write_generic,
754 0x00000000);
755 spr_register(env, SPR_SPRG5, "SPRG5",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_generic, &spr_write_generic,
758 0x00000000);
759 spr_register(env, SPR_SPRG6, "SPRG6",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_generic,
762 0x00000000);
763 spr_register(env, SPR_SPRG7, "SPRG7",
764 SPR_NOACCESS, SPR_NOACCESS,
765 &spr_read_generic, &spr_write_generic,
766 0x00000000);
767 }
768
769 /* SPR common to all 7xx PowerPC implementations */
770 static void gen_spr_7xx (CPUPPCState *env)
771 {
772 /* Breakpoints */
773 /* XXX : not implemented */
774 spr_register(env, SPR_DABR, "DABR",
775 SPR_NOACCESS, SPR_NOACCESS,
776 &spr_read_generic, &spr_write_generic,
777 0x00000000);
778 /* XXX : not implemented */
779 spr_register(env, SPR_IABR, "IABR",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_generic, &spr_write_generic,
782 0x00000000);
783 /* Cache management */
784 /* XXX : not implemented */
785 spr_register(env, SPR_ICTC, "ICTC",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_generic,
788 0x00000000);
789 /* Performance monitors */
790 /* XXX : not implemented */
791 spr_register(env, SPR_MMCR0, "MMCR0",
792 SPR_NOACCESS, SPR_NOACCESS,
793 &spr_read_generic, &spr_write_generic,
794 0x00000000);
795 /* XXX : not implemented */
796 spr_register(env, SPR_MMCR1, "MMCR1",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_generic, &spr_write_generic,
799 0x00000000);
800 /* XXX : not implemented */
801 spr_register(env, SPR_PMC1, "PMC1",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_generic, &spr_write_generic,
804 0x00000000);
805 /* XXX : not implemented */
806 spr_register(env, SPR_PMC2, "PMC2",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 0x00000000);
810 /* XXX : not implemented */
811 spr_register(env, SPR_PMC3, "PMC3",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_generic, &spr_write_generic,
814 0x00000000);
815 /* XXX : not implemented */
816 spr_register(env, SPR_PMC4, "PMC4",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_generic, &spr_write_generic,
819 0x00000000);
820 /* XXX : not implemented */
821 spr_register(env, SPR_SIAR, "SIAR",
822 SPR_NOACCESS, SPR_NOACCESS,
823 &spr_read_generic, SPR_NOACCESS,
824 0x00000000);
825 /* XXX : not implemented */
826 spr_register(env, SPR_UMMCR0, "UMMCR0",
827 &spr_read_ureg, SPR_NOACCESS,
828 &spr_read_ureg, SPR_NOACCESS,
829 0x00000000);
830 /* XXX : not implemented */
831 spr_register(env, SPR_UMMCR1, "UMMCR1",
832 &spr_read_ureg, SPR_NOACCESS,
833 &spr_read_ureg, SPR_NOACCESS,
834 0x00000000);
835 /* XXX : not implemented */
836 spr_register(env, SPR_UPMC1, "UPMC1",
837 &spr_read_ureg, SPR_NOACCESS,
838 &spr_read_ureg, SPR_NOACCESS,
839 0x00000000);
840 /* XXX : not implemented */
841 spr_register(env, SPR_UPMC2, "UPMC2",
842 &spr_read_ureg, SPR_NOACCESS,
843 &spr_read_ureg, SPR_NOACCESS,
844 0x00000000);
845 /* XXX : not implemented */
846 spr_register(env, SPR_UPMC3, "UPMC3",
847 &spr_read_ureg, SPR_NOACCESS,
848 &spr_read_ureg, SPR_NOACCESS,
849 0x00000000);
850 /* XXX : not implemented */
851 spr_register(env, SPR_UPMC4, "UPMC4",
852 &spr_read_ureg, SPR_NOACCESS,
853 &spr_read_ureg, SPR_NOACCESS,
854 0x00000000);
855 /* XXX : not implemented */
856 spr_register(env, SPR_USIAR, "USIAR",
857 &spr_read_ureg, SPR_NOACCESS,
858 &spr_read_ureg, SPR_NOACCESS,
859 0x00000000);
860 /* External access control */
861 /* XXX : not implemented */
862 spr_register(env, SPR_EAR, "EAR",
863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_generic, &spr_write_generic,
865 0x00000000);
866 }
867
868 static void gen_spr_thrm (CPUPPCState *env)
869 {
870 /* Thermal management */
871 /* XXX : not implemented */
872 spr_register(env, SPR_THRM1, "THRM1",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_generic, &spr_write_generic,
875 0x00000000);
876 /* XXX : not implemented */
877 spr_register(env, SPR_THRM2, "THRM2",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_generic, &spr_write_generic,
880 0x00000000);
881 /* XXX : not implemented */
882 spr_register(env, SPR_THRM3, "THRM3",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_generic,
885 0x00000000);
886 }
887
888 /* SPR specific to PowerPC 604 implementation */
889 static void gen_spr_604 (CPUPPCState *env)
890 {
891 /* Processor identification */
892 spr_register(env, SPR_PIR, "PIR",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_generic, &spr_write_pir,
895 0x00000000);
896 /* Breakpoints */
897 /* XXX : not implemented */
898 spr_register(env, SPR_IABR, "IABR",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_generic, &spr_write_generic,
901 0x00000000);
902 /* XXX : not implemented */
903 spr_register(env, SPR_DABR, "DABR",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 /* Performance counters */
908 /* XXX : not implemented */
909 spr_register(env, SPR_MMCR0, "MMCR0",
910 SPR_NOACCESS, SPR_NOACCESS,
911 &spr_read_generic, &spr_write_generic,
912 0x00000000);
913 /* XXX : not implemented */
914 spr_register(env, SPR_PMC1, "PMC1",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 /* XXX : not implemented */
919 spr_register(env, SPR_PMC2, "PMC2",
920 SPR_NOACCESS, SPR_NOACCESS,
921 &spr_read_generic, &spr_write_generic,
922 0x00000000);
923 /* XXX : not implemented */
924 spr_register(env, SPR_SIAR, "SIAR",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, SPR_NOACCESS,
927 0x00000000);
928 /* XXX : not implemented */
929 spr_register(env, SPR_SDA, "SDA",
930 SPR_NOACCESS, SPR_NOACCESS,
931 &spr_read_generic, SPR_NOACCESS,
932 0x00000000);
933 /* External access control */
934 /* XXX : not implemented */
935 spr_register(env, SPR_EAR, "EAR",
936 SPR_NOACCESS, SPR_NOACCESS,
937 &spr_read_generic, &spr_write_generic,
938 0x00000000);
939 }
940
941 /* SPR specific to PowerPC 603 implementation */
942 static void gen_spr_603 (CPUPPCState *env)
943 {
944 /* External access control */
945 /* XXX : not implemented */
946 spr_register(env, SPR_EAR, "EAR",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, &spr_write_generic,
949 0x00000000);
950 }
951
952 /* SPR specific to PowerPC G2 implementation */
953 static void gen_spr_G2 (CPUPPCState *env)
954 {
955 /* Memory base address */
956 /* MBAR */
957 /* XXX : not implemented */
958 spr_register(env, SPR_MBAR, "MBAR",
959 SPR_NOACCESS, SPR_NOACCESS,
960 &spr_read_generic, &spr_write_generic,
961 0x00000000);
962 /* Exception processing */
963 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, &spr_write_generic,
966 0x00000000);
967 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
968 SPR_NOACCESS, SPR_NOACCESS,
969 &spr_read_generic, &spr_write_generic,
970 0x00000000);
971 /* Breakpoints */
972 /* XXX : not implemented */
973 spr_register(env, SPR_DABR, "DABR",
974 SPR_NOACCESS, SPR_NOACCESS,
975 &spr_read_generic, &spr_write_generic,
976 0x00000000);
977 /* XXX : not implemented */
978 spr_register(env, SPR_DABR2, "DABR2",
979 SPR_NOACCESS, SPR_NOACCESS,
980 &spr_read_generic, &spr_write_generic,
981 0x00000000);
982 /* XXX : not implemented */
983 spr_register(env, SPR_IABR, "IABR",
984 SPR_NOACCESS, SPR_NOACCESS,
985 &spr_read_generic, &spr_write_generic,
986 0x00000000);
987 /* XXX : not implemented */
988 spr_register(env, SPR_IABR2, "IABR2",
989 SPR_NOACCESS, SPR_NOACCESS,
990 &spr_read_generic, &spr_write_generic,
991 0x00000000);
992 /* XXX : not implemented */
993 spr_register(env, SPR_IBCR, "IBCR",
994 SPR_NOACCESS, SPR_NOACCESS,
995 &spr_read_generic, &spr_write_generic,
996 0x00000000);
997 /* XXX : not implemented */
998 spr_register(env, SPR_DBCR, "DBCR",
999 SPR_NOACCESS, SPR_NOACCESS,
1000 &spr_read_generic, &spr_write_generic,
1001 0x00000000);
1002 }
1003
1004 /* SPR specific to PowerPC 602 implementation */
1005 static void gen_spr_602 (CPUPPCState *env)
1006 {
1007 /* ESA registers */
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_SER, "SER",
1010 SPR_NOACCESS, SPR_NOACCESS,
1011 &spr_read_generic, &spr_write_generic,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_SEBR, "SEBR",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_ESASRR, "ESASRR",
1020 SPR_NOACCESS, SPR_NOACCESS,
1021 &spr_read_generic, &spr_write_generic,
1022 0x00000000);
1023 /* Floating point status */
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_SP, "SP",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 /* XXX : not implemented */
1030 spr_register(env, SPR_LT, "LT",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 /* Watchdog timer */
1035 /* XXX : not implemented */
1036 spr_register(env, SPR_TCR, "TCR",
1037 SPR_NOACCESS, SPR_NOACCESS,
1038 &spr_read_generic, &spr_write_generic,
1039 0x00000000);
1040 /* Interrupt base */
1041 spr_register(env, SPR_IBR, "IBR",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 /* XXX : not implemented */
1046 spr_register(env, SPR_IABR, "IABR",
1047 SPR_NOACCESS, SPR_NOACCESS,
1048 &spr_read_generic, &spr_write_generic,
1049 0x00000000);
1050 }
1051
1052 /* SPR specific to PowerPC 601 implementation */
1053 static void gen_spr_601 (CPUPPCState *env)
1054 {
1055 /* Multiplication/division register */
1056 /* MQ */
1057 spr_register(env, SPR_MQ, "MQ",
1058 &spr_read_generic, &spr_write_generic,
1059 &spr_read_generic, &spr_write_generic,
1060 0x00000000);
1061 /* RTC registers */
1062 spr_register(env, SPR_601_RTCU, "RTCU",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 SPR_NOACCESS, &spr_write_601_rtcu,
1065 0x00000000);
1066 spr_register(env, SPR_601_VRTCU, "RTCU",
1067 &spr_read_601_rtcu, SPR_NOACCESS,
1068 &spr_read_601_rtcu, SPR_NOACCESS,
1069 0x00000000);
1070 spr_register(env, SPR_601_RTCL, "RTCL",
1071 SPR_NOACCESS, SPR_NOACCESS,
1072 SPR_NOACCESS, &spr_write_601_rtcl,
1073 0x00000000);
1074 spr_register(env, SPR_601_VRTCL, "RTCL",
1075 &spr_read_601_rtcl, SPR_NOACCESS,
1076 &spr_read_601_rtcl, SPR_NOACCESS,
1077 0x00000000);
1078 /* Timer */
1079 #if 0 /* ? */
1080 spr_register(env, SPR_601_UDECR, "UDECR",
1081 &spr_read_decr, SPR_NOACCESS,
1082 &spr_read_decr, SPR_NOACCESS,
1083 0x00000000);
1084 #endif
1085 /* External access control */
1086 /* XXX : not implemented */
1087 spr_register(env, SPR_EAR, "EAR",
1088 SPR_NOACCESS, SPR_NOACCESS,
1089 &spr_read_generic, &spr_write_generic,
1090 0x00000000);
1091 /* Memory management */
1092 #if !defined(CONFIG_USER_ONLY)
1093 spr_register(env, SPR_IBAT0U, "IBAT0U",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_601_ubat, &spr_write_601_ubatu,
1096 0x00000000);
1097 spr_register(env, SPR_IBAT0L, "IBAT0L",
1098 SPR_NOACCESS, SPR_NOACCESS,
1099 &spr_read_601_ubat, &spr_write_601_ubatl,
1100 0x00000000);
1101 spr_register(env, SPR_IBAT1U, "IBAT1U",
1102 SPR_NOACCESS, SPR_NOACCESS,
1103 &spr_read_601_ubat, &spr_write_601_ubatu,
1104 0x00000000);
1105 spr_register(env, SPR_IBAT1L, "IBAT1L",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_601_ubat, &spr_write_601_ubatl,
1108 0x00000000);
1109 spr_register(env, SPR_IBAT2U, "IBAT2U",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_601_ubat, &spr_write_601_ubatu,
1112 0x00000000);
1113 spr_register(env, SPR_IBAT2L, "IBAT2L",
1114 SPR_NOACCESS, SPR_NOACCESS,
1115 &spr_read_601_ubat, &spr_write_601_ubatl,
1116 0x00000000);
1117 spr_register(env, SPR_IBAT3U, "IBAT3U",
1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_601_ubat, &spr_write_601_ubatu,
1120 0x00000000);
1121 spr_register(env, SPR_IBAT3L, "IBAT3L",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_601_ubat, &spr_write_601_ubatl,
1124 0x00000000);
1125 env->nb_BATs = 4;
1126 #endif
1127 }
1128
1129 static void gen_spr_74xx (CPUPPCState *env)
1130 {
1131 /* Processor identification */
1132 spr_register(env, SPR_PIR, "PIR",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_pir,
1135 0x00000000);
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_MMCR2, "MMCR2",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_UMMCR2, "UMMCR2",
1143 &spr_read_ureg, SPR_NOACCESS,
1144 &spr_read_ureg, SPR_NOACCESS,
1145 0x00000000);
1146 /* XXX: not implemented */
1147 spr_register(env, SPR_BAMR, "BAMR",
1148 SPR_NOACCESS, SPR_NOACCESS,
1149 &spr_read_generic, &spr_write_generic,
1150 0x00000000);
1151 /* XXX : not implemented */
1152 spr_register(env, SPR_UBAMR, "UBAMR",
1153 &spr_read_ureg, SPR_NOACCESS,
1154 &spr_read_ureg, SPR_NOACCESS,
1155 0x00000000);
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_MSSCR0, "MSSCR0",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161 /* Hardware implementation registers */
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_HID0, "HID0",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 /* XXX : not implemented */
1168 spr_register(env, SPR_HID1, "HID1",
1169 SPR_NOACCESS, SPR_NOACCESS,
1170 &spr_read_generic, &spr_write_generic,
1171 0x00000000);
1172 /* Altivec */
1173 spr_register(env, SPR_VRSAVE, "VRSAVE",
1174 &spr_read_generic, &spr_write_generic,
1175 &spr_read_generic, &spr_write_generic,
1176 0x00000000);
1177 /* XXX : not implemented */
1178 spr_register(env, SPR_L2CR, "L2CR",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 }
1183
1184 static void gen_l3_ctrl (CPUPPCState *env)
1185 {
1186 /* L3CR */
1187 /* XXX : not implemented */
1188 spr_register(env, SPR_L3CR, "L3CR",
1189 SPR_NOACCESS, SPR_NOACCESS,
1190 &spr_read_generic, &spr_write_generic,
1191 0x00000000);
1192 /* L3ITCR0 */
1193 /* XXX : not implemented */
1194 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198 /* L3ITCR1 */
1199 /* XXX : not implemented */
1200 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
1204 /* L3ITCR2 */
1205 /* XXX : not implemented */
1206 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 /* L3ITCR3 */
1211 /* XXX : not implemented */
1212 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1213 SPR_NOACCESS, SPR_NOACCESS,
1214 &spr_read_generic, &spr_write_generic,
1215 0x00000000);
1216 /* L3OHCR */
1217 /* XXX : not implemented */
1218 spr_register(env, SPR_L3OHCR, "L3OHCR",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 /* L3PM */
1223 /* XXX : not implemented */
1224 spr_register(env, SPR_L3PM, "L3PM",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_generic, &spr_write_generic,
1227 0x00000000);
1228 }
1229
1230 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1231 {
1232 #if !defined(CONFIG_USER_ONLY)
1233 env->nb_tlb = nb_tlbs;
1234 env->nb_ways = nb_ways;
1235 env->id_tlbs = 1;
1236 /* XXX : not implemented */
1237 spr_register(env, SPR_PTEHI, "PTEHI",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_generic, &spr_write_generic,
1240 0x00000000);
1241 /* XXX : not implemented */
1242 spr_register(env, SPR_PTELO, "PTELO",
1243 SPR_NOACCESS, SPR_NOACCESS,
1244 &spr_read_generic, &spr_write_generic,
1245 0x00000000);
1246 /* XXX : not implemented */
1247 spr_register(env, SPR_TLBMISS, "TLBMISS",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0x00000000);
1251 #endif
1252 }
1253
1254 static void gen_spr_usprgh (CPUPPCState *env)
1255 {
1256 spr_register(env, SPR_USPRG4, "USPRG4",
1257 &spr_read_ureg, SPR_NOACCESS,
1258 &spr_read_ureg, SPR_NOACCESS,
1259 0x00000000);
1260 spr_register(env, SPR_USPRG5, "USPRG5",
1261 &spr_read_ureg, SPR_NOACCESS,
1262 &spr_read_ureg, SPR_NOACCESS,
1263 0x00000000);
1264 spr_register(env, SPR_USPRG6, "USPRG6",
1265 &spr_read_ureg, SPR_NOACCESS,
1266 &spr_read_ureg, SPR_NOACCESS,
1267 0x00000000);
1268 spr_register(env, SPR_USPRG7, "USPRG7",
1269 &spr_read_ureg, SPR_NOACCESS,
1270 &spr_read_ureg, SPR_NOACCESS,
1271 0x00000000);
1272 }
1273
1274 /* PowerPC BookE SPR */
1275 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1276 {
1277 const unsigned char *ivor_names[64] = {
1278 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1279 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1280 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1281 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1282 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1283 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1284 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1285 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1286 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1287 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1288 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1289 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1290 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1291 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1292 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1293 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1294 };
1295 #define SPR_BOOKE_IVORxx (-1)
1296 int ivor_sprn[64] = {
1297 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1298 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1299 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1300 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1301 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1302 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1303 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1304 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1305 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1306 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1307 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1308 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1309 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1310 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1311 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1312 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1313 };
1314 int i;
1315
1316 /* Interrupt processing */
1317 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_generic, &spr_write_generic,
1320 0x00000000);
1321 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
1325 /* Debug */
1326 /* XXX : not implemented */
1327 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1328 SPR_NOACCESS, SPR_NOACCESS,
1329 &spr_read_generic, &spr_write_generic,
1330 0x00000000);
1331 /* XXX : not implemented */
1332 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1333 SPR_NOACCESS, SPR_NOACCESS,
1334 &spr_read_generic, &spr_write_generic,
1335 0x00000000);
1336 /* XXX : not implemented */
1337 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1338 SPR_NOACCESS, SPR_NOACCESS,
1339 &spr_read_generic, &spr_write_generic,
1340 0x00000000);
1341 /* XXX : not implemented */
1342 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346 /* XXX : not implemented */
1347 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1348 SPR_NOACCESS, SPR_NOACCESS,
1349 &spr_read_generic, &spr_write_generic,
1350 0x00000000);
1351 /* XXX : not implemented */
1352 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1353 SPR_NOACCESS, SPR_NOACCESS,
1354 &spr_read_generic, &spr_write_generic,
1355 0x00000000);
1356 /* XXX : not implemented */
1357 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1358 SPR_NOACCESS, SPR_NOACCESS,
1359 &spr_read_generic, &spr_write_generic,
1360 0x00000000);
1361 /* XXX : not implemented */
1362 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1363 SPR_NOACCESS, SPR_NOACCESS,
1364 &spr_read_generic, &spr_write_clear,
1365 0x00000000);
1366 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370 spr_register(env, SPR_BOOKE_ESR, "ESR",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_excp_prefix,
1377 0x00000000);
1378 /* Exception vectors */
1379 for (i = 0; i < 64; i++) {
1380 if (ivor_mask & (1ULL << i)) {
1381 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1382 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1383 exit(1);
1384 }
1385 spr_register(env, ivor_sprn[i], ivor_names[i],
1386 SPR_NOACCESS, SPR_NOACCESS,
1387 &spr_read_generic, &spr_write_excp_vector,
1388 0x00000000);
1389 }
1390 }
1391 spr_register(env, SPR_BOOKE_PID, "PID",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, &spr_write_generic,
1394 0x00000000);
1395 spr_register(env, SPR_BOOKE_TCR, "TCR",
1396 SPR_NOACCESS, SPR_NOACCESS,
1397 &spr_read_generic, &spr_write_booke_tcr,
1398 0x00000000);
1399 spr_register(env, SPR_BOOKE_TSR, "TSR",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_booke_tsr,
1402 0x00000000);
1403 /* Timer */
1404 spr_register(env, SPR_DECR, "DECR",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_decr, &spr_write_decr,
1407 0x00000000);
1408 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 SPR_NOACCESS, &spr_write_generic,
1411 0x00000000);
1412 /* SPRGs */
1413 spr_register(env, SPR_USPRG0, "USPRG0",
1414 &spr_read_generic, &spr_write_generic,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 spr_register(env, SPR_SPRG4, "SPRG4",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 &spr_read_generic, &spr_write_generic,
1420 0x00000000);
1421 spr_register(env, SPR_SPRG5, "SPRG5",
1422 SPR_NOACCESS, SPR_NOACCESS,
1423 &spr_read_generic, &spr_write_generic,
1424 0x00000000);
1425 spr_register(env, SPR_SPRG6, "SPRG6",
1426 SPR_NOACCESS, SPR_NOACCESS,
1427 &spr_read_generic, &spr_write_generic,
1428 0x00000000);
1429 spr_register(env, SPR_SPRG7, "SPRG7",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
1433 }
1434
1435 /* FSL storage control registers */
1436 static void gen_spr_BookE_FSL (CPUPPCState *env, uint32_t mas_mask)
1437 {
1438 #if !defined(CONFIG_USER_ONLY)
1439 const unsigned char *mas_names[8] = {
1440 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1441 };
1442 int mas_sprn[8] = {
1443 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1444 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1445 };
1446 int i;
1447
1448 /* TLB assist registers */
1449 /* XXX : not implemented */
1450 for (i = 0; i < 8; i++) {
1451 if (mas_mask & (1 << i)) {
1452 spr_register(env, mas_sprn[i], mas_names[i],
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
1456 }
1457 }
1458 if (env->nb_pids > 1) {
1459 /* XXX : not implemented */
1460 spr_register(env, SPR_BOOKE_PID1, "PID1",
1461 SPR_NOACCESS, SPR_NOACCESS,
1462 &spr_read_generic, &spr_write_generic,
1463 0x00000000);
1464 }
1465 if (env->nb_pids > 2) {
1466 /* XXX : not implemented */
1467 spr_register(env, SPR_BOOKE_PID2, "PID2",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 &spr_read_generic, &spr_write_generic,
1470 0x00000000);
1471 }
1472 /* XXX : not implemented */
1473 spr_register(env, SPR_MMUCFG, "MMUCFG",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_generic, SPR_NOACCESS,
1476 0x00000000); /* TOFIX */
1477 /* XXX : not implemented */
1478 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
1479 SPR_NOACCESS, SPR_NOACCESS,
1480 &spr_read_generic, &spr_write_generic,
1481 0x00000000); /* TOFIX */
1482 switch (env->nb_ways) {
1483 case 4:
1484 /* XXX : not implemented */
1485 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1486 SPR_NOACCESS, SPR_NOACCESS,
1487 &spr_read_generic, SPR_NOACCESS,
1488 0x00000000); /* TOFIX */
1489 /* Fallthru */
1490 case 3:
1491 /* XXX : not implemented */
1492 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1493 SPR_NOACCESS, SPR_NOACCESS,
1494 &spr_read_generic, SPR_NOACCESS,
1495 0x00000000); /* TOFIX */
1496 /* Fallthru */
1497 case 2:
1498 /* XXX : not implemented */
1499 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1500 SPR_NOACCESS, SPR_NOACCESS,
1501 &spr_read_generic, SPR_NOACCESS,
1502 0x00000000); /* TOFIX */
1503 /* Fallthru */
1504 case 1:
1505 /* XXX : not implemented */
1506 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, SPR_NOACCESS,
1509 0x00000000); /* TOFIX */
1510 /* Fallthru */
1511 case 0:
1512 default:
1513 break;
1514 }
1515 #endif
1516 }
1517
1518 /* SPR specific to PowerPC 440 implementation */
1519 static void gen_spr_440 (CPUPPCState *env)
1520 {
1521 /* Cache control */
1522 /* XXX : not implemented */
1523 spr_register(env, SPR_440_DNV0, "DNV0",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_generic,
1526 0x00000000);
1527 /* XXX : not implemented */
1528 spr_register(env, SPR_440_DNV1, "DNV1",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
1532 /* XXX : not implemented */
1533 spr_register(env, SPR_440_DNV2, "DNV2",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
1537 /* XXX : not implemented */
1538 spr_register(env, SPR_440_DNV3, "DNV3",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542 /* XXX : not implemented */
1543 spr_register(env, SPR_440_DTV0, "DTV0",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547 /* XXX : not implemented */
1548 spr_register(env, SPR_440_DTV1, "DTV1",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_440_DTV2, "DTV2",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_440_DTV3, "DTV3",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 /* XXX : not implemented */
1563 spr_register(env, SPR_440_DVLIM, "DVLIM",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567 /* XXX : not implemented */
1568 spr_register(env, SPR_440_INV0, "INV0",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
1572 /* XXX : not implemented */
1573 spr_register(env, SPR_440_INV1, "INV1",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
1577 /* XXX : not implemented */
1578 spr_register(env, SPR_440_INV2, "INV2",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
1582 /* XXX : not implemented */
1583 spr_register(env, SPR_440_INV3, "INV3",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587 /* XXX : not implemented */
1588 spr_register(env, SPR_440_ITV0, "ITV0",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_generic,
1591 0x00000000);
1592 /* XXX : not implemented */
1593 spr_register(env, SPR_440_ITV1, "ITV1",
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_generic,
1596 0x00000000);
1597 /* XXX : not implemented */
1598 spr_register(env, SPR_440_ITV2, "ITV2",
1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, &spr_write_generic,
1601 0x00000000);
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_440_ITV3, "ITV3",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1606 0x00000000);
1607 /* XXX : not implemented */
1608 spr_register(env, SPR_440_IVLIM, "IVLIM",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_generic,
1611 0x00000000);
1612 /* Cache debug */
1613 /* XXX : not implemented */
1614 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1615 SPR_NOACCESS, SPR_NOACCESS,
1616 &spr_read_generic, SPR_NOACCESS,
1617 0x00000000);
1618 /* XXX : not implemented */
1619 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, SPR_NOACCESS,
1622 0x00000000);
1623 /* XXX : not implemented */
1624 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, SPR_NOACCESS,
1627 0x00000000);
1628 /* XXX : not implemented */
1629 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1630 SPR_NOACCESS, SPR_NOACCESS,
1631 &spr_read_generic, SPR_NOACCESS,
1632 0x00000000);
1633 /* XXX : not implemented */
1634 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, SPR_NOACCESS,
1637 0x00000000);
1638 /* XXX : not implemented */
1639 spr_register(env, SPR_440_DBDR, "DBDR",
1640 SPR_NOACCESS, SPR_NOACCESS,
1641 &spr_read_generic, &spr_write_generic,
1642 0x00000000);
1643 /* Processor control */
1644 spr_register(env, SPR_4xx_CCR0, "CCR0",
1645 SPR_NOACCESS, SPR_NOACCESS,
1646 &spr_read_generic, &spr_write_generic,
1647 0x00000000);
1648 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1649 SPR_NOACCESS, SPR_NOACCESS,
1650 &spr_read_generic, SPR_NOACCESS,
1651 0x00000000);
1652 /* Storage control */
1653 spr_register(env, SPR_440_MMUCR, "MMUCR",
1654 SPR_NOACCESS, SPR_NOACCESS,
1655 &spr_read_generic, &spr_write_generic,
1656 0x00000000);
1657 }
1658
1659 /* SPR shared between PowerPC 40x implementations */
1660 static void gen_spr_40x (CPUPPCState *env)
1661 {
1662 /* Cache */
1663 /* not emulated, as Qemu do not emulate caches */
1664 spr_register(env, SPR_40x_DCCR, "DCCR",
1665 SPR_NOACCESS, SPR_NOACCESS,
1666 &spr_read_generic, &spr_write_generic,
1667 0x00000000);
1668 /* not emulated, as Qemu do not emulate caches */
1669 spr_register(env, SPR_40x_ICCR, "ICCR",
1670 SPR_NOACCESS, SPR_NOACCESS,
1671 &spr_read_generic, &spr_write_generic,
1672 0x00000000);
1673 /* not emulated, as Qemu do not emulate caches */
1674 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1675 SPR_NOACCESS, SPR_NOACCESS,
1676 &spr_read_generic, SPR_NOACCESS,
1677 0x00000000);
1678 /* Exception */
1679 spr_register(env, SPR_40x_DEAR, "DEAR",
1680 SPR_NOACCESS, SPR_NOACCESS,
1681 &spr_read_generic, &spr_write_generic,
1682 0x00000000);
1683 spr_register(env, SPR_40x_ESR, "ESR",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 spr_register(env, SPR_40x_EVPR, "EVPR",
1688 SPR_NOACCESS, SPR_NOACCESS,
1689 &spr_read_generic, &spr_write_excp_prefix,
1690 0x00000000);
1691 spr_register(env, SPR_40x_SRR2, "SRR2",
1692 &spr_read_generic, &spr_write_generic,
1693 &spr_read_generic, &spr_write_generic,
1694 0x00000000);
1695 spr_register(env, SPR_40x_SRR3, "SRR3",
1696 &spr_read_generic, &spr_write_generic,
1697 &spr_read_generic, &spr_write_generic,
1698 0x00000000);
1699 /* Timers */
1700 spr_register(env, SPR_40x_PIT, "PIT",
1701 SPR_NOACCESS, SPR_NOACCESS,
1702 &spr_read_40x_pit, &spr_write_40x_pit,
1703 0x00000000);
1704 spr_register(env, SPR_40x_TCR, "TCR",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_booke_tcr,
1707 0x00000000);
1708 spr_register(env, SPR_40x_TSR, "TSR",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_booke_tsr,
1711 0x00000000);
1712 }
1713
1714 /* SPR specific to PowerPC 405 implementation */
1715 static void gen_spr_405 (CPUPPCState *env)
1716 {
1717 /* MMU */
1718 spr_register(env, SPR_40x_PID, "PID",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 spr_register(env, SPR_4xx_CCR0, "CCR0",
1723 SPR_NOACCESS, SPR_NOACCESS,
1724 &spr_read_generic, &spr_write_generic,
1725 0x00700000);
1726 /* Debug interface */
1727 /* XXX : not implemented */
1728 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_40x_dbcr0,
1731 0x00000000);
1732 /* XXX : not implemented */
1733 spr_register(env, SPR_405_DBCR1, "DBCR1",
1734 SPR_NOACCESS, SPR_NOACCESS,
1735 &spr_read_generic, &spr_write_generic,
1736 0x00000000);
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_40x_DBSR, "DBSR",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_clear,
1741 /* Last reset was system reset */
1742 0x00000300);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_40x_DAC1, "DAC1",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_generic,
1747 0x00000000);
1748 spr_register(env, SPR_40x_DAC2, "DAC2",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_405_DVC1, "DVC1",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_405_DVC2, "DVC2",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_40x_IAC1, "IAC1",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 spr_register(env, SPR_40x_IAC2, "IAC2",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, &spr_write_generic,
1770 0x00000000);
1771 /* XXX : not implemented */
1772 spr_register(env, SPR_405_IAC3, "IAC3",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, &spr_write_generic,
1775 0x00000000);
1776 /* XXX : not implemented */
1777 spr_register(env, SPR_405_IAC4, "IAC4",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, &spr_write_generic,
1780 0x00000000);
1781 /* Storage control */
1782 /* XXX: TODO: not implemented */
1783 spr_register(env, SPR_405_SLER, "SLER",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_40x_sler,
1786 0x00000000);
1787 spr_register(env, SPR_40x_ZPR, "ZPR",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 /* XXX : not implemented */
1792 spr_register(env, SPR_405_SU0R, "SU0R",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_generic,
1795 0x00000000);
1796 /* SPRG */
1797 spr_register(env, SPR_USPRG0, "USPRG0",
1798 &spr_read_ureg, SPR_NOACCESS,
1799 &spr_read_ureg, SPR_NOACCESS,
1800 0x00000000);
1801 spr_register(env, SPR_SPRG4, "SPRG4",
1802 SPR_NOACCESS, SPR_NOACCESS,
1803 &spr_read_generic, &spr_write_generic,
1804 0x00000000);
1805 spr_register(env, SPR_SPRG5, "SPRG5",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 spr_register(env, SPR_SPRG6, "SPRG6",
1810 SPR_NOACCESS, SPR_NOACCESS,
1811 spr_read_generic, &spr_write_generic,
1812 0x00000000);
1813 spr_register(env, SPR_SPRG7, "SPRG7",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817 gen_spr_usprgh(env);
1818 }
1819
1820 /* SPR shared between PowerPC 401 & 403 implementations */
1821 static void gen_spr_401_403 (CPUPPCState *env)
1822 {
1823 /* Time base */
1824 spr_register(env, SPR_403_VTBL, "TBL",
1825 &spr_read_tbl, SPR_NOACCESS,
1826 &spr_read_tbl, SPR_NOACCESS,
1827 0x00000000);
1828 spr_register(env, SPR_403_TBL, "TBL",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 SPR_NOACCESS, &spr_write_tbl,
1831 0x00000000);
1832 spr_register(env, SPR_403_VTBU, "TBU",
1833 &spr_read_tbu, SPR_NOACCESS,
1834 &spr_read_tbu, SPR_NOACCESS,
1835 0x00000000);
1836 spr_register(env, SPR_403_TBU, "TBU",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 SPR_NOACCESS, &spr_write_tbu,
1839 0x00000000);
1840 /* Debug */
1841 /* not emulated, as Qemu do not emulate caches */
1842 spr_register(env, SPR_403_CDBCR, "CDBCR",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_generic,
1845 0x00000000);
1846 }
1847
1848 /* SPR specific to PowerPC 401 implementation */
1849 static void gen_spr_401 (CPUPPCState *env)
1850 {
1851 /* Debug interface */
1852 /* XXX : not implemented */
1853 spr_register(env, SPR_40x_DBCR0, "DBCR",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, &spr_write_40x_dbcr0,
1856 0x00000000);
1857 /* XXX : not implemented */
1858 spr_register(env, SPR_40x_DBSR, "DBSR",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_clear,
1861 /* Last reset was system reset */
1862 0x00000300);
1863 /* XXX : not implemented */
1864 spr_register(env, SPR_40x_DAC1, "DAC",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_generic,
1867 0x00000000);
1868 /* XXX : not implemented */
1869 spr_register(env, SPR_40x_IAC1, "IAC",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_generic,
1872 0x00000000);
1873 /* Storage control */
1874 /* XXX: TODO: not implemented */
1875 spr_register(env, SPR_405_SLER, "SLER",
1876 SPR_NOACCESS, SPR_NOACCESS,
1877 &spr_read_generic, &spr_write_40x_sler,
1878 0x00000000);
1879 /* not emulated, as Qemu never does speculative access */
1880 spr_register(env, SPR_40x_SGR, "SGR",
1881 SPR_NOACCESS, SPR_NOACCESS,
1882 &spr_read_generic, &spr_write_generic,
1883 0xFFFFFFFF);
1884 /* not emulated, as Qemu do not emulate caches */
1885 spr_register(env, SPR_40x_DCWR, "DCWR",
1886 SPR_NOACCESS, SPR_NOACCESS,
1887 &spr_read_generic, &spr_write_generic,
1888 0x00000000);
1889 }
1890
1891 static void gen_spr_401x2 (CPUPPCState *env)
1892 {
1893 gen_spr_401(env);
1894 spr_register(env, SPR_40x_PID, "PID",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 spr_register(env, SPR_40x_ZPR, "ZPR",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 }
1903
1904 /* SPR specific to PowerPC 403 implementation */
1905 static void gen_spr_403 (CPUPPCState *env)
1906 {
1907 /* Debug interface */
1908 /* XXX : not implemented */
1909 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_generic, &spr_write_40x_dbcr0,
1912 0x00000000);
1913 /* XXX : not implemented */
1914 spr_register(env, SPR_40x_DBSR, "DBSR",
1915 SPR_NOACCESS, SPR_NOACCESS,
1916 &spr_read_generic, &spr_write_clear,
1917 /* Last reset was system reset */
1918 0x00000300);
1919 /* XXX : not implemented */
1920 spr_register(env, SPR_40x_DAC1, "DAC1",
1921 SPR_NOACCESS, SPR_NOACCESS,
1922 &spr_read_generic, &spr_write_generic,
1923 0x00000000);
1924 /* XXX : not implemented */
1925 spr_register(env, SPR_40x_DAC2, "DAC2",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 /* XXX : not implemented */
1930 spr_register(env, SPR_40x_IAC1, "IAC1",
1931 SPR_NOACCESS, SPR_NOACCESS,
1932 &spr_read_generic, &spr_write_generic,
1933 0x00000000);
1934 /* XXX : not implemented */
1935 spr_register(env, SPR_40x_IAC2, "IAC2",
1936 SPR_NOACCESS, SPR_NOACCESS,
1937 &spr_read_generic, &spr_write_generic,
1938 0x00000000);
1939 }
1940
1941 static void gen_spr_403_real (CPUPPCState *env)
1942 {
1943 spr_register(env, SPR_403_PBL1, "PBL1",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_403_pbr, &spr_write_403_pbr,
1946 0x00000000);
1947 spr_register(env, SPR_403_PBU1, "PBU1",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_403_pbr, &spr_write_403_pbr,
1950 0x00000000);
1951 spr_register(env, SPR_403_PBL2, "PBL2",
1952 SPR_NOACCESS, SPR_NOACCESS,
1953 &spr_read_403_pbr, &spr_write_403_pbr,
1954 0x00000000);
1955 spr_register(env, SPR_403_PBU2, "PBU2",
1956 SPR_NOACCESS, SPR_NOACCESS,
1957 &spr_read_403_pbr, &spr_write_403_pbr,
1958 0x00000000);
1959 }
1960
1961 static void gen_spr_403_mmu (CPUPPCState *env)
1962 {
1963 /* MMU */
1964 spr_register(env, SPR_40x_PID, "PID",
1965 SPR_NOACCESS, SPR_NOACCESS,
1966 &spr_read_generic, &spr_write_generic,
1967 0x00000000);
1968 spr_register(env, SPR_40x_ZPR, "ZPR",
1969 SPR_NOACCESS, SPR_NOACCESS,
1970 &spr_read_generic, &spr_write_generic,
1971 0x00000000);
1972 }
1973
1974 /* SPR specific to PowerPC compression coprocessor extension */
1975 static void gen_spr_compress (CPUPPCState *env)
1976 {
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_401_SKR, "SKR",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 }
1983
1984 #if defined (TARGET_PPC64)
1985 /* SPR specific to PowerPC 620 */
1986 static void gen_spr_620 (CPUPPCState *env)
1987 {
1988 /* Processor identification */
1989 spr_register(env, SPR_PIR, "PIR",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_pir,
1992 0x00000000);
1993 spr_register(env, SPR_ASR, "ASR",
1994 SPR_NOACCESS, SPR_NOACCESS,
1995 &spr_read_asr, &spr_write_asr,
1996 0x00000000);
1997 /* Breakpoints */
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_IABR, "IABR",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, &spr_write_generic,
2002 0x00000000);
2003 /* XXX : not implemented */
2004 spr_register(env, SPR_DABR, "DABR",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, &spr_write_generic,
2007 0x00000000);
2008 /* XXX : not implemented */
2009 spr_register(env, SPR_SIAR, "SIAR",
2010 SPR_NOACCESS, SPR_NOACCESS,
2011 &spr_read_generic, SPR_NOACCESS,
2012 0x00000000);
2013 /* XXX : not implemented */
2014 spr_register(env, SPR_SDA, "SDA",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, SPR_NOACCESS,
2017 0x00000000);
2018 /* XXX : not implemented */
2019 spr_register(env, SPR_620_PMC1R, "PMC1",
2020 SPR_NOACCESS, SPR_NOACCESS,
2021 &spr_read_generic, SPR_NOACCESS,
2022 0x00000000);
2023 spr_register(env, SPR_620_PMC1W, "PMC1",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 SPR_NOACCESS, &spr_write_generic,
2026 0x00000000);
2027 /* XXX : not implemented */
2028 spr_register(env, SPR_620_PMC2R, "PMC2",
2029 SPR_NOACCESS, SPR_NOACCESS,
2030 &spr_read_generic, SPR_NOACCESS,
2031 0x00000000);
2032 spr_register(env, SPR_620_PMC2W, "PMC2",
2033 SPR_NOACCESS, SPR_NOACCESS,
2034 SPR_NOACCESS, &spr_write_generic,
2035 0x00000000);
2036 /* XXX : not implemented */
2037 spr_register(env, SPR_620_MMCR0R, "MMCR0",
2038 SPR_NOACCESS, SPR_NOACCESS,
2039 &spr_read_generic, SPR_NOACCESS,
2040 0x00000000);
2041 spr_register(env, SPR_620_MMCR0W, "MMCR0",
2042 SPR_NOACCESS, SPR_NOACCESS,
2043 SPR_NOACCESS, &spr_write_generic,
2044 0x00000000);
2045 /* External access control */
2046 /* XXX : not implemented */
2047 spr_register(env, SPR_EAR, "EAR",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 &spr_read_generic, &spr_write_generic,
2050 0x00000000);
2051 #if 0 // XXX: check this
2052 /* XXX : not implemented */
2053 spr_register(env, SPR_620_PMR0, "PMR0",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, &spr_write_generic,
2056 0x00000000);
2057 /* XXX : not implemented */
2058 spr_register(env, SPR_620_PMR1, "PMR1",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_generic, &spr_write_generic,
2061 0x00000000);
2062 /* XXX : not implemented */
2063 spr_register(env, SPR_620_PMR2, "PMR2",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_generic, &spr_write_generic,
2066 0x00000000);
2067 /* XXX : not implemented */
2068 spr_register(env, SPR_620_PMR3, "PMR3",
2069 SPR_NOACCESS, SPR_NOACCESS,
2070 &spr_read_generic, &spr_write_generic,
2071 0x00000000);
2072 /* XXX : not implemented */
2073 spr_register(env, SPR_620_PMR4, "PMR4",
2074 SPR_NOACCESS, SPR_NOACCESS,
2075 &spr_read_generic, &spr_write_generic,
2076 0x00000000);
2077 /* XXX : not implemented */
2078 spr_register(env, SPR_620_PMR5, "PMR5",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, &spr_write_generic,
2081 0x00000000);
2082 /* XXX : not implemented */
2083 spr_register(env, SPR_620_PMR6, "PMR6",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
2087 /* XXX : not implemented */
2088 spr_register(env, SPR_620_PMR7, "PMR7",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 /* XXX : not implemented */
2093 spr_register(env, SPR_620_PMR8, "PMR8",
2094 SPR_NOACCESS, SPR_NOACCESS,
2095 &spr_read_generic, &spr_write_generic,
2096 0x00000000);
2097 /* XXX : not implemented */
2098 spr_register(env, SPR_620_PMR9, "PMR9",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
2102 /* XXX : not implemented */
2103 spr_register(env, SPR_620_PMRA, "PMR10",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 /* XXX : not implemented */
2108 spr_register(env, SPR_620_PMRB, "PMR11",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_generic, &spr_write_generic,
2111 0x00000000);
2112 /* XXX : not implemented */
2113 spr_register(env, SPR_620_PMRC, "PMR12",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_generic,
2116 0x00000000);
2117 /* XXX : not implemented */
2118 spr_register(env, SPR_620_PMRD, "PMR13",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0x00000000);
2122 /* XXX : not implemented */
2123 spr_register(env, SPR_620_PMRE, "PMR14",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127 /* XXX : not implemented */
2128 spr_register(env, SPR_620_PMRF, "PMR15",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132 #endif
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_620_BUSCSR, "BUSCSR",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_generic,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_620_L2CR, "L2CR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_generic,
2142 0x00000000);
2143 /* XXX : not implemented */
2144 spr_register(env, SPR_620_L2SR, "L2SR",
2145 SPR_NOACCESS, SPR_NOACCESS,
2146 &spr_read_generic, &spr_write_generic,
2147 0x00000000);
2148 }
2149 #endif /* defined (TARGET_PPC64) */
2150
2151 static void gen_spr_5xx_8xx (CPUPPCState *env)
2152 {
2153 /* Exception processing */
2154 spr_register(env, SPR_DSISR, "DSISR",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, &spr_write_generic,
2157 0x00000000);
2158 spr_register(env, SPR_DAR, "DAR",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
2162 /* Timer */
2163 spr_register(env, SPR_DECR, "DECR",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_decr, &spr_write_decr,
2166 0x00000000);
2167 /* XXX : not implemented */
2168 spr_register(env, SPR_MPC_EIE, "EIE",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_generic, &spr_write_generic,
2171 0x00000000);
2172 /* XXX : not implemented */
2173 spr_register(env, SPR_MPC_EID, "EID",
2174 SPR_NOACCESS, SPR_NOACCESS,
2175 &spr_read_generic, &spr_write_generic,
2176 0x00000000);
2177 /* XXX : not implemented */
2178 spr_register(env, SPR_MPC_NRI, "NRI",
2179 SPR_NOACCESS, SPR_NOACCESS,
2180 &spr_read_generic, &spr_write_generic,
2181 0x00000000);
2182 /* XXX : not implemented */
2183 spr_register(env, SPR_MPC_CMPA, "CMPA",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 /* XXX : not implemented */
2188 spr_register(env, SPR_MPC_CMPB, "CMPB",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
2192 /* XXX : not implemented */
2193 spr_register(env, SPR_MPC_CMPC, "CMPC",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 /* XXX : not implemented */
2198 spr_register(env, SPR_MPC_CMPD, "CMPD",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 /* XXX : not implemented */
2203 spr_register(env, SPR_MPC_ECR, "ECR",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207 /* XXX : not implemented */
2208 spr_register(env, SPR_MPC_DER, "DER",
2209 SPR_NOACCESS, SPR_NOACCESS,
2210 &spr_read_generic, &spr_write_generic,
2211 0x00000000);
2212 /* XXX : not implemented */
2213 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 /* XXX : not implemented */
2218 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 &spr_read_generic, &spr_write_generic,
2221 0x00000000);
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_MPC_CMPE, "CMPE",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_generic,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_MPC_CMPF, "CMPF",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 /* XXX : not implemented */
2233 spr_register(env, SPR_MPC_CMPG, "CMPG",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 &spr_read_generic, &spr_write_generic,
2236 0x00000000);
2237 /* XXX : not implemented */
2238 spr_register(env, SPR_MPC_CMPH, "CMPH",
2239 SPR_NOACCESS, SPR_NOACCESS,
2240 &spr_read_generic, &spr_write_generic,
2241 0x00000000);
2242 /* XXX : not implemented */
2243 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2244 SPR_NOACCESS, SPR_NOACCESS,
2245 &spr_read_generic, &spr_write_generic,
2246 0x00000000);
2247 /* XXX : not implemented */
2248 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2249 SPR_NOACCESS, SPR_NOACCESS,
2250 &spr_read_generic, &spr_write_generic,
2251 0x00000000);
2252 /* XXX : not implemented */
2253 spr_register(env, SPR_MPC_BAR, "BAR",
2254 SPR_NOACCESS, SPR_NOACCESS,
2255 &spr_read_generic, &spr_write_generic,
2256 0x00000000);
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_MPC_DPDR, "DPDR",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_generic,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_MPC_IMMR, "IMMR",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 }
2268
2269 static void gen_spr_5xx (CPUPPCState *env)
2270 {
2271 /* XXX : not implemented */
2272 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_generic,
2275 0x00000000);
2276 /* XXX : not implemented */
2277 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2278 SPR_NOACCESS, SPR_NOACCESS,
2279 &spr_read_generic, &spr_write_generic,
2280 0x00000000);
2281 /* XXX : not implemented */
2282 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_generic,
2285 0x00000000);
2286 /* XXX : not implemented */
2287 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2288 SPR_NOACCESS, SPR_NOACCESS,
2289 &spr_read_generic, &spr_write_generic,
2290 0x00000000);
2291 /* XXX : not implemented */
2292 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2293 SPR_NOACCESS, SPR_NOACCESS,
2294 &spr_read_generic, &spr_write_generic,
2295 0x00000000);
2296 /* XXX : not implemented */
2297 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2298 SPR_NOACCESS, SPR_NOACCESS,
2299 &spr_read_generic, &spr_write_generic,
2300 0x00000000);
2301 /* XXX : not implemented */
2302 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2303 SPR_NOACCESS, SPR_NOACCESS,
2304 &spr_read_generic, &spr_write_generic,
2305 0x00000000);
2306 /* XXX : not implemented */
2307 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2308 SPR_NOACCESS, SPR_NOACCESS,
2309 &spr_read_generic, &spr_write_generic,
2310 0x00000000);
2311 /* XXX : not implemented */
2312 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2313 SPR_NOACCESS, SPR_NOACCESS,
2314 &spr_read_generic, &spr_write_generic,
2315 0x00000000);
2316 /* XXX : not implemented */
2317 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2318 SPR_NOACCESS, SPR_NOACCESS,
2319 &spr_read_generic, &spr_write_generic,
2320 0x00000000);
2321 /* XXX : not implemented */
2322 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2323 SPR_NOACCESS, SPR_NOACCESS,
2324 &spr_read_generic, &spr_write_generic,
2325 0x00000000);
2326 /* XXX : not implemented */
2327 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2328 SPR_NOACCESS, SPR_NOACCESS,
2329 &spr_read_generic, &spr_write_generic,
2330 0x00000000);
2331 /* XXX : not implemented */
2332 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2333 SPR_NOACCESS, SPR_NOACCESS,
2334 &spr_read_generic, &spr_write_generic,
2335 0x00000000);
2336 /* XXX : not implemented */
2337 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2338 SPR_NOACCESS, SPR_NOACCESS,
2339 &spr_read_generic, &spr_write_generic,
2340 0x00000000);
2341 /* XXX : not implemented */
2342 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2343 SPR_NOACCESS, SPR_NOACCESS,
2344 &spr_read_generic, &spr_write_generic,
2345 0x00000000);
2346 /* XXX : not implemented */
2347 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351 /* XXX : not implemented */
2352 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_generic, &spr_write_generic,
2355 0x00000000);
2356 /* XXX : not implemented */
2357 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 0x00000000);
2361 /* XXX : not implemented */
2362 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_generic, &spr_write_generic,
2365 0x00000000);
2366 /* XXX : not implemented */
2367 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2368 SPR_NOACCESS, SPR_NOACCESS,
2369 &spr_read_generic, &spr_write_generic,
2370 0x00000000);
2371 /* XXX : not implemented */
2372 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2373 SPR_NOACCESS, SPR_NOACCESS,
2374 &spr_read_generic, &spr_write_generic,
2375 0x00000000);
2376 }
2377
2378 static void gen_spr_8xx (CPUPPCState *env)
2379 {
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 /* XXX : not implemented */
2401 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_generic, &spr_write_generic,
2404 0x00000000);
2405 /* XXX : not implemented */
2406 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 0x00000000);
2410 /* XXX : not implemented */
2411 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2412 SPR_NOACCESS, SPR_NOACCESS,
2413 &spr_read_generic, &spr_write_generic,
2414 0x00000000);
2415 /* XXX : not implemented */
2416 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2417 SPR_NOACCESS, SPR_NOACCESS,
2418 &spr_read_generic, &spr_write_generic,
2419 0x00000000);
2420 /* XXX : not implemented */
2421 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 /* XXX : not implemented */
2426 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_generic,
2429 0x00000000);
2430 /* XXX : not implemented */
2431 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435 /* XXX : not implemented */
2436 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2437 SPR_NOACCESS, SPR_NOACCESS,
2438 &spr_read_generic, &spr_write_generic,
2439 0x00000000);
2440 /* XXX : not implemented */
2441 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2442 SPR_NOACCESS, SPR_NOACCESS,
2443 &spr_read_generic, &spr_write_generic,
2444 0x00000000);
2445 /* XXX : not implemented */
2446 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 0x00000000);
2450 /* XXX : not implemented */
2451 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2452 SPR_NOACCESS, SPR_NOACCESS,
2453 &spr_read_generic, &spr_write_generic,
2454 0x00000000);
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 /* XXX : not implemented */
2471 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2472 SPR_NOACCESS, SPR_NOACCESS,
2473 &spr_read_generic, &spr_write_generic,
2474 0x00000000);
2475 /* XXX : not implemented */
2476 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2477 SPR_NOACCESS, SPR_NOACCESS,
2478 &spr_read_generic, &spr_write_generic,
2479 0x00000000);
2480 /* XXX : not implemented */
2481 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2482 SPR_NOACCESS, SPR_NOACCESS,
2483 &spr_read_generic, &spr_write_generic,
2484 0x00000000);
2485 /* XXX : not implemented */
2486 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2487 SPR_NOACCESS, SPR_NOACCESS,
2488 &spr_read_generic, &spr_write_generic,
2489 0x00000000);
2490 /* XXX : not implemented */
2491 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2492 SPR_NOACCESS, SPR_NOACCESS,
2493 &spr_read_generic, &spr_write_generic,
2494 0x00000000);
2495 /* XXX : not implemented */
2496 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2497 SPR_NOACCESS, SPR_NOACCESS,
2498 &spr_read_generic, &spr_write_generic,
2499 0x00000000);
2500 /* XXX : not implemented */
2501 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2502 SPR_NOACCESS, SPR_NOACCESS,
2503 &spr_read_generic, &spr_write_generic,
2504 0x00000000);
2505 }
2506
2507 // XXX: TODO
2508 /*
2509 * AMR => SPR 29 (Power 2.04)
2510 * CTRL => SPR 136 (Power 2.04)
2511 * CTRL => SPR 152 (Power 2.04)
2512 * SCOMC => SPR 276 (64 bits ?)
2513 * SCOMD => SPR 277 (64 bits ?)
2514 * TBU40 => SPR 286 (Power 2.04 hypv)
2515 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2516 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2517 * HDSISR => SPR 306 (Power 2.04 hypv)
2518 * HDAR => SPR 307 (Power 2.04 hypv)
2519 * PURR => SPR 309 (Power 2.04 hypv)
2520 * HDEC => SPR 310 (Power 2.04 hypv)
2521 * HIOR => SPR 311 (hypv)
2522 * RMOR => SPR 312 (970)
2523 * HRMOR => SPR 313 (Power 2.04 hypv)
2524 * HSRR0 => SPR 314 (Power 2.04 hypv)
2525 * HSRR1 => SPR 315 (Power 2.04 hypv)
2526 * LPCR => SPR 316 (970)
2527 * LPIDR => SPR 317 (970)
2528 * SPEFSCR => SPR 512 (Power 2.04 emb)
2529 * EPR => SPR 702 (Power 2.04 emb)
2530 * perf => 768-783 (Power 2.04)
2531 * perf => 784-799 (Power 2.04)
2532 * PPR => SPR 896 (Power 2.04)
2533 * EPLC => SPR 947 (Power 2.04 emb)
2534 * EPSC => SPR 948 (Power 2.04 emb)
2535 * DABRX => 1015 (Power 2.04 hypv)
2536 * FPECR => SPR 1022 (?)
2537 * ... and more (thermal management, performance counters, ...)
2538 */
2539
2540 /*****************************************************************************/
2541 /* Exception vectors models */
2542 static void init_excp_4xx_real (CPUPPCState *env)
2543 {
2544 #if !defined(CONFIG_USER_ONLY)
2545 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2546 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2547 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2548 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2549 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2550 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2551 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2552 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2553 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2554 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2555 env->excp_prefix = 0x00000000UL;
2556 env->ivor_mask = 0x0000FFF0UL;
2557 env->ivpr_mask = 0xFFFF0000UL;
2558 /* Hardware reset vector */
2559 env->hreset_vector = 0xFFFFFFFCUL;
2560 #endif
2561 }
2562
2563 static void init_excp_4xx_softmmu (CPUPPCState *env)
2564 {
2565 #if !defined(CONFIG_USER_ONLY)
2566 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2567 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2568 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2569 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2570 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2571 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2572 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2573 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2574 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2575 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2576 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2577 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2578 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2579 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2580 env->excp_prefix = 0x00000000UL;
2581 env->ivor_mask = 0x0000FFF0UL;
2582 env->ivpr_mask = 0xFFFF0000UL;
2583 /* Hardware reset vector */
2584 env->hreset_vector = 0xFFFFFFFCUL;
2585 #endif
2586 }
2587
2588 static void init_excp_MPC5xx (CPUPPCState *env)
2589 {
2590 #if !defined(CONFIG_USER_ONLY)
2591 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2592 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2593 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2594 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2595 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2596 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2597 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2598 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2599 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2600 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2601 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2602 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2603 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2604 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2605 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2606 env->excp_prefix = 0x00000000UL;
2607 env->ivor_mask = 0x0000FFF0UL;
2608 env->ivpr_mask = 0xFFFF0000UL;
2609 /* Hardware reset vector */
2610 env->hreset_vector = 0xFFFFFFFCUL;
2611 #endif
2612 }
2613
2614 static void init_excp_MPC8xx (CPUPPCState *env)
2615 {
2616 #if !defined(CONFIG_USER_ONLY)
2617 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2618 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2619 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2620 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2621 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2622 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2623 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2624 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2625 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2626 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2627 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2628 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2629 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2630 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2631 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2632 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2633 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2634 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2635 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2636 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2637 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2638 env->excp_prefix = 0x00000000UL;
2639 env->ivor_mask = 0x0000FFF0UL;
2640 env->ivpr_mask = 0xFFFF0000UL;
2641 /* Hardware reset vector */
2642 env->hreset_vector = 0xFFFFFFFCUL;
2643 #endif
2644 }
2645
2646 static void init_excp_G2 (CPUPPCState *env)
2647 {
2648 #if !defined(CONFIG_USER_ONLY)
2649 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2650 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2651 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2652 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2653 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2654 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2655 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2656 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2657 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2658 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2659 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2660 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2661 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2662 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2663 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2664 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2665 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2666 env->excp_prefix = 0x00000000UL;
2667 /* Hardware reset vector */
2668 env->hreset_vector = 0xFFFFFFFCUL;
2669 #endif
2670 }
2671
2672 static void init_excp_e200 (CPUPPCState *env)
2673 {
2674 #if !defined(CONFIG_USER_ONLY)
2675 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2676 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2677 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2678 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2679 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2680 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2681 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2682 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2683 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2684 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2685 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2686 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2687 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2688 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2689 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2690 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2691 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2692 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2693 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2694 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2695 env->excp_prefix = 0x00000000UL;
2696 env->ivor_mask = 0x0000FFF7UL;
2697 env->ivpr_mask = 0xFFFF0000UL;
2698 /* Hardware reset vector */
2699 env->hreset_vector = 0xFFFFFFFCUL;
2700 #endif
2701 }
2702
2703 static void init_excp_BookE (CPUPPCState *env)
2704 {
2705 #if !defined(CONFIG_USER_ONLY)
2706 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2707 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2708 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2709 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2710 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2711 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2712 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2713 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2714 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2715 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2716 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2717 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2718 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2719 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2720 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2721 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2722 env->excp_prefix = 0x00000000UL;
2723 env->ivor_mask = 0x0000FFE0UL;
2724 env->ivpr_mask = 0xFFFF0000UL;
2725 /* Hardware reset vector */
2726 env->hreset_vector = 0xFFFFFFFCUL;
2727 #endif
2728 }
2729
2730 static void init_excp_601 (CPUPPCState *env)
2731 {
2732 #if !defined(CONFIG_USER_ONLY)
2733 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2734 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2735 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2736 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2737 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2738 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2739 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2740 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2741 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2742 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2743 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2744 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2745 env->excp_prefix = 0xFFF00000UL;
2746 /* Hardware reset vector */
2747 env->hreset_vector = 0x00000100UL;
2748 #endif
2749 }
2750
2751 static void init_excp_602 (CPUPPCState *env)
2752 {
2753 #if !defined(CONFIG_USER_ONLY)
2754 /* XXX: exception prefix has a special behavior on 602 */
2755 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2756 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2757 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2758 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2759 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2760 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2761 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2762 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2763 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2764 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2765 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2766 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2767 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2768 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2769 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2770 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2771 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2772 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2773 env->excp_prefix = 0xFFF00000UL;
2774 /* Hardware reset vector */
2775 env->hreset_vector = 0xFFFFFFFCUL;
2776 #endif
2777 }
2778
2779 static void init_excp_603 (CPUPPCState *env)
2780 {
2781 #if !defined(CONFIG_USER_ONLY)
2782 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2783 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2784 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2785 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2786 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2787 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2788 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2789 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2790 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2791 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2792 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2793 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2794 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2795 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2796 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2797 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2798 env->excp_prefix = 0x00000000UL;
2799 /* Hardware reset vector */
2800 env->hreset_vector = 0xFFFFFFFCUL;
2801 #endif
2802 }
2803
2804 static void init_excp_604 (CPUPPCState *env)
2805 {
2806 #if !defined(CONFIG_USER_ONLY)
2807 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2808 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2809 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2810 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2811 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2812 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2813 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2814 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2815 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2816 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2817 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2818 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2819 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2820 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2821 env->excp_prefix = 0x00000000UL;
2822 /* Hardware reset vector */
2823 env->hreset_vector = 0xFFFFFFFCUL;
2824 #endif
2825 }
2826
2827 #if defined(TARGET_PPC64)
2828 static void init_excp_620 (CPUPPCState *env)
2829 {
2830 #if !defined(CONFIG_USER_ONLY)
2831 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2832 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2833 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2834 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2835 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2836 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2837 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2838 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2839 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2840 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2841 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2842 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2843 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2844 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2845 env->excp_prefix = 0xFFF00000UL;
2846 /* Hardware reset vector */
2847 env->hreset_vector = 0x0000000000000100ULL;
2848 #endif
2849 }
2850 #endif /* defined(TARGET_PPC64) */
2851
2852 static void init_excp_7x0 (CPUPPCState *env)
2853 {
2854 #if !defined(CONFIG_USER_ONLY)
2855 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2856 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2857 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2858 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2859 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2860 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2861 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2862 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2863 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2864 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2865 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2866 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2867 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2868 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2869 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2870 env->excp_prefix = 0x00000000UL;
2871 /* Hardware reset vector */
2872 env->hreset_vector = 0xFFFFFFFCUL;
2873 #endif
2874 }
2875
2876 static void init_excp_750cl (CPUPPCState *env)
2877 {
2878 #if !defined(CONFIG_USER_ONLY)
2879 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2880 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2881 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2882 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2883 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2884 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2885 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2886 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2887 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2888 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2889 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2890 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2891 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2892 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2893 env->excp_prefix = 0x00000000UL;
2894 /* Hardware reset vector */
2895 env->hreset_vector = 0xFFFFFFFCUL;
2896 #endif
2897 }
2898
2899 static void init_excp_750cx (CPUPPCState *env)
2900 {
2901 #if !defined(CONFIG_USER_ONLY)
2902 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2903 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2904 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2905 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2906 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2907 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2908 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2909 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2910 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2911 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2912 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2913 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2914 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2915 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2916 env->excp_prefix = 0x00000000UL;
2917 /* Hardware reset vector */
2918 env->hreset_vector = 0xFFFFFFFCUL;
2919 #endif
2920 }
2921
2922 /* XXX: Check if this is correct */
2923 static void init_excp_7x5 (CPUPPCState *env)
2924 {
2925 #if !defined(CONFIG_USER_ONLY)
2926 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2927 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2928 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2929 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2930 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2931 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2932 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2933 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2934 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2935 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2936 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2937 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2938 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2939 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2940 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2941 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2942 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2943 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2944 env->excp_prefix = 0x00000000UL;
2945 /* Hardware reset vector */
2946 env->hreset_vector = 0xFFFFFFFCUL;
2947 #endif
2948 }
2949
2950 static void init_excp_7400 (CPUPPCState *env)
2951 {
2952 #if !defined(CONFIG_USER_ONLY)
2953 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2954 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2955 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2956 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2957 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2958 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2959 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2960 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2961 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2962 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2963 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2964 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2965 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2966 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2967 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2968 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2969 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2970 env->excp_prefix = 0x00000000UL;
2971 /* Hardware reset vector */
2972 env->hreset_vector = 0xFFFFFFFCUL;
2973 #endif
2974 }
2975
2976 static void init_excp_7450 (CPUPPCState *env)
2977 {
2978 #if !defined(CONFIG_USER_ONLY)
2979 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2980 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2981 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2982 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2983 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2984 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2985 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2986 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2987 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2988 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2989 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2990 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2991 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2992 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2993 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2994 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2995 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2996 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2997 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2998 env->excp_prefix = 0x00000000UL;
2999 /* Hardware reset vector */
3000 env->hreset_vector = 0xFFFFFFFCUL;
3001 #endif
3002 }
3003
3004 #if defined (TARGET_PPC64)
3005 static void init_excp_970 (CPUPPCState *env)
3006 {
3007 #if !defined(CONFIG_USER_ONLY)
3008 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3009 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3010 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3011 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3012 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3013 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3014 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3015 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3016 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3017 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3018 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3019 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3020 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3021 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3022 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3023 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3024 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3025 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3026 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3027 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3028 env->excp_prefix = 0x00000000FFF00000ULL;
3029 /* Hardware reset vector */
3030 env->hreset_vector = 0x0000000000000100ULL;
3031 #endif
3032 }
3033 #endif
3034
3035 /*****************************************************************************/
3036 /* Power management enable checks */
3037 static int check_pow_none (CPUPPCState *env)
3038 {
3039 return 0;
3040 }
3041
3042 static int check_pow_nocheck (CPUPPCState *env)
3043 {
3044 return 1;
3045 }
3046
3047 static int check_pow_hid0 (CPUPPCState *env)
3048 {
3049 if (env->spr[SPR_HID0] & 0x00E00000)
3050 return 1;
3051
3052 return 0;
3053 }
3054
3055 /*****************************************************************************/
3056 /* PowerPC implementations definitions */
3057
3058 /* PowerPC 401 */
3059 #define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING | \
3060 PPC_WRTEE | PPC_DCR | \
3061 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3062 PPC_CACHE_DCBZ | \
3063 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3064 PPC_4xx_COMMON | PPC_40x_EXCP)
3065 #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
3066 #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
3067 #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
3068 #define POWERPC_INPUT_401 (PPC_FLAGS_INPUT_401)
3069 #define POWERPC_BFDM_401 (bfd_mach_ppc_403)
3070 #define POWERPC_FLAG_401 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3071 POWERPC_FLAG_BUS_CLK)
3072 #define check_pow_401 check_pow_nocheck
3073
3074 static void init_proc_401 (CPUPPCState *env)
3075 {
3076 gen_spr_40x(env);
3077 gen_spr_401_403(env);
3078 gen_spr_401(env);
3079 init_excp_4xx_real(env);
3080 env->dcache_line_size = 32;
3081 env->icache_line_size = 32;
3082 /* Allocate hardware IRQ controller */
3083 ppc40x_irq_init(env);
3084 }
3085
3086 /* PowerPC 401x2 */
3087 #define POWERPC_INSNS_401x2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3088 PPC_DCR | PPC_WRTEE | \
3089 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3090 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3091 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3092 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3093 PPC_4xx_COMMON | PPC_40x_EXCP)
3094 #define POWERPC_MSRM_401x2 (0x00000000001FD231ULL)
3095 #define POWERPC_MMU_401x2 (POWERPC_MMU_SOFT_4xx_Z)
3096 #define POWERPC_EXCP_401x2 (POWERPC_EXCP_40x)
3097 #define POWERPC_INPUT_401x2 (PPC_FLAGS_INPUT_401)
3098 #define POWERPC_BFDM_401x2 (bfd_mach_ppc_403)
3099 #define POWERPC_FLAG_401x2 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3100 POWERPC_FLAG_BUS_CLK)
3101 #define check_pow_401x2 check_pow_nocheck
3102
3103 static void init_proc_401x2 (CPUPPCState *env)
3104 {
3105 gen_spr_40x(env);
3106 gen_spr_401_403(env);
3107 gen_spr_401x2(env);
3108 gen_spr_compress(env);
3109 /* Memory management */
3110 #if !defined(CONFIG_USER_ONLY)
3111 env->nb_tlb = 64;
3112 env->nb_ways = 1;
3113 env->id_tlbs = 0;
3114 #endif
3115 init_excp_4xx_softmmu(env);
3116 env->dcache_line_size = 32;
3117 env->icache_line_size = 32;
3118 /* Allocate hardware IRQ controller */
3119 ppc40x_irq_init(env);
3120 }
3121
3122 /* PowerPC 401x3 */
3123 #define POWERPC_INSNS_401x3 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3124 PPC_DCR | PPC_WRTEE | \
3125 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3126 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3127 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3128 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3129 PPC_4xx_COMMON | PPC_40x_EXCP)
3130 #define POWERPC_MSRM_401x3 (0x00000000001FD631ULL)
3131 #define POWERPC_MMU_401x3 (POWERPC_MMU_SOFT_4xx_Z)
3132 #define POWERPC_EXCP_401x3 (POWERPC_EXCP_40x)
3133 #define POWERPC_INPUT_401x3 (PPC_FLAGS_INPUT_401)
3134 #define POWERPC_BFDM_401x3 (bfd_mach_ppc_403)
3135 #define POWERPC_FLAG_401x3 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3136 POWERPC_FLAG_BUS_CLK)
3137 #define check_pow_401x3 check_pow_nocheck
3138
3139 __attribute__ (( unused ))
3140 static void init_proc_401x3 (CPUPPCState *env)
3141 {
3142 gen_spr_40x(env);
3143 gen_spr_401_403(env);
3144 gen_spr_401(env);
3145 gen_spr_401x2(env);
3146 gen_spr_compress(env);
3147 init_excp_4xx_softmmu(env);
3148 env->dcache_line_size = 32;
3149 env->icache_line_size = 32;
3150 /* Allocate hardware IRQ controller */
3151 ppc40x_irq_init(env);
3152 }
3153
3154 /* IOP480 */
3155 #define POWERPC_INSNS_IOP480 (PPC_INSNS_BASE | PPC_STRING | \
3156 PPC_DCR | PPC_WRTEE | \
3157 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3158 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3159 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3160 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3161 PPC_4xx_COMMON | PPC_40x_EXCP)
3162 #define POWERPC_MSRM_IOP480 (0x00000000001FD231ULL)
3163 #define POWERPC_MMU_IOP480 (POWERPC_MMU_SOFT_4xx_Z)
3164 #define POWERPC_EXCP_IOP480 (POWERPC_EXCP_40x)
3165 #define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
3166 #define POWERPC_BFDM_IOP480 (bfd_mach_ppc_403)
3167 #define POWERPC_FLAG_IOP480 (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \
3168 POWERPC_FLAG_BUS_CLK)
3169 #define check_pow_IOP480 check_pow_nocheck
3170
3171 static void init_proc_IOP480 (CPUPPCState *env)
3172 {
3173 gen_spr_40x(env);
3174 gen_spr_401_403(env);
3175 gen_spr_401x2(env);
3176 gen_spr_compress(env);
3177 /* Memory management */
3178 #if !defined(CONFIG_USER_ONLY)
3179 env->nb_tlb = 64;
3180 env->nb_ways = 1;
3181 env->id_tlbs = 0;
3182 #endif
3183 init_excp_4xx_softmmu(env);
3184 env->dcache_line_size = 32;
3185 env->icache_line_size = 32;
3186 /* Allocate hardware IRQ controller */
3187 ppc40x_irq_init(env);
3188 }
3189
3190 /* PowerPC 403 */
3191 #define POWERPC_INSNS_403 (PPC_INSNS_BASE | PPC_STRING | \
3192 PPC_DCR | PPC_WRTEE | \
3193 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3194 PPC_CACHE_DCBZ | \
3195 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3196 PPC_4xx_COMMON | PPC_40x_EXCP)
3197 #define POWERPC_MSRM_403 (0x000000000007D00DULL)
3198 #define POWERPC_MMU_403 (POWERPC_MMU_REAL)
3199 #define POWERPC_EXCP_403 (POWERPC_EXCP_40x)
3200 #define POWERPC_INPUT_403 (PPC_FLAGS_INPUT_401)
3201 #define POWERPC_BFDM_403 (bfd_mach_ppc_403)
3202 #define POWERPC_FLAG_403 (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3203 POWERPC_FLAG_BUS_CLK)
3204 #define check_pow_403 check_pow_nocheck
3205
3206 static void init_proc_403 (CPUPPCState *env)
3207 {
3208 gen_spr_40x(env);
3209 gen_spr_401_403(env);
3210 gen_spr_403(env);
3211 gen_spr_403_real(env);
3212 init_excp_4xx_real(env);
3213 env->dcache_line_size = 32;
3214 env->icache_line_size = 32;
3215 /* Allocate hardware IRQ controller */
3216 ppc40x_irq_init(env);
3217 }
3218
3219 /* PowerPC 403 GCX */
3220 #define POWERPC_INSNS_403GCX (PPC_INSNS_BASE | PPC_STRING | \
3221 PPC_DCR | PPC_WRTEE | \
3222 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3223 PPC_CACHE_DCBZ | \
3224 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3225 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3226 PPC_4xx_COMMON | PPC_40x_EXCP)
3227 #define POWERPC_MSRM_403GCX (0x000000000007D00DULL)
3228 #define POWERPC_MMU_403GCX (POWERPC_MMU_SOFT_4xx_Z)
3229 #define POWERPC_EXCP_403GCX (POWERPC_EXCP_40x)
3230 #define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
3231 #define POWERPC_BFDM_403GCX (bfd_mach_ppc_403)
3232 #define POWERPC_FLAG_403GCX (POWERPC_FLAG_CE | POWERPC_FLAG_PX | \
3233 POWERPC_FLAG_BUS_CLK)
3234 #define check_pow_403GCX check_pow_nocheck
3235
3236 static void init_proc_403GCX (CPUPPCState *env)
3237 {
3238 gen_spr_40x(env);
3239 gen_spr_401_403(env);
3240 gen_spr_403(env);
3241 gen_spr_403_real(env);
3242 gen_spr_403_mmu(env);
3243 /* Bus access control */
3244 /* not emulated, as Qemu never does speculative access */
3245 spr_register(env, SPR_40x_SGR, "SGR",
3246 SPR_NOACCESS, SPR_NOACCESS,
3247 &spr_read_generic, &spr_write_generic,
3248 0xFFFFFFFF);
3249 /* not emulated, as Qemu do not emulate caches */
3250 spr_register(env, SPR_40x_DCWR, "DCWR",
3251 SPR_NOACCESS, SPR_NOACCESS,
3252 &spr_read_generic, &spr_write_generic,
3253 0x00000000);
3254 /* Memory management */
3255 #if !defined(CONFIG_USER_ONLY)
3256 env->nb_tlb = 64;
3257 env->nb_ways = 1;
3258 env->id_tlbs = 0;
3259 #endif
3260 init_excp_4xx_softmmu(env);
3261 env->dcache_line_size = 32;
3262 env->icache_line_size = 32;
3263 /* Allocate hardware IRQ controller */
3264 ppc40x_irq_init(env);
3265 }
3266
3267 /* PowerPC 405 */
3268 #define POWERPC_INSNS_405 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3269 PPC_DCR | PPC_WRTEE | \
3270 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | \
3271 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3272 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3273 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
3274 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP)
3275 #define POWERPC_MSRM_405 (0x000000000006E630ULL)
3276 #define POWERPC_MMU_405 (POWERPC_MMU_SOFT_4xx)
3277 #define POWERPC_EXCP_405 (POWERPC_EXCP_40x)
3278 #define POWERPC_INPUT_405 (PPC_FLAGS_INPUT_405)
3279 #define POWERPC_BFDM_405 (bfd_mach_ppc_403)
3280 #define POWERPC_FLAG_405 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3281 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3282 #define check_pow_405 check_pow_nocheck
3283
3284 static void init_proc_405 (CPUPPCState *env)
3285 {
3286 /* Time base */
3287 gen_tbl(env);
3288 gen_spr_40x(env);
3289 gen_spr_405(env);
3290 /* Bus access control */
3291 /* not emulated, as Qemu never does speculative access */
3292 spr_register(env, SPR_40x_SGR, "SGR",
3293 SPR_NOACCESS, SPR_NOACCESS,
3294 &spr_read_generic, &spr_write_generic,
3295 0xFFFFFFFF);
3296 /* not emulated, as Qemu do not emulate caches */
3297 spr_register(env, SPR_40x_DCWR, "DCWR",
3298 SPR_NOACCESS, SPR_NOACCESS,
3299 &spr_read_generic, &spr_write_generic,
3300 0x00000000);
3301 /* Memory management */
3302 #if !defined(CONFIG_USER_ONLY)
3303 env->nb_tlb = 64;
3304 env->nb_ways = 1;
3305 env->id_tlbs = 0;
3306 #endif
3307 init_excp_4xx_softmmu(env);
3308 env->dcache_line_size = 32;
3309 env->icache_line_size = 32;
3310 /* Allocate hardware IRQ controller */
3311 ppc40x_irq_init(env);
3312 }
3313
3314 /* PowerPC 440 EP */
3315 #define POWERPC_INSNS_440EP (PPC_INSNS_BASE | PPC_STRING | \
3316 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3317 PPC_CACHE | PPC_CACHE_ICBI | \
3318 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3319 PPC_MEM_TLBSYNC | \
3320 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3321 PPC_440_SPEC)
3322 #define POWERPC_MSRM_440EP (0x000000000006D630ULL)
3323 #define POWERPC_MMU_440EP (POWERPC_MMU_BOOKE)
3324 #define POWERPC_EXCP_440EP (POWERPC_EXCP_BOOKE)
3325 #define POWERPC_INPUT_440EP (PPC_FLAGS_INPUT_BookE)
3326 #define POWERPC_BFDM_440EP (bfd_mach_ppc_403)
3327 #define POWERPC_FLAG_440EP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3328 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3329 #define check_pow_440EP check_pow_nocheck
3330
3331 __attribute__ (( unused ))
3332 static void init_proc_440EP (CPUPPCState *env)
3333 {
3334 /* Time base */
3335 gen_tbl(env);
3336 gen_spr_BookE(env, 0x000000000000FFFFULL);
3337 gen_spr_440(env);
3338 gen_spr_usprgh(env);
3339 /* Processor identification */
3340 spr_register(env, SPR_BOOKE_PIR, "PIR",
3341 SPR_NOACCESS, SPR_NOACCESS,
3342 &spr_read_generic, &spr_write_pir,
3343 0x00000000);
3344 /* XXX : not implemented */
3345 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3346 SPR_NOACCESS, SPR_NOACCESS,
3347 &spr_read_generic, &spr_write_generic,
3348 0x00000000);
3349 /* XXX : not implemented */
3350 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3351 SPR_NOACCESS, SPR_NOACCESS,
3352 &spr_read_generic, &spr_write_generic,
3353 0x00000000);
3354 /* XXX : not implemented */
3355 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3356 SPR_NOACCESS, SPR_NOACCESS,
3357 &spr_read_generic, &spr_write_generic,
3358 0x00000000);
3359 /* XXX : not implemented */
3360 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3361 SPR_NOACCESS, SPR_NOACCESS,
3362 &spr_read_generic, &spr_write_generic,
3363 0x00000000);
3364 /* XXX : not implemented */
3365 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3366 SPR_NOACCESS, SPR_NOACCESS,
3367 &spr_read_generic, &spr_write_generic,
3368 0x00000000);
3369 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3370 SPR_NOACCESS, SPR_NOACCESS,
3371 &spr_read_generic, &spr_write_generic,
3372 0x00000000);
3373 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3374 SPR_NOACCESS, SPR_NOACCESS,
3375 &spr_read_generic, &spr_write_generic,
3376 0x00000000);
3377 /* XXX : not implemented */
3378 spr_register(env, SPR_440_CCR1, "CCR1",
3379 SPR_NOACCESS, SPR_NOACCESS,
3380 &spr_read_generic, &spr_write_generic,
3381 0x00000000);
3382 /* Memory management */
3383 #if !defined(CONFIG_USER_ONLY)
3384 env->nb_tlb = 64;
3385 env->nb_ways = 1;
3386 env->id_tlbs = 0;
3387 #endif
3388 init_excp_BookE(env);
3389 env->dcache_line_size = 32;
3390 env->icache_line_size = 32;
3391 /* XXX: TODO: allocate internal IRQ controller */
3392 }
3393
3394 /* PowerPC 440 GP */
3395 #define POWERPC_INSNS_440GP (PPC_INSNS_BASE | PPC_STRING | \
3396 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | \
3397 PPC_CACHE | PPC_CACHE_ICBI | \
3398 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3399 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3400 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3401 PPC_440_SPEC)
3402 #define POWERPC_MSRM_440GP (0x000000000006FF30ULL)
3403 #define POWERPC_MMU_440GP (POWERPC_MMU_BOOKE)
3404 #define POWERPC_EXCP_440GP (POWERPC_EXCP_BOOKE)
3405 #define POWERPC_INPUT_440GP (PPC_FLAGS_INPUT_BookE)
3406 #define POWERPC_BFDM_440GP (bfd_mach_ppc_403)
3407 #define POWERPC_FLAG_440GP (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3408 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3409 #define check_pow_440GP check_pow_nocheck
3410
3411 __attribute__ (( unused ))
3412 static void init_proc_440GP (CPUPPCState *env)
3413 {
3414 /* Time base */
3415 gen_tbl(env);
3416 gen_spr_BookE(env, 0x000000000000FFFFULL);
3417 gen_spr_440(env);
3418 gen_spr_usprgh(env);
3419 /* Processor identification */
3420 spr_register(env, SPR_BOOKE_PIR, "PIR",
3421 SPR_NOACCESS, SPR_NOACCESS,
3422 &spr_read_generic, &spr_write_pir,
3423 0x00000000);
3424 /* XXX : not implemented */
3425 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3426 SPR_NOACCESS, SPR_NOACCESS,
3427 &spr_read_generic, &spr_write_generic,
3428 0x00000000);
3429 /* XXX : not implemented */
3430 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3431 SPR_NOACCESS, SPR_NOACCESS,
3432 &spr_read_generic, &spr_write_generic,
3433 0x00000000);
3434 /* XXX : not implemented */
3435 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3436 SPR_NOACCESS, SPR_NOACCESS,
3437 &spr_read_generic, &spr_write_generic,
3438 0x00000000);
3439 /* XXX : not implemented */
3440 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3441 SPR_NOACCESS, SPR_NOACCESS,
3442 &spr_read_generic, &spr_write_generic,
3443 0x00000000);
3444 /* Memory management */
3445 #if !defined(CONFIG_USER_ONLY)
3446 env->nb_tlb = 64;
3447 env->nb_ways = 1;
3448 env->id_tlbs = 0;
3449 #endif
3450 init_excp_BookE(env);
3451 env->dcache_line_size = 32;
3452 env->icache_line_size = 32;
3453 /* XXX: TODO: allocate internal IRQ controller */
3454 }
3455
3456 /* PowerPC 440x4 */
3457 #define POWERPC_INSNS_440x4 (PPC_INSNS_BASE | PPC_STRING | \
3458 PPC_DCR | PPC_WRTEE | \
3459 PPC_CACHE | PPC_CACHE_ICBI | \
3460 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3461 PPC_MEM_TLBSYNC | \
3462 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3463 PPC_440_SPEC)
3464 #define POWERPC_MSRM_440x4 (0x000000000006FF30ULL)
3465 #define POWERPC_MMU_440x4 (POWERPC_MMU_BOOKE)
3466 #define POWERPC_EXCP_440x4 (POWERPC_EXCP_BOOKE)
3467 #define POWERPC_INPUT_440x4 (PPC_FLAGS_INPUT_BookE)
3468 #define POWERPC_BFDM_440x4 (bfd_mach_ppc_403)
3469 #define POWERPC_FLAG_440x4 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3470 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3471 #define check_pow_440x4 check_pow_nocheck
3472
3473 __attribute__ (( unused ))
3474 static void init_proc_440x4 (CPUPPCState *env)
3475 {
3476 /* Time base */
3477 gen_tbl(env);
3478 gen_spr_BookE(env, 0x000000000000FFFFULL);
3479 gen_spr_440(env);
3480 gen_spr_usprgh(env);
3481 /* Processor identification */
3482 spr_register(env, SPR_BOOKE_PIR, "PIR",
3483 SPR_NOACCESS, SPR_NOACCESS,
3484 &spr_read_generic, &spr_write_pir,
3485 0x00000000);
3486 /* XXX : not implemented */
3487 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3488 SPR_NOACCESS, SPR_NOACCESS,
3489 &spr_read_generic, &spr_write_generic,
3490 0x00000000);
3491 /* XXX : not implemented */
3492 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3493 SPR_NOACCESS, SPR_NOACCESS,
3494 &spr_read_generic, &spr_write_generic,
3495 0x00000000);
3496 /* XXX : not implemented */
3497 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3498 SPR_NOACCESS, SPR_NOACCESS,
3499 &spr_read_generic, &spr_write_generic,
3500 0x00000000);
3501 /* XXX : not implemented */
3502 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3503 SPR_NOACCESS, SPR_NOACCESS,
3504 &spr_read_generic, &spr_write_generic,
3505 0x00000000);
3506 /* Memory management */
3507 #if !defined(CONFIG_USER_ONLY)
3508 env->nb_tlb = 64;
3509 env->nb_ways = 1;
3510 env->id_tlbs = 0;
3511 #endif
3512 init_excp_BookE(env);
3513 env->dcache_line_size = 32;
3514 env->icache_line_size = 32;
3515 /* XXX: TODO: allocate internal IRQ controller */
3516 }
3517
3518 /* PowerPC 440x5 */
3519 #define POWERPC_INSNS_440x5 (PPC_INSNS_BASE | PPC_STRING | \
3520 PPC_DCR | PPC_WRTEE | PPC_RFMCI | \
3521 PPC_CACHE | PPC_CACHE_ICBI | \
3522 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3523 PPC_MEM_TLBSYNC | \
3524 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3525 PPC_440_SPEC)
3526 #define POWERPC_MSRM_440x5 (0x000000000006FF30ULL)
3527 #define POWERPC_MMU_440x5 (POWERPC_MMU_BOOKE)
3528 #define POWERPC_EXCP_440x5 (POWERPC_EXCP_BOOKE)
3529 #define POWERPC_INPUT_440x5 (PPC_FLAGS_INPUT_BookE)
3530 #define POWERPC_BFDM_440x5 (bfd_mach_ppc_403)
3531 #define POWERPC_FLAG_440x5 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3532 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3533 #define check_pow_440x5 check_pow_nocheck
3534
3535 __attribute__ (( unused ))
3536 static void init_proc_440x5 (CPUPPCState *env)
3537 {
3538 /* Time base */
3539 gen_tbl(env);
3540 gen_spr_BookE(env, 0x000000000000FFFFULL);
3541 gen_spr_440(env);
3542 gen_spr_usprgh(env);
3543 /* Processor identification */
3544 spr_register(env, SPR_BOOKE_PIR, "PIR",
3545 SPR_NOACCESS, SPR_NOACCESS,
3546 &spr_read_generic, &spr_write_pir,
3547 0x00000000);
3548 /* XXX : not implemented */
3549 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3550 SPR_NOACCESS, SPR_NOACCESS,
3551 &spr_read_generic, &spr_write_generic,
3552 0x00000000);
3553 /* XXX : not implemented */
3554 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3555 SPR_NOACCESS, SPR_NOACCESS,
3556 &spr_read_generic, &spr_write_generic,
3557 0x00000000);
3558 /* XXX : not implemented */
3559 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3560 SPR_NOACCESS, SPR_NOACCESS,
3561 &spr_read_generic, &spr_write_generic,
3562 0x00000000);
3563 /* XXX : not implemented */
3564 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3565 SPR_NOACCESS, SPR_NOACCESS,
3566 &spr_read_generic, &spr_write_generic,
3567 0x00000000);
3568 /* XXX : not implemented */
3569 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3570 SPR_NOACCESS, SPR_NOACCESS,
3571 &spr_read_generic, &spr_write_generic,
3572 0x00000000);
3573 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3574 SPR_NOACCESS, SPR_NOACCESS,
3575 &spr_read_generic, &spr_write_generic,
3576 0x00000000);
3577 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3578 SPR_NOACCESS, SPR_NOACCESS,
3579 &spr_read_generic, &spr_write_generic,
3580 0x00000000);
3581 /* XXX : not implemented */
3582 spr_register(env, SPR_440_CCR1, "CCR1",
3583 SPR_NOACCESS, SPR_NOACCESS,
3584 &spr_read_generic, &spr_write_generic,
3585 0x00000000);
3586 /* Memory management */
3587 #if !defined(CONFIG_USER_ONLY)
3588 env->nb_tlb = 64;
3589 env->nb_ways = 1;
3590 env->id_tlbs = 0;
3591 #endif
3592 init_excp_BookE(env);
3593 env->dcache_line_size = 32;
3594 env->icache_line_size = 32;
3595 /* XXX: TODO: allocate internal IRQ controller */
3596 }
3597
3598 /* PowerPC 460 (guessed) */
3599 #define POWERPC_INSNS_460 (PPC_INSNS_BASE | PPC_STRING | \
3600 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3601 PPC_WRTEE | PPC_MFAPIDI | \
3602 PPC_CACHE | PPC_CACHE_ICBI | \
3603 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3604 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3605 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3606 PPC_440_SPEC)
3607 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3608 #define POWERPC_MMU_460 (POWERPC_MMU_BOOKE)
3609 #define POWERPC_EXCP_460 (POWERPC_EXCP_BOOKE)
3610 #define POWERPC_INPUT_460 (PPC_FLAGS_INPUT_BookE)
3611 #define POWERPC_BFDM_460 (bfd_mach_ppc_403)
3612 #define POWERPC_FLAG_460 (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3613 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3614 #define check_pow_460 check_pow_nocheck
3615
3616 __attribute__ (( unused ))
3617 static void init_proc_460 (CPUPPCState *env)
3618 {
3619 /* Time base */
3620 gen_tbl(env);
3621 gen_spr_BookE(env, 0x000000000000FFFFULL);
3622 gen_spr_440(env);
3623 gen_spr_usprgh(env);
3624 /* Processor identification */
3625 spr_register(env, SPR_BOOKE_PIR, "PIR",
3626 SPR_NOACCESS, SPR_NOACCESS,
3627 &spr_read_generic, &spr_write_pir,
3628 0x00000000);
3629 /* XXX : not implemented */
3630 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3631 SPR_NOACCESS, SPR_NOACCESS,
3632 &spr_read_generic, &spr_write_generic,
3633 0x00000000);
3634 /* XXX : not implemented */
3635 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3636 SPR_NOACCESS, SPR_NOACCESS,
3637 &spr_read_generic, &spr_write_generic,
3638 0x00000000);
3639 /* XXX : not implemented */
3640 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3641 SPR_NOACCESS, SPR_NOACCESS,
3642 &spr_read_generic, &spr_write_generic,
3643 0x00000000);
3644 /* XXX : not implemented */
3645 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3646 SPR_NOACCESS, SPR_NOACCESS,
3647 &spr_read_generic, &spr_write_generic,
3648 0x00000000);
3649 /* XXX : not implemented */
3650 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3651 SPR_NOACCESS, SPR_NOACCESS,
3652 &spr_read_generic, &spr_write_generic,
3653 0x00000000);
3654 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3655 SPR_NOACCESS, SPR_NOACCESS,
3656 &spr_read_generic, &spr_write_generic,
3657 0x00000000);
3658 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3659 SPR_NOACCESS, SPR_NOACCESS,
3660 &spr_read_generic, &spr_write_generic,
3661 0x00000000);
3662 /* XXX : not implemented */
3663 spr_register(env, SPR_440_CCR1, "CCR1",
3664 SPR_NOACCESS, SPR_NOACCESS,
3665 &spr_read_generic, &spr_write_generic,
3666 0x00000000);
3667 /* XXX : not implemented */
3668 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3669 &spr_read_generic, &spr_write_generic,
3670 &spr_read_generic, &spr_write_generic,
3671 0x00000000);
3672 /* Memory management */
3673 #if !defined(CONFIG_USER_ONLY)
3674 env->nb_tlb = 64;
3675 env->nb_ways = 1;
3676 env->id_tlbs = 0;
3677 #endif
3678 init_excp_BookE(env);
3679 env->dcache_line_size = 32;
3680 env->icache_line_size = 32;
3681 /* XXX: TODO: allocate internal IRQ controller */
3682 }
3683
3684 /* PowerPC 460F (guessed) */
3685 #define POWERPC_INSNS_460F (PPC_INSNS_BASE | PPC_STRING | \
3686 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | \
3687 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
3688 PPC_FLOAT_STFIWX | \
3689 PPC_DCR | PPC_DCRX | PPC_DCRUX | \
3690 PPC_WRTEE | PPC_MFAPIDI | \
3691 PPC_CACHE | PPC_CACHE_ICBI | \
3692 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3693 PPC_MEM_TLBSYNC | PPC_TLBIVA | \
3694 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | \
3695 PPC_440_SPEC)
3696 #define POWERPC_MSRM_460 (0x000000000006FF30ULL)
3697 #define POWERPC_MMU_460F (POWERPC_MMU_BOOKE)
3698 #define POWERPC_EXCP_460F (POWERPC_EXCP_BOOKE)
3699 #define POWERPC_INPUT_460F (PPC_FLAGS_INPUT_BookE)
3700 #define POWERPC_BFDM_460F (bfd_mach_ppc_403)
3701 #define POWERPC_FLAG_460F (POWERPC_FLAG_CE | POWERPC_FLAG_DWE | \
3702 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK)
3703 #define check_pow_460F check_pow_nocheck
3704
3705 __attribute__ (( unused ))
3706 static void init_proc_460F (CPUPPCState *env)
3707 {
3708 /* Time base */
3709 gen_tbl(env);
3710 gen_spr_BookE(env, 0x000000000000FFFFULL);
3711 gen_spr_440(env);
3712 gen_spr_usprgh(env);
3713 /* Processor identification */
3714 spr_register(env, SPR_BOOKE_PIR, "PIR",
3715 SPR_NOACCESS, SPR_NOACCESS,
3716 &spr_read_generic, &spr_write_pir,
3717 0x00000000);
3718 /* XXX : not implemented */
3719 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
3723 /* XXX : not implemented */
3724 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_generic,
3727 0x00000000);
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 /* XXX : not implemented */
3734 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3735 SPR_NOACCESS, SPR_NOACCESS,
3736 &spr_read_generic, &spr_write_generic,
3737 0x00000000);
3738 /* XXX : not implemented */
3739 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3740 SPR_NOACCESS, SPR_NOACCESS,
3741 &spr_read_generic, &spr_write_generic,
3742 0x00000000);
3743 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3744 SPR_NOACCESS, SPR_NOACCESS,
3745 &spr_read_generic, &spr_write_generic,
3746 0x00000000);
3747 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3748 SPR_NOACCESS, SPR_NOACCESS,
3749 &spr_read_generic, &spr_write_generic,
3750 0x00000000);
3751 /* XXX : not implemented */
3752 spr_register(env, SPR_440_CCR1, "CCR1",
3753 SPR_NOACCESS, SPR_NOACCESS,
3754 &spr_read_generic, &spr_write_generic,
3755 0x00000000);
3756 /* XXX : not implemented */
3757 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3758 &spr_read_generic, &spr_write_generic,
3759 &spr_read_generic, &spr_write_generic,
3760 0x00000000);
3761 /* Memory management */
3762 #if !defined(CONFIG_USER_ONLY)
3763 env->nb_tlb = 64;
3764 env->nb_ways = 1;
3765 env->id_tlbs = 0;
3766 #endif
3767 init_excp_BookE(env);
3768 env->dcache_line_size = 32;
3769 env->icache_line_size = 32;
3770 /* XXX: TODO: allocate internal IRQ controller */
3771 }
3772
3773 /* Freescale 5xx cores (aka RCPU) */
3774 #define POWERPC_INSNS_MPC5xx (PPC_INSNS_BASE | PPC_STRING | \
3775 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3776 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | \
3777 PPC_MFTB)
3778 #define POWERPC_MSRM_MPC5xx (0x000000000001FF43ULL)
3779 #define POWERPC_MMU_MPC5xx (POWERPC_MMU_REAL)
3780 #define POWERPC_EXCP_MPC5xx (POWERPC_EXCP_603)
3781 #define POWERPC_INPUT_MPC5xx (PPC_FLAGS_INPUT_RCPU)
3782 #define POWERPC_BFDM_MPC5xx (bfd_mach_ppc_505)
3783 #define POWERPC_FLAG_MPC5xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3784 POWERPC_FLAG_BUS_CLK)
3785 #define check_pow_MPC5xx check_pow_none
3786
3787 __attribute__ (( unused ))
3788 static void init_proc_MPC5xx (CPUPPCState *env)
3789 {
3790 /* Time base */
3791 gen_tbl(env);
3792 gen_spr_5xx_8xx(env);
3793 gen_spr_5xx(env);
3794 init_excp_MPC5xx(env);
3795 env->dcache_line_size = 32;
3796 env->icache_line_size = 32;
3797 /* XXX: TODO: allocate internal IRQ controller */
3798 }
3799
3800 /* Freescale 8xx cores (aka PowerQUICC) */
3801 #define POWERPC_INSNS_MPC8xx (PPC_INSNS_BASE | PPC_STRING | \
3802 PPC_MEM_EIEIO | PPC_MEM_SYNC | \
3803 PPC_CACHE_ICBI | PPC_MFTB)
3804 #define POWERPC_MSRM_MPC8xx (0x000000000001F673ULL)
3805 #define POWERPC_MMU_MPC8xx (POWERPC_MMU_MPC8xx)
3806 #define POWERPC_EXCP_MPC8xx (POWERPC_EXCP_603)
3807 #define POWERPC_INPUT_MPC8xx (PPC_FLAGS_INPUT_RCPU)
3808 #define POWERPC_BFDM_MPC8xx (bfd_mach_ppc_860)
3809 #define POWERPC_FLAG_MPC8xx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
3810 POWERPC_FLAG_BUS_CLK)
3811 #define check_pow_MPC8xx check_pow_none
3812
3813 __attribute__ (( unused ))
3814 static void init_proc_MPC8xx (CPUPPCState *env)
3815 {
3816 /* Time base */
3817 gen_tbl(env);
3818 gen_spr_5xx_8xx(env);
3819 gen_spr_8xx(env);
3820 init_excp_MPC8xx(env);
3821 env->dcache_line_size = 32;
3822 env->icache_line_size = 32;
3823 /* XXX: TODO: allocate internal IRQ controller */
3824 }
3825
3826 /* Freescale 82xx cores (aka PowerQUICC-II) */
3827 /* PowerPC G2 */
3828 #define POWERPC_INSNS_G2 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3829 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3830 PPC_FLOAT_STFIWX | \
3831 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3832 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3833 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3834 PPC_SEGMENT | PPC_EXTERN)
3835 #define POWERPC_MSRM_G2 (0x000000000006FFF2ULL)
3836 #define POWERPC_MMU_G2 (POWERPC_MMU_SOFT_6xx)
3837 //#define POWERPC_EXCP_G2 (POWERPC_EXCP_G2)
3838 #define POWERPC_INPUT_G2 (PPC_FLAGS_INPUT_6xx)
3839 #define POWERPC_BFDM_G2 (bfd_mach_ppc_ec603e)
3840 #define POWERPC_FLAG_G2 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3841 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3842 #define check_pow_G2 check_pow_hid0
3843
3844 static void init_proc_G2 (CPUPPCState *env)
3845 {
3846 gen_spr_ne_601(env);
3847 gen_spr_G2_755(env);
3848 gen_spr_G2(env);
3849 /* Time base */
3850 gen_tbl(env);
3851 /* External access control */
3852 /* XXX : not implemented */
3853 spr_register(env, SPR_EAR, "EAR",
3854 SPR_NOACCESS, SPR_NOACCESS,
3855 &spr_read_generic, &spr_write_generic,
3856 0x00000000);
3857 /* Hardware implementation register */
3858 /* XXX : not implemented */
3859 spr_register(env, SPR_HID0, "HID0",
3860 SPR_NOACCESS, SPR_NOACCESS,
3861 &spr_read_generic, &spr_write_generic,
3862 0x00000000);
3863 /* XXX : not implemented */
3864 spr_register(env, SPR_HID1, "HID1",
3865 SPR_NOACCESS, SPR_NOACCESS,
3866 &spr_read_generic, &spr_write_generic,
3867 0x00000000);
3868 /* XXX : not implemented */
3869 spr_register(env, SPR_HID2, "HID2",
3870 SPR_NOACCESS, SPR_NOACCESS,
3871 &spr_read_generic, &spr_write_generic,
3872 0x00000000);
3873 /* Memory management */
3874 gen_low_BATs(env);
3875 gen_high_BATs(env);
3876 gen_6xx_7xx_soft_tlb(env, 64, 2);
3877 init_excp_G2(env);
3878 env->dcache_line_size = 32;
3879 env->icache_line_size = 32;
3880 /* Allocate hardware IRQ controller */
3881 ppc6xx_irq_init(env);
3882 }
3883
3884 /* PowerPC G2LE */
3885 #define POWERPC_INSNS_G2LE (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
3886 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
3887 PPC_FLOAT_STFIWX | \
3888 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
3889 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
3890 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
3891 PPC_SEGMENT | PPC_EXTERN)
3892 #define POWERPC_MSRM_G2LE (0x000000000007FFF3ULL)
3893 #define POWERPC_MMU_G2LE (POWERPC_MMU_SOFT_6xx)
3894 #define POWERPC_EXCP_G2LE (POWERPC_EXCP_G2)
3895 #define POWERPC_INPUT_G2LE (PPC_FLAGS_INPUT_6xx)
3896 #define POWERPC_BFDM_G2LE (bfd_mach_ppc_ec603e)
3897 #define POWERPC_FLAG_G2LE (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
3898 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
3899 #define check_pow_G2LE check_pow_hid0
3900
3901 static void init_proc_G2LE (CPUPPCState *env)
3902 {
3903 gen_spr_ne_601(env);
3904 gen_spr_G2_755(env);
3905 gen_spr_G2(env);
3906 /* Time base */
3907 gen_tbl(env);
3908 /* External access control */
3909 /* XXX : not implemented */
3910 spr_register(env, SPR_EAR, "EAR",
3911 SPR_NOACCESS, SPR_NOACCESS,
3912 &spr_read_generic, &spr_write_generic,
3913 0x00000000);
3914 /* Hardware implementation register */
3915 /* XXX : not implemented */
3916 spr_register(env, SPR_HID0, "HID0",
3917 SPR_NOACCESS, SPR_NOACCESS,
3918 &spr_read_generic, &spr_write_generic,
3919 0x00000000);
3920 /* XXX : not implemented */
3921 spr_register(env, SPR_HID1, "HID1",
3922 SPR_NOACCESS, SPR_NOACCESS,
3923 &spr_read_generic, &spr_write_generic,
3924 0x00000000);
3925 /* XXX : not implemented */
3926 spr_register(env, SPR_HID2, "HID2",
3927 SPR_NOACCESS, SPR_NOACCESS,
3928 &spr_read_generic, &spr_write_generic,
3929 0x00000000);
3930 /* Memory management */
3931 gen_low_BATs(env);
3932 gen_high_BATs(env);
3933 gen_6xx_7xx_soft_tlb(env, 64, 2);
3934 init_excp_G2(env);
3935 env->dcache_line_size = 32;
3936 env->icache_line_size = 32;
3937 /* Allocate hardware IRQ controller */
3938 ppc6xx_irq_init(env);
3939 }
3940
3941 /* e200 core */
3942 /* XXX: unimplemented instructions:
3943 * dcblc
3944 * dcbtlst
3945 * dcbtstls
3946 * icblc
3947 * icbtls
3948 * tlbivax
3949 * all SPE multiply-accumulate instructions
3950 */
3951 #define POWERPC_INSNS_e200 (PPC_INSNS_BASE | PPC_ISEL | \
3952 PPC_SPE | PPC_SPEFPU | \
3953 PPC_WRTEE | PPC_RFDI | \
3954 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
3955 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
3956 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
3957 PPC_BOOKE)
3958 #define POWERPC_MSRM_e200 (0x000000000606FF30ULL)
3959 #define POWERPC_MMU_e200 (POWERPC_MMU_BOOKE_FSL)
3960 #define POWERPC_EXCP_e200 (POWERPC_EXCP_BOOKE)
3961 #define POWERPC_INPUT_e200 (PPC_FLAGS_INPUT_BookE)
3962 #define POWERPC_BFDM_e200 (bfd_mach_ppc_860)
3963 #define POWERPC_FLAG_e200 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
3964 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
3965 POWERPC_FLAG_BUS_CLK)
3966 #define check_pow_e200 check_pow_hid0
3967
3968 __attribute__ (( unused ))
3969 static void init_proc_e200 (CPUPPCState *env)
3970 {
3971 /* Time base */
3972 gen_tbl(env);
3973 gen_spr_BookE(env, 0x000000070000FFFFULL);
3974 /* XXX : not implemented */
3975 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
3976 SPR_NOACCESS, SPR_NOACCESS,
3977 &spr_read_generic, &spr_write_generic,
3978 0x00000000);
3979 /* Memory management */
3980 gen_spr_BookE_FSL(env, 0x0000005D);
3981 /* XXX : not implemented */
3982 spr_register(env, SPR_HID0, "HID0",
3983 SPR_NOACCESS, SPR_NOACCESS,
3984 &spr_read_generic, &spr_write_generic,
3985 0x00000000);
3986 /* XXX : not implemented */
3987 spr_register(env, SPR_HID1, "HID1",
3988 SPR_NOACCESS, SPR_NOACCESS,
3989 &spr_read_generic, &spr_write_generic,
3990 0x00000000);
3991 /* XXX : not implemented */
3992 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
3993 SPR_NOACCESS, SPR_NOACCESS,
3994 &spr_read_generic, &spr_write_generic,
3995 0x00000000);
3996 /* XXX : not implemented */
3997 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
3998 SPR_NOACCESS, SPR_NOACCESS,
3999 &spr_read_generic, &spr_write_generic,
4000 0x00000000);
4001 /* XXX : not implemented */
4002 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4003 SPR_NOACCESS, SPR_NOACCESS,
4004 &spr_read_generic, &spr_write_generic,
4005 0x00000000);
4006 /* XXX : not implemented */
4007 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4008 SPR_NOACCESS, SPR_NOACCESS,
4009 &spr_read_generic, &spr_write_generic,
4010 0x00000000);
4011 /* XXX : not implemented */
4012 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4013 SPR_NOACCESS, SPR_NOACCESS,
4014 &spr_read_generic, &spr_write_generic,
4015 0x00000000);
4016 /* XXX : not implemented */
4017 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4018 SPR_NOACCESS, SPR_NOACCESS,
4019 &spr_read_generic, &spr_write_generic,
4020 0x00000000);
4021 /* XXX : not implemented */
4022 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4023 SPR_NOACCESS, SPR_NOACCESS,
4024 &spr_read_generic, &spr_write_generic,
4025 0x00000000);
4026 /* XXX : not implemented */
4027 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4028 SPR_NOACCESS, SPR_NOACCESS,
4029 &spr_read_generic, &spr_write_generic,
4030 0x00000000);
4031 /* XXX : not implemented */
4032 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4033 SPR_NOACCESS, SPR_NOACCESS,
4034 &spr_read_generic, &spr_write_generic,
4035 0x00000000);
4036 /* XXX : not implemented */
4037 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4038 SPR_NOACCESS, SPR_NOACCESS,
4039 &spr_read_generic, &spr_write_generic,
4040 0x00000000);
4041 /* XXX : not implemented */
4042 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4043 SPR_NOACCESS, SPR_NOACCESS,
4044 &spr_read_generic, &spr_write_generic,
4045 0x00000000);
4046 /* XXX : not implemented */
4047 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4048 SPR_NOACCESS, SPR_NOACCESS,
4049 &spr_read_generic, &spr_write_generic,
4050 0x00000000);
4051 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4052 SPR_NOACCESS, SPR_NOACCESS,
4053 &spr_read_generic, &spr_write_generic,
4054 0x00000000);
4055 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4056 SPR_NOACCESS, SPR_NOACCESS,
4057 &spr_read_generic, &spr_write_generic,
4058 0x00000000);
4059 #if !defined(CONFIG_USER_ONLY)
4060 env->nb_tlb = 64;
4061 env->nb_ways = 1;
4062 env->id_tlbs = 0;
4063 #endif
4064 init_excp_e200(env);
4065 env->dcache_line_size = 32;
4066 env->icache_line_size = 32;
4067 /* XXX: TODO: allocate internal IRQ controller */
4068 }
4069
4070 /* e300 core */
4071 #define POWERPC_INSNS_e300 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4072 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4073 PPC_FLOAT_STFIWX | \
4074 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4075 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4076 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4077 PPC_SEGMENT | PPC_EXTERN)
4078 #define POWERPC_MSRM_e300 (0x000000000007FFF3ULL)
4079 #define POWERPC_MMU_e300 (POWERPC_MMU_SOFT_6xx)
4080 #define POWERPC_EXCP_e300 (POWERPC_EXCP_603)
4081 #define POWERPC_INPUT_e300 (PPC_FLAGS_INPUT_6xx)
4082 #define POWERPC_BFDM_e300 (bfd_mach_ppc_603)
4083 #define POWERPC_FLAG_e300 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4084 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4085 #define check_pow_e300 check_pow_hid0
4086
4087 __attribute__ (( unused ))
4088 static void init_proc_e300 (CPUPPCState *env)
4089 {
4090 gen_spr_ne_601(env);
4091 gen_spr_603(env);
4092 /* Time base */
4093 gen_tbl(env);
4094 /* hardware implementation registers */
4095 /* XXX : not implemented */
4096 spr_register(env, SPR_HID0, "HID0",
4097 SPR_NOACCESS, SPR_NOACCESS,
4098 &spr_read_generic, &spr_write_generic,
4099 0x00000000);
4100 /* XXX : not implemented */
4101 spr_register(env, SPR_HID1, "HID1",
4102 SPR_NOACCESS, SPR_NOACCESS,
4103 &spr_read_generic, &spr_write_generic,
4104 0x00000000);
4105 /* Memory management */
4106 gen_low_BATs(env);
4107 gen_6xx_7xx_soft_tlb(env, 64, 2);
4108 init_excp_603(env);
4109 env->dcache_line_size = 32;
4110 env->icache_line_size = 32;
4111 /* Allocate hardware IRQ controller */
4112 ppc6xx_irq_init(env);
4113 }
4114
4115 /* e500 core */
4116 #define POWERPC_INSNS_e500 (PPC_INSNS_BASE | PPC_ISEL | \
4117 PPC_SPE | PPC_SPEFPU | \
4118 PPC_WRTEE | PPC_RFDI | \
4119 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \
4120 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \
4121 PPC_MEM_TLBSYNC | PPC_TLBIVAX | \
4122 PPC_BOOKE)
4123 #define POWERPC_MSRM_e500 (0x000000000606FF30ULL)
4124 #define POWERPC_MMU_e500 (POWERPC_MMU_BOOKE_FSL)
4125 #define POWERPC_EXCP_e500 (POWERPC_EXCP_BOOKE)
4126 #define POWERPC_INPUT_e500 (PPC_FLAGS_INPUT_BookE)
4127 #define POWERPC_BFDM_e500 (bfd_mach_ppc_860)
4128 #define POWERPC_FLAG_e500 (POWERPC_FLAG_SPE | POWERPC_FLAG_CE | \
4129 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | \
4130 POWERPC_FLAG_BUS_CLK)
4131 #define check_pow_e500 check_pow_hid0
4132
4133 __attribute__ (( unused ))
4134 static void init_proc_e500 (CPUPPCState *env)
4135 {
4136 /* Time base */
4137 gen_tbl(env);
4138 gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4139 /* Processor identification */
4140 spr_register(env, SPR_BOOKE_PIR, "PIR",
4141 SPR_NOACCESS, SPR_NOACCESS,
4142 &spr_read_generic, &spr_write_pir,
4143 0x00000000);
4144 /* XXX : not implemented */
4145 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4146 SPR_NOACCESS, SPR_NOACCESS,
4147 &spr_read_generic, &spr_write_generic,
4148 0x00000000);
4149 /* Memory management */
4150 #if !defined(CONFIG_USER_ONLY)
4151 env->nb_pids = 3;
4152 #endif
4153 gen_spr_BookE_FSL(env, 0x0000005F);
4154 /* XXX : not implemented */
4155 spr_register(env, SPR_HID0, "HID0",
4156 SPR_NOACCESS, SPR_NOACCESS,
4157 &spr_read_generic, &spr_write_generic,
4158 0x00000000);
4159 /* XXX : not implemented */
4160 spr_register(env, SPR_HID1, "HID1",
4161 SPR_NOACCESS, SPR_NOACCESS,
4162 &spr_read_generic, &spr_write_generic,
4163 0x00000000);
4164 /* XXX : not implemented */
4165 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4166 SPR_NOACCESS, SPR_NOACCESS,
4167 &spr_read_generic, &spr_write_generic,
4168 0x00000000);
4169 /* XXX : not implemented */
4170 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4171 SPR_NOACCESS, SPR_NOACCESS,
4172 &spr_read_generic, &spr_write_generic,
4173 0x00000000);
4174 /* XXX : not implemented */
4175 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4176 SPR_NOACCESS, SPR_NOACCESS,
4177 &spr_read_generic, &spr_write_generic,
4178 0x00000000);
4179 /* XXX : not implemented */
4180 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4181 SPR_NOACCESS, SPR_NOACCESS,
4182 &spr_read_generic, &spr_write_generic,
4183 0x00000000);
4184 /* XXX : not implemented */
4185 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4186 SPR_NOACCESS, SPR_NOACCESS,
4187 &spr_read_generic, &spr_write_generic,
4188 0x00000000);
4189 /* XXX : not implemented */
4190 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4191 SPR_NOACCESS, SPR_NOACCESS,
4192 &spr_read_generic, &spr_write_generic,
4193 0x00000000);
4194 /* XXX : not implemented */
4195 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4196 SPR_NOACCESS, SPR_NOACCESS,
4197 &spr_read_generic, &spr_write_generic,
4198 0x00000000);
4199 /* XXX : not implemented */
4200 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4201 SPR_NOACCESS, SPR_NOACCESS,
4202 &spr_read_generic, &spr_write_generic,
4203 0x00000000);
4204 /* XXX : not implemented */
4205 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4206 SPR_NOACCESS, SPR_NOACCESS,
4207 &spr_read_generic, &spr_write_generic,
4208 0x00000000);
4209 /* XXX : not implemented */
4210 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4211 SPR_NOACCESS, SPR_NOACCESS,
4212 &spr_read_generic, &spr_write_generic,
4213 0x00000000);
4214 /* XXX : not implemented */
4215 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4216 SPR_NOACCESS, SPR_NOACCESS,
4217 &spr_read_generic, &spr_write_generic,
4218 0x00000000);
4219 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4220 SPR_NOACCESS, SPR_NOACCESS,
4221 &spr_read_generic, &spr_write_generic,
4222 0x00000000);
4223 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4224 SPR_NOACCESS, SPR_NOACCESS,
4225 &spr_read_generic, &spr_write_generic,
4226 0x00000000);
4227 #if !defined(CONFIG_USER_ONLY)
4228 env->nb_tlb = 64;
4229 env->nb_ways = 1;
4230 env->id_tlbs = 0;
4231 #endif
4232 init_excp_e200(env);
4233 env->dcache_line_size = 32;
4234 env->icache_line_size = 32;
4235 /* XXX: TODO: allocate internal IRQ controller */
4236 }
4237
4238 /* Non-embedded PowerPC */
4239
4240 /* POWER : same as 601, without mfmsr, mfsr */
4241 #if defined(TODO)
4242 #define POWERPC_INSNS_POWER (XXX_TODO)
4243 /* POWER RSC (from RAD6000) */
4244 #define POWERPC_MSRM_POWER (0x00000000FEF0ULL)
4245 #endif /* TODO */
4246
4247 /* PowerPC 601 */
4248 #define POWERPC_INSNS_601 (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4249 PPC_FLOAT | \
4250 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4251 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4252 PPC_SEGMENT | PPC_EXTERN)
4253 #define POWERPC_MSRM_601 (0x000000000000FD70ULL)
4254 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4255 //#define POWERPC_MMU_601 (POWERPC_MMU_601)
4256 //#define POWERPC_EXCP_601 (POWERPC_EXCP_601)
4257 #define POWERPC_INPUT_601 (PPC_FLAGS_INPUT_6xx)
4258 #define POWERPC_BFDM_601 (bfd_mach_ppc_601)
4259 #define POWERPC_FLAG_601 (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4260 #define check_pow_601 check_pow_none
4261
4262 static void init_proc_601 (CPUPPCState *env)
4263 {
4264 gen_spr_ne_601(env);
4265 gen_spr_601(env);
4266 /* Hardware implementation registers */
4267 /* XXX : not implemented */
4268 spr_register(env, SPR_HID0, "HID0",
4269 SPR_NOACCESS, SPR_NOACCESS,
4270 &spr_read_generic, &spr_write_hid0_601,
4271 0x80010080);
4272 /* XXX : not implemented */
4273 spr_register(env, SPR_HID1, "HID1",
4274 SPR_NOACCESS, SPR_NOACCESS,
4275 &spr_read_generic, &spr_write_generic,
4276 0x00000000);
4277 /* XXX : not implemented */
4278 spr_register(env, SPR_601_HID2, "HID2",
4279 SPR_NOACCESS, SPR_NOACCESS,
4280 &spr_read_generic, &spr_write_generic,
4281 0x00000000);
4282 /* XXX : not implemented */
4283 spr_register(env, SPR_601_HID5, "HID5",
4284 SPR_NOACCESS, SPR_NOACCESS,
4285 &spr_read_generic, &spr_write_generic,
4286 0x00000000);
4287 /* Memory management */
4288 init_excp_601(env);
4289 /* XXX: beware that dcache line size is 64
4290 * but dcbz uses 32 bytes "sectors"
4291 * XXX: this breaks clcs instruction !
4292 */
4293 env->dcache_line_size = 32;
4294 env->icache_line_size = 64;
4295 /* Allocate hardware IRQ controller */
4296 ppc6xx_irq_init(env);
4297 }
4298
4299 /* PowerPC 601v */
4300 #define POWERPC_INSNS_601v (PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | \
4301 PPC_FLOAT | \
4302 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4303 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | \
4304 PPC_SEGMENT | PPC_EXTERN)
4305 #define POWERPC_MSRM_601v (0x000000000000FD70ULL)
4306 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4307 #define POWERPC_MMU_601v (POWERPC_MMU_601)
4308 #define POWERPC_EXCP_601v (POWERPC_EXCP_601)
4309 #define POWERPC_INPUT_601v (PPC_FLAGS_INPUT_6xx)
4310 #define POWERPC_BFDM_601v (bfd_mach_ppc_601)
4311 #define POWERPC_FLAG_601v (POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK)
4312 #define check_pow_601v check_pow_none
4313
4314 static void init_proc_601v (CPUPPCState *env)
4315 {
4316 init_proc_601(env);
4317 /* XXX : not implemented */
4318 spr_register(env, SPR_601_HID15, "HID15",
4319 SPR_NOACCESS, SPR_NOACCESS,
4320 &spr_read_generic, &spr_write_generic,
4321 0x00000000);
4322 }
4323
4324 /* PowerPC 602 */
4325 #define POWERPC_INSNS_602 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4326 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4327 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4328 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4329 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4330 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | \
4331 PPC_SEGMENT | PPC_602_SPEC)
4332 #define POWERPC_MSRM_602 (0x0000000000C7FF73ULL)
4333 /* XXX: 602 MMU is quite specific. Should add a special case */
4334 #define POWERPC_MMU_602 (POWERPC_MMU_SOFT_6xx)
4335 //#define POWERPC_EXCP_602 (POWERPC_EXCP_602)
4336 #define POWERPC_INPUT_602 (PPC_FLAGS_INPUT_6xx)
4337 #define POWERPC_BFDM_602 (bfd_mach_ppc_602)
4338 #define POWERPC_FLAG_602 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4339 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4340 #define check_pow_602 check_pow_hid0
4341
4342 static void init_proc_602 (CPUPPCState *env)
4343 {
4344 gen_spr_ne_601(env);
4345 gen_spr_602(env);
4346 /* Time base */
4347 gen_tbl(env);
4348 /* hardware implementation registers */
4349 /* XXX : not implemented */
4350 spr_register(env, SPR_HID0, "HID0",
4351 SPR_NOACCESS, SPR_NOACCESS,
4352 &spr_read_generic, &spr_write_generic,
4353 0x00000000);
4354 /* XXX : not implemented */
4355 spr_register(env, SPR_HID1, "HID1",
4356 SPR_NOACCESS, SPR_NOACCESS,
4357 &spr_read_generic, &spr_write_generic,
4358 0x00000000);
4359 /* Memory management */
4360 gen_low_BATs(env);
4361 gen_6xx_7xx_soft_tlb(env, 64, 2);
4362 init_excp_602(env);
4363 env->dcache_line_size = 32;
4364 env->icache_line_size = 32;
4365 /* Allocate hardware IRQ controller */
4366 ppc6xx_irq_init(env);
4367 }
4368
4369 /* PowerPC 603 */
4370 #define POWERPC_INSNS_603 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4371 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4372 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4373 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4374 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4375 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4376 PPC_SEGMENT | PPC_EXTERN)
4377 #define POWERPC_MSRM_603 (0x000000000007FF73ULL)
4378 #define POWERPC_MMU_603 (POWERPC_MMU_SOFT_6xx)
4379 //#define POWERPC_EXCP_603 (POWERPC_EXCP_603)
4380 #define POWERPC_INPUT_603 (PPC_FLAGS_INPUT_6xx)
4381 #define POWERPC_BFDM_603 (bfd_mach_ppc_603)
4382 #define POWERPC_FLAG_603 (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4383 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4384 #define check_pow_603 check_pow_hid0
4385
4386 static void init_proc_603 (CPUPPCState *env)
4387 {
4388 gen_spr_ne_601(env);
4389 gen_spr_603(env);
4390 /* Time base */
4391 gen_tbl(env);
4392 /* hardware implementation registers */
4393 /* XXX : not implemented */
4394 spr_register(env, SPR_HID0, "HID0",
4395 SPR_NOACCESS, SPR_NOACCESS,
4396 &spr_read_generic, &spr_write_generic,
4397 0x00000000);
4398 /* XXX : not implemented */
4399 spr_register(env, SPR_HID1, "HID1",
4400 SPR_NOACCESS, SPR_NOACCESS,
4401 &spr_read_generic, &spr_write_generic,
4402 0x00000000);
4403 /* Memory management */
4404 gen_low_BATs(env);
4405 gen_6xx_7xx_soft_tlb(env, 64, 2);
4406 init_excp_603(env);
4407 env->dcache_line_size = 32;
4408 env->icache_line_size = 32;
4409 /* Allocate hardware IRQ controller */
4410 ppc6xx_irq_init(env);
4411 }
4412
4413 /* PowerPC 603e */
4414 #define POWERPC_INSNS_603E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4415 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4416 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4417 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4418 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4419 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
4420 PPC_SEGMENT | PPC_EXTERN)
4421 #define POWERPC_MSRM_603E (0x000000000007FF73ULL)
4422 #define POWERPC_MMU_603E (POWERPC_MMU_SOFT_6xx)
4423 //#define POWERPC_EXCP_603E (POWERPC_EXCP_603E)
4424 #define POWERPC_INPUT_603E (PPC_FLAGS_INPUT_6xx)
4425 #define POWERPC_BFDM_603E (bfd_mach_ppc_ec603e)
4426 #define POWERPC_FLAG_603E (POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | \
4427 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK)
4428 #define check_pow_603E check_pow_hid0
4429
4430 static void init_proc_603E (CPUPPCState *env)
4431 {
4432 gen_spr_ne_601(env);
4433 gen_spr_603(env);
4434 /* Time base */
4435 gen_tbl(env);
4436 /* hardware implementation registers */
4437 /* XXX : not implemented */
4438 spr_register(env, SPR_HID0, "HID0",
4439 SPR_NOACCESS, SPR_NOACCESS,
4440 &spr_read_generic, &spr_write_generic,
4441 0x00000000);
4442 /* XXX : not implemented */
4443 spr_register(env, SPR_HID1, "HID1",
4444 SPR_NOACCESS, SPR_NOACCESS,
4445 &spr_read_generic, &spr_write_generic,
4446 0x00000000);
4447 /* XXX : not implemented */
4448 spr_register(env, SPR_IABR, "IABR",
4449 SPR_NOACCESS, SPR_NOACCESS,
4450 &spr_read_generic, &spr_write_generic,
4451 0x00000000);
4452 /* Memory management */
4453 gen_low_BATs(env);
4454 gen_6xx_7xx_soft_tlb(env, 64, 2);
4455 init_excp_603(env);
4456 env->dcache_line_size = 32;
4457 env->icache_line_size = 32;
4458 /* Allocate hardware IRQ controller */
4459 ppc6xx_irq_init(env);
4460 }
4461
4462 /* PowerPC 604 */
4463 #define POWERPC_INSNS_604 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4464 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4465 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4466 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4467 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4468 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4469 PPC_SEGMENT | PPC_EXTERN)
4470 #define POWERPC_MSRM_604 (0x000000000005FF77ULL)
4471 #define POWERPC_MMU_604 (POWERPC_MMU_32B)
4472 //#define POWERPC_EXCP_604 (POWERPC_EXCP_604)
4473 #define POWERPC_INPUT_604 (PPC_FLAGS_INPUT_6xx)
4474 #define POWERPC_BFDM_604 (bfd_mach_ppc_604)
4475 #define POWERPC_FLAG_604 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4476 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4477 #define check_pow_604 check_pow_nocheck
4478
4479 static void init_proc_604 (CPUPPCState *env)
4480 {
4481 gen_spr_ne_601(env);
4482 gen_spr_604(env);
4483 /* Time base */
4484 gen_tbl(env);
4485 /* Hardware implementation registers */
4486 /* XXX : not implemented */
4487 spr_register(env, SPR_HID0, "HID0",
4488 SPR_NOACCESS, SPR_NOACCESS,
4489 &spr_read_generic, &spr_write_generic,
4490 0x00000000);
4491 /* Memory management */
4492 gen_low_BATs(env);
4493 init_excp_604(env);
4494 env->dcache_line_size = 32;
4495 env->icache_line_size = 32;
4496 /* Allocate hardware IRQ controller */
4497 ppc6xx_irq_init(env);
4498 }
4499
4500 /* PowerPC 604E */
4501 #define POWERPC_INSNS_604E (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4502 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4503 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4504 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4505 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4506 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4507 PPC_SEGMENT | PPC_EXTERN)
4508 #define POWERPC_MSRM_604E (0x000000000005FF77ULL)
4509 #define POWERPC_MMU_604E (POWERPC_MMU_32B)
4510 #define POWERPC_EXCP_604E (POWERPC_EXCP_604)
4511 #define POWERPC_INPUT_604E (PPC_FLAGS_INPUT_6xx)
4512 #define POWERPC_BFDM_604E (bfd_mach_ppc_604)
4513 #define POWERPC_FLAG_604E (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4514 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4515 #define check_pow_604E check_pow_nocheck
4516
4517 static void init_proc_604E (CPUPPCState *env)
4518 {
4519 gen_spr_ne_601(env);
4520 gen_spr_604(env);
4521 /* XXX : not implemented */
4522 spr_register(env, SPR_MMCR1, "MMCR1",
4523 SPR_NOACCESS, SPR_NOACCESS,
4524 &spr_read_generic, &spr_write_generic,
4525 0x00000000);
4526 /* XXX : not implemented */
4527 spr_register(env, SPR_PMC3, "PMC3",
4528 SPR_NOACCESS, SPR_NOACCESS,
4529 &spr_read_generic, &spr_write_generic,
4530 0x00000000);
4531 /* XXX : not implemented */
4532 spr_register(env, SPR_PMC4, "PMC4",
4533 SPR_NOACCESS, SPR_NOACCESS,
4534 &spr_read_generic, &spr_write_generic,
4535 0x00000000);
4536 /* Time base */
4537 gen_tbl(env);
4538 /* Hardware implementation registers */
4539 /* XXX : not implemented */
4540 spr_register(env, SPR_HID0, "HID0",
4541 SPR_NOACCESS, SPR_NOACCESS,
4542 &spr_read_generic, &spr_write_generic,
4543 0x00000000);
4544 /* XXX : not implemented */
4545 spr_register(env, SPR_HID1, "HID1",
4546 SPR_NOACCESS, SPR_NOACCESS,
4547 &spr_read_generic, &spr_write_generic,
4548 0x00000000);
4549 /* Memory management */
4550 gen_low_BATs(env);
4551 init_excp_604(env);
4552 env->dcache_line_size = 32;
4553 env->icache_line_size = 32;
4554 /* Allocate hardware IRQ controller */
4555 ppc6xx_irq_init(env);
4556 }
4557
4558 /* PowerPC 740 */
4559 #define POWERPC_INSNS_740 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4560 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4561 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4562 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4563 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4564 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4565 PPC_SEGMENT | PPC_EXTERN)
4566 #define POWERPC_MSRM_740 (0x000000000005FF77ULL)
4567 #define POWERPC_MMU_740 (POWERPC_MMU_32B)
4568 #define POWERPC_EXCP_740 (POWERPC_EXCP_7x0)
4569 #define POWERPC_INPUT_740 (PPC_FLAGS_INPUT_6xx)
4570 #define POWERPC_BFDM_740 (bfd_mach_ppc_750)
4571 #define POWERPC_FLAG_740 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4572 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4573 #define check_pow_740 check_pow_hid0
4574
4575 static void init_proc_740 (CPUPPCState *env)
4576 {
4577 gen_spr_ne_601(env);
4578 gen_spr_7xx(env);
4579 /* Time base */
4580 gen_tbl(env);
4581 /* Thermal management */
4582 gen_spr_thrm(env);
4583 /* Hardware implementation registers */
4584 /* XXX : not implemented */
4585 spr_register(env, SPR_HID0, "HID0",
4586 SPR_NOACCESS, SPR_NOACCESS,
4587 &spr_read_generic, &spr_write_generic,
4588 0x00000000);
4589 /* XXX : not implemented */
4590 spr_register(env, SPR_HID1, "HID1",
4591 SPR_NOACCESS, SPR_NOACCESS,
4592 &spr_read_generic, &spr_write_generic,
4593 0x00000000);
4594 /* Memory management */
4595 gen_low_BATs(env);
4596 init_excp_7x0(env);
4597 env->dcache_line_size = 32;
4598 env->icache_line_size = 32;
4599 /* Allocate hardware IRQ controller */
4600 ppc6xx_irq_init(env);
4601 }
4602
4603 /* PowerPC 750 */
4604 #define POWERPC_INSNS_750 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4605 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4606 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4607 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4608 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4609 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4610 PPC_SEGMENT | PPC_EXTERN)
4611 #define POWERPC_MSRM_750 (0x000000000005FF77ULL)
4612 #define POWERPC_MMU_750 (POWERPC_MMU_32B)
4613 #define POWERPC_EXCP_750 (POWERPC_EXCP_7x0)
4614 #define POWERPC_INPUT_750 (PPC_FLAGS_INPUT_6xx)
4615 #define POWERPC_BFDM_750 (bfd_mach_ppc_750)
4616 #define POWERPC_FLAG_750 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4617 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4618 #define check_pow_750 check_pow_hid0
4619
4620 static void init_proc_750 (CPUPPCState *env)
4621 {
4622 gen_spr_ne_601(env);
4623 gen_spr_7xx(env);
4624 /* XXX : not implemented */
4625 spr_register(env, SPR_L2CR, "L2CR",
4626 SPR_NOACCESS, SPR_NOACCESS,
4627 &spr_read_generic, &spr_write_generic,
4628 0x00000000);
4629 /* Time base */
4630 gen_tbl(env);
4631 /* Thermal management */
4632 gen_spr_thrm(env);
4633 /* Hardware implementation registers */
4634 /* XXX : not implemented */
4635 spr_register(env, SPR_HID0, "HID0",
4636 SPR_NOACCESS, SPR_NOACCESS,
4637 &spr_read_generic, &spr_write_generic,
4638 0x00000000);
4639 /* XXX : not implemented */
4640 spr_register(env, SPR_HID1, "HID1",
4641 SPR_NOACCESS, SPR_NOACCESS,
4642 &spr_read_generic, &spr_write_generic,
4643 0x00000000);
4644 /* Memory management */
4645 gen_low_BATs(env);
4646 /* XXX: high BATs are also present but are known to be bugged on
4647 * die version 1.x
4648 */
4649 init_excp_7x0(env);
4650 env->dcache_line_size = 32;
4651 env->icache_line_size = 32;
4652 /* Allocate hardware IRQ controller */
4653 ppc6xx_irq_init(env);
4654 }
4655
4656 /* PowerPC 750 CL */
4657 /* XXX: not implemented:
4658 * cache lock instructions:
4659 * dcbz_l
4660 * floating point paired instructions
4661 * psq_lux
4662 * psq_lx
4663 * psq_stux
4664 * psq_stx
4665 * ps_abs
4666 * ps_add
4667 * ps_cmpo0
4668 * ps_cmpo1
4669 * ps_cmpu0
4670 * ps_cmpu1
4671 * ps_div
4672 * ps_madd
4673 * ps_madds0
4674 * ps_madds1
4675 * ps_merge00
4676 * ps_merge01
4677 * ps_merge10
4678 * ps_merge11
4679 * ps_mr
4680 * ps_msub
4681 * ps_mul
4682 * ps_muls0
4683 * ps_muls1
4684 * ps_nabs
4685 * ps_neg
4686 * ps_nmadd
4687 * ps_nmsub
4688 * ps_res
4689 * ps_rsqrte
4690 * ps_sel
4691 * ps_sub
4692 * ps_sum0
4693 * ps_sum1
4694 */
4695 #define POWERPC_INSNS_750cl (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4696 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4697 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4698 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4699 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4700 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4701 PPC_SEGMENT | PPC_EXTERN)
4702 #define POWERPC_MSRM_750cl (0x000000000005FF77ULL)
4703 #define POWERPC_MMU_750cl (POWERPC_MMU_32B)
4704 #define POWERPC_EXCP_750cl (POWERPC_EXCP_7x0)
4705 #define POWERPC_INPUT_750cl (PPC_FLAGS_INPUT_6xx)
4706 #define POWERPC_BFDM_750cl (bfd_mach_ppc_750)
4707 #define POWERPC_FLAG_750cl (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4708 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4709 #define check_pow_750cl check_pow_hid0
4710
4711 static void init_proc_750cl (CPUPPCState *env)
4712 {
4713 gen_spr_ne_601(env);
4714 gen_spr_7xx(env);
4715 /* XXX : not implemented */
4716 spr_register(env, SPR_L2CR, "L2CR",
4717 SPR_NOACCESS, SPR_NOACCESS,
4718 &spr_read_generic, &spr_write_generic,
4719 0x00000000);
4720 /* Time base */
4721 gen_tbl(env);
4722 /* Thermal management */
4723 /* Those registers are fake on 750CL */
4724 spr_register(env, SPR_THRM1, "THRM1",
4725 SPR_NOACCESS, SPR_NOACCESS,
4726 &spr_read_generic, &spr_write_generic,
4727 0x00000000);
4728 spr_register(env, SPR_THRM2, "THRM2",
4729 SPR_NOACCESS, SPR_NOACCESS,
4730 &spr_read_generic, &spr_write_generic,
4731 0x00000000);
4732 spr_register(env, SPR_THRM3, "THRM3",
4733 SPR_NOACCESS, SPR_NOACCESS,
4734 &spr_read_generic, &spr_write_generic,
4735 0x00000000);
4736 /* XXX: not implemented */
4737 spr_register(env, SPR_750_TDCL, "TDCL",
4738 SPR_NOACCESS, SPR_NOACCESS,
4739 &spr_read_generic, &spr_write_generic,
4740 0x00000000);
4741 spr_register(env, SPR_750_TDCH, "TDCH",
4742 SPR_NOACCESS, SPR_NOACCESS,
4743 &spr_read_generic, &spr_write_generic,
4744 0x00000000);
4745 /* DMA */
4746 /* XXX : not implemented */
4747 spr_register(env, SPR_750_WPAR, "WPAR",
4748 SPR_NOACCESS, SPR_NOACCESS,
4749 &spr_read_generic, &spr_write_generic,
4750 0x00000000);
4751 spr_register(env, SPR_750_DMAL, "DMAL",
4752 SPR_NOACCESS, SPR_NOACCESS,
4753 &spr_read_generic, &spr_write_generic,
4754 0x00000000);
4755 spr_register(env, SPR_750_DMAU, "DMAU",
4756 SPR_NOACCESS, SPR_NOACCESS,
4757 &spr_read_generic, &spr_write_generic,
4758 0x00000000);
4759 /* Hardware implementation registers */
4760 /* XXX : not implemented */
4761 spr_register(env, SPR_HID0, "HID0",
4762 SPR_NOACCESS, SPR_NOACCESS,
4763 &spr_read_generic, &spr_write_generic,
4764 0x00000000);
4765 /* XXX : not implemented */
4766 spr_register(env, SPR_HID1, "HID1",
4767 SPR_NOACCESS, SPR_NOACCESS,
4768 &spr_read_generic, &spr_write_generic,
4769 0x00000000);
4770 /* XXX : not implemented */
4771 spr_register(env, SPR_750CL_HID2, "HID2",
4772 SPR_NOACCESS, SPR_NOACCESS,
4773 &spr_read_generic, &spr_write_generic,
4774 0x00000000);
4775 /* XXX : not implemented */
4776 spr_register(env, SPR_750CL_HID4, "HID4",
4777 SPR_NOACCESS, SPR_NOACCESS,
4778 &spr_read_generic, &spr_write_generic,
4779 0x00000000);
4780 /* Quantization registers */
4781 /* XXX : not implemented */
4782 spr_register(env, SPR_750_GQR0, "GQR0",
4783 SPR_NOACCESS, SPR_NOACCESS,
4784 &spr_read_generic, &spr_write_generic,
4785 0x00000000);
4786 /* XXX : not implemented */
4787 spr_register(env, SPR_750_GQR1, "GQR1",
4788 SPR_NOACCESS, SPR_NOACCESS,
4789 &spr_read_generic, &spr_write_generic,
4790 0x00000000);
4791 /* XXX : not implemented */
4792 spr_register(env, SPR_750_GQR2, "GQR2",
4793 SPR_NOACCESS, SPR_NOACCESS,
4794 &spr_read_generic, &spr_write_generic,
4795 0x00000000);
4796 /* XXX : not implemented */
4797 spr_register(env, SPR_750_GQR3, "GQR3",
4798 SPR_NOACCESS, SPR_NOACCESS,
4799 &spr_read_generic, &spr_write_generic,
4800 0x00000000);
4801 /* XXX : not implemented */
4802 spr_register(env, SPR_750_GQR4, "GQR4",
4803 SPR_NOACCESS, SPR_NOACCESS,
4804 &spr_read_generic, &spr_write_generic,
4805 0x00000000);
4806 /* XXX : not implemented */
4807 spr_register(env, SPR_750_GQR5, "GQR5",
4808 SPR_NOACCESS, SPR_NOACCESS,
4809 &spr_read_generic, &spr_write_generic,
4810 0x00000000);
4811 /* XXX : not implemented */
4812 spr_register(env, SPR_750_GQR6, "GQR6",
4813 SPR_NOACCESS, SPR_NOACCESS,
4814 &spr_read_generic, &spr_write_generic,
4815 0x00000000);
4816 /* XXX : not implemented */
4817 spr_register(env, SPR_750_GQR7, "GQR7",
4818 SPR_NOACCESS, SPR_NOACCESS,
4819 &spr_read_generic, &spr_write_generic,
4820 0x00000000);
4821 /* Memory management */
4822 gen_low_BATs(env);
4823 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
4824 gen_high_BATs(env);
4825 init_excp_750cl(env);
4826 env->dcache_line_size = 32;
4827 env->icache_line_size = 32;
4828 /* Allocate hardware IRQ controller */
4829 ppc6xx_irq_init(env);
4830 }
4831
4832 #define POWERPC_INSNS_750cx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4833 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4834 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4835 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4836 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4837 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4838 PPC_SEGMENT | PPC_EXTERN)
4839 #define POWERPC_MSRM_750cx (0x000000000005FF77ULL)
4840 #define POWERPC_MMU_750cx (POWERPC_MMU_32B)
4841 #define POWERPC_EXCP_750cx (POWERPC_EXCP_7x0)
4842 #define POWERPC_INPUT_750cx (PPC_FLAGS_INPUT_6xx)
4843 #define POWERPC_BFDM_750cx (bfd_mach_ppc_750)
4844 #define POWERPC_FLAG_750cx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4845 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4846 #define check_pow_750cx check_pow_hid0
4847
4848 static void init_proc_750cx (CPUPPCState *env)
4849 {
4850 gen_spr_ne_601(env);
4851 gen_spr_7xx(env);
4852 /* XXX : not implemented */
4853 spr_register(env, SPR_L2CR, "L2CR",
4854 SPR_NOACCESS, SPR_NOACCESS,
4855 &spr_read_generic, &spr_write_generic,
4856 0x00000000);
4857 /* Time base */
4858 gen_tbl(env);
4859 /* Thermal management */
4860 gen_spr_thrm(env);
4861 /* This register is not implemented but is present for compatibility */
4862 spr_register(env, SPR_SDA, "SDA",
4863 SPR_NOACCESS, SPR_NOACCESS,
4864 &spr_read_generic, &spr_write_generic,
4865 0x00000000);
4866 /* Hardware implementation registers */
4867 /* XXX : not implemented */
4868 spr_register(env, SPR_HID0, "HID0",
4869 SPR_NOACCESS, SPR_NOACCESS,
4870 &spr_read_generic, &spr_write_generic,
4871 0x00000000);
4872 /* XXX : not implemented */
4873 spr_register(env, SPR_HID1, "HID1",
4874 SPR_NOACCESS, SPR_NOACCESS,
4875 &spr_read_generic, &spr_write_generic,
4876 0x00000000);
4877 /* Memory management */
4878 gen_low_BATs(env);
4879 /* XXX: high BATs are also present but are known to be bugged on
4880 * die version 1.x
4881 */
4882 init_excp_750cx(env);
4883 env->dcache_line_size = 32;
4884 env->icache_line_size = 32;
4885 /* Allocate hardware IRQ controller */
4886 ppc6xx_irq_init(env);
4887 }
4888
4889 /* PowerPC 750FX */
4890 #define POWERPC_INSNS_750fx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4891 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4892 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4893 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4894 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4895 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4896 PPC_SEGMENT | PPC_EXTERN)
4897 #define POWERPC_MSRM_750fx (0x000000000005FF77ULL)
4898 #define POWERPC_MMU_750fx (POWERPC_MMU_32B)
4899 #define POWERPC_EXCP_750fx (POWERPC_EXCP_7x0)
4900 #define POWERPC_INPUT_750fx (PPC_FLAGS_INPUT_6xx)
4901 #define POWERPC_BFDM_750fx (bfd_mach_ppc_750)
4902 #define POWERPC_FLAG_750fx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4903 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4904 #define check_pow_750fx check_pow_hid0
4905
4906 static void init_proc_750fx (CPUPPCState *env)
4907 {
4908 gen_spr_ne_601(env);
4909 gen_spr_7xx(env);
4910 /* XXX : not implemented */
4911 spr_register(env, SPR_L2CR, "L2CR",
4912 SPR_NOACCESS, SPR_NOACCESS,
4913 &spr_read_generic, &spr_write_generic,
4914 0x00000000);
4915 /* Time base */
4916 gen_tbl(env);
4917 /* Thermal management */
4918 gen_spr_thrm(env);
4919 /* XXX : not implemented */
4920 spr_register(env, SPR_750_THRM4, "THRM4",
4921 SPR_NOACCESS, SPR_NOACCESS,
4922 &spr_read_generic, &spr_write_generic,
4923 0x00000000);
4924 /* Hardware implementation registers */
4925 /* XXX : not implemented */
4926 spr_register(env, SPR_HID0, "HID0",
4927 SPR_NOACCESS, SPR_NOACCESS,
4928 &spr_read_generic, &spr_write_generic,
4929 0x00000000);
4930 /* XXX : not implemented */
4931 spr_register(env, SPR_HID1, "HID1",
4932 SPR_NOACCESS, SPR_NOACCESS,
4933 &spr_read_generic, &spr_write_generic,
4934 0x00000000);
4935 /* XXX : not implemented */
4936 spr_register(env, SPR_750FX_HID2, "HID2",
4937 SPR_NOACCESS, SPR_NOACCESS,
4938 &spr_read_generic, &spr_write_generic,
4939 0x00000000);
4940 /* Memory management */
4941 gen_low_BATs(env);
4942 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
4943 gen_high_BATs(env);
4944 init_excp_7x0(env);
4945 env->dcache_line_size = 32;
4946 env->icache_line_size = 32;
4947 /* Allocate hardware IRQ controller */
4948 ppc6xx_irq_init(env);
4949 }
4950
4951 /* PowerPC 750GX */
4952 #define POWERPC_INSNS_750gx (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
4953 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
4954 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
4955 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
4956 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
4957 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
4958 PPC_SEGMENT | PPC_EXTERN)
4959 #define POWERPC_MSRM_750gx (0x000000000005FF77ULL)
4960 #define POWERPC_MMU_750gx (POWERPC_MMU_32B)
4961 #define POWERPC_EXCP_750gx (POWERPC_EXCP_7x0)
4962 #define POWERPC_INPUT_750gx (PPC_FLAGS_INPUT_6xx)
4963 #define POWERPC_BFDM_750gx (bfd_mach_ppc_750)
4964 #define POWERPC_FLAG_750gx (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
4965 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
4966 #define check_pow_750gx check_pow_hid0
4967
4968 static void init_proc_750gx (CPUPPCState *env)
4969 {
4970 gen_spr_ne_601(env);
4971 gen_spr_7xx(env);
4972 /* XXX : not implemented (XXX: different from 750fx) */
4973 spr_register(env, SPR_L2CR, "L2CR",
4974 SPR_NOACCESS, SPR_NOACCESS,
4975 &spr_read_generic, &spr_write_generic,
4976 0x00000000);
4977 /* Time base */
4978 gen_tbl(env);
4979 /* Thermal management */
4980 gen_spr_thrm(env);
4981 /* XXX : not implemented */
4982 spr_register(env, SPR_750_THRM4, "THRM4",
4983 SPR_NOACCESS, SPR_NOACCESS,
4984 &spr_read_generic, &spr_write_generic,
4985 0x00000000);
4986 /* Hardware implementation registers */
4987 /* XXX : not implemented (XXX: different from 750fx) */
4988 spr_register(env, SPR_HID0, "HID0",
4989 SPR_NOACCESS, SPR_NOACCESS,
4990 &spr_read_generic, &spr_write_generic,
4991 0x00000000);
4992 /* XXX : not implemented */
4993 spr_register(env, SPR_HID1, "HID1",
4994 SPR_NOACCESS, SPR_NOACCESS,
4995 &spr_read_generic, &spr_write_generic,
4996 0x00000000);
4997 /* XXX : not implemented (XXX: different from 750fx) */
4998 spr_register(env, SPR_750FX_HID2, "HID2",
4999 SPR_NOACCESS, SPR_NOACCESS,
5000 &spr_read_generic, &spr_write_generic,
5001 0x00000000);
5002 /* Memory management */
5003 gen_low_BATs(env);
5004 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5005 gen_high_BATs(env);
5006 init_excp_7x0(env);
5007 env->dcache_line_size = 32;
5008 env->icache_line_size = 32;
5009 /* Allocate hardware IRQ controller */
5010 ppc6xx_irq_init(env);
5011 }
5012
5013 /* PowerPC 745 */
5014 #define POWERPC_INSNS_745 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5015 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5016 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5017 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5018 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5019 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5020 PPC_SEGMENT | PPC_EXTERN)
5021 #define POWERPC_MSRM_745 (0x000000000005FF77ULL)
5022 #define POWERPC_MMU_745 (POWERPC_MMU_SOFT_6xx)
5023 #define POWERPC_EXCP_745 (POWERPC_EXCP_7x5)
5024 #define POWERPC_INPUT_745 (PPC_FLAGS_INPUT_6xx)
5025 #define POWERPC_BFDM_745 (bfd_mach_ppc_750)
5026 #define POWERPC_FLAG_745 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5027 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5028 #define check_pow_745 check_pow_hid0
5029
5030 static void init_proc_745 (CPUPPCState *env)
5031 {
5032 gen_spr_ne_601(env);
5033 gen_spr_7xx(env);
5034 gen_spr_G2_755(env);
5035 /* Time base */
5036 gen_tbl(env);
5037 /* Thermal management */
5038 gen_spr_thrm(env);
5039 /* Hardware implementation registers */
5040 /* XXX : not implemented */
5041 spr_register(env, SPR_HID0, "HID0",
5042 SPR_NOACCESS, SPR_NOACCESS,
5043 &spr_read_generic, &spr_write_generic,
5044 0x00000000);
5045 /* XXX : not implemented */
5046 spr_register(env, SPR_HID1, "HID1",
5047 SPR_NOACCESS, SPR_NOACCESS,
5048 &spr_read_generic, &spr_write_generic,
5049 0x00000000);
5050 /* XXX : not implemented */
5051 spr_register(env, SPR_HID2, "HID2",
5052 SPR_NOACCESS, SPR_NOACCESS,
5053 &spr_read_generic, &spr_write_generic,
5054 0x00000000);
5055 /* Memory management */
5056 gen_low_BATs(env);
5057 gen_high_BATs(env);
5058 gen_6xx_7xx_soft_tlb(env, 64, 2);
5059 init_excp_7x5(env);
5060 env->dcache_line_size = 32;
5061 env->icache_line_size = 32;
5062 /* Allocate hardware IRQ controller */
5063 ppc6xx_irq_init(env);
5064 }
5065
5066 /* PowerPC 755 */
5067 #define POWERPC_INSNS_755 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5068 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5069 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | \
5070 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5071 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5072 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | \
5073 PPC_SEGMENT | PPC_EXTERN)
5074 #define POWERPC_MSRM_755 (0x000000000005FF77ULL)
5075 #define POWERPC_MMU_755 (POWERPC_MMU_SOFT_6xx)
5076 #define POWERPC_EXCP_755 (POWERPC_EXCP_7x5)
5077 #define POWERPC_INPUT_755 (PPC_FLAGS_INPUT_6xx)
5078 #define POWERPC_BFDM_755 (bfd_mach_ppc_750)
5079 #define POWERPC_FLAG_755 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5080 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5081 #define check_pow_755 check_pow_hid0
5082
5083 static void init_proc_755 (CPUPPCState *env)
5084 {
5085 gen_spr_ne_601(env);
5086 gen_spr_7xx(env);
5087 gen_spr_G2_755(env);
5088 /* Time base */
5089 gen_tbl(env);
5090 /* L2 cache control */
5091 /* XXX : not implemented */
5092 spr_register(env, SPR_L2CR, "L2CR",
5093 SPR_NOACCESS, SPR_NOACCESS,
5094 &spr_read_generic, &spr_write_generic,
5095 0x00000000);
5096 /* XXX : not implemented */
5097 spr_register(env, SPR_L2PMCR, "L2PMCR",
5098 SPR_NOACCESS, SPR_NOACCESS,
5099 &spr_read_generic, &spr_write_generic,
5100 0x00000000);
5101 /* Thermal management */
5102 gen_spr_thrm(env);
5103 /* Hardware implementation registers */
5104 /* XXX : not implemented */
5105 spr_register(env, SPR_HID0, "HID0",
5106 SPR_NOACCESS, SPR_NOACCESS,
5107 &spr_read_generic, &spr_write_generic,
5108 0x00000000);
5109 /* XXX : not implemented */
5110 spr_register(env, SPR_HID1, "HID1",
5111 SPR_NOACCESS, SPR_NOACCESS,
5112 &spr_read_generic, &spr_write_generic,
5113 0x00000000);
5114 /* XXX : not implemented */
5115 spr_register(env, SPR_HID2, "HID2",
5116 SPR_NOACCESS, SPR_NOACCESS,
5117 &spr_read_generic, &spr_write_generic,
5118 0x00000000);
5119 /* Memory management */
5120 gen_low_BATs(env);
5121 gen_high_BATs(env);
5122 gen_6xx_7xx_soft_tlb(env, 64, 2);
5123 init_excp_7x5(env);
5124 env->dcache_line_size = 32;
5125 env->icache_line_size = 32;
5126 /* Allocate hardware IRQ controller */
5127 ppc6xx_irq_init(env);
5128 }
5129
5130 /* PowerPC 7400 (aka G4) */
5131 #define POWERPC_INSNS_7400 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5132 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5133 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5134 PPC_FLOAT_STFIWX | \
5135 PPC_CACHE | PPC_CACHE_ICBI | \
5136 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5137 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5138 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5139 PPC_MEM_TLBIA | \
5140 PPC_SEGMENT | PPC_EXTERN | \
5141 PPC_ALTIVEC)
5142 #define POWERPC_MSRM_7400 (0x000000000205FF77ULL)
5143 #define POWERPC_MMU_7400 (POWERPC_MMU_32B)
5144 #define POWERPC_EXCP_7400 (POWERPC_EXCP_74xx)
5145 #define POWERPC_INPUT_7400 (PPC_FLAGS_INPUT_6xx)
5146 #define POWERPC_BFDM_7400 (bfd_mach_ppc_7400)
5147 #define POWERPC_FLAG_7400 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5148 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5149 POWERPC_FLAG_BUS_CLK)
5150 #define check_pow_7400 check_pow_hid0
5151
5152 static void init_proc_7400 (CPUPPCState *env)
5153 {
5154 gen_spr_ne_601(env);
5155 gen_spr_7xx(env);
5156 /* Time base */
5157 gen_tbl(env);
5158 /* 74xx specific SPR */
5159 gen_spr_74xx(env);
5160 /* Thermal management */
5161 gen_spr_thrm(env);
5162 /* Memory management */
5163 gen_low_BATs(env);
5164 init_excp_7400(env);
5165 env->dcache_line_size = 32;
5166 env->icache_line_size = 32;
5167 /* Allocate hardware IRQ controller */
5168 ppc6xx_irq_init(env);
5169 }
5170
5171 /* PowerPC 7410 (aka G4) */
5172 #define POWERPC_INSNS_7410 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5173 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5174 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5175 PPC_FLOAT_STFIWX | \
5176 PPC_CACHE | PPC_CACHE_ICBI | \
5177 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5178 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5179 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5180 PPC_MEM_TLBIA | \
5181 PPC_SEGMENT | PPC_EXTERN | \
5182 PPC_ALTIVEC)
5183 #define POWERPC_MSRM_7410 (0x000000000205FF77ULL)
5184 #define POWERPC_MMU_7410 (POWERPC_MMU_32B)
5185 #define POWERPC_EXCP_7410 (POWERPC_EXCP_74xx)
5186 #define POWERPC_INPUT_7410 (PPC_FLAGS_INPUT_6xx)
5187 #define POWERPC_BFDM_7410 (bfd_mach_ppc_7400)
5188 #define POWERPC_FLAG_7410 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5189 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5190 POWERPC_FLAG_BUS_CLK)
5191 #define check_pow_7410 check_pow_hid0
5192
5193 static void init_proc_7410 (CPUPPCState *env)
5194 {
5195 gen_spr_ne_601(env);
5196 gen_spr_7xx(env);
5197 /* Time base */
5198 gen_tbl(env);
5199 /* 74xx specific SPR */
5200 gen_spr_74xx(env);
5201 /* Thermal management */
5202 gen_spr_thrm(env);
5203 /* L2PMCR */
5204 /* XXX : not implemented */
5205 spr_register(env, SPR_L2PMCR, "L2PMCR",
5206 SPR_NOACCESS, SPR_NOACCESS,
5207 &spr_read_generic, &spr_write_generic,
5208 0x00000000);
5209 /* LDSTDB */
5210 /* XXX : not implemented */
5211 spr_register(env, SPR_LDSTDB, "LDSTDB",
5212 SPR_NOACCESS, SPR_NOACCESS,
5213 &spr_read_generic, &spr_write_generic,
5214 0x00000000);
5215 /* Memory management */
5216 gen_low_BATs(env);
5217 init_excp_7400(env);
5218 env->dcache_line_size = 32;
5219 env->icache_line_size = 32;
5220 /* Allocate hardware IRQ controller */
5221 ppc6xx_irq_init(env);
5222 }
5223
5224 /* PowerPC 7440 (aka G4) */
5225 #define POWERPC_INSNS_7440 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5226 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5227 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5228 PPC_FLOAT_STFIWX | \
5229 PPC_CACHE | PPC_CACHE_ICBI | \
5230 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5231 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5232 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5233 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5234 PPC_SEGMENT | PPC_EXTERN | \
5235 PPC_ALTIVEC)
5236 #define POWERPC_MSRM_7440 (0x000000000205FF77ULL)
5237 #define POWERPC_MMU_7440 (POWERPC_MMU_SOFT_74xx)
5238 #define POWERPC_EXCP_7440 (POWERPC_EXCP_74xx)
5239 #define POWERPC_INPUT_7440 (PPC_FLAGS_INPUT_6xx)
5240 #define POWERPC_BFDM_7440 (bfd_mach_ppc_7400)
5241 #define POWERPC_FLAG_7440 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5242 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5243 POWERPC_FLAG_BUS_CLK)
5244 #define check_pow_7440 check_pow_hid0
5245
5246 __attribute__ (( unused ))
5247 static void init_proc_7440 (CPUPPCState *env)
5248 {
5249 gen_spr_ne_601(env);
5250 gen_spr_7xx(env);
5251 /* Time base */
5252 gen_tbl(env);
5253 /* 74xx specific SPR */
5254 gen_spr_74xx(env);
5255 /* LDSTCR */
5256 /* XXX : not implemented */
5257 spr_register(env, SPR_LDSTCR, "LDSTCR",
5258 SPR_NOACCESS, SPR_NOACCESS,
5259 &spr_read_generic, &spr_write_generic,
5260 0x00000000);
5261 /* ICTRL */
5262 /* XXX : not implemented */
5263 spr_register(env, SPR_ICTRL, "ICTRL",
5264 SPR_NOACCESS, SPR_NOACCESS,
5265 &spr_read_generic, &spr_write_generic,
5266 0x00000000);
5267 /* MSSSR0 */
5268 /* XXX : not implemented */
5269 spr_register(env, SPR_MSSSR0, "MSSSR0",
5270 SPR_NOACCESS, SPR_NOACCESS,
5271 &spr_read_generic, &spr_write_generic,
5272 0x00000000);
5273 /* PMC */
5274 /* XXX : not implemented */
5275 spr_register(env, SPR_PMC5, "PMC5",
5276 SPR_NOACCESS, SPR_NOACCESS,
5277 &spr_read_generic, &spr_write_generic,
5278 0x00000000);
5279 /* XXX : not implemented */
5280 spr_register(env, SPR_UPMC5, "UPMC5",
5281 &spr_read_ureg, SPR_NOACCESS,
5282 &spr_read_ureg, SPR_NOACCESS,
5283 0x00000000);
5284 /* XXX : not implemented */
5285 spr_register(env, SPR_PMC6, "PMC6",
5286 SPR_NOACCESS, SPR_NOACCESS,
5287 &spr_read_generic, &spr_write_generic,
5288 0x00000000);
5289 /* XXX : not implemented */
5290 spr_register(env, SPR_UPMC6, "UPMC6",
5291 &spr_read_ureg, SPR_NOACCESS,
5292 &spr_read_ureg, SPR_NOACCESS,
5293 0x00000000);
5294 /* Memory management */
5295 gen_low_BATs(env);
5296 gen_74xx_soft_tlb(env, 128, 2);
5297 init_excp_7450(env);
5298 env->dcache_line_size = 32;
5299 env->icache_line_size = 32;
5300 /* Allocate hardware IRQ controller */
5301 ppc6xx_irq_init(env);
5302 }
5303
5304 /* PowerPC 7450 (aka G4) */
5305 #define POWERPC_INSNS_7450 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5306 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5307 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5308 PPC_FLOAT_STFIWX | \
5309 PPC_CACHE | PPC_CACHE_ICBI | \
5310 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5311 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5312 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5313 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5314 PPC_SEGMENT | PPC_EXTERN | \
5315 PPC_ALTIVEC)
5316 #define POWERPC_MSRM_7450 (0x000000000205FF77ULL)
5317 #define POWERPC_MMU_7450 (POWERPC_MMU_SOFT_74xx)
5318 #define POWERPC_EXCP_7450 (POWERPC_EXCP_74xx)
5319 #define POWERPC_INPUT_7450 (PPC_FLAGS_INPUT_6xx)
5320 #define POWERPC_BFDM_7450 (bfd_mach_ppc_7400)
5321 #define POWERPC_FLAG_7450 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5322 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5323 POWERPC_FLAG_BUS_CLK)
5324 #define check_pow_7450 check_pow_hid0
5325
5326 __attribute__ (( unused ))
5327 static void init_proc_7450 (CPUPPCState *env)
5328 {
5329 gen_spr_ne_601(env);
5330 gen_spr_7xx(env);
5331 /* Time base */
5332 gen_tbl(env);
5333 /* 74xx specific SPR */
5334 gen_spr_74xx(env);
5335 /* Level 3 cache control */
5336 gen_l3_ctrl(env);
5337 /* LDSTCR */
5338 /* XXX : not implemented */
5339 spr_register(env, SPR_LDSTCR, "LDSTCR",
5340 SPR_NOACCESS, SPR_NOACCESS,
5341 &spr_read_generic, &spr_write_generic,
5342 0x00000000);
5343 /* ICTRL */
5344 /* XXX : not implemented */
5345 spr_register(env, SPR_ICTRL, "ICTRL",
5346 SPR_NOACCESS, SPR_NOACCESS,
5347 &spr_read_generic, &spr_write_generic,
5348 0x00000000);
5349 /* MSSSR0 */
5350 /* XXX : not implemented */
5351 spr_register(env, SPR_MSSSR0, "MSSSR0",
5352 SPR_NOACCESS, SPR_NOACCESS,
5353 &spr_read_generic, &spr_write_generic,
5354 0x00000000);
5355 /* PMC */
5356 /* XXX : not implemented */
5357 spr_register(env, SPR_PMC5, "PMC5",
5358 SPR_NOACCESS, SPR_NOACCESS,
5359 &spr_read_generic, &spr_write_generic,
5360 0x00000000);
5361 /* XXX : not implemented */
5362 spr_register(env, SPR_UPMC5, "UPMC5",
5363 &spr_read_ureg, SPR_NOACCESS,
5364 &spr_read_ureg, SPR_NOACCESS,
5365 0x00000000);
5366 /* XXX : not implemented */
5367 spr_register(env, SPR_PMC6, "PMC6",
5368 SPR_NOACCESS, SPR_NOACCESS,
5369 &spr_read_generic, &spr_write_generic,
5370 0x00000000);
5371 /* XXX : not implemented */
5372 spr_register(env, SPR_UPMC6, "UPMC6",
5373 &spr_read_ureg, SPR_NOACCESS,
5374 &spr_read_ureg, SPR_NOACCESS,
5375 0x00000000);
5376 /* Memory management */
5377 gen_low_BATs(env);
5378 gen_74xx_soft_tlb(env, 128, 2);
5379 init_excp_7450(env);
5380 env->dcache_line_size = 32;
5381 env->icache_line_size = 32;
5382 /* Allocate hardware IRQ controller */
5383 ppc6xx_irq_init(env);
5384 }
5385
5386 /* PowerPC 7445 (aka G4) */
5387 #define POWERPC_INSNS_7445 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5388 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5389 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5390 PPC_FLOAT_STFIWX | \
5391 PPC_CACHE | PPC_CACHE_ICBI | \
5392 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5393 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5394 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5395 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5396 PPC_SEGMENT | PPC_EXTERN | \
5397 PPC_ALTIVEC)
5398 #define POWERPC_MSRM_7445 (0x000000000205FF77ULL)
5399 #define POWERPC_MMU_7445 (POWERPC_MMU_SOFT_74xx)
5400 #define POWERPC_EXCP_7445 (POWERPC_EXCP_74xx)
5401 #define POWERPC_INPUT_7445 (PPC_FLAGS_INPUT_6xx)
5402 #define POWERPC_BFDM_7445 (bfd_mach_ppc_7400)
5403 #define POWERPC_FLAG_7445 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5404 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5405 POWERPC_FLAG_BUS_CLK)
5406 #define check_pow_7445 check_pow_hid0
5407
5408 __attribute__ (( unused ))
5409 static void init_proc_7445 (CPUPPCState *env)
5410 {
5411 gen_spr_ne_601(env);
5412 gen_spr_7xx(env);
5413 /* Time base */
5414 gen_tbl(env);
5415 /* 74xx specific SPR */
5416 gen_spr_74xx(env);
5417 /* LDSTCR */
5418 /* XXX : not implemented */
5419 spr_register(env, SPR_LDSTCR, "LDSTCR",
5420 SPR_NOACCESS, SPR_NOACCESS,
5421 &spr_read_generic, &spr_write_generic,
5422 0x00000000);
5423 /* ICTRL */
5424 /* XXX : not implemented */
5425 spr_register(env, SPR_ICTRL, "ICTRL",
5426 SPR_NOACCESS, SPR_NOACCESS,
5427 &spr_read_generic, &spr_write_generic,
5428 0x00000000);
5429 /* MSSSR0 */
5430 /* XXX : not implemented */
5431 spr_register(env, SPR_MSSSR0, "MSSSR0",
5432 SPR_NOACCESS, SPR_NOACCESS,
5433 &spr_read_generic, &spr_write_generic,
5434 0x00000000);
5435 /* PMC */
5436 /* XXX : not implemented */
5437 spr_register(env, SPR_PMC5, "PMC5",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 &spr_read_generic, &spr_write_generic,
5440 0x00000000);
5441 /* XXX : not implemented */
5442 spr_register(env, SPR_UPMC5, "UPMC5",
5443 &spr_read_ureg, SPR_NOACCESS,
5444 &spr_read_ureg, SPR_NOACCESS,
5445 0x00000000);
5446 /* XXX : not implemented */
5447 spr_register(env, SPR_PMC6, "PMC6",
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_generic,
5450 0x00000000);
5451 /* XXX : not implemented */
5452 spr_register(env, SPR_UPMC6, "UPMC6",
5453 &spr_read_ureg, SPR_NOACCESS,
5454 &spr_read_ureg, SPR_NOACCESS,
5455 0x00000000);
5456 /* SPRGs */
5457 spr_register(env, SPR_SPRG4, "SPRG4",
5458 SPR_NOACCESS, SPR_NOACCESS,
5459 &spr_read_generic, &spr_write_generic,
5460 0x00000000);
5461 spr_register(env, SPR_USPRG4, "USPRG4",
5462 &spr_read_ureg, SPR_NOACCESS,
5463 &spr_read_ureg, SPR_NOACCESS,
5464 0x00000000);
5465 spr_register(env, SPR_SPRG5, "SPRG5",
5466 SPR_NOACCESS, SPR_NOACCESS,
5467 &spr_read_generic, &spr_write_generic,
5468 0x00000000);
5469 spr_register(env, SPR_USPRG5, "USPRG5",
5470 &spr_read_ureg, SPR_NOACCESS,
5471 &spr_read_ureg, SPR_NOACCESS,
5472 0x00000000);
5473 spr_register(env, SPR_SPRG6, "SPRG6",
5474 SPR_NOACCESS, SPR_NOACCESS,
5475 &spr_read_generic, &spr_write_generic,
5476 0x00000000);
5477 spr_register(env, SPR_USPRG6, "USPRG6",
5478 &spr_read_ureg, SPR_NOACCESS,
5479 &spr_read_ureg, SPR_NOACCESS,
5480 0x00000000);
5481 spr_register(env, SPR_SPRG7, "SPRG7",
5482 SPR_NOACCESS, SPR_NOACCESS,
5483 &spr_read_generic, &spr_write_generic,
5484 0x00000000);
5485 spr_register(env, SPR_USPRG7, "USPRG7",
5486 &spr_read_ureg, SPR_NOACCESS,
5487 &spr_read_ureg, SPR_NOACCESS,
5488 0x00000000);
5489 /* Memory management */
5490 gen_low_BATs(env);
5491 gen_high_BATs(env);
5492 gen_74xx_soft_tlb(env, 128, 2);
5493 init_excp_7450(env);
5494 env->dcache_line_size = 32;
5495 env->icache_line_size = 32;
5496 /* Allocate hardware IRQ controller */
5497 ppc6xx_irq_init(env);
5498 }
5499
5500 /* PowerPC 7455 (aka G4) */
5501 #define POWERPC_INSNS_7455 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5502 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5503 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5504 PPC_FLOAT_STFIWX | \
5505 PPC_CACHE | PPC_CACHE_ICBI | \
5506 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | \
5507 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5508 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5509 PPC_MEM_TLBIA | PPC_74xx_TLB | \
5510 PPC_SEGMENT | PPC_EXTERN | \
5511 PPC_ALTIVEC)
5512 #define POWERPC_MSRM_7455 (0x000000000205FF77ULL)
5513 #define POWERPC_MMU_7455 (POWERPC_MMU_SOFT_74xx)
5514 #define POWERPC_EXCP_7455 (POWERPC_EXCP_74xx)
5515 #define POWERPC_INPUT_7455 (PPC_FLAGS_INPUT_6xx)
5516 #define POWERPC_BFDM_7455 (bfd_mach_ppc_7400)
5517 #define POWERPC_FLAG_7455 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5518 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5519 POWERPC_FLAG_BUS_CLK)
5520 #define check_pow_7455 check_pow_hid0
5521
5522 __attribute__ (( unused ))
5523 static void init_proc_7455 (CPUPPCState *env)
5524 {
5525 gen_spr_ne_601(env);
5526 gen_spr_7xx(env);
5527 /* Time base */
5528 gen_tbl(env);
5529 /* 74xx specific SPR */
5530 gen_spr_74xx(env);
5531 /* Level 3 cache control */
5532 gen_l3_ctrl(env);
5533 /* LDSTCR */
5534 /* XXX : not implemented */
5535 spr_register(env, SPR_LDSTCR, "LDSTCR",
5536 SPR_NOACCESS, SPR_NOACCESS,
5537 &spr_read_generic, &spr_write_generic,
5538 0x00000000);
5539 /* ICTRL */
5540 /* XXX : not implemented */
5541 spr_register(env, SPR_ICTRL, "ICTRL",
5542 SPR_NOACCESS, SPR_NOACCESS,
5543 &spr_read_generic, &spr_write_generic,
5544 0x00000000);
5545 /* MSSSR0 */
5546 /* XXX : not implemented */
5547 spr_register(env, SPR_MSSSR0, "MSSSR0",
5548 SPR_NOACCESS, SPR_NOACCESS,
5549 &spr_read_generic, &spr_write_generic,
5550 0x00000000);
5551 /* PMC */
5552 /* XXX : not implemented */
5553 spr_register(env, SPR_PMC5, "PMC5",
5554 SPR_NOACCESS, SPR_NOACCESS,
5555 &spr_read_generic, &spr_write_generic,
5556 0x00000000);
5557 /* XXX : not implemented */
5558 spr_register(env, SPR_UPMC5, "UPMC5",
5559 &spr_read_ureg, SPR_NOACCESS,
5560 &spr_read_ureg, SPR_NOACCESS,
5561 0x00000000);
5562 /* XXX : not implemented */
5563 spr_register(env, SPR_PMC6, "PMC6",
5564 SPR_NOACCESS, SPR_NOACCESS,
5565 &spr_read_generic, &spr_write_generic,
5566 0x00000000);
5567 /* XXX : not implemented */
5568 spr_register(env, SPR_UPMC6, "UPMC6",
5569 &spr_read_ureg, SPR_NOACCESS,
5570 &spr_read_ureg, SPR_NOACCESS,
5571 0x00000000);
5572 /* SPRGs */
5573 spr_register(env, SPR_SPRG4, "SPRG4",
5574 SPR_NOACCESS, SPR_NOACCESS,
5575 &spr_read_generic, &spr_write_generic,
5576 0x00000000);
5577 spr_register(env, SPR_USPRG4, "USPRG4",
5578 &spr_read_ureg, SPR_NOACCESS,
5579 &spr_read_ureg, SPR_NOACCESS,
5580 0x00000000);
5581 spr_register(env, SPR_SPRG5, "SPRG5",
5582 SPR_NOACCESS, SPR_NOACCESS,
5583 &spr_read_generic, &spr_write_generic,
5584 0x00000000);
5585 spr_register(env, SPR_USPRG5, "USPRG5",
5586 &spr_read_ureg, SPR_NOACCESS,
5587 &spr_read_ureg, SPR_NOACCESS,
5588 0x00000000);
5589 spr_register(env, SPR_SPRG6, "SPRG6",
5590 SPR_NOACCESS, SPR_NOACCESS,
5591 &spr_read_generic, &spr_write_generic,
5592 0x00000000);
5593 spr_register(env, SPR_USPRG6, "USPRG6",
5594 &spr_read_ureg, SPR_NOACCESS,
5595 &spr_read_ureg, SPR_NOACCESS,
5596 0x00000000);
5597 spr_register(env, SPR_SPRG7, "SPRG7",
5598 SPR_NOACCESS, SPR_NOACCESS,
5599 &spr_read_generic, &spr_write_generic,
5600 0x00000000);
5601 spr_register(env, SPR_USPRG7, "USPRG7",
5602 &spr_read_ureg, SPR_NOACCESS,
5603 &spr_read_ureg, SPR_NOACCESS,
5604 0x00000000);
5605 /* Memory management */
5606 gen_low_BATs(env);
5607 gen_high_BATs(env);
5608 gen_74xx_soft_tlb(env, 128, 2);
5609 init_excp_7450(env);
5610 env->dcache_line_size = 32;
5611 env->icache_line_size = 32;
5612 /* Allocate hardware IRQ controller */
5613 ppc6xx_irq_init(env);
5614 }
5615
5616 #if defined (TARGET_PPC64)
5617 /* PowerPC 970 */
5618 #define POWERPC_INSNS_970 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5619 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5620 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5621 PPC_FLOAT_STFIWX | \
5622 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5623 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5624 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5625 PPC_64B | PPC_ALTIVEC | \
5626 PPC_SEGMENT_64B | PPC_SLBI)
5627 #define POWERPC_MSRM_970 (0x900000000204FF36ULL)
5628 #define POWERPC_MMU_970 (POWERPC_MMU_64B)
5629 //#define POWERPC_EXCP_970 (POWERPC_EXCP_970)
5630 #define POWERPC_INPUT_970 (PPC_FLAGS_INPUT_970)
5631 #define POWERPC_BFDM_970 (bfd_mach_ppc64)
5632 #define POWERPC_FLAG_970 (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5633 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5634 POWERPC_FLAG_BUS_CLK)
5635
5636 #if defined(CONFIG_USER_ONLY)
5637 #define POWERPC970_HID5_INIT 0x00000080
5638 #else
5639 #define POWERPC970_HID5_INIT 0x00000000
5640 #endif
5641
5642 static int check_pow_970 (CPUPPCState *env)
5643 {
5644 if (env->spr[SPR_HID0] & 0x00600000)
5645 return 1;
5646
5647 return 0;
5648 }
5649
5650 static void init_proc_970 (CPUPPCState *env)
5651 {
5652 gen_spr_ne_601(env);
5653 gen_spr_7xx(env);
5654 /* Time base */
5655 gen_tbl(env);
5656 /* Hardware implementation registers */
5657 /* XXX : not implemented */
5658 spr_register(env, SPR_HID0, "HID0",
5659 SPR_NOACCESS, SPR_NOACCESS,
5660 &spr_read_generic, &spr_write_clear,
5661 0x60000000);
5662 /* XXX : not implemented */
5663 spr_register(env, SPR_HID1, "HID1",
5664 SPR_NOACCESS, SPR_NOACCESS,
5665 &spr_read_generic, &spr_write_generic,
5666 0x00000000);
5667 /* XXX : not implemented */
5668 spr_register(env, SPR_750FX_HID2, "HID2",
5669 SPR_NOACCESS, SPR_NOACCESS,
5670 &spr_read_generic, &spr_write_generic,
5671 0x00000000);
5672 /* XXX : not implemented */
5673 spr_register(env, SPR_970_HID5, "HID5",
5674 SPR_NOACCESS, SPR_NOACCESS,
5675 &spr_read_generic, &spr_write_generic,
5676 POWERPC970_HID5_INIT);
5677 /* XXX : not implemented */
5678 spr_register(env, SPR_L2CR, "L2CR",
5679 SPR_NOACCESS, SPR_NOACCESS,
5680 &spr_read_generic, &spr_write_generic,
5681 0x00000000);
5682 /* Memory management */
5683 /* XXX: not correct */
5684 gen_low_BATs(env);
5685 /* XXX : not implemented */
5686 spr_register(env, SPR_MMUCFG, "MMUCFG",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, SPR_NOACCESS,
5689 0x00000000); /* TOFIX */
5690 /* XXX : not implemented */
5691 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5692 SPR_NOACCESS, SPR_NOACCESS,
5693 &spr_read_generic, &spr_write_generic,
5694 0x00000000); /* TOFIX */
5695 spr_register(env, SPR_HIOR, "SPR_HIOR",
5696 SPR_NOACCESS, SPR_NOACCESS,
5697 &spr_read_generic, &spr_write_generic,
5698 0xFFF00000); /* XXX: This is a hack */
5699 #if !defined(CONFIG_USER_ONLY)
5700 env->slb_nr = 32;
5701 #endif
5702 init_excp_970(env);
5703 env->dcache_line_size = 128;
5704 env->icache_line_size = 128;
5705 /* Allocate hardware IRQ controller */
5706 ppc970_irq_init(env);
5707 }
5708
5709 /* PowerPC 970FX (aka G5) */
5710 #define POWERPC_INSNS_970FX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5711 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5712 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5713 PPC_FLOAT_STFIWX | \
5714 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5715 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5716 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5717 PPC_64B | PPC_ALTIVEC | \
5718 PPC_SEGMENT_64B | PPC_SLBI)
5719 #define POWERPC_MSRM_970FX (0x800000000204FF36ULL)
5720 #define POWERPC_MMU_970FX (POWERPC_MMU_64B)
5721 #define POWERPC_EXCP_970FX (POWERPC_EXCP_970)
5722 #define POWERPC_INPUT_970FX (PPC_FLAGS_INPUT_970)
5723 #define POWERPC_BFDM_970FX (bfd_mach_ppc64)
5724 #define POWERPC_FLAG_970FX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5725 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5726 POWERPC_FLAG_BUS_CLK)
5727
5728 static int check_pow_970FX (CPUPPCState *env)
5729 {
5730 if (env->spr[SPR_HID0] & 0x00600000)
5731 return 1;
5732
5733 return 0;
5734 }
5735
5736 static void init_proc_970FX (CPUPPCState *env)
5737 {
5738 gen_spr_ne_601(env);
5739 gen_spr_7xx(env);
5740 /* Time base */
5741 gen_tbl(env);
5742 /* Hardware implementation registers */
5743 /* XXX : not implemented */
5744 spr_register(env, SPR_HID0, "HID0",
5745 SPR_NOACCESS, SPR_NOACCESS,
5746 &spr_read_generic, &spr_write_clear,
5747 0x60000000);
5748 /* XXX : not implemented */
5749 spr_register(env, SPR_HID1, "HID1",
5750 SPR_NOACCESS, SPR_NOACCESS,
5751 &spr_read_generic, &spr_write_generic,
5752 0x00000000);
5753 /* XXX : not implemented */
5754 spr_register(env, SPR_750FX_HID2, "HID2",
5755 SPR_NOACCESS, SPR_NOACCESS,
5756 &spr_read_generic, &spr_write_generic,
5757 0x00000000);
5758 /* XXX : not implemented */
5759 spr_register(env, SPR_970_HID5, "HID5",
5760 SPR_NOACCESS, SPR_NOACCESS,
5761 &spr_read_generic, &spr_write_generic,
5762 POWERPC970_HID5_INIT);
5763 /* XXX : not implemented */
5764 spr_register(env, SPR_L2CR, "L2CR",
5765 SPR_NOACCESS, SPR_NOACCESS,
5766 &spr_read_generic, &spr_write_generic,
5767 0x00000000);
5768 /* Memory management */
5769 /* XXX: not correct */
5770 gen_low_BATs(env);
5771 /* XXX : not implemented */
5772 spr_register(env, SPR_MMUCFG, "MMUCFG",
5773 SPR_NOACCESS, SPR_NOACCESS,
5774 &spr_read_generic, SPR_NOACCESS,
5775 0x00000000); /* TOFIX */
5776 /* XXX : not implemented */
5777 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5778 SPR_NOACCESS, SPR_NOACCESS,
5779 &spr_read_generic, &spr_write_generic,
5780 0x00000000); /* TOFIX */
5781 spr_register(env, SPR_HIOR, "SPR_HIOR",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 &spr_read_generic, &spr_write_generic,
5784 0xFFF00000); /* XXX: This is a hack */
5785 #if !defined(CONFIG_USER_ONLY)
5786 env->slb_nr = 32;
5787 #endif
5788 init_excp_970(env);
5789 env->dcache_line_size = 128;
5790 env->icache_line_size = 128;
5791 /* Allocate hardware IRQ controller */
5792 ppc970_irq_init(env);
5793 }
5794
5795 /* PowerPC 970 GX */
5796 #define POWERPC_INSNS_970GX (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5797 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5798 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5799 PPC_FLOAT_STFIWX | \
5800 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5801 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5802 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5803 PPC_64B | PPC_ALTIVEC | \
5804 PPC_SEGMENT_64B | PPC_SLBI)
5805 #define POWERPC_MSRM_970GX (0x800000000204FF36ULL)
5806 #define POWERPC_MMU_970GX (POWERPC_MMU_64B)
5807 #define POWERPC_EXCP_970GX (POWERPC_EXCP_970)
5808 #define POWERPC_INPUT_970GX (PPC_FLAGS_INPUT_970)
5809 #define POWERPC_BFDM_970GX (bfd_mach_ppc64)
5810 #define POWERPC_FLAG_970GX (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5811 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5812 POWERPC_FLAG_BUS_CLK)
5813
5814 static int check_pow_970GX (CPUPPCState *env)
5815 {
5816 if (env->spr[SPR_HID0] & 0x00600000)
5817 return 1;
5818
5819 return 0;
5820 }
5821
5822 static void init_proc_970GX (CPUPPCState *env)
5823 {
5824 gen_spr_ne_601(env);
5825 gen_spr_7xx(env);
5826 /* Time base */
5827 gen_tbl(env);
5828 /* Hardware implementation registers */
5829 /* XXX : not implemented */
5830 spr_register(env, SPR_HID0, "HID0",
5831 SPR_NOACCESS, SPR_NOACCESS,
5832 &spr_read_generic, &spr_write_clear,
5833 0x60000000);
5834 /* XXX : not implemented */
5835 spr_register(env, SPR_HID1, "HID1",
5836 SPR_NOACCESS, SPR_NOACCESS,
5837 &spr_read_generic, &spr_write_generic,
5838 0x00000000);
5839 /* XXX : not implemented */
5840 spr_register(env, SPR_750FX_HID2, "HID2",
5841 SPR_NOACCESS, SPR_NOACCESS,
5842 &spr_read_generic, &spr_write_generic,
5843 0x00000000);
5844 /* XXX : not implemented */
5845 spr_register(env, SPR_970_HID5, "HID5",
5846 SPR_NOACCESS, SPR_NOACCESS,
5847 &spr_read_generic, &spr_write_generic,
5848 POWERPC970_HID5_INIT);
5849 /* XXX : not implemented */
5850 spr_register(env, SPR_L2CR, "L2CR",
5851 SPR_NOACCESS, SPR_NOACCESS,
5852 &spr_read_generic, &spr_write_generic,
5853 0x00000000);
5854 /* Memory management */
5855 /* XXX: not correct */
5856 gen_low_BATs(env);
5857 /* XXX : not implemented */
5858 spr_register(env, SPR_MMUCFG, "MMUCFG",
5859 SPR_NOACCESS, SPR_NOACCESS,
5860 &spr_read_generic, SPR_NOACCESS,
5861 0x00000000); /* TOFIX */
5862 /* XXX : not implemented */
5863 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5864 SPR_NOACCESS, SPR_NOACCESS,
5865 &spr_read_generic, &spr_write_generic,
5866 0x00000000); /* TOFIX */
5867 spr_register(env, SPR_HIOR, "SPR_HIOR",
5868 SPR_NOACCESS, SPR_NOACCESS,
5869 &spr_read_generic, &spr_write_generic,
5870 0xFFF00000); /* XXX: This is a hack */
5871 #if !defined(CONFIG_USER_ONLY)
5872 env->slb_nr = 32;
5873 #endif
5874 init_excp_970(env);
5875 env->dcache_line_size = 128;
5876 env->icache_line_size = 128;
5877 /* Allocate hardware IRQ controller */
5878 ppc970_irq_init(env);
5879 }
5880
5881 /* PowerPC 970 MP */
5882 #define POWERPC_INSNS_970MP (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5883 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5884 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5885 PPC_FLOAT_STFIWX | \
5886 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
5887 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5888 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5889 PPC_64B | PPC_ALTIVEC | \
5890 PPC_SEGMENT_64B | PPC_SLBI)
5891 #define POWERPC_MSRM_970MP (0x900000000204FF36ULL)
5892 #define POWERPC_MMU_970MP (POWERPC_MMU_64B)
5893 #define POWERPC_EXCP_970MP (POWERPC_EXCP_970)
5894 #define POWERPC_INPUT_970MP (PPC_FLAGS_INPUT_970)
5895 #define POWERPC_BFDM_970MP (bfd_mach_ppc64)
5896 #define POWERPC_FLAG_970MP (POWERPC_FLAG_VRE | POWERPC_FLAG_SE | \
5897 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | \
5898 POWERPC_FLAG_BUS_CLK)
5899
5900 static int check_pow_970MP (CPUPPCState *env)
5901 {
5902 if (env->spr[SPR_HID0] & 0x01C00000)
5903 return 1;
5904
5905 return 0;
5906 }
5907
5908 static void init_proc_970MP (CPUPPCState *env)
5909 {
5910 gen_spr_ne_601(env);
5911 gen_spr_7xx(env);
5912 /* Time base */
5913 gen_tbl(env);
5914 /* Hardware implementation registers */
5915 /* XXX : not implemented */
5916 spr_register(env, SPR_HID0, "HID0",
5917 SPR_NOACCESS, SPR_NOACCESS,
5918 &spr_read_generic, &spr_write_clear,
5919 0x60000000);
5920 /* XXX : not implemented */
5921 spr_register(env, SPR_HID1, "HID1",
5922 SPR_NOACCESS, SPR_NOACCESS,
5923 &spr_read_generic, &spr_write_generic,
5924 0x00000000);
5925 /* XXX : not implemented */
5926 spr_register(env, SPR_750FX_HID2, "HID2",
5927 SPR_NOACCESS, SPR_NOACCESS,
5928 &spr_read_generic, &spr_write_generic,
5929 0x00000000);
5930 /* XXX : not implemented */
5931 spr_register(env, SPR_970_HID5, "HID5",
5932 SPR_NOACCESS, SPR_NOACCESS,
5933 &spr_read_generic, &spr_write_generic,
5934 POWERPC970_HID5_INIT);
5935 /* XXX : not implemented */
5936 spr_register(env, SPR_L2CR, "L2CR",
5937 SPR_NOACCESS, SPR_NOACCESS,
5938 &spr_read_generic, &spr_write_generic,
5939 0x00000000);
5940 /* Memory management */
5941 /* XXX: not correct */
5942 gen_low_BATs(env);
5943 /* XXX : not implemented */
5944 spr_register(env, SPR_MMUCFG, "MMUCFG",
5945 SPR_NOACCESS, SPR_NOACCESS,
5946 &spr_read_generic, SPR_NOACCESS,
5947 0x00000000); /* TOFIX */
5948 /* XXX : not implemented */
5949 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
5950 SPR_NOACCESS, SPR_NOACCESS,
5951 &spr_read_generic, &spr_write_generic,
5952 0x00000000); /* TOFIX */
5953 spr_register(env, SPR_HIOR, "SPR_HIOR",
5954 SPR_NOACCESS, SPR_NOACCESS,
5955 &spr_read_generic, &spr_write_generic,
5956 0xFFF00000); /* XXX: This is a hack */
5957 #if !defined(CONFIG_USER_ONLY)
5958 env->slb_nr = 32;
5959 #endif
5960 init_excp_970(env);
5961 env->dcache_line_size = 128;
5962 env->icache_line_size = 128;
5963 /* Allocate hardware IRQ controller */
5964 ppc970_irq_init(env);
5965 }
5966
5967 /* PowerPC 620 */
5968 #define POWERPC_INSNS_620 (PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | \
5969 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
5970 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
5971 PPC_FLOAT_STFIWX | \
5972 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
5973 PPC_MEM_SYNC | PPC_MEM_EIEIO | \
5974 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
5975 PPC_SEGMENT | PPC_EXTERN | \
5976 PPC_64B | PPC_SLBI)
5977 #define POWERPC_MSRM_620 (0x800000000005FF77ULL)
5978 //#define POWERPC_MMU_620 (POWERPC_MMU_620)
5979 #define POWERPC_EXCP_620 (POWERPC_EXCP_970)
5980 #define POWERPC_INPUT_620 (PPC_FLAGS_INPUT_6xx)
5981 #define POWERPC_BFDM_620 (bfd_mach_ppc64)
5982 #define POWERPC_FLAG_620 (POWERPC_FLAG_SE | POWERPC_FLAG_BE | \
5983 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK)
5984 #define check_pow_620 check_pow_nocheck /* Check this */
5985
5986 __attribute__ (( unused ))
5987 static void init_proc_620 (CPUPPCState *env)
5988 {
5989 gen_spr_ne_601(env);
5990 gen_spr_620(env);
5991 /* Time base */
5992 gen_tbl(env);
5993 /* Hardware implementation registers */
5994 /* XXX : not implemented */
5995 spr_register(env, SPR_HID0, "HID0",
5996 SPR_NOACCESS, SPR_NOACCESS,
5997 &spr_read_generic, &spr_write_generic,
5998 0x00000000);
5999 /* Memory management */
6000 gen_low_BATs(env);
6001 init_excp_620(env);
6002 env->dcache_line_size = 64;
6003 env->icache_line_size = 64;
6004 /* Allocate hardware IRQ controller */
6005 ppc6xx_irq_init(env);
6006 }
6007 #endif /* defined (TARGET_PPC64) */
6008
6009 /* Default 32 bits PowerPC target will be 604 */
6010 #define CPU_POWERPC_PPC32 CPU_POWERPC_604
6011 #define POWERPC_INSNS_PPC32 POWERPC_INSNS_604
6012 #define POWERPC_MSRM_PPC32 POWERPC_MSRM_604
6013 #define POWERPC_MMU_PPC32 POWERPC_MMU_604
6014 #define POWERPC_EXCP_PPC32 POWERPC_EXCP_604
6015 #define POWERPC_INPUT_PPC32 POWERPC_INPUT_604
6016 #define POWERPC_BFDM_PPC32 POWERPC_BFDM_604
6017 #define POWERPC_FLAG_PPC32 POWERPC_FLAG_604
6018 #define check_pow_PPC32 check_pow_604
6019 #define init_proc_PPC32 init_proc_604
6020
6021 /* Default 64 bits PowerPC target will be 970 FX */
6022 #define CPU_POWERPC_PPC64 CPU_POWERPC_970FX
6023 #define POWERPC_INSNS_PPC64 POWERPC_INSNS_970FX
6024 #define POWERPC_MSRM_PPC64 POWERPC_MSRM_970FX
6025 #define POWERPC_MMU_PPC64 POWERPC_MMU_970FX
6026 #define POWERPC_EXCP_PPC64 POWERPC_EXCP_970FX
6027 #define POWERPC_INPUT_PPC64 POWERPC_INPUT_970FX
6028 #define POWERPC_BFDM_PPC64 POWERPC_BFDM_970FX
6029 #define POWERPC_FLAG_PPC64 POWERPC_FLAG_970FX
6030 #define check_pow_PPC64 check_pow_970FX
6031 #define init_proc_PPC64 init_proc_970FX
6032
6033 /* Default PowerPC target will be PowerPC 32 */
6034 #if defined (TARGET_PPC64) && 0 // XXX: TODO
6035 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC64
6036 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
6037 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC64
6038 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC64
6039 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC64
6040 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
6041 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC64
6042 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC64
6043 #define check_pow_DEFAULT check_pow_PPC64
6044 #define init_proc_DEFAULT init_proc_PPC64
6045 #else
6046 #define CPU_POWERPC_DEFAULT CPU_POWERPC_PPC32
6047 #define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
6048 #define POWERPC_MSRM_DEFAULT POWERPC_MSRM_PPC32
6049 #define POWERPC_MMU_DEFAULT POWERPC_MMU_PPC32
6050 #define POWERPC_EXCP_DEFAULT POWERPC_EXCP_PPC32
6051 #define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
6052 #define POWERPC_BFDM_DEFAULT POWERPC_BFDM_PPC32
6053 #define POWERPC_FLAG_DEFAULT POWERPC_FLAG_PPC32
6054 #define check_pow_DEFAULT check_pow_PPC32
6055 #define init_proc_DEFAULT init_proc_PPC32
6056 #endif
6057
6058 /*****************************************************************************/
6059 /* PVR definitions for most known PowerPC */
6060 enum {
6061 /* PowerPC 401 family */
6062 /* Generic PowerPC 401 */
6063 #define CPU_POWERPC_401 CPU_POWERPC_401G2
6064 /* PowerPC 401 cores */
6065 CPU_POWERPC_401A1 = 0x00210000,
6066 CPU_POWERPC_401B2 = 0x00220000,
6067 #if 0
6068 CPU_POWERPC_401B3 = xxx,
6069 #endif
6070 CPU_POWERPC_401C2 = 0x00230000,
6071 CPU_POWERPC_401D2 = 0x00240000,
6072 CPU_POWERPC_401E2 = 0x00250000,
6073 CPU_POWERPC_401F2 = 0x00260000,
6074 CPU_POWERPC_401G2 = 0x00270000,
6075 /* PowerPC 401 microcontrolers */
6076 #if 0
6077 CPU_POWERPC_401GF = xxx,
6078 #endif
6079 #define CPU_POWERPC_IOP480 CPU_POWERPC_401B2
6080 /* IBM Processor for Network Resources */
6081 CPU_POWERPC_COBRA = 0x10100000, /* XXX: 405 ? */
6082 #if 0
6083 CPU_POWERPC_XIPCHIP = xxx,
6084 #endif
6085 /* PowerPC 403 family */
6086 /* Generic PowerPC 403 */
6087 #define CPU_POWERPC_403 CPU_POWERPC_403GC
6088 /* PowerPC 403 microcontrollers */
6089 CPU_POWERPC_403GA = 0x00200011,
6090 CPU_POWERPC_403GB = 0x00200100,
6091 CPU_POWERPC_403GC = 0x00200200,
6092 CPU_POWERPC_403GCX = 0x00201400,
6093 #if 0
6094 CPU_POWERPC_403GP = xxx,
6095 #endif
6096 /* PowerPC 405 family */
6097 /* Generic PowerPC 405 */
6098 #define CPU_POWERPC_405 CPU_POWERPC_405D4
6099 /* PowerPC 405 cores */
6100 #if 0
6101 CPU_POWERPC_405A3 = xxx,
6102 #endif
6103 #if 0
6104 CPU_POWERPC_405A4 = xxx,
6105 #endif
6106 #if 0
6107 CPU_POWERPC_405B3 = xxx,
6108 #endif
6109 #if 0
6110 CPU_POWERPC_405B4 = xxx,
6111 #endif
6112 #if 0
6113 CPU_POWERPC_405C3 = xxx,
6114 #endif
6115 #if 0
6116 CPU_POWERPC_405C4 = xxx,
6117 #endif
6118 CPU_POWERPC_405D2 = 0x20010000,
6119 #if 0
6120 CPU_POWERPC_405D3 = xxx,
6121 #endif
6122 CPU_POWERPC_405D4 = 0x41810000,
6123 #if 0
6124 CPU_POWERPC_405D5 = xxx,
6125 #endif
6126 #if 0
6127 CPU_POWERPC_405E4 = xxx,
6128 #endif
6129 #if 0
6130 CPU_POWERPC_405F4 = xxx,
6131 #endif
6132 #if 0
6133 CPU_POWERPC_405F5 = xxx,
6134 #endif
6135 #if 0
6136 CPU_POWERPC_405F6 = xxx,
6137 #endif
6138 /* PowerPC 405 microcontrolers */
6139 /* XXX: missing 0x200108a0 */
6140 #define CPU_POWERPC_405CR CPU_POWERPC_405CRc
6141 CPU_POWERPC_405CRa = 0x40110041,
6142 CPU_POWERPC_405CRb = 0x401100C5,
6143 CPU_POWERPC_405CRc = 0x40110145,
6144 CPU_POWERPC_405EP = 0x51210950,
6145 #if 0
6146 CPU_POWERPC_405EXr = xxx,
6147 #endif
6148 CPU_POWERPC_405EZ = 0x41511460, /* 0x51210950 ? */
6149 #if 0
6150 CPU_POWERPC_405FX = xxx,
6151 #endif
6152 #define CPU_POWERPC_405GP CPU_POWERPC_405GPd
6153 CPU_POWERPC_405GPa = 0x40110000,
6154 CPU_POWERPC_405GPb = 0x40110040,
6155 CPU_POWERPC_405GPc = 0x40110082,
6156 CPU_POWERPC_405GPd = 0x401100C4,
6157 #define CPU_POWERPC_405GPe CPU_POWERPC_405CRc
6158 CPU_POWERPC_405GPR = 0x50910951,
6159 #if 0
6160 CPU_POWERPC_405H = xxx,
6161 #endif
6162 #if 0
6163 CPU_POWERPC_405L = xxx,
6164 #endif
6165 CPU_POWERPC_405LP = 0x41F10000,
6166 #if 0
6167 CPU_POWERPC_405PM = xxx,
6168 #endif
6169 #if 0
6170 CPU_POWERPC_405PS = xxx,
6171 #endif
6172 #if 0
6173 CPU_POWERPC_405S = xxx,
6174 #endif
6175 /* IBM network processors */
6176 CPU_POWERPC_NPE405H = 0x414100C0,
6177 CPU_POWERPC_NPE405H2 = 0x41410140,
6178 CPU_POWERPC_NPE405L = 0x416100C0,
6179 CPU_POWERPC_NPE4GS3 = 0x40B10000,
6180 #if 0
6181 CPU_POWERPC_NPCxx1 = xxx,
6182 #endif
6183 #if 0
6184 CPU_POWERPC_NPR161 = xxx,
6185 #endif
6186 #if 0
6187 CPU_POWERPC_LC77700 = xxx,
6188 #endif
6189 /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
6190 #if 0
6191 CPU_POWERPC_STB01000 = xxx,
6192 #endif
6193 #if 0
6194 CPU_POWERPC_STB01010 = xxx,
6195 #endif
6196 #if 0
6197 CPU_POWERPC_STB0210 = xxx, /* 401B3 */
6198 #endif
6199 CPU_POWERPC_STB03 = 0x40310000, /* 0x40130000 ? */
6200 #if 0
6201 CPU_POWERPC_STB043 = xxx,
6202 #endif
6203 #if 0
6204 CPU_POWERPC_STB045 = xxx,
6205 #endif
6206 CPU_POWERPC_STB04 = 0x41810000,
6207 CPU_POWERPC_STB25 = 0x51510950,
6208 #if 0
6209 CPU_POWERPC_STB130 = xxx,
6210 #endif
6211 /* Xilinx cores */
6212 CPU_POWERPC_X2VP4 = 0x20010820,
6213 #define CPU_POWERPC_X2VP7 CPU_POWERPC_X2VP4
6214 CPU_POWERPC_X2VP20 = 0x20010860,
6215 #define CPU_POWERPC_X2VP50 CPU_POWERPC_X2VP20
6216 #if 0
6217 CPU_POWERPC_ZL10310 = xxx,
6218 #endif
6219 #if 0
6220 CPU_POWERPC_ZL10311 = xxx,
6221 #endif
6222 #if 0
6223 CPU_POWERPC_ZL10320 = xxx,
6224 #endif
6225 #if 0
6226 CPU_POWERPC_ZL10321 = xxx,
6227 #endif
6228 /* PowerPC 440 family */
6229 /* Generic PowerPC 440 */
6230 #define CPU_POWERPC_440 CPU_POWERPC_440GXf
6231 /* PowerPC 440 cores */
6232 #if 0
6233 CPU_POWERPC_440A4 = xxx,
6234 #endif
6235 #if 0
6236 CPU_POWERPC_440A5 = xxx,
6237 #endif
6238 #if 0
6239 CPU_POWERPC_440B4 = xxx,
6240 #endif
6241 #if 0
6242 CPU_POWERPC_440F5 = xxx,
6243 #endif
6244 #if 0
6245 CPU_POWERPC_440G5 = xxx,
6246 #endif
6247 #if 0
6248 CPU_POWERPC_440H4 = xxx,
6249 #endif
6250 #if 0
6251 CPU_POWERPC_440H6 = xxx,
6252 #endif
6253 /* PowerPC 440 microcontrolers */
6254 #define CPU_POWERPC_440EP CPU_POWERPC_440EPb
6255 CPU_POWERPC_440EPa = 0x42221850,
6256 CPU_POWERPC_440EPb = 0x422218D3,
6257 #define CPU_POWERPC_440GP CPU_POWERPC_440GPc
6258 CPU_POWERPC_440GPb = 0x40120440,
6259 CPU_POWERPC_440GPc = 0x40120481,
6260 #define CPU_POWERPC_440GR CPU_POWERPC_440GRa
6261 #define CPU_POWERPC_440GRa CPU_POWERPC_440EPb
6262 CPU_POWERPC_440GRX = 0x200008D0,
6263 #define CPU_POWERPC_440EPX CPU_POWERPC_440GRX
6264 #define CPU_POWERPC_440GX CPU_POWERPC_440GXf
6265 CPU_POWERPC_440GXa = 0x51B21850,
6266 CPU_POWERPC_440GXb = 0x51B21851,
6267 CPU_POWERPC_440GXc = 0x51B21892,
6268 CPU_POWERPC_440GXf = 0x51B21894,
6269 #if 0
6270 CPU_POWERPC_440S = xxx,
6271 #endif
6272 CPU_POWERPC_440SP = 0x53221850,
6273 CPU_POWERPC_440SP2 = 0x53221891,
6274 CPU_POWERPC_440SPE = 0x53421890,
6275 /* PowerPC 460 family */
6276 #if 0
6277 /* Generic PowerPC 464 */
6278 #define CPU_POWERPC_464 CPU_POWERPC_464H90
6279 #endif
6280 /* PowerPC 464 microcontrolers */
6281 #if 0
6282 CPU_POWERPC_464H90 = xxx,
6283 #endif
6284 #if 0
6285 CPU_POWERPC_464H90FP = xxx,
6286 #endif
6287 /* Freescale embedded PowerPC cores */
6288 /* PowerPC MPC 5xx cores (aka RCPU) */
6289 CPU_POWERPC_MPC5xx = 0x00020020,
6290 #define CPU_POWERPC_MGT560 CPU_POWERPC_MPC5xx
6291 #define CPU_POWERPC_MPC509 CPU_POWERPC_MPC5xx
6292 #define CPU_POWERPC_MPC533 CPU_POWERPC_MPC5xx
6293 #define CPU_POWERPC_MPC534 CPU_POWERPC_MPC5xx
6294 #define CPU_POWERPC_MPC555 CPU_POWERPC_MPC5xx
6295 #define CPU_POWERPC_MPC556 CPU_POWERPC_MPC5xx
6296 #define CPU_POWERPC_MPC560 CPU_POWERPC_MPC5xx
6297 #define CPU_POWERPC_MPC561 CPU_POWERPC_MPC5xx
6298 #define CPU_POWERPC_MPC562 CPU_POWERPC_MPC5xx
6299 #define CPU_POWERPC_MPC563 CPU_POWERPC_MPC5xx
6300 #define CPU_POWERPC_MPC564 CPU_POWERPC_MPC5xx
6301 #define CPU_POWERPC_MPC565 CPU_POWERPC_MPC5xx
6302 #define CPU_POWERPC_MPC566 CPU_POWERPC_MPC5xx
6303 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
6304 CPU_POWERPC_MPC8xx = 0x00500000,
6305 #define CPU_POWERPC_MGT823 CPU_POWERPC_MPC8xx
6306 #define CPU_POWERPC_MPC821 CPU_POWERPC_MPC8xx
6307 #define CPU_POWERPC_MPC823 CPU_POWERPC_MPC8xx
6308 #define CPU_POWERPC_MPC850 CPU_POWERPC_MPC8xx
6309 #define CPU_POWERPC_MPC852T CPU_POWERPC_MPC8xx
6310 #define CPU_POWERPC_MPC855T CPU_POWERPC_MPC8xx
6311 #define CPU_POWERPC_MPC857 CPU_POWERPC_MPC8xx
6312 #define CPU_POWERPC_MPC859 CPU_POWERPC_MPC8xx
6313 #define CPU_POWERPC_MPC860 CPU_POWERPC_MPC8xx
6314 #define CPU_POWERPC_MPC862 CPU_POWERPC_MPC8xx
6315 #define CPU_POWERPC_MPC866 CPU_POWERPC_MPC8xx
6316 #define CPU_POWERPC_MPC870 CPU_POWERPC_MPC8xx
6317 #define CPU_POWERPC_MPC875 CPU_POWERPC_MPC8xx
6318 #define CPU_POWERPC_MPC880 CPU_POWERPC_MPC8xx
6319 #define CPU_POWERPC_MPC885 CPU_POWERPC_MPC8xx
6320 /* G2 cores (aka PowerQUICC-II) */
6321 CPU_POWERPC_G2 = 0x00810011,
6322 CPU_POWERPC_G2H4 = 0x80811010,
6323 CPU_POWERPC_G2gp = 0x80821010,
6324 CPU_POWERPC_G2ls = 0x90810010,
6325 CPU_POWERPC_MPC603 = 0x00810100,
6326 CPU_POWERPC_G2_HIP3 = 0x00810101,
6327 CPU_POWERPC_G2_HIP4 = 0x80811014,
6328 /* G2_LE core (aka PowerQUICC-II) */
6329 CPU_POWERPC_G2LE = 0x80820010,
6330 CPU_POWERPC_G2LEgp = 0x80822010,
6331 CPU_POWERPC_G2LEls = 0xA0822010,
6332 CPU_POWERPC_G2LEgp1 = 0x80822011,
6333 CPU_POWERPC_G2LEgp3 = 0x80822013,
6334 /* MPC52xx microcontrollers */
6335 /* XXX: MPC 5121 ? */
6336 #define CPU_POWERPC_MPC52xx CPU_POWERPC_MPC5200
6337 #define CPU_POWERPC_MPC5200 CPU_POWERPC_MPC5200_v12
6338 #define CPU_POWERPC_MPC5200_v10 CPU_POWERPC_G2LEgp1
6339 #define CPU_POWERPC_MPC5200_v11 CPU_POWERPC_G2LEgp1
6340 #define CPU_POWERPC_MPC5200_v12 CPU_POWERPC_G2LEgp1
6341 #define CPU_POWERPC_MPC5200B CPU_POWERPC_MPC5200B_v21
6342 #define CPU_POWERPC_MPC5200B_v20 CPU_POWERPC_G2LEgp1
6343 #define CPU_POWERPC_MPC5200B_v21 CPU_POWERPC_G2LEgp1
6344 /* MPC82xx microcontrollers */
6345 #define CPU_POWERPC_MPC82xx CPU_POWERPC_MPC8280
6346 #define CPU_POWERPC_MPC8240 CPU_POWERPC_MPC603
6347 #define CPU_POWERPC_MPC8241 CPU_POWERPC_G2_HIP4
6348 #define CPU_POWERPC_MPC8245 CPU_POWERPC_G2_HIP4
6349 #define CPU_POWERPC_MPC8247 CPU_POWERPC_G2LEgp3
6350 #define CPU_POWERPC_MPC8248 CPU_POWERPC_G2LEgp3
6351 #define CPU_POWERPC_MPC8250 CPU_POWERPC_MPC8250_HiP4
6352 #define CPU_POWERPC_MPC8250_HiP3 CPU_POWERPC_G2_HIP3
6353 #define CPU_POWERPC_MPC8250_HiP4 CPU_POWERPC_G2_HIP4
6354 #define CPU_POWERPC_MPC8255 CPU_POWERPC_MPC8255_HiP4
6355 #define CPU_POWERPC_MPC8255_HiP3 CPU_POWERPC_G2_HIP3
6356 #define CPU_POWERPC_MPC8255_HiP4 CPU_POWERPC_G2_HIP4
6357 #define CPU_POWERPC_MPC8260 CPU_POWERPC_MPC8260_HiP4
6358 #define CPU_POWERPC_MPC8260_HiP3 CPU_POWERPC_G2_HIP3
6359 #define CPU_POWERPC_MPC8260_HiP4 CPU_POWERPC_G2_HIP4
6360 #define CPU_POWERPC_MPC8264 CPU_POWERPC_MPC8264_HiP4
6361 #define CPU_POWERPC_MPC8264_HiP3 CPU_POWERPC_G2_HIP3
6362 #define CPU_POWERPC_MPC8264_HiP4 CPU_POWERPC_G2_HIP4
6363 #define CPU_POWERPC_MPC8265 CPU_POWERPC_MPC8265_HiP4
6364 #define CPU_POWERPC_MPC8265_HiP3 CPU_POWERPC_G2_HIP3
6365 #define CPU_POWERPC_MPC8265_HiP4 CPU_POWERPC_G2_HIP4
6366 #define CPU_POWERPC_MPC8266 CPU_POWERPC_MPC8266_HiP4
6367 #define CPU_POWERPC_MPC8266_HiP3 CPU_POWERPC_G2_HIP3
6368 #define CPU_POWERPC_MPC8266_HiP4 CPU_POWERPC_G2_HIP4
6369 #define CPU_POWERPC_MPC8270 CPU_POWERPC_G2LEgp3
6370 #define CPU_POWERPC_MPC8271 CPU_POWERPC_G2LEgp3
6371 #define CPU_POWERPC_MPC8272 CPU_POWERPC_G2LEgp3
6372 #define CPU_POWERPC_MPC8275 CPU_POWERPC_G2LEgp3
6373 #define CPU_POWERPC_MPC8280 CPU_POWERPC_G2LEgp3
6374 /* e200 family */
6375 /* e200 cores */
6376 #define CPU_POWERPC_e200 CPU_POWERPC_e200z6
6377 #if 0
6378 CPU_POWERPC_e200z0 = xxx,
6379 #endif
6380 #if 0
6381 CPU_POWERPC_e200z1 = xxx,
6382 #endif
6383 #if 0 /* ? */
6384 CPU_POWERPC_e200z3 = 0x81120000,
6385 #endif
6386 CPU_POWERPC_e200z5 = 0x81000000,
6387 CPU_POWERPC_e200z6 = 0x81120000,
6388 /* MPC55xx microcontrollers */
6389 #define CPU_POWERPC_MPC55xx CPU_POWERPC_MPC5567
6390 #if 0
6391 #define CPU_POWERPC_MPC5514E CPU_POWERPC_MPC5514E_v1
6392 #define CPU_POWERPC_MPC5514E_v0 CPU_POWERPC_e200z0
6393 #define CPU_POWERPC_MPC5514E_v1 CPU_POWERPC_e200z1
6394 #define CPU_POWERPC_MPC5514G CPU_POWERPC_MPC5514G_v1
6395 #define CPU_POWERPC_MPC5514G_v0 CPU_POWERPC_e200z0
6396 #define CPU_POWERPC_MPC5514G_v1 CPU_POWERPC_e200z1
6397 #define CPU_POWERPC_MPC5515S CPU_POWERPC_e200z1
6398 #define CPU_POWERPC_MPC5516E CPU_POWERPC_MPC5516E_v1
6399 #define CPU_POWERPC_MPC5516E_v0 CPU_POWERPC_e200z0
6400 #define CPU_POWERPC_MPC5516E_v1 CPU_POWERPC_e200z1
6401 #define CPU_POWERPC_MPC5516G CPU_POWERPC_MPC5516G_v1
6402 #define CPU_POWERPC_MPC5516G_v0 CPU_POWERPC_e200z0
6403 #define CPU_POWERPC_MPC5516G_v1 CPU_POWERPC_e200z1
6404 #define CPU_POWERPC_MPC5516S CPU_POWERPC_e200z1
6405 #endif
6406 #if 0
6407 #define CPU_POWERPC_MPC5533 CPU_POWERPC_e200z3
6408 #define CPU_POWERPC_MPC5534 CPU_POWERPC_e200z3
6409 #endif
6410 #define CPU_POWERPC_MPC5553 CPU_POWERPC_e200z6
6411 #define CPU_POWERPC_MPC5554 CPU_POWERPC_e200z6
6412 #define CPU_POWERPC_MPC5561 CPU_POWERPC_e200z6
6413 #define CPU_POWERPC_MPC5565 CPU_POWERPC_e200z6
6414 #define CPU_POWERPC_MPC5566 CPU_POWERPC_e200z6
6415 #define CPU_POWERPC_MPC5567 CPU_POWERPC_e200z6
6416 /* e300 family */
6417 /* e300 cores */
6418 #define CPU_POWERPC_e300 CPU_POWERPC_e300c3
6419 CPU_POWERPC_e300c1 = 0x00830010,
6420 CPU_POWERPC_e300c2 = 0x00840010,
6421 CPU_POWERPC_e300c3 = 0x00850010,
6422 CPU_POWERPC_e300c4 = 0x00860010,
6423 /* MPC83xx microcontrollers */
6424 #define CPU_POWERPC_MPC8313 CPU_POWERPC_e300c3
6425 #define CPU_POWERPC_MPC8313E CPU_POWERPC_e300c3
6426 #define CPU_POWERPC_MPC8314 CPU_POWERPC_e300c3
6427 #define CPU_POWERPC_MPC8314E CPU_POWERPC_e300c3
6428 #define CPU_POWERPC_MPC8315 CPU_POWERPC_e300c3
6429 #define CPU_POWERPC_MPC8315E CPU_POWERPC_e300c3
6430 #define CPU_POWERPC_MPC8321 CPU_POWERPC_e300c2
6431 #define CPU_POWERPC_MPC8321E CPU_POWERPC_e300c2
6432 #define CPU_POWERPC_MPC8323 CPU_POWERPC_e300c2
6433 #define CPU_POWERPC_MPC8323E CPU_POWERPC_e300c2
6434 #define CPU_POWERPC_MPC8343A CPU_POWERPC_e300c1
6435 #define CPU_POWERPC_MPC8343EA CPU_POWERPC_e300c1
6436 #define CPU_POWERPC_MPC8347A CPU_POWERPC_e300c1
6437 #define CPU_POWERPC_MPC8347AT CPU_POWERPC_e300c1
6438 #define CPU_POWERPC_MPC8347AP CPU_POWERPC_e300c1
6439 #define CPU_POWERPC_MPC8347EA CPU_POWERPC_e300c1
6440 #define CPU_POWERPC_MPC8347EAT CPU_POWERPC_e300c1
6441 #define CPU_POWERPC_MPC8347EAP CPU_POWERPC_e300c1
6442 #define CPU_POWERPC_MPC8349 CPU_POWERPC_e300c1
6443 #define CPU_POWERPC_MPC8349A CPU_POWERPC_e300c1
6444 #define CPU_POWERPC_MPC8349E CPU_POWERPC_e300c1
6445 #define CPU_POWERPC_MPC8349EA CPU_POWERPC_e300c1
6446 #define CPU_POWERPC_MPC8358E CPU_POWERPC_e300c1
6447 #define CPU_POWERPC_MPC8360E CPU_POWERPC_e300c1
6448 #define CPU_POWERPC_MPC8377 CPU_POWERPC_e300c4
6449 #define CPU_POWERPC_MPC8377E CPU_POWERPC_e300c4
6450 #define CPU_POWERPC_MPC8378 CPU_POWERPC_e300c4
6451 #define CPU_POWERPC_MPC8378E CPU_POWERPC_e300c4
6452 #define CPU_POWERPC_MPC8379 CPU_POWERPC_e300c4
6453 #define CPU_POWERPC_MPC8379E CPU_POWERPC_e300c4
6454 /* e500 family */
6455 /* e500 cores */
6456 #define CPU_POWERPC_e500 CPU_POWERPC_e500v2_v22
6457 #define CPU_POWERPC_e500v2 CPU_POWERPC_e500v2_v22
6458 CPU_POWERPC_e500_v10 = 0x80200010,
6459 CPU_POWERPC_e500_v20 = 0x80200020,
6460 CPU_POWERPC_e500v2_v10 = 0x80210010,
6461 CPU_POWERPC_e500v2_v11 = 0x80210011,
6462 CPU_POWERPC_e500v2_v20 = 0x80210020,
6463 CPU_POWERPC_e500v2_v21 = 0x80210021,
6464 CPU_POWERPC_e500v2_v22 = 0x80210022,
6465 CPU_POWERPC_e500v2_v30 = 0x80210030,
6466 /* MPC85xx microcontrollers */
6467 #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11
6468 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21
6469 #define CPU_POWERPC_MPC8533_v11 CPU_POWERPC_e500v2_v22
6470 #define CPU_POWERPC_MPC8533E CPU_POWERPC_MPC8533E_v11
6471 #define CPU_POWERPC_MPC8533E_v10 CPU_POWERPC_e500v2_v21
6472 #define CPU_POWERPC_MPC8533E_v11 CPU_POWERPC_e500v2_v22
6473 #define CPU_POWERPC_MPC8540 CPU_POWERPC_MPC8540_v21
6474 #define CPU_POWERPC_MPC8540_v10 CPU_POWERPC_e500_v10
6475 #define CPU_POWERPC_MPC8540_v20 CPU_POWERPC_e500_v20
6476 #define CPU_POWERPC_MPC8540_v21 CPU_POWERPC_e500_v20
6477 #define CPU_POWERPC_MPC8541 CPU_POWERPC_MPC8541_v11
6478 #define CPU_POWERPC_MPC8541_v10 CPU_POWERPC_e500_v20
6479 #define CPU_POWERPC_MPC8541_v11 CPU_POWERPC_e500_v20
6480 #define CPU_POWERPC_MPC8541E CPU_POWERPC_MPC8541E_v11
6481 #define CPU_POWERPC_MPC8541E_v10 CPU_POWERPC_e500_v20
6482 #define CPU_POWERPC_MPC8541E_v11 CPU_POWERPC_e500_v20
6483 #define CPU_POWERPC_MPC8543 CPU_POWERPC_MPC8543_v21
6484 #define CPU_POWERPC_MPC8543_v10 CPU_POWERPC_e500v2_v10
6485 #define CPU_POWERPC_MPC8543_v11 CPU_POWERPC_e500v2_v11
6486 #define CPU_POWERPC_MPC8543_v20 CPU_POWERPC_e500v2_v20
6487 #define CPU_POWERPC_MPC8543_v21 CPU_POWERPC_e500v2_v21
6488 #define CPU_POWERPC_MPC8543E CPU_POWERPC_MPC8543E_v21
6489 #define CPU_POWERPC_MPC8543E_v10 CPU_POWERPC_e500v2_v10
6490 #define CPU_POWERPC_MPC8543E_v11 CPU_POWERPC_e500v2_v11
6491 #define CPU_POWERPC_MPC8543E_v20 CPU_POWERPC_e500v2_v20
6492 #define CPU_POWERPC_MPC8543E_v21 CPU_POWERPC_e500v2_v21
6493 #define CPU_POWERPC_MPC8544 CPU_POWERPC_MPC8544_v11
6494 #define CPU_POWERPC_MPC8544_v10 CPU_POWERPC_e500v2_v21
6495 #define CPU_POWERPC_MPC8544_v11 CPU_POWERPC_e500v2_v22
6496 #define CPU_POWERPC_MPC8544E_v11 CPU_POWERPC_e500v2_v22
6497 #define CPU_POWERPC_MPC8544E CPU_POWERPC_MPC8544E_v11
6498 #define CPU_POWERPC_MPC8544E_v10 CPU_POWERPC_e500v2_v21
6499 #define CPU_POWERPC_MPC8545 CPU_POWERPC_MPC8545_v21
6500 #define CPU_POWERPC_MPC8545_v10 CPU_POWERPC_e500v2_v10
6501 #define CPU_POWERPC_MPC8545_v20 CPU_POWERPC_e500v2_v20
6502 #define CPU_POWERPC_MPC8545_v21 CPU_POWERPC_e500v2_v21
6503 #define CPU_POWERPC_MPC8545E CPU_POWERPC_MPC8545E_v21
6504 #define CPU_POWERPC_MPC8545E_v10 CPU_POWERPC_e500v2_v10
6505 #define CPU_POWERPC_MPC8545E_v20 CPU_POWERPC_e500v2_v20
6506 #define CPU_POWERPC_MPC8545E_v21 CPU_POWERPC_e500v2_v21
6507 #define CPU_POWERPC_MPC8547E CPU_POWERPC_MPC8545E_v21
6508 #define CPU_POWERPC_MPC8547E_v10 CPU_POWERPC_e500v2_v10
6509 #define CPU_POWERPC_MPC8547E_v20 CPU_POWERPC_e500v2_v20
6510 #define CPU_POWERPC_MPC8547E_v21 CPU_POWERPC_e500v2_v21
6511 #define CPU_POWERPC_MPC8548 CPU_POWERPC_MPC8548_v21
6512 #define CPU_POWERPC_MPC8548_v10 CPU_POWERPC_e500v2_v10
6513 #define CPU_POWERPC_MPC8548_v11 CPU_POWERPC_e500v2_v11
6514 #define CPU_POWERPC_MPC8548_v20 CPU_POWERPC_e500v2_v20
6515 #define CPU_POWERPC_MPC8548_v21 CPU_POWERPC_e500v2_v21
6516 #define CPU_POWERPC_MPC8548E CPU_POWERPC_MPC8548E_v21
6517 #define CPU_POWERPC_MPC8548E_v10 CPU_POWERPC_e500v2_v10
6518 #define CPU_POWERPC_MPC8548E_v11 CPU_POWERPC_e500v2_v11
6519 #define CPU_POWERPC_MPC8548E_v20 CPU_POWERPC_e500v2_v20
6520 #define CPU_POWERPC_MPC8548E_v21 CPU_POWERPC_e500v2_v21
6521 #define CPU_POWERPC_MPC8555 CPU_POWERPC_MPC8555_v11
6522 #define CPU_POWERPC_MPC8555_v10 CPU_POWERPC_e500v2_v10
6523 #define CPU_POWERPC_MPC8555_v11 CPU_POWERPC_e500v2_v11
6524 #define CPU_POWERPC_MPC8555E CPU_POWERPC_MPC8555E_v11
6525 #define CPU_POWERPC_MPC8555E_v10 CPU_POWERPC_e500v2_v10
6526 #define CPU_POWERPC_MPC8555E_v11 CPU_POWERPC_e500v2_v11
6527 #define CPU_POWERPC_MPC8560 CPU_POWERPC_MPC8560_v21
6528 #define CPU_POWERPC_MPC8560_v10 CPU_POWERPC_e500v2_v10
6529 #define CPU_POWERPC_MPC8560_v20 CPU_POWERPC_e500v2_v20
6530 #define CPU_POWERPC_MPC8560_v21 CPU_POWERPC_e500v2_v21
6531 #define CPU_POWERPC_MPC8567 CPU_POWERPC_e500v2_v22
6532 #define CPU_POWERPC_MPC8567E CPU_POWERPC_e500v2_v22
6533 #define CPU_POWERPC_MPC8568 CPU_POWERPC_e500v2_v22
6534 #define CPU_POWERPC_MPC8568E CPU_POWERPC_e500v2_v22
6535 #define CPU_POWERPC_MPC8572 CPU_POWERPC_e500v2_v30
6536 #define CPU_POWERPC_MPC8572E CPU_POWERPC_e500v2_v30
6537 /* e600 family */
6538 /* e600 cores */
6539 CPU_POWERPC_e600 = 0x80040010,
6540 /* MPC86xx microcontrollers */
6541 #define CPU_POWERPC_MPC8610 CPU_POWERPC_e600
6542 #define CPU_POWERPC_MPC8641 CPU_POWERPC_e600
6543 #define CPU_POWERPC_MPC8641D CPU_POWERPC_e600
6544 /* PowerPC 6xx cores */
6545 #define CPU_POWERPC_601 CPU_POWERPC_601_v2
6546 CPU_POWERPC_601_v0 = 0x00010001,
6547 CPU_POWERPC_601_v1 = 0x00010001,
6548 #define CPU_POWERPC_601v CPU_POWERPC_601_v2
6549 CPU_POWERPC_601_v2 = 0x00010002,
6550 CPU_POWERPC_602 = 0x00050100,
6551 CPU_POWERPC_603 = 0x00030100,
6552 #define CPU_POWERPC_603E CPU_POWERPC_603E_v41
6553 CPU_POWERPC_603E_v11 = 0x00060101,
6554 CPU_POWERPC_603E_v12 = 0x00060102,
6555 CPU_POWERPC_603E_v13 = 0x00060103,
6556 CPU_POWERPC_603E_v14 = 0x00060104,
6557 CPU_POWERPC_603E_v22 = 0x00060202,
6558 CPU_POWERPC_603E_v3 = 0x00060300,
6559 CPU_POWERPC_603E_v4 = 0x00060400,
6560 CPU_POWERPC_603E_v41 = 0x00060401,
6561 CPU_POWERPC_603E7t = 0x00071201,
6562 CPU_POWERPC_603E7v = 0x00070100,
6563 CPU_POWERPC_603E7v1 = 0x00070101,
6564 CPU_POWERPC_603E7v2 = 0x00070201,
6565 CPU_POWERPC_603E7 = 0x00070200,
6566 CPU_POWERPC_603P = 0x00070000,
6567 #define CPU_POWERPC_603R CPU_POWERPC_603E7t
6568 /* XXX: missing 0x00040303 (604) */
6569 CPU_POWERPC_604 = 0x00040103,
6570 #define CPU_POWERPC_604E CPU_POWERPC_604E_v24
6571 /* XXX: missing 0x00091203 */
6572 /* XXX: missing 0x00092110 */
6573 /* XXX: missing 0x00092120 */
6574 CPU_POWERPC_604E_v10 = 0x00090100,
6575 CPU_POWERPC_604E_v22 = 0x00090202,
6576 CPU_POWERPC_604E_v24 = 0x00090204,
6577 /* XXX: missing 0x000a0100 */
6578 /* XXX: missing 0x00093102 */
6579 CPU_POWERPC_604R = 0x000a0101,
6580 #if 0
6581 CPU_POWERPC_604EV = xxx, /* XXX: same as 604R ? */
6582 #endif
6583 /* PowerPC 740/750 cores (aka G3) */
6584 /* XXX: missing 0x00084202 */
6585 #define CPU_POWERPC_7x0 CPU_POWERPC_7x0_v31
6586 CPU_POWERPC_7x0_v10 = 0x00080100,
6587 CPU_POWERPC_7x0_v20 = 0x00080200,
6588 CPU_POWERPC_7x0_v21 = 0x00080201,
6589 CPU_POWERPC_7x0_v22 = 0x00080202,
6590 CPU_POWERPC_7x0_v30 = 0x00080300,
6591 CPU_POWERPC_7x0_v31 = 0x00080301,
6592 CPU_POWERPC_740E = 0x00080100,
6593 CPU_POWERPC_750E = 0x00080200,
6594 CPU_POWERPC_7x0P = 0x10080000,
6595 /* XXX: missing 0x00087010 (CL ?) */
6596 #define CPU_POWERPC_750CL CPU_POWERPC_750CL_v20
6597 CPU_POWERPC_750CL_v10 = 0x00087200,
6598 CPU_POWERPC_750CL_v20 = 0x00087210, /* aka rev E */
6599 #define CPU_POWERPC_750CX CPU_POWERPC_750CX_v22
6600 CPU_POWERPC_750CX_v10 = 0x00082100,
6601 CPU_POWERPC_750CX_v20 = 0x00082200,
6602 CPU_POWERPC_750CX_v21 = 0x00082201,
6603 CPU_POWERPC_750CX_v22 = 0x00082202,
6604 #define CPU_POWERPC_750CXE CPU_POWERPC_750CXE_v31b
6605 CPU_POWERPC_750CXE_v21 = 0x00082211,
6606 CPU_POWERPC_750CXE_v22 = 0x00082212,
6607 CPU_POWERPC_750CXE_v23 = 0x00082213,
6608 CPU_POWERPC_750CXE_v24 = 0x00082214,
6609 CPU_POWERPC_750CXE_v24b = 0x00083214,
6610 CPU_POWERPC_750CXE_v30 = 0x00082310,
6611 CPU_POWERPC_750CXE_v31 = 0x00082311,
6612 CPU_POWERPC_750CXE_v31b = 0x00083311,
6613 CPU_POWERPC_750CXR = 0x00083410,
6614 CPU_POWERPC_750FL = 0x70000203,
6615 #define CPU_POWERPC_750FX CPU_POWERPC_750FX_v23
6616 CPU_POWERPC_750FX_v10 = 0x70000100,
6617 CPU_POWERPC_750FX_v20 = 0x70000200,
6618 CPU_POWERPC_750FX_v21 = 0x70000201,
6619 CPU_POWERPC_750FX_v22 = 0x70000202,
6620 CPU_POWERPC_750FX_v23 = 0x70000203,
6621 CPU_POWERPC_750GL = 0x70020102,
6622 #define CPU_POWERPC_750GX CPU_POWERPC_750GX_v12
6623 CPU_POWERPC_750GX_v10 = 0x70020100,
6624 CPU_POWERPC_750GX_v11 = 0x70020101,
6625 CPU_POWERPC_750GX_v12 = 0x70020102,
6626 #define CPU_POWERPC_750L CPU_POWERPC_750L_v32 /* Aka LoneStar */
6627 CPU_POWERPC_750L_v20 = 0x00088200,
6628 CPU_POWERPC_750L_v21 = 0x00088201,
6629 CPU_POWERPC_750L_v22 = 0x00088202,
6630 CPU_POWERPC_750L_v30 = 0x00088300,
6631 CPU_POWERPC_750L_v32 = 0x00088302,
6632 /* PowerPC 745/755 cores */
6633 #define CPU_POWERPC_7x5 CPU_POWERPC_7x5_v28
6634 CPU_POWERPC_7x5_v10 = 0x00083100,
6635 CPU_POWERPC_7x5_v11 = 0x00083101,
6636 CPU_POWERPC_7x5_v20 = 0x00083200,
6637 CPU_POWERPC_7x5_v21 = 0x00083201,
6638 CPU_POWERPC_7x5_v22 = 0x00083202, /* aka D */
6639 CPU_POWERPC_7x5_v23 = 0x00083203, /* aka E */
6640 CPU_POWERPC_7x5_v24 = 0x00083204,
6641 CPU_POWERPC_7x5_v25 = 0x00083205,
6642 CPU_POWERPC_7x5_v26 = 0x00083206,
6643 CPU_POWERPC_7x5_v27 = 0x00083207,
6644 CPU_POWERPC_7x5_v28 = 0x00083208,
6645 #if 0
6646 CPU_POWERPC_7x5P = xxx,
6647 #endif
6648 /* PowerPC 74xx cores (aka G4) */
6649 /* XXX: missing 0x000C1101 */
6650 #define CPU_POWERPC_7400 CPU_POWERPC_7400_v29
6651 CPU_POWERPC_7400_v10 = 0x000C0100,
6652 CPU_POWERPC_7400_v11 = 0x000C0101,
6653 CPU_POWERPC_7400_v20 = 0x000C0200,
6654 CPU_POWERPC_7400_v22 = 0x000C0202,
6655 CPU_POWERPC_7400_v26 = 0x000C0206,
6656 CPU_POWERPC_7400_v27 = 0x000C0207,
6657 CPU_POWERPC_7400_v28 = 0x000C0208,
6658 CPU_POWERPC_7400_v29 = 0x000C0209,
6659 #define CPU_POWERPC_7410 CPU_POWERPC_7410_v14
6660 CPU_POWERPC_7410_v10 = 0x800C1100,
6661 CPU_POWERPC_7410_v11 = 0x800C1101,
6662 CPU_POWERPC_7410_v12 = 0x800C1102, /* aka C */
6663 CPU_POWERPC_7410_v13 = 0x800C1103, /* aka D */
6664 CPU_POWERPC_7410_v14 = 0x800C1104, /* aka E */
6665 #define CPU_POWERPC_7448 CPU_POWERPC_7448_v21
6666 CPU_POWERPC_7448_v10 = 0x80040100,
6667 CPU_POWERPC_7448_v11 = 0x80040101,
6668 CPU_POWERPC_7448_v20 = 0x80040200,
6669 CPU_POWERPC_7448_v21 = 0x80040201,
6670 #define CPU_POWERPC_7450 CPU_POWERPC_7450_v21
6671 CPU_POWERPC_7450_v10 = 0x80000100,
6672 CPU_POWERPC_7450_v11 = 0x80000101,
6673 CPU_POWERPC_7450_v12 = 0x80000102,
6674 CPU_POWERPC_7450_v20 = 0x80000200, /* aka D: 2.04 */
6675 CPU_POWERPC_7450_v21 = 0x80000201, /* aka E */
6676 CPU_POWERPC_74x1 = 0x80000203,
6677 CPU_POWERPC_74x1G = 0x80000210, /* aka G: 2.3 */
6678 #define CPU_POWERPC_74x5 CPU_POWERPC_74x5_v32
6679 CPU_POWERPC_74x5_v10 = 0x80010100,
6680 /* XXX: missing 0x80010200 */
6681 CPU_POWERPC_74x5_v21 = 0x80010201, /* aka C: 2.1 */
6682 CPU_POWERPC_74x5_v32 = 0x80010302,
6683 CPU_POWERPC_74x5_v33 = 0x80010303, /* aka F: 3.3 */
6684 CPU_POWERPC_74x5_v34 = 0x80010304, /* aka G: 3.4 */
6685 #define CPU_POWERPC_74x7 CPU_POWERPC_74x7_v12
6686 CPU_POWERPC_74x7_v10 = 0x80020100, /* aka A: 1.0 */
6687 CPU_POWERPC_74x7_v11 = 0x80020101, /* aka B: 1.1 */
6688 CPU_POWERPC_74x7_v12 = 0x80020102, /* aka C: 1.2 */
6689 #define CPU_POWERPC_74x7A CPU_POWERPC_74x7A_v12
6690 CPU_POWERPC_74x7A_v10 = 0x80030100, /* aka A: 1.0 */
6691 CPU_POWERPC_74x7A_v11 = 0x80030101, /* aka B: 1.1 */
6692 CPU_POWERPC_74x7A_v12 = 0x80030102, /* aka C: 1.2 */
6693 /* 64 bits PowerPC */
6694 #if defined(TARGET_PPC64)
6695 CPU_POWERPC_620 = 0x00140000,
6696 CPU_POWERPC_630 = 0x00400000,
6697 CPU_POWERPC_631 = 0x00410104,
6698 CPU_POWERPC_POWER4 = 0x00350000,
6699 CPU_POWERPC_POWER4P = 0x00380000,
6700 /* XXX: missing 0x003A0201 */
6701 CPU_POWERPC_POWER5 = 0x003A0203,
6702 #define CPU_POWERPC_POWER5GR CPU_POWERPC_POWER5
6703 CPU_POWERPC_POWER5P = 0x003B0000,
6704 #define CPU_POWERPC_POWER5GS CPU_POWERPC_POWER5P
6705 CPU_POWERPC_POWER6 = 0x003E0000,
6706 CPU_POWERPC_POWER6_5 = 0x0F000001, /* POWER6 in POWER5 mode */
6707 CPU_POWERPC_POWER6A = 0x0F000002,
6708 CPU_POWERPC_970 = 0x00390202,
6709 #define CPU_POWERPC_970FX CPU_POWERPC_970FX_v31
6710 CPU_POWERPC_970FX_v10 = 0x00391100,
6711 CPU_POWERPC_970FX_v20 = 0x003C0200,
6712 CPU_POWERPC_970FX_v21 = 0x003C0201,
6713 CPU_POWERPC_970FX_v30 = 0x003C0300,
6714 CPU_POWERPC_970FX_v31 = 0x003C0301,
6715 CPU_POWERPC_970GX = 0x00450000,
6716 #define CPU_POWERPC_970MP CPU_POWERPC_970MP_v11
6717 CPU_POWERPC_970MP_v10 = 0x00440100,
6718 CPU_POWERPC_970MP_v11 = 0x00440101,
6719 #define CPU_POWERPC_CELL CPU_POWERPC_CELL_v32
6720 CPU_POWERPC_CELL_v10 = 0x00700100,
6721 CPU_POWERPC_CELL_v20 = 0x00700400,
6722 CPU_POWERPC_CELL_v30 = 0x00700500,
6723 CPU_POWERPC_CELL_v31 = 0x00700501,
6724 #define CPU_POWERPC_CELL_v32 CPU_POWERPC_CELL_v31
6725 CPU_POWERPC_RS64 = 0x00330000,
6726 CPU_POWERPC_RS64II = 0x00340000,
6727 CPU_POWERPC_RS64III = 0x00360000,
6728 CPU_POWERPC_RS64IV = 0x00370000,
6729 #endif /* defined(TARGET_PPC64) */
6730 /* Original POWER */
6731 /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
6732 * POWER2 (RIOS2) & RSC2 (P2SC) here
6733 */
6734 #if 0
6735 CPU_POWER = xxx, /* 0x20000 ? 0x30000 for RSC ? */
6736 #endif
6737 #if 0
6738 CPU_POWER2 = xxx, /* 0x40000 ? */
6739 #endif
6740 /* PA Semi core */
6741 CPU_POWERPC_PA6T = 0x00900000,
6742 };
6743
6744 /* System version register (used on MPC 8xxx) */
6745 enum {
6746 POWERPC_SVR_NONE = 0x00000000,
6747 #define POWERPC_SVR_52xx POWERPC_SVR_5200
6748 #define POWERPC_SVR_5200 POWERPC_SVR_5200_v12
6749 POWERPC_SVR_5200_v10 = 0x80110010,
6750 POWERPC_SVR_5200_v11 = 0x80110011,
6751 POWERPC_SVR_5200_v12 = 0x80110012,
6752 #define POWERPC_SVR_5200B POWERPC_SVR_5200B_v21
6753 POWERPC_SVR_5200B_v20 = 0x80110020,
6754 POWERPC_SVR_5200B_v21 = 0x80110021,
6755 #define POWERPC_SVR_55xx POWERPC_SVR_5567
6756 #if 0
6757 POWERPC_SVR_5533 = xxx,
6758 #endif
6759 #if 0
6760 POWERPC_SVR_5534 = xxx,
6761 #endif
6762 #if 0
6763 POWERPC_SVR_5553 = xxx,
6764 #endif
6765 #if 0
6766 POWERPC_SVR_5554 = xxx,
6767 #endif
6768 #if 0
6769 POWERPC_SVR_5561 = xxx,
6770 #endif
6771 #if 0
6772 POWERPC_SVR_5565 = xxx,
6773 #endif
6774 #if 0
6775 POWERPC_SVR_5566 = xxx,
6776 #endif
6777 #if 0
6778 POWERPC_SVR_5567 = xxx,
6779 #endif
6780 #if 0
6781 POWERPC_SVR_8313 = xxx,
6782 #endif
6783 #if 0
6784 POWERPC_SVR_8313E = xxx,
6785 #endif
6786 #if 0
6787 POWERPC_SVR_8314 = xxx,
6788 #endif
6789 #if 0
6790 POWERPC_SVR_8314E = xxx,
6791 #endif
6792 #if 0
6793 POWERPC_SVR_8315 = xxx,
6794 #endif
6795 #if 0
6796 POWERPC_SVR_8315E = xxx,
6797 #endif
6798 #if 0
6799 POWERPC_SVR_8321 = xxx,
6800 #endif
6801 #if 0
6802 POWERPC_SVR_8321E = xxx,
6803 #endif
6804 #if 0
6805 POWERPC_SVR_8323 = xxx,
6806 #endif
6807 #if 0
6808 POWERPC_SVR_8323E = xxx,
6809 #endif
6810 POWERPC_SVR_8343A = 0x80570030,
6811 POWERPC_SVR_8343EA = 0x80560030,
6812 #define POWERPC_SVR_8347A POWERPC_SVR_8347AT
6813 POWERPC_SVR_8347AP = 0x80550030, /* PBGA package */
6814 POWERPC_SVR_8347AT = 0x80530030, /* TBGA package */
6815 #define POWERPC_SVR_8347EA POWERPC_SVR_8347EAT
6816 POWERPC_SVR_8347EAP = 0x80540030, /* PBGA package */
6817 POWERPC_SVR_8347EAT = 0x80520030, /* TBGA package */
6818 POWERPC_SVR_8349 = 0x80510010,
6819 POWERPC_SVR_8349A = 0x80510030,
6820 POWERPC_SVR_8349E = 0x80500010,
6821 POWERPC_SVR_8349EA = 0x80500030,
6822 #if 0
6823 POWERPC_SVR_8358E = xxx,
6824 #endif
6825 #if 0
6826 POWERPC_SVR_8360E = xxx,
6827 #endif
6828 #define POWERPC_SVR_E500 0x40000000
6829 POWERPC_SVR_8377 = 0x80C70010 | POWERPC_SVR_E500,
6830 POWERPC_SVR_8377E = 0x80C60010 | POWERPC_SVR_E500,
6831 POWERPC_SVR_8378 = 0x80C50010 | POWERPC_SVR_E500,
6832 POWERPC_SVR_8378E = 0x80C40010 | POWERPC_SVR_E500,
6833 POWERPC_SVR_8379 = 0x80C30010 | POWERPC_SVR_E500,
6834 POWERPC_SVR_8379E = 0x80C00010 | POWERPC_SVR_E500,
6835 #define POWERPC_SVR_8533 POWERPC_SVR_8533_v11
6836 POWERPC_SVR_8533_v10 = 0x80340010 | POWERPC_SVR_E500,
6837 POWERPC_SVR_8533_v11 = 0x80340011 | POWERPC_SVR_E500,
6838 #define POWERPC_SVR_8533E POWERPC_SVR_8533E_v11
6839 POWERPC_SVR_8533E_v10 = 0x803C0010 | POWERPC_SVR_E500,
6840 POWERPC_SVR_8533E_v11 = 0x803C0011 | POWERPC_SVR_E500,
6841 #define POWERPC_SVR_8540 POWERPC_SVR_8540_v21
6842 POWERPC_SVR_8540_v10 = 0x80300010 | POWERPC_SVR_E500,
6843 POWERPC_SVR_8540_v20 = 0x80300020 | POWERPC_SVR_E500,
6844 POWERPC_SVR_8540_v21 = 0x80300021 | POWERPC_SVR_E500,
6845 #define POWERPC_SVR_8541 POWERPC_SVR_8541_v11
6846 POWERPC_SVR_8541_v10 = 0x80720010 | POWERPC_SVR_E500,
6847 POWERPC_SVR_8541_v11 = 0x80720011 | POWERPC_SVR_E500,
6848 #define POWERPC_SVR_8541E POWERPC_SVR_8541E_v11
6849 POWERPC_SVR_8541E_v10 = 0x807A0010 | POWERPC_SVR_E500,
6850 POWERPC_SVR_8541E_v11 = 0x807A0011 | POWERPC_SVR_E500,
6851 #define POWERPC_SVR_8543 POWERPC_SVR_8543_v21
6852 POWERPC_SVR_8543_v10 = 0x80320010 | POWERPC_SVR_E500,
6853 POWERPC_SVR_8543_v11 = 0x80320011 | POWERPC_SVR_E500,
6854 POWERPC_SVR_8543_v20 = 0x80320020 | POWERPC_SVR_E500,
6855 POWERPC_SVR_8543_v21 = 0x80320021 | POWERPC_SVR_E500,
6856 #define POWERPC_SVR_8543E POWERPC_SVR_8543E_v21
6857 POWERPC_SVR_8543E_v10 = 0x803A0010 | POWERPC_SVR_E500,
6858 POWERPC_SVR_8543E_v11 = 0x803A0011 | POWERPC_SVR_E500,
6859 POWERPC_SVR_8543E_v20 = 0x803A0020 | POWERPC_SVR_E500,
6860 POWERPC_SVR_8543E_v21 = 0x803A0021 | POWERPC_SVR_E500,
6861 #define POWERPC_SVR_8544 POWERPC_SVR_8544_v11
6862 POWERPC_SVR_8544_v10 = 0x80340110 | POWERPC_SVR_E500,
6863 POWERPC_SVR_8544_v11 = 0x80340111 | POWERPC_SVR_E500,
6864 #define POWERPC_SVR_8544E POWERPC_SVR_8544E_v11
6865 POWERPC_SVR_8544E_v10 = 0x803C0110 | POWERPC_SVR_E500,
6866 POWERPC_SVR_8544E_v11 = 0x803C0111 | POWERPC_SVR_E500,
6867 #define POWERPC_SVR_8545 POWERPC_SVR_8545_v21
6868 POWERPC_SVR_8545_v20 = 0x80310220 | POWERPC_SVR_E500,
6869 POWERPC_SVR_8545_v21 = 0x80310221 | POWERPC_SVR_E500,
6870 #define POWERPC_SVR_8545E POWERPC_SVR_8545E_v21
6871 POWERPC_SVR_8545E_v20 = 0x80390220 | POWERPC_SVR_E500,
6872 POWERPC_SVR_8545E_v21 = 0x80390221 | POWERPC_SVR_E500,
6873 #define POWERPC_SVR_8547E POWERPC_SVR_8547E_v21
6874 POWERPC_SVR_8547E_v20 = 0x80390120 | POWERPC_SVR_E500,
6875 POWERPC_SVR_8547E_v21 = 0x80390121 | POWERPC_SVR_E500,
6876 #define POWERPC_SVR_8548 POWERPC_SVR_8548_v21
6877 POWERPC_SVR_8548_v10 = 0x80310010 | POWERPC_SVR_E500,
6878 POWERPC_SVR_8548_v11 = 0x80310011 | POWERPC_SVR_E500,
6879 POWERPC_SVR_8548_v20 = 0x80310020 | POWERPC_SVR_E500,
6880 POWERPC_SVR_8548_v21 = 0x80310021 | POWERPC_SVR_E500,
6881 #define POWERPC_SVR_8548E POWERPC_SVR_8548E_v21
6882 POWERPC_SVR_8548E_v10 = 0x80390010 | POWERPC_SVR_E500,
6883 POWERPC_SVR_8548E_v11 = 0x80390011 | POWERPC_SVR_E500,
6884 POWERPC_SVR_8548E_v20 = 0x80390020 | POWERPC_SVR_E500,
6885 POWERPC_SVR_8548E_v21 = 0x80390021 | POWERPC_SVR_E500,
6886 #define POWERPC_SVR_8555 POWERPC_SVR_8555_v11
6887 POWERPC_SVR_8555_v10 = 0x80710010 | POWERPC_SVR_E500,
6888 POWERPC_SVR_8555_v11 = 0x80710011 | POWERPC_SVR_E500,
6889 #define POWERPC_SVR_8555E POWERPC_SVR_8555_v11
6890 POWERPC_SVR_8555E_v10 = 0x80790010 | POWERPC_SVR_E500,
6891 POWERPC_SVR_8555E_v11 = 0x80790011 | POWERPC_SVR_E500,
6892 #define POWERPC_SVR_8560 POWERPC_SVR_8560_v21
6893 POWERPC_SVR_8560_v10 = 0x80700010 | POWERPC_SVR_E500,
6894 POWERPC_SVR_8560_v20 = 0x80700020 | POWERPC_SVR_E500,
6895 POWERPC_SVR_8560_v21 = 0x80700021 | POWERPC_SVR_E500,
6896 POWERPC_SVR_8567 = 0x80750111 | POWERPC_SVR_E500,
6897 POWERPC_SVR_8567E = 0x807D0111 | POWERPC_SVR_E500,
6898 POWERPC_SVR_8568 = 0x80750011 | POWERPC_SVR_E500,
6899 POWERPC_SVR_8568E = 0x807D0011 | POWERPC_SVR_E500,
6900 POWERPC_SVR_8572 = 0x80E00010 | POWERPC_SVR_E500,
6901 POWERPC_SVR_8572E = 0x80E80010 | POWERPC_SVR_E500,
6902 #if 0
6903 POWERPC_SVR_8610 = xxx,
6904 #endif
6905 POWERPC_SVR_8641 = 0x80900021,
6906 POWERPC_SVR_8641D = 0x80900121,
6907 };
6908
6909 /*****************************************************************************/
6910 /* PowerPC CPU definitions */
6911 #define POWERPC_DEF_SVR(_name, _pvr, _svr, _type) \
6912 { \
6913 .name = _name, \
6914 .pvr = _pvr, \
6915 .svr = _svr, \
6916 .insns_flags = glue(POWERPC_INSNS_,_type), \
6917 .msr_mask = glue(POWERPC_MSRM_,_type), \
6918 .mmu_model = glue(POWERPC_MMU_,_type), \
6919 .excp_model = glue(POWERPC_EXCP_,_type), \
6920 .bus_model = glue(POWERPC_INPUT_,_type), \
6921 .bfd_mach = glue(POWERPC_BFDM_,_type), \
6922 .flags = glue(POWERPC_FLAG_,_type), \
6923 .init_proc = &glue(init_proc_,_type), \
6924 .check_pow = &glue(check_pow_,_type), \
6925 }
6926 #define POWERPC_DEF(_name, _pvr, _type) \
6927 POWERPC_DEF_SVR(_name, _pvr, POWERPC_SVR_NONE, _type)
6928
6929 static const ppc_def_t ppc_defs[] = {
6930 /* Embedded PowerPC */
6931 /* PowerPC 401 family */
6932 /* Generic PowerPC 401 */
6933 POWERPC_DEF("401", CPU_POWERPC_401, 401),
6934 /* PowerPC 401 cores */
6935 /* PowerPC 401A1 */
6936 POWERPC_DEF("401A1", CPU_POWERPC_401A1, 401),
6937 /* PowerPC 401B2 */
6938 POWERPC_DEF("401B2", CPU_POWERPC_401B2, 401x2),
6939 #if defined (TODO)
6940 /* PowerPC 401B3 */
6941 POWERPC_DEF("401B3", CPU_POWERPC_401B3, 401x3),
6942 #endif
6943 /* PowerPC 401C2 */
6944 POWERPC_DEF("401C2", CPU_POWERPC_401C2, 401x2),
6945 /* PowerPC 401D2 */
6946 POWERPC_DEF("401D2", CPU_POWERPC_401D2, 401x2),
6947 /* PowerPC 401E2 */
6948 POWERPC_DEF("401E2", CPU_POWERPC_401E2, 401x2),
6949 /* PowerPC 401F2 */
6950 POWERPC_DEF("401F2", CPU_POWERPC_401F2, 401x2),
6951 /* PowerPC 401G2 */
6952 /* XXX: to be checked */
6953 POWERPC_DEF("401G2", CPU_POWERPC_401G2, 401x2),
6954 /* PowerPC 401 microcontrolers */
6955 #if defined (TODO)
6956 /* PowerPC 401GF */
6957 POWERPC_DEF("401GF", CPU_POWERPC_401GF, 401),
6958 #endif
6959 /* IOP480 (401 microcontroler) */
6960 POWERPC_DEF("IOP480", CPU_POWERPC_IOP480, IOP480),
6961 /* IBM Processor for Network Resources */
6962 POWERPC_DEF("Cobra", CPU_POWERPC_COBRA, 401),
6963 #if defined (TODO)
6964 POWERPC_DEF("Xipchip", CPU_POWERPC_XIPCHIP, 401),
6965 #endif
6966 /* PowerPC 403 family */
6967 /* Generic PowerPC 403 */
6968 POWERPC_DEF("403", CPU_POWERPC_403, 403),
6969 /* PowerPC 403 microcontrolers */
6970 /* PowerPC 403 GA */
6971 POWERPC_DEF("403GA", CPU_POWERPC_403GA, 403),
6972 /* PowerPC 403 GB */
6973 POWERPC_DEF("403GB", CPU_POWERPC_403GB, 403),
6974 /* PowerPC 403 GC */
6975 POWERPC_DEF("403GC", CPU_POWERPC_403GC, 403),
6976 /* PowerPC 403 GCX */
6977 POWERPC_DEF("403GCX", CPU_POWERPC_403GCX, 403GCX),
6978 #if defined (TODO)
6979 /* PowerPC 403 GP */
6980 POWERPC_DEF("403GP", CPU_POWERPC_403GP, 403),
6981 #endif
6982 /* PowerPC 405 family */
6983 /* Generic PowerPC 405 */
6984 POWERPC_DEF("405", CPU_POWERPC_405, 405),
6985 /* PowerPC 405 cores */
6986 #if defined (TODO)
6987 /* PowerPC 405 A3 */
6988 POWERPC_DEF("405A3", CPU_POWERPC_405A3, 405),
6989 #endif
6990 #if defined (TODO)
6991 /* PowerPC 405 A4 */
6992 POWERPC_DEF("405A4", CPU_POWERPC_405A4, 405),
6993 #endif
6994 #if defined (TODO)
6995 /* PowerPC 405 B3 */
6996 POWERPC_DEF("405B3", CPU_POWERPC_405B3, 405),
6997 #endif
6998 #if defined (TODO)
6999 /* PowerPC 405 B4 */
7000 POWERPC_DEF("405B4", CPU_POWERPC_405B4, 405),
7001 #endif
7002 #if defined (TODO)
7003 /* PowerPC 405 C3 */
7004 POWERPC_DEF("405C3", CPU_POWERPC_405C3, 405),
7005 #endif
7006 #if defined (TODO)
7007 /* PowerPC 405 C4 */
7008 POWERPC_DEF("405C4", CPU_POWERPC_405C4, 405),
7009 #endif
7010 /* PowerPC 405 D2 */
7011 POWERPC_DEF("405D2", CPU_POWERPC_405D2, 405),
7012 #if defined (TODO)
7013 /* PowerPC 405 D3 */
7014 POWERPC_DEF("405D3", CPU_POWERPC_405D3, 405),
7015 #endif
7016 /* PowerPC 405 D4 */
7017 POWERPC_DEF("405D4", CPU_POWERPC_405D4, 405),
7018 #if defined (TODO)
7019 /* PowerPC 405 D5 */
7020 POWERPC_DEF("405D5", CPU_POWERPC_405D5, 405),
7021 #endif
7022 #if defined (TODO)
7023 /* PowerPC 405 E4 */
7024 POWERPC_DEF("405E4", CPU_POWERPC_405E4, 405),
7025 #endif
7026 #if defined (TODO)
7027 /* PowerPC 405 F4 */
7028 POWERPC_DEF("405F4", CPU_POWERPC_405F4, 405),
7029 #endif
7030 #if defined (TODO)
7031 /* PowerPC 405 F5 */
7032 POWERPC_DEF("405F5", CPU_POWERPC_405F5, 405),
7033 #endif
7034 #if defined (TODO)
7035 /* PowerPC 405 F6 */
7036 POWERPC_DEF("405F6", CPU_POWERPC_405F6, 405),
7037 #endif
7038 /* PowerPC 405 microcontrolers */
7039 /* PowerPC 405 CR */
7040 POWERPC_DEF("405CR", CPU_POWERPC_405CR, 405),
7041 /* PowerPC 405 CRa */
7042 POWERPC_DEF("405CRa", CPU_POWERPC_405CRa, 405),
7043 /* PowerPC 405 CRb */
7044 POWERPC_DEF("405CRb", CPU_POWERPC_405CRb, 405),
7045 /* PowerPC 405 CRc */
7046 POWERPC_DEF("405CRc", CPU_POWERPC_405CRc, 405),
7047 /* PowerPC 405 EP */
7048 POWERPC_DEF("405EP", CPU_POWERPC_405EP, 405),
7049 #if defined(TODO)
7050 /* PowerPC 405 EXr */
7051 POWERPC_DEF("405EXr", CPU_POWERPC_405EXr, 405),
7052 #endif
7053 /* PowerPC 405 EZ */
7054 POWERPC_DEF("405EZ", CPU_POWERPC_405EZ, 405),
7055 #if defined(TODO)
7056 /* PowerPC 405 FX */
7057 POWERPC_DEF("405FX", CPU_POWERPC_405FX, 405),
7058 #endif
7059 /* PowerPC 405 GP */
7060 POWERPC_DEF("405GP", CPU_POWERPC_405GP, 405),
7061 /* PowerPC 405 GPa */
7062 POWERPC_DEF("405GPa", CPU_POWERPC_405GPa, 405),
7063 /* PowerPC 405 GPb */
7064 POWERPC_DEF("405GPb", CPU_POWERPC_405GPb, 405),
7065 /* PowerPC 405 GPc */
7066 POWERPC_DEF("405GPc", CPU_POWERPC_405GPc, 405),
7067 /* PowerPC 405 GPd */
7068 POWERPC_DEF("405GPd", CPU_POWERPC_405GPd, 405),
7069 /* PowerPC 405 GPe */
7070 POWERPC_DEF("405GPe", CPU_POWERPC_405GPe, 405),
7071 /* PowerPC 405 GPR */
7072 POWERPC_DEF("405GPR", CPU_POWERPC_405GPR, 405),
7073 #if defined(TODO)
7074 /* PowerPC 405 H */
7075 POWERPC_DEF("405H", CPU_POWERPC_405H, 405),
7076 #endif
7077 #if defined(TODO)
7078 /* PowerPC 405 L */
7079 POWERPC_DEF("405L", CPU_POWERPC_405L, 405),
7080 #endif
7081 /* PowerPC 405 LP */
7082 POWERPC_DEF("405LP", CPU_POWERPC_405LP, 405),
7083 #if defined(TODO)
7084 /* PowerPC 405 PM */
7085 POWERPC_DEF("405PM", CPU_POWERPC_405PM, 405),
7086 #endif
7087 #if defined(TODO)
7088 /* PowerPC 405 PS */
7089 POWERPC_DEF("405PS", CPU_POWERPC_405PS, 405),
7090 #endif
7091 #if defined(TODO)
7092 /* PowerPC 405 S */
7093 POWERPC_DEF("405S", CPU_POWERPC_405S, 405),
7094 #endif
7095 /* Npe405 H */
7096 POWERPC_DEF("Npe405H", CPU_POWERPC_NPE405H, 405),
7097 /* Npe405 H2 */
7098 POWERPC_DEF("Npe405H2", CPU_POWERPC_NPE405H2, 405),
7099 /* Npe405 L */
7100 POWERPC_DEF("Npe405L", CPU_POWERPC_NPE405L, 405),
7101 /* Npe4GS3 */
7102 POWERPC_DEF("Npe4GS3", CPU_POWERPC_NPE4GS3, 405),
7103 #if defined (TODO)
7104 POWERPC_DEF("Npcxx1", CPU_POWERPC_NPCxx1, 405),
7105 #endif
7106 #if defined (TODO)
7107 POWERPC_DEF("Npr161", CPU_POWERPC_NPR161, 405),
7108 #endif
7109 #if defined (TODO)
7110 /* PowerPC LC77700 (Sanyo) */
7111 POWERPC_DEF("LC77700", CPU_POWERPC_LC77700, 405),
7112 #endif
7113 /* PowerPC 401/403/405 based set-top-box microcontrolers */
7114 #if defined (TODO)
7115 /* STB010000 */
7116 POWERPC_DEF("STB01000", CPU_POWERPC_STB01000, 401x2),
7117 #endif
7118 #if defined (TODO)
7119 /* STB01010 */
7120 POWERPC_DEF("STB01010", CPU_POWERPC_STB01010, 401x2),
7121 #endif
7122 #if defined (TODO)
7123 /* STB0210 */
7124 POWERPC_DEF("STB0210", CPU_POWERPC_STB0210, 401x3),
7125 #endif
7126 /* STB03xx */
7127 POWERPC_DEF("STB03", CPU_POWERPC_STB03, 405),
7128 #if defined (TODO)
7129 /* STB043x */
7130 POWERPC_DEF("STB043", CPU_POWERPC_STB043, 405),
7131 #endif
7132 #if defined (TODO)
7133 /* STB045x */
7134 POWERPC_DEF("STB045", CPU_POWERPC_STB045, 405),
7135 #endif
7136 /* STB04xx */
7137 POWERPC_DEF("STB04", CPU_POWERPC_STB04, 405),
7138 /* STB25xx */
7139 POWERPC_DEF("STB25", CPU_POWERPC_STB25, 405),
7140 #if defined (TODO)
7141 /* STB130 */
7142 POWERPC_DEF("STB130", CPU_POWERPC_STB130, 405),
7143 #endif
7144 /* Xilinx PowerPC 405 cores */
7145 POWERPC_DEF("x2vp4", CPU_POWERPC_X2VP4, 405),
7146 POWERPC_DEF("x2vp7", CPU_POWERPC_X2VP7, 405),
7147 POWERPC_DEF("x2vp20", CPU_POWERPC_X2VP20, 405),
7148 POWERPC_DEF("x2vp50", CPU_POWERPC_X2VP50, 405),
7149 #if defined (TODO)
7150 /* Zarlink ZL10310 */
7151 POWERPC_DEF("zl10310", CPU_POWERPC_ZL10310, 405),
7152 #endif
7153 #if defined (TODO)
7154 /* Zarlink ZL10311 */
7155 POWERPC_DEF("zl10311", CPU_POWERPC_ZL10311, 405),
7156 #endif
7157 #if defined (TODO)
7158 /* Zarlink ZL10320 */
7159 POWERPC_DEF("zl10320", CPU_POWERPC_ZL10320, 405),
7160 #endif
7161 #if defined (TODO)
7162 /* Zarlink ZL10321 */
7163 POWERPC_DEF("zl10321", CPU_POWERPC_ZL10321, 405),
7164 #endif
7165 /* PowerPC 440 family */
7166 #if defined(TODO_USER_ONLY)
7167 /* Generic PowerPC 440 */
7168 POWERPC_DEF("440", CPU_POWERPC_440, 440GP),
7169 #endif
7170 /* PowerPC 440 cores */
7171 #if defined (TODO)
7172 /* PowerPC 440 A4 */
7173 POWERPC_DEF("440A4", CPU_POWERPC_440A4, 440x4),
7174 #endif
7175 #if defined (TODO)
7176 /* PowerPC 440 A5 */
7177 POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5),
7178 #endif
7179 #if defined (TODO)
7180 /* PowerPC 440 B4 */
7181 POWERPC_DEF("440B4", CPU_POWERPC_440B4, 440x4),
7182 #endif
7183 #if defined (TODO)
7184 /* PowerPC 440 G4 */
7185 POWERPC_DEF("440G4", CPU_POWERPC_440G4, 440x4),
7186 #endif
7187 #if defined (TODO)
7188 /* PowerPC 440 F5 */
7189 POWERPC_DEF("440F5", CPU_POWERPC_440F5, 440x5),
7190 #endif
7191 #if defined (TODO)
7192 /* PowerPC 440 G5 */
7193 POWERPC_DEF("440G5", CPU_POWERPC_440G5, 440x5),
7194 #endif
7195 #if defined (TODO)
7196 /* PowerPC 440H4 */
7197 POWERPC_DEF("440H4", CPU_POWERPC_440H4, 440x4),
7198 #endif
7199 #if defined (TODO)
7200 /* PowerPC 440H6 */
7201 POWERPC_DEF("440H6", CPU_POWERPC_440H6, 440Gx5),
7202 #endif
7203 /* PowerPC 440 microcontrolers */
7204 #if defined(TODO_USER_ONLY)
7205 /* PowerPC 440 EP */
7206 POWERPC_DEF("440EP", CPU_POWERPC_440EP, 440EP),
7207 #endif
7208 #if defined(TODO_USER_ONLY)
7209 /* PowerPC 440 EPa */
7210 POWERPC_DEF("440EPa", CPU_POWERPC_440EPa, 440EP),
7211 #endif
7212 #if defined(TODO_USER_ONLY)
7213 /* PowerPC 440 EPb */
7214 POWERPC_DEF("440EPb", CPU_POWERPC_440EPb, 440EP),
7215 #endif
7216 #if defined(TODO_USER_ONLY)
7217 /* PowerPC 440 EPX */
7218 POWERPC_DEF("440EPX", CPU_POWERPC_440EPX, 440EP),
7219 #endif
7220 #if defined(TODO_USER_ONLY)
7221 /* PowerPC 440 GP */
7222 POWERPC_DEF("440GP", CPU_POWERPC_440GP, 440GP),
7223 #endif
7224 #if defined(TODO_USER_ONLY)
7225 /* PowerPC 440 GPb */
7226 POWERPC_DEF("440GPb", CPU_POWERPC_440GPb, 440GP),
7227 #endif
7228 #if defined(TODO_USER_ONLY)
7229 /* PowerPC 440 GPc */
7230 POWERPC_DEF("440GPc", CPU_POWERPC_440GPc, 440GP),
7231 #endif
7232 #if defined(TODO_USER_ONLY)
7233 /* PowerPC 440 GR */
7234 POWERPC_DEF("440GR", CPU_POWERPC_440GR, 440x5),
7235 #endif
7236 #if defined(TODO_USER_ONLY)
7237 /* PowerPC 440 GRa */
7238 POWERPC_DEF("440GRa", CPU_POWERPC_440GRa, 440x5),
7239 #endif
7240 #if defined(TODO_USER_ONLY)
7241 /* PowerPC 440 GRX */
7242 POWERPC_DEF("440GRX", CPU_POWERPC_440GRX, 440x5),
7243 #endif
7244 #if defined(TODO_USER_ONLY)
7245 /* PowerPC 440 GX */
7246 POWERPC_DEF("440GX", CPU_POWERPC_440GX, 440EP),
7247 #endif
7248 #if defined(TODO_USER_ONLY)
7249 /* PowerPC 440 GXa */
7250 POWERPC_DEF("440GXa", CPU_POWERPC_440GXa, 440EP),
7251 #endif
7252 #if defined(TODO_USER_ONLY)
7253 /* PowerPC 440 GXb */
7254 POWERPC_DEF("440GXb", CPU_POWERPC_440GXb, 440EP),
7255 #endif
7256 #if defined(TODO_USER_ONLY)
7257 /* PowerPC 440 GXc */
7258 POWERPC_DEF("440GXc", CPU_POWERPC_440GXc, 440EP),
7259 #endif
7260 #if defined(TODO_USER_ONLY)
7261 /* PowerPC 440 GXf */
7262 POWERPC_DEF("440GXf", CPU_POWERPC_440GXf, 440EP),
7263 #endif
7264 #if defined(TODO)
7265 /* PowerPC 440 S */
7266 POWERPC_DEF("440S", CPU_POWERPC_440S, 440),
7267 #endif
7268 #if defined(TODO_USER_ONLY)
7269 /* PowerPC 440 SP */
7270 POWERPC_DEF("440SP", CPU_POWERPC_440SP, 440EP),
7271 #endif
7272 #if defined(TODO_USER_ONLY)
7273 /* PowerPC 440 SP2 */
7274 POWERPC_DEF("440SP2", CPU_POWERPC_440SP2, 440EP),
7275 #endif
7276 #if defined(TODO_USER_ONLY)
7277 /* PowerPC 440 SPE */
7278 POWERPC_DEF("440SPE", CPU_POWERPC_440SPE, 440EP),
7279 #endif
7280 /* PowerPC 460 family */
7281 #if defined (TODO)
7282 /* Generic PowerPC 464 */
7283 POWERPC_DEF("464", CPU_POWERPC_464, 460),
7284 #endif
7285 /* PowerPC 464 microcontrolers */
7286 #if defined (TODO)
7287 /* PowerPC 464H90 */
7288 POWERPC_DEF("464H90", CPU_POWERPC_464H90, 460),
7289 #endif
7290 #if defined (TODO)
7291 /* PowerPC 464H90F */
7292 POWERPC_DEF("464H90F", CPU_POWERPC_464H90F, 460F),
7293 #endif
7294 /* Freescale embedded PowerPC cores */
7295 /* MPC5xx family (aka RCPU) */
7296 #if defined(TODO_USER_ONLY)
7297 /* Generic MPC5xx core */
7298 POWERPC_DEF("MPC5xx", CPU_POWERPC_MPC5xx, MPC5xx),
7299 #endif
7300 #if defined(TODO_USER_ONLY)
7301 /* Codename for MPC5xx core */
7302 POWERPC_DEF("RCPU", CPU_POWERPC_MPC5xx, MPC5xx),
7303 #endif
7304 /* MPC5xx microcontrollers */
7305 #if defined(TODO_USER_ONLY)
7306 /* MGT560 */
7307 POWERPC_DEF("MGT560", CPU_POWERPC_MGT560, MPC5xx),
7308 #endif
7309 #if defined(TODO_USER_ONLY)
7310 /* MPC509 */
7311 POWERPC_DEF("MPC509", CPU_POWERPC_MPC509, MPC5xx),
7312 #endif
7313 #if defined(TODO_USER_ONLY)
7314 /* MPC533 */
7315 POWERPC_DEF("MPC533", CPU_POWERPC_MPC533, MPC5xx),
7316 #endif
7317 #if defined(TODO_USER_ONLY)
7318 /* MPC534 */
7319 POWERPC_DEF("MPC534", CPU_POWERPC_MPC534, MPC5xx),
7320 #endif
7321 #if defined(TODO_USER_ONLY)
7322 /* MPC555 */
7323 POWERPC_DEF("MPC555", CPU_POWERPC_MPC555, MPC5xx),
7324 #endif
7325 #if defined(TODO_USER_ONLY)
7326 /* MPC556 */
7327 POWERPC_DEF("MPC556", CPU_POWERPC_MPC556, MPC5xx),
7328 #endif
7329 #if defined(TODO_USER_ONLY)
7330 /* MPC560 */
7331 POWERPC_DEF("MPC560", CPU_POWERPC_MPC560, MPC5xx),
7332 #endif
7333 #if defined(TODO_USER_ONLY)
7334 /* MPC561 */
7335 POWERPC_DEF("MPC561", CPU_POWERPC_MPC561, MPC5xx),
7336 #endif
7337 #if defined(TODO_USER_ONLY)
7338 /* MPC562 */
7339 POWERPC_DEF("MPC562", CPU_POWERPC_MPC562, MPC5xx),
7340 #endif
7341 #if defined(TODO_USER_ONLY)
7342 /* MPC563 */
7343 POWERPC_DEF("MPC563", CPU_POWERPC_MPC563, MPC5xx),
7344 #endif
7345 #if defined(TODO_USER_ONLY)
7346 /* MPC564 */
7347 POWERPC_DEF("MPC564", CPU_POWERPC_MPC564, MPC5xx),
7348 #endif
7349 #if defined(TODO_USER_ONLY)
7350 /* MPC565 */
7351 POWERPC_DEF("MPC565", CPU_POWERPC_MPC565, MPC5xx),
7352 #endif
7353 #if defined(TODO_USER_ONLY)
7354 /* MPC566 */
7355 POWERPC_DEF("MPC566", CPU_POWERPC_MPC566, MPC5xx),
7356 #endif
7357 /* MPC8xx family (aka PowerQUICC) */
7358 #if defined(TODO_USER_ONLY)
7359 /* Generic MPC8xx core */
7360 POWERPC_DEF("MPC8xx", CPU_POWERPC_MPC8xx, MPC8xx),
7361 #endif
7362 #if defined(TODO_USER_ONLY)
7363 /* Codename for MPC8xx core */
7364 POWERPC_DEF("PowerQUICC", CPU_POWERPC_MPC8xx, MPC8xx),
7365 #endif
7366 /* MPC8xx microcontrollers */
7367 #if defined(TODO_USER_ONLY)
7368 /* MGT823 */
7369 POWERPC_DEF("MGT823", CPU_POWERPC_MGT823, MPC8xx),
7370 #endif
7371 #if defined(TODO_USER_ONLY)
7372 /* MPC821 */
7373 POWERPC_DEF("MPC821", CPU_POWERPC_MPC821, MPC8xx),
7374 #endif
7375 #if defined(TODO_USER_ONLY)
7376 /* MPC823 */
7377 POWERPC_DEF("MPC823", CPU_POWERPC_MPC823, MPC8xx),
7378 #endif
7379 #if defined(TODO_USER_ONLY)
7380 /* MPC850 */
7381 POWERPC_DEF("MPC850", CPU_POWERPC_MPC850, MPC8xx),
7382 #endif
7383 #if defined(TODO_USER_ONLY)
7384 /* MPC852T */
7385 POWERPC_DEF("MPC852T", CPU_POWERPC_MPC852T, MPC8xx),
7386 #endif
7387 #if defined(TODO_USER_ONLY)
7388 /* MPC855T */
7389 POWERPC_DEF("MPC855T", CPU_POWERPC_MPC855T, MPC8xx),
7390 #endif
7391 #if defined(TODO_USER_ONLY)
7392 /* MPC857 */
7393 POWERPC_DEF("MPC857", CPU_POWERPC_MPC857, MPC8xx),
7394 #endif
7395 #if defined(TODO_USER_ONLY)
7396 /* MPC859 */
7397 POWERPC_DEF("MPC859", CPU_POWERPC_MPC859, MPC8xx),
7398 #endif
7399 #if defined(TODO_USER_ONLY)
7400 /* MPC860 */
7401 POWERPC_DEF("MPC860", CPU_POWERPC_MPC860, MPC8xx),
7402 #endif
7403 #if defined(TODO_USER_ONLY)
7404 /* MPC862 */
7405 POWERPC_DEF("MPC862", CPU_POWERPC_MPC862, MPC8xx),
7406 #endif
7407 #if defined(TODO_USER_ONLY)
7408 /* MPC866 */
7409 POWERPC_DEF("MPC866", CPU_POWERPC_MPC866, MPC8xx),
7410 #endif
7411 #if defined(TODO_USER_ONLY)
7412 /* MPC870 */
7413 POWERPC_DEF("MPC870", CPU_POWERPC_MPC870, MPC8xx),
7414 #endif
7415 #if defined(TODO_USER_ONLY)
7416 /* MPC875 */
7417 POWERPC_DEF("MPC875", CPU_POWERPC_MPC875, MPC8xx),
7418 #endif
7419 #if defined(TODO_USER_ONLY)
7420 /* MPC880 */
7421 POWERPC_DEF("MPC880", CPU_POWERPC_MPC880, MPC8xx),
7422 #endif
7423 #if defined(TODO_USER_ONLY)
7424 /* MPC885 */
7425 POWERPC_DEF("MPC885", CPU_POWERPC_MPC885, MPC8xx),
7426 #endif
7427 /* MPC82xx family (aka PowerQUICC-II) */
7428 /* Generic MPC52xx core */
7429 POWERPC_DEF_SVR("MPC52xx",
7430 CPU_POWERPC_MPC52xx, POWERPC_SVR_52xx, G2LE),
7431 /* Generic MPC82xx core */
7432 POWERPC_DEF("MPC82xx", CPU_POWERPC_MPC82xx, G2),
7433 /* Codename for MPC82xx */
7434 POWERPC_DEF("PowerQUICC-II", CPU_POWERPC_MPC82xx, G2),
7435 /* PowerPC G2 core */
7436 POWERPC_DEF("G2", CPU_POWERPC_G2, G2),
7437 /* PowerPC G2 H4 core */
7438 POWERPC_DEF("G2H4", CPU_POWERPC_G2H4, G2),
7439 /* PowerPC G2 GP core */
7440 POWERPC_DEF("G2GP", CPU_POWERPC_G2gp, G2),
7441 /* PowerPC G2 LS core */
7442 POWERPC_DEF("G2LS", CPU_POWERPC_G2ls, G2),
7443 /* PowerPC G2 HiP3 core */
7444 POWERPC_DEF("G2HiP3", CPU_POWERPC_G2_HIP3, G2),
7445 /* PowerPC G2 HiP4 core */
7446 POWERPC_DEF("G2HiP4", CPU_POWERPC_G2_HIP4, G2),
7447 /* PowerPC MPC603 core */
7448 POWERPC_DEF("MPC603", CPU_POWERPC_MPC603, 603E),
7449 /* PowerPC G2le core (same as G2 plus little-endian mode support) */
7450 POWERPC_DEF("G2le", CPU_POWERPC_G2LE, G2LE),
7451 /* PowerPC G2LE GP core */
7452 POWERPC_DEF("G2leGP", CPU_POWERPC_G2LEgp, G2LE),
7453 /* PowerPC G2LE LS core */
7454 POWERPC_DEF("G2leLS", CPU_POWERPC_G2LEls, G2LE),
7455 /* PowerPC G2LE GP1 core */
7456 POWERPC_DEF("G2leGP1", CPU_POWERPC_G2LEgp1, G2LE),
7457 /* PowerPC G2LE GP3 core */
7458 POWERPC_DEF("G2leGP3", CPU_POWERPC_G2LEgp1, G2LE),
7459 /* PowerPC MPC603 microcontrollers */
7460 /* MPC8240 */
7461 POWERPC_DEF("MPC8240", CPU_POWERPC_MPC8240, 603E),
7462 /* PowerPC G2 microcontrollers */
7463 #if defined(TODO)
7464 /* MPC5121 */
7465 POWERPC_DEF_SVR("MPC5121",
7466 CPU_POWERPC_MPC5121, POWERPC_SVR_5121, G2LE),
7467 #endif
7468 /* MPC5200 */
7469 POWERPC_DEF_SVR("MPC5200",
7470 CPU_POWERPC_MPC5200, POWERPC_SVR_5200, G2LE),
7471 /* MPC5200 v1.0 */
7472 POWERPC_DEF_SVR("MPC5200_v10",
7473 CPU_POWERPC_MPC5200_v10, POWERPC_SVR_5200_v10, G2LE),
7474 /* MPC5200 v1.1 */
7475 POWERPC_DEF_SVR("MPC5200_v11",
7476 CPU_POWERPC_MPC5200_v11, POWERPC_SVR_5200_v11, G2LE),
7477 /* MPC5200 v1.2 */
7478 POWERPC_DEF_SVR("MPC5200_v12",
7479 CPU_POWERPC_MPC5200_v12, POWERPC_SVR_5200_v12, G2LE),
7480 /* MPC5200B */
7481 POWERPC_DEF_SVR("MPC5200B",
7482 CPU_POWERPC_MPC5200B, POWERPC_SVR_5200B, G2LE),
7483 /* MPC5200B v2.0 */
7484 POWERPC_DEF_SVR("MPC5200B_v20",
7485 CPU_POWERPC_MPC5200B_v20, POWERPC_SVR_5200B_v20, G2LE),
7486 /* MPC5200B v2.1 */
7487 POWERPC_DEF_SVR("MPC5200B_v21",
7488 CPU_POWERPC_MPC5200B_v21, POWERPC_SVR_5200B_v21, G2LE),
7489 /* MPC8241 */
7490 POWERPC_DEF("MPC8241", CPU_POWERPC_MPC8241, G2),
7491 /* MPC8245 */
7492 POWERPC_DEF("MPC8245", CPU_POWERPC_MPC8245, G2),
7493 /* MPC8247 */
7494 POWERPC_DEF("MPC8247", CPU_POWERPC_MPC8247, G2LE),
7495 /* MPC8248 */
7496 POWERPC_DEF("MPC8248", CPU_POWERPC_MPC8248, G2LE),
7497 /* MPC8250 */
7498 POWERPC_DEF("MPC8250", CPU_POWERPC_MPC8250, G2),
7499 /* MPC8250 HiP3 */
7500 POWERPC_DEF("MPC8250_HiP3", CPU_POWERPC_MPC8250_HiP3, G2),
7501 /* MPC8250 HiP4 */
7502 POWERPC_DEF("MPC8250_HiP4", CPU_POWERPC_MPC8250_HiP4, G2),
7503 /* MPC8255 */
7504 POWERPC_DEF("MPC8255", CPU_POWERPC_MPC8255, G2),
7505 /* MPC8255 HiP3 */
7506 POWERPC_DEF("MPC8255_HiP3", CPU_POWERPC_MPC8255_HiP3, G2),
7507 /* MPC8255 HiP4 */
7508 POWERPC_DEF("MPC8255_HiP4", CPU_POWERPC_MPC8255_HiP4, G2),
7509 /* MPC8260 */
7510 POWERPC_DEF("MPC8260", CPU_POWERPC_MPC8260, G2),
7511 /* MPC8260 HiP3 */
7512 POWERPC_DEF("MPC8260_HiP3", CPU_POWERPC_MPC8260_HiP3, G2),
7513 /* MPC8260 HiP4 */
7514 POWERPC_DEF("MPC8260_HiP4", CPU_POWERPC_MPC8260_HiP4, G2),
7515 /* MPC8264 */
7516 POWERPC_DEF("MPC8264", CPU_POWERPC_MPC8264, G2),
7517 /* MPC8264 HiP3 */
7518 POWERPC_DEF("MPC8264_HiP3", CPU_POWERPC_MPC8264_HiP3, G2),
7519 /* MPC8264 HiP4 */
7520 POWERPC_DEF("MPC8264_HiP4", CPU_POWERPC_MPC8264_HiP4, G2),
7521 /* MPC8265 */
7522 POWERPC_DEF("MPC8265", CPU_POWERPC_MPC8265, G2),
7523 /* MPC8265 HiP3 */
7524 POWERPC_DEF("MPC8265_HiP3", CPU_POWERPC_MPC8265_HiP3, G2),
7525 /* MPC8265 HiP4 */
7526 POWERPC_DEF("MPC8265_HiP4", CPU_POWERPC_MPC8265_HiP4, G2),
7527 /* MPC8266 */
7528 POWERPC_DEF("MPC8266", CPU_POWERPC_MPC8266, G2),
7529 /* MPC8266 HiP3 */
7530 POWERPC_DEF("MPC8266_HiP3", CPU_POWERPC_MPC8266_HiP3, G2),
7531 /* MPC8266 HiP4 */
7532 POWERPC_DEF("MPC8266_HiP4", CPU_POWERPC_MPC8266_HiP4, G2),
7533 /* MPC8270 */
7534 POWERPC_DEF("MPC8270", CPU_POWERPC_MPC8270, G2LE),
7535 /* MPC8271 */
7536 POWERPC_DEF("MPC8271", CPU_POWERPC_MPC8271, G2LE),
7537 /* MPC8272 */
7538 POWERPC_DEF("MPC8272", CPU_POWERPC_MPC8272, G2LE),
7539 /* MPC8275 */
7540 POWERPC_DEF("MPC8275", CPU_POWERPC_MPC8275, G2LE),
7541 /* MPC8280 */
7542 POWERPC_DEF("MPC8280", CPU_POWERPC_MPC8280, G2LE),
7543 /* e200 family */
7544 /* Generic PowerPC e200 core */
7545 POWERPC_DEF("e200", CPU_POWERPC_e200, e200),
7546 /* Generic MPC55xx core */
7547 #if defined (TODO)
7548 POWERPC_DEF_SVR("MPC55xx",
7549 CPU_POWERPC_MPC55xx, POWERPC_SVR_55xx, e200),
7550 #endif
7551 #if defined (TODO)
7552 /* PowerPC e200z0 core */
7553 POWERPC_DEF("e200z0", CPU_POWERPC_e200z0, e200),
7554 #endif
7555 #if defined (TODO)
7556 /* PowerPC e200z1 core */
7557 POWERPC_DEF("e200z1", CPU_POWERPC_e200z1, e200),
7558 #endif
7559 #if defined (TODO)
7560 /* PowerPC e200z3 core */
7561 POWERPC_DEF("e200z3", CPU_POWERPC_e200z3, e200),
7562 #endif
7563 /* PowerPC e200z5 core */
7564 POWERPC_DEF("e200z5", CPU_POWERPC_e200z5, e200),
7565 /* PowerPC e200z6 core */
7566 POWERPC_DEF("e200z6", CPU_POWERPC_e200z6, e200),
7567 /* PowerPC e200 microcontrollers */
7568 #if defined (TODO)
7569 /* MPC5514E */
7570 POWERPC_DEF_SVR("MPC5514E",
7571 CPU_POWERPC_MPC5514E, POWERPC_SVR_5514E, e200),
7572 #endif
7573 #if defined (TODO)
7574 /* MPC5514E v0 */
7575 POWERPC_DEF_SVR("MPC5514E_v0",
7576 CPU_POWERPC_MPC5514E_v0, POWERPC_SVR_5514E_v0, e200),
7577 #endif
7578 #if defined (TODO)
7579 /* MPC5514E v1 */
7580 POWERPC_DEF_SVR("MPC5514E_v1",
7581 CPU_POWERPC_MPC5514E_v1, POWERPC_SVR_5514E_v1, e200),
7582 #endif
7583 #if defined (TODO)
7584 /* MPC5514G */
7585 POWERPC_DEF_SVR("MPC5514G",
7586 CPU_POWERPC_MPC5514G, POWERPC_SVR_5514G, e200),
7587 #endif
7588 #if defined (TODO)
7589 /* MPC5514G v0 */
7590 POWERPC_DEF_SVR("MPC5514G_v0",
7591 CPU_POWERPC_MPC5514G_v0, POWERPC_SVR_5514G_v0, e200),
7592 #endif
7593 #if defined (TODO)
7594 /* MPC5514G v1 */
7595 POWERPC_DEF_SVR("MPC5514G_v1",
7596 CPU_POWERPC_MPC5514G_v1, POWERPC_SVR_5514G_v1, e200),
7597 #endif
7598 #if defined (TODO)
7599 /* MPC5515S */
7600 POWERPC_DEF_SVR("MPC5515S",
7601 CPU_POWERPC_MPC5515S, POWERPC_SVR_5515S, e200),
7602 #endif
7603 #if defined (TODO)
7604 /* MPC5516E */
7605 POWERPC_DEF_SVR("MPC5516E",
7606 CPU_POWERPC_MPC5516E, POWERPC_SVR_5516E, e200),
7607 #endif
7608 #if defined (TODO)
7609 /* MPC5516E v0 */
7610 POWERPC_DEF_SVR("MPC5516E_v0",
7611 CPU_POWERPC_MPC5516E_v0, POWERPC_SVR_5516E_v0, e200),
7612 #endif
7613 #if defined (TODO)
7614 /* MPC5516E v1 */
7615 POWERPC_DEF_SVR("MPC5516E_v1",
7616 CPU_POWERPC_MPC5516E_v1, POWERPC_SVR_5516E_v1, e200),
7617 #endif
7618 #if defined (TODO)
7619 /* MPC5516G */
7620 POWERPC_DEF_SVR("MPC5516G",
7621 CPU_POWERPC_MPC5516G, POWERPC_SVR_5516G, e200),
7622 #endif
7623 #if defined (TODO)
7624 /* MPC5516G v0 */
7625 POWERPC_DEF_SVR("MPC5516G_v0",
7626 CPU_POWERPC_MPC5516G_v0, POWERPC_SVR_5516G_v0, e200),
7627 #endif
7628 #if defined (TODO)
7629 /* MPC5516G v1 */
7630 POWERPC_DEF_SVR("MPC5516G_v1",
7631 CPU_POWERPC_MPC5516G_v1, POWERPC_SVR_5516G_v1, e200),
7632 #endif
7633 #if defined (TODO)
7634 /* MPC5516S */
7635 POWERPC_DEF_SVR("MPC5516S",
7636 CPU_POWERPC_MPC5516S, POWERPC_SVR_5516S, e200),
7637 #endif
7638 #if defined (TODO)
7639 /* MPC5533 */
7640 POWERPC_DEF_SVR("MPC5533",
7641 CPU_POWERPC_MPC5533, POWERPC_SVR_5533, e200),
7642 #endif
7643 #if defined (TODO)
7644 /* MPC5534 */
7645 POWERPC_DEF_SVR("MPC5534",
7646 CPU_POWERPC_MPC5534, POWERPC_SVR_5534, e200),
7647 #endif
7648 #if defined (TODO)
7649 /* MPC5553 */
7650 POWERPC_DEF_SVR("MPC5553",
7651 CPU_POWERPC_MPC5553, POWERPC_SVR_5553, e200),
7652 #endif
7653 #if defined (TODO)
7654 /* MPC5554 */
7655 POWERPC_DEF_SVR("MPC5554",
7656 CPU_POWERPC_MPC5554, POWERPC_SVR_5554, e200),
7657 #endif
7658 #if defined (TODO)
7659 /* MPC5561 */
7660 POWERPC_DEF_SVR("MPC5561",
7661 CPU_POWERPC_MPC5561, POWERPC_SVR_5561, e200),
7662 #endif
7663 #if defined (TODO)
7664 /* MPC5565 */
7665 POWERPC_DEF_SVR("MPC5565",
7666 CPU_POWERPC_MPC5565, POWERPC_SVR_5565, e200),
7667 #endif
7668 #if defined (TODO)
7669 /* MPC5566 */
7670 POWERPC_DEF_SVR("MPC5566",
7671 CPU_POWERPC_MPC5566, POWERPC_SVR_5566, e200),
7672 #endif
7673 #if defined (TODO)
7674 /* MPC5567 */
7675 POWERPC_DEF_SVR("MPC5567",
7676 CPU_POWERPC_MPC5567, POWERPC_SVR_5567, e200),
7677 #endif
7678 /* e300 family */
7679 /* Generic PowerPC e300 core */
7680 POWERPC_DEF("e300", CPU_POWERPC_e300, e300),
7681 /* PowerPC e300c1 core */
7682 POWERPC_DEF("e300c1", CPU_POWERPC_e300c1, e300),
7683 /* PowerPC e300c2 core */
7684 POWERPC_DEF("e300c2", CPU_POWERPC_e300c2, e300),
7685 /* PowerPC e300c3 core */
7686 POWERPC_DEF("e300c3", CPU_POWERPC_e300c3, e300),
7687 /* PowerPC e300c4 core */
7688 POWERPC_DEF("e300c4", CPU_POWERPC_e300c4, e300),
7689 /* PowerPC e300 microcontrollers */
7690 #if defined (TODO)
7691 /* MPC8313 */
7692 POWERPC_DEF_SVR("MPC8313",
7693 CPU_POWERPC_MPC8313, POWERPC_SVR_8313, e300),
7694 #endif
7695 #if defined (TODO)
7696 /* MPC8313E */
7697 POWERPC_DEF_SVR("MPC8313E",
7698 CPU_POWERPC_MPC8313E, POWERPC_SVR_8313E, e300),
7699 #endif
7700 #if defined (TODO)
7701 /* MPC8314 */
7702 POWERPC_DEF_SVR("MPC8314",
7703 CPU_POWERPC_MPC8314, POWERPC_SVR_8314, e300),
7704 #endif
7705 #if defined (TODO)
7706 /* MPC8314E */
7707 POWERPC_DEF_SVR("MPC8314E",
7708 CPU_POWERPC_MPC8314E, POWERPC_SVR_8314E, e300),
7709 #endif
7710 #if defined (TODO)
7711 /* MPC8315 */
7712 POWERPC_DEF_SVR("MPC8315",
7713 CPU_POWERPC_MPC8315, POWERPC_SVR_8315, e300),
7714 #endif
7715 #if defined (TODO)
7716 /* MPC8315E */
7717 POWERPC_DEF_SVR("MPC8315E",
7718 CPU_POWERPC_MPC8315E, POWERPC_SVR_8315E, e300),
7719 #endif
7720 #if defined (TODO)
7721 /* MPC8321 */
7722 POWERPC_DEF_SVR("MPC8321",
7723 CPU_POWERPC_MPC8321, POWERPC_SVR_8321, e300),
7724 #endif
7725 #if defined (TODO)
7726 /* MPC8321E */
7727 POWERPC_DEF_SVR("MPC8321E",
7728 CPU_POWERPC_MPC8321E, POWERPC_SVR_8321E, e300),
7729 #endif
7730 #if defined (TODO)
7731 /* MPC8323 */
7732 POWERPC_DEF_SVR("MPC8323",
7733 CPU_POWERPC_MPC8323, POWERPC_SVR_8323, e300),
7734 #endif
7735 #if defined (TODO)
7736 /* MPC8323E */
7737 POWERPC_DEF_SVR("MPC8323E",
7738 CPU_POWERPC_MPC8323E, POWERPC_SVR_8323E, e300),
7739 #endif
7740 /* MPC8343A */
7741 POWERPC_DEF_SVR("MPC8343A",
7742 CPU_POWERPC_MPC8343A, POWERPC_SVR_8343A, e300),
7743 /* MPC8343EA */
7744 POWERPC_DEF_SVR("MPC8343EA",
7745 CPU_POWERPC_MPC8343EA, POWERPC_SVR_8343EA, e300),
7746 /* MPC8347A */
7747 POWERPC_DEF_SVR("MPC8347A",
7748 CPU_POWERPC_MPC8347A, POWERPC_SVR_8347A, e300),
7749 /* MPC8347AT */
7750 POWERPC_DEF_SVR("MPC8347AT",
7751 CPU_POWERPC_MPC8347AT, POWERPC_SVR_8347AT, e300),
7752 /* MPC8347AP */
7753 POWERPC_DEF_SVR("MPC8347AP",
7754 CPU_POWERPC_MPC8347AP, POWERPC_SVR_8347AP, e300),
7755 /* MPC8347EA */
7756 POWERPC_DEF_SVR("MPC8347EA",
7757 CPU_POWERPC_MPC8347EA, POWERPC_SVR_8347EA, e300),
7758 /* MPC8347EAT */
7759 POWERPC_DEF_SVR("MPC8347EAT",
7760 CPU_POWERPC_MPC8347EAT, POWERPC_SVR_8347EAT, e300),
7761 /* MPC8343EAP */
7762 POWERPC_DEF_SVR("MPC8347EAP",
7763 CPU_POWERPC_MPC8347EAP, POWERPC_SVR_8347EAP, e300),
7764 /* MPC8349 */
7765 POWERPC_DEF_SVR("MPC8349",
7766 CPU_POWERPC_MPC8349, POWERPC_SVR_8349, e300),
7767 /* MPC8349A */
7768 POWERPC_DEF_SVR("MPC8349A",
7769 CPU_POWERPC_MPC8349A, POWERPC_SVR_8349A, e300),
7770 /* MPC8349E */
7771 POWERPC_DEF_SVR("MPC8349E",
7772 CPU_POWERPC_MPC8349E, POWERPC_SVR_8349E, e300),
7773 /* MPC8349EA */
7774 POWERPC_DEF_SVR("MPC8349EA",
7775 CPU_POWERPC_MPC8349EA, POWERPC_SVR_8349EA, e300),
7776 #if defined (TODO)
7777 /* MPC8358E */
7778 POWERPC_DEF_SVR("MPC8358E",
7779 CPU_POWERPC_MPC8358E, POWERPC_SVR_8358E, e300),
7780 #endif
7781 #if defined (TODO)
7782 /* MPC8360E */
7783 POWERPC_DEF_SVR("MPC8360E",
7784 CPU_POWERPC_MPC8360E, POWERPC_SVR_8360E, e300),
7785 #endif
7786 /* MPC8377 */
7787 POWERPC_DEF_SVR("MPC8377",
7788 CPU_POWERPC_MPC8377, POWERPC_SVR_8377, e300),
7789 /* MPC8377E */
7790 POWERPC_DEF_SVR("MPC8377E",
7791 CPU_POWERPC_MPC8377E, POWERPC_SVR_8377E, e300),
7792 /* MPC8378 */
7793 POWERPC_DEF_SVR("MPC8378",
7794 CPU_POWERPC_MPC8378, POWERPC_SVR_8378, e300),
7795 /* MPC8378E */
7796 POWERPC_DEF_SVR("MPC8378E",
7797 CPU_POWERPC_MPC8378E, POWERPC_SVR_8378E, e300),
7798 /* MPC8379 */
7799 POWERPC_DEF_SVR("MPC8379",
7800 CPU_POWERPC_MPC8379, POWERPC_SVR_8379, e300),
7801 /* MPC8379E */
7802 POWERPC_DEF_SVR("MPC8379E",
7803 CPU_POWERPC_MPC8379E, POWERPC_SVR_8379E, e300),
7804 /* e500 family */
7805 /* PowerPC e500 core */
7806 POWERPC_DEF("e500", CPU_POWERPC_e500, e500),
7807 /* PowerPC e500 v1.0 core */
7808 POWERPC_DEF("e500_v10", CPU_POWERPC_e500_v10, e500),
7809 /* PowerPC e500 v2.0 core */
7810 POWERPC_DEF("e500_v20", CPU_POWERPC_e500_v20, e500),
7811 /* PowerPC e500v2 core */
7812 POWERPC_DEF("e500v2", CPU_POWERPC_e500v2, e500),
7813 /* PowerPC e500v2 v1.0 core */
7814 POWERPC_DEF("e500v2_v10", CPU_POWERPC_e500v2_v10, e500),
7815 /* PowerPC e500v2 v2.0 core */
7816 POWERPC_DEF("e500v2_v20", CPU_POWERPC_e500v2_v20, e500),
7817 /* PowerPC e500v2 v2.1 core */
7818 POWERPC_DEF("e500v2_v21", CPU_POWERPC_e500v2_v21, e500),
7819 /* PowerPC e500v2 v2.2 core */
7820 POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500),
7821 /* PowerPC e500v2 v3.0 core */
7822 POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500),
7823 /* PowerPC e500 microcontrollers */
7824 /* MPC8533 */
7825 POWERPC_DEF_SVR("MPC8533",
7826 CPU_POWERPC_MPC8533, POWERPC_SVR_8533, e500),
7827 /* MPC8533 v1.0 */
7828 POWERPC_DEF_SVR("MPC8533_v10",
7829 CPU_POWERPC_MPC8533_v10, POWERPC_SVR_8533_v10, e500),
7830 /* MPC8533 v1.1 */
7831 POWERPC_DEF_SVR("MPC8533_v11",
7832 CPU_POWERPC_MPC8533_v11, POWERPC_SVR_8533_v11, e500),
7833 /* MPC8533E */
7834 POWERPC_DEF_SVR("MPC8533E",
7835 CPU_POWERPC_MPC8533E, POWERPC_SVR_8533E, e500),
7836 /* MPC8533E v1.0 */
7837 POWERPC_DEF_SVR("MPC8533E_v10",
7838 CPU_POWERPC_MPC8533E_v10, POWERPC_SVR_8533E_v10, e500),
7839 POWERPC_DEF_SVR("MPC8533E_v11",
7840 CPU_POWERPC_MPC8533E_v11, POWERPC_SVR_8533E_v11, e500),
7841 /* MPC8540 */
7842 POWERPC_DEF_SVR("MPC8540",
7843 CPU_POWERPC_MPC8540, POWERPC_SVR_8540, e500),
7844 /* MPC8540 v1.0 */
7845 POWERPC_DEF_SVR("MPC8540_v10",
7846 CPU_POWERPC_MPC8540_v10, POWERPC_SVR_8540_v10, e500),
7847 /* MPC8540 v2.0 */
7848 POWERPC_DEF_SVR("MPC8540_v20",
7849 CPU_POWERPC_MPC8540_v20, POWERPC_SVR_8540_v20, e500),
7850 /* MPC8540 v2.1 */
7851 POWERPC_DEF_SVR("MPC8540_v21",
7852 CPU_POWERPC_MPC8540_v21, POWERPC_SVR_8540_v21, e500),
7853 /* MPC8541 */
7854 POWERPC_DEF_SVR("MPC8541",
7855 CPU_POWERPC_MPC8541, POWERPC_SVR_8541, e500),
7856 /* MPC8541 v1.0 */
7857 POWERPC_DEF_SVR("MPC8541_v10",
7858 CPU_POWERPC_MPC8541_v10, POWERPC_SVR_8541_v10, e500),
7859 /* MPC8541 v1.1 */
7860 POWERPC_DEF_SVR("MPC8541_v11",
7861 CPU_POWERPC_MPC8541_v11, POWERPC_SVR_8541_v11, e500),
7862 /* MPC8541E */
7863 POWERPC_DEF_SVR("MPC8541E",
7864 CPU_POWERPC_MPC8541E, POWERPC_SVR_8541E, e500),
7865 /* MPC8541E v1.0 */
7866 POWERPC_DEF_SVR("MPC8541E_v10",
7867 CPU_POWERPC_MPC8541E_v10, POWERPC_SVR_8541E_v10, e500),
7868 /* MPC8541E v1.1 */
7869 POWERPC_DEF_SVR("MPC8541E_v11",
7870 CPU_POWERPC_MPC8541E_v11, POWERPC_SVR_8541E_v11, e500),
7871 /* MPC8543 */
7872 POWERPC_DEF_SVR("MPC8543",
7873 CPU_POWERPC_MPC8543, POWERPC_SVR_8543, e500),
7874 /* MPC8543 v1.0 */
7875 POWERPC_DEF_SVR("MPC8543_v10",
7876 CPU_POWERPC_MPC8543_v10, POWERPC_SVR_8543_v10, e500),
7877 /* MPC8543 v1.1 */
7878 POWERPC_DEF_SVR("MPC8543_v11",
7879 CPU_POWERPC_MPC8543_v11, POWERPC_SVR_8543_v11, e500),
7880 /* MPC8543 v2.0 */
7881 POWERPC_DEF_SVR("MPC8543_v20",
7882 CPU_POWERPC_MPC8543_v20, POWERPC_SVR_8543_v20, e500),
7883 /* MPC8543 v2.1 */
7884 POWERPC_DEF_SVR("MPC8543_v21",
7885 CPU_POWERPC_MPC8543_v21, POWERPC_SVR_8543_v21, e500),
7886 /* MPC8543E */
7887 POWERPC_DEF_SVR("MPC8543E",
7888 CPU_POWERPC_MPC8543E, POWERPC_SVR_8543E, e500),
7889 /* MPC8543E v1.0 */
7890 POWERPC_DEF_SVR("MPC8543E_v10",
7891 CPU_POWERPC_MPC8543E_v10, POWERPC_SVR_8543E_v10, e500),
7892 /* MPC8543E v1.1 */
7893 POWERPC_DEF_SVR("MPC8543E_v11",
7894 CPU_POWERPC_MPC8543E_v11, POWERPC_SVR_8543E_v11, e500),
7895 /* MPC8543E v2.0 */
7896 POWERPC_DEF_SVR("MPC8543E_v20",
7897 CPU_POWERPC_MPC8543E_v20, POWERPC_SVR_8543E_v20, e500),
7898 /* MPC8543E v2.1 */
7899 POWERPC_DEF_SVR("MPC8543E_v21",
7900 CPU_POWERPC_MPC8543E_v21, POWERPC_SVR_8543E_v21, e500),
7901 /* MPC8544 */
7902 POWERPC_DEF_SVR("MPC8544",
7903 CPU_POWERPC_MPC8544, POWERPC_SVR_8544, e500),
7904 /* MPC8544 v1.0 */
7905 POWERPC_DEF_SVR("MPC8544_v10",
7906 CPU_POWERPC_MPC8544_v10, POWERPC_SVR_8544_v10, e500),
7907 /* MPC8544 v1.1 */
7908 POWERPC_DEF_SVR("MPC8544_v11",
7909 CPU_POWERPC_MPC8544_v11, POWERPC_SVR_8544_v11, e500),
7910 /* MPC8544E */
7911 POWERPC_DEF_SVR("MPC8544E",
7912 CPU_POWERPC_MPC8544E, POWERPC_SVR_8544E, e500),
7913 /* MPC8544E v1.0 */
7914 POWERPC_DEF_SVR("MPC8544E_v10",
7915 CPU_POWERPC_MPC8544E_v10, POWERPC_SVR_8544E_v10, e500),
7916 /* MPC8544E v1.1 */
7917 POWERPC_DEF_SVR("MPC8544E_v11",
7918 CPU_POWERPC_MPC8544E_v11, POWERPC_SVR_8544E_v11, e500),
7919 /* MPC8545 */
7920 POWERPC_DEF_SVR("MPC8545",
7921 CPU_POWERPC_MPC8545, POWERPC_SVR_8545, e500),
7922 /* MPC8545 v2.0 */
7923 POWERPC_DEF_SVR("MPC8545_v20",
7924 CPU_POWERPC_MPC8545_v20, POWERPC_SVR_8545_v20, e500),
7925 /* MPC8545 v2.1 */
7926 POWERPC_DEF_SVR("MPC8545_v21",
7927 CPU_POWERPC_MPC8545_v21, POWERPC_SVR_8545_v21, e500),
7928 /* MPC8545E */
7929 POWERPC_DEF_SVR("MPC8545E",
7930 CPU_POWERPC_MPC8545E, POWERPC_SVR_8545E, e500),
7931 /* MPC8545E v2.0 */
7932 POWERPC_DEF_SVR("MPC8545E_v20",
7933 CPU_POWERPC_MPC8545E_v20, POWERPC_SVR_8545E_v20, e500),
7934 /* MPC8545E v2.1 */
7935 POWERPC_DEF_SVR("MPC8545E_v21",
7936 CPU_POWERPC_MPC8545E_v21, POWERPC_SVR_8545E_v21, e500),
7937 /* MPC8547E */
7938 POWERPC_DEF_SVR("MPC8547E",
7939 CPU_POWERPC_MPC8547E, POWERPC_SVR_8547E, e500),
7940 /* MPC8547E v2.0 */
7941 POWERPC_DEF_SVR("MPC8547E_v20",
7942 CPU_POWERPC_MPC8547E_v20, POWERPC_SVR_8547E_v20, e500),
7943 /* MPC8547E v2.1 */
7944 POWERPC_DEF_SVR("MPC8547E_v21",
7945 CPU_POWERPC_MPC8547E_v21, POWERPC_SVR_8547E_v21, e500),
7946 /* MPC8548 */
7947 POWERPC_DEF_SVR("MPC8548",
7948 CPU_POWERPC_MPC8548, POWERPC_SVR_8548, e500),
7949 /* MPC8548 v1.0 */
7950 POWERPC_DEF_SVR("MPC8548_v10",
7951 CPU_POWERPC_MPC8548_v10, POWERPC_SVR_8548_v10, e500),
7952 /* MPC8548 v1.1 */
7953 POWERPC_DEF_SVR("MPC8548_v11",
7954 CPU_POWERPC_MPC8548_v11, POWERPC_SVR_8548_v11, e500),
7955 /* MPC8548 v2.0 */
7956 POWERPC_DEF_SVR("MPC8548_v20",
7957 CPU_POWERPC_MPC8548_v20, POWERPC_SVR_8548_v20, e500),
7958 /* MPC8548 v2.1 */
7959 POWERPC_DEF_SVR("MPC8548_v21",
7960 CPU_POWERPC_MPC8548_v21, POWERPC_SVR_8548_v21, e500),
7961 /* MPC8548E */
7962 POWERPC_DEF_SVR("MPC8548E",
7963 CPU_POWERPC_MPC8548E, POWERPC_SVR_8548E, e500),
7964 /* MPC8548E v1.0 */
7965 POWERPC_DEF_SVR("MPC8548E_v10",
7966 CPU_POWERPC_MPC8548E_v10, POWERPC_SVR_8548E_v10, e500),
7967 /* MPC8548E v1.1 */
7968 POWERPC_DEF_SVR("MPC8548E_v11",
7969 CPU_POWERPC_MPC8548E_v11, POWERPC_SVR_8548E_v11, e500),
7970 /* MPC8548E v2.0 */
7971 POWERPC_DEF_SVR("MPC8548E_v20",
7972 CPU_POWERPC_MPC8548E_v20, POWERPC_SVR_8548E_v20, e500),
7973 /* MPC8548E v2.1 */
7974 POWERPC_DEF_SVR("MPC8548E_v21",
7975 CPU_POWERPC_MPC8548E_v21, POWERPC_SVR_8548E_v21, e500),
7976 /* MPC8555 */
7977 POWERPC_DEF_SVR("MPC8555",
7978 CPU_POWERPC_MPC8555, POWERPC_SVR_8555, e500),
7979 /* MPC8555 v1.0 */
7980 POWERPC_DEF_SVR("MPC8555_v10",
7981 CPU_POWERPC_MPC8555_v10, POWERPC_SVR_8555_v10, e500),
7982 /* MPC8555 v1.1 */
7983 POWERPC_DEF_SVR("MPC8555_v11",
7984 CPU_POWERPC_MPC8555_v11, POWERPC_SVR_8555_v11, e500),
7985 /* MPC8555E */
7986 POWERPC_DEF_SVR("MPC8555E",
7987 CPU_POWERPC_MPC8555E, POWERPC_SVR_8555E, e500),
7988 /* MPC8555E v1.0 */
7989 POWERPC_DEF_SVR("MPC8555E_v10",
7990 CPU_POWERPC_MPC8555E_v10, POWERPC_SVR_8555E_v10, e500),
7991 /* MPC8555E v1.1 */
7992 POWERPC_DEF_SVR("MPC8555E_v11",
7993 CPU_POWERPC_MPC8555E_v11, POWERPC_SVR_8555E_v11, e500),
7994 /* MPC8560 */
7995 POWERPC_DEF_SVR("MPC8560",
7996 CPU_POWERPC_MPC8560, POWERPC_SVR_8560, e500),
7997 /* MPC8560 v1.0 */
7998 POWERPC_DEF_SVR("MPC8560_v10",
7999 CPU_POWERPC_MPC8560_v10, POWERPC_SVR_8560_v10, e500),
8000 /* MPC8560 v2.0 */
8001 POWERPC_DEF_SVR("MPC8560_v20",
8002 CPU_POWERPC_MPC8560_v20, POWERPC_SVR_8560_v20, e500),
8003 /* MPC8560 v2.1 */
8004 POWERPC_DEF_SVR("MPC8560_v21",
8005 CPU_POWERPC_MPC8560_v21, POWERPC_SVR_8560_v21, e500),
8006 /* MPC8567 */
8007 POWERPC_DEF_SVR("MPC8567",
8008 CPU_POWERPC_MPC8567, POWERPC_SVR_8567, e500),
8009 /* MPC8567E */
8010 POWERPC_DEF_SVR("MPC8567E",
8011 CPU_POWERPC_MPC8567E, POWERPC_SVR_8567E, e500),
8012 /* MPC8568 */
8013 POWERPC_DEF_SVR("MPC8568",
8014 CPU_POWERPC_MPC8568, POWERPC_SVR_8568, e500),
8015 /* MPC8568E */
8016 POWERPC_DEF_SVR("MPC8568E",
8017 CPU_POWERPC_MPC8568E, POWERPC_SVR_8568E, e500),
8018 /* MPC8572 */
8019 POWERPC_DEF_SVR("MPC8572",
8020 CPU_POWERPC_MPC8572, POWERPC_SVR_8572, e500),
8021 /* MPC8572E */
8022 POWERPC_DEF_SVR("MPC8572E",
8023 CPU_POWERPC_MPC8572E, POWERPC_SVR_8572E, e500),
8024 /* e600 family */
8025 /* PowerPC e600 core */
8026 POWERPC_DEF("e600", CPU_POWERPC_e600, 7400),
8027 /* PowerPC e600 microcontrollers */
8028 #if defined (TODO)
8029 /* MPC8610 */
8030 POWERPC_DEF_SVR("MPC8610",
8031 CPU_POWERPC_MPC8610, POWERPC_SVR_8610, 7400),
8032 #endif
8033 /* MPC8641 */
8034 POWERPC_DEF_SVR("MPC8641",
8035 CPU_POWERPC_MPC8641, POWERPC_SVR_8641, 7400),
8036 /* MPC8641D */
8037 POWERPC_DEF_SVR("MPC8641D",
8038 CPU_POWERPC_MPC8641D, POWERPC_SVR_8641D, 7400),
8039 /* 32 bits "classic" PowerPC */
8040 /* PowerPC 6xx family */
8041 /* PowerPC 601 */
8042 POWERPC_DEF("601", CPU_POWERPC_601, 601v),
8043 /* PowerPC 601v0 */
8044 POWERPC_DEF("601_v0", CPU_POWERPC_601_v0, 601),
8045 /* PowerPC 601v1 */
8046 POWERPC_DEF("601_v1", CPU_POWERPC_601_v1, 601),
8047 /* PowerPC 601v */
8048 POWERPC_DEF("601v", CPU_POWERPC_601v, 601v),
8049 /* PowerPC 601v2 */
8050 POWERPC_DEF("601_v2", CPU_POWERPC_601_v2, 601v),
8051 /* PowerPC 602 */
8052 POWERPC_DEF("602", CPU_POWERPC_602, 602),
8053 /* PowerPC 603 */
8054 POWERPC_DEF("603", CPU_POWERPC_603, 603),
8055 /* Code name for PowerPC 603 */
8056 POWERPC_DEF("Vanilla", CPU_POWERPC_603, 603),
8057 /* PowerPC 603e (aka PID6) */
8058 POWERPC_DEF("603e", CPU_POWERPC_603E, 603E),
8059 /* Code name for PowerPC 603e */
8060 POWERPC_DEF("Stretch", CPU_POWERPC_603E, 603E),
8061 /* PowerPC 603e v1.1 */
8062 POWERPC_DEF("603e_v1.1", CPU_POWERPC_603E_v11, 603E),
8063 /* PowerPC 603e v1.2 */
8064 POWERPC_DEF("603e_v1.2", CPU_POWERPC_603E_v12, 603E),
8065 /* PowerPC 603e v1.3 */
8066 POWERPC_DEF("603e_v1.3", CPU_POWERPC_603E_v13, 603E),
8067 /* PowerPC 603e v1.4 */
8068 POWERPC_DEF("603e_v1.4", CPU_POWERPC_603E_v14, 603E),
8069 /* PowerPC 603e v2.2 */
8070 POWERPC_DEF("603e_v2.2", CPU_POWERPC_603E_v22, 603E),
8071 /* PowerPC 603e v3 */
8072 POWERPC_DEF("603e_v3", CPU_POWERPC_603E_v3, 603E),
8073 /* PowerPC 603e v4 */
8074 POWERPC_DEF("603e_v4", CPU_POWERPC_603E_v4, 603E),
8075 /* PowerPC 603e v4.1 */
8076 POWERPC_DEF("603e_v4.1", CPU_POWERPC_603E_v41, 603E),
8077 /* PowerPC 603e (aka PID7) */
8078 POWERPC_DEF("603e7", CPU_POWERPC_603E7, 603E),
8079 /* PowerPC 603e7t */
8080 POWERPC_DEF("603e7t", CPU_POWERPC_603E7t, 603E),
8081 /* PowerPC 603e7v */
8082 POWERPC_DEF("603e7v", CPU_POWERPC_603E7v, 603E),
8083 /* Code name for PowerPC 603ev */
8084 POWERPC_DEF("Vaillant", CPU_POWERPC_603E7v, 603E),
8085 /* PowerPC 603e7v1 */
8086 POWERPC_DEF("603e7v1", CPU_POWERPC_603E7v1, 603E),
8087 /* PowerPC 603e7v2 */
8088 POWERPC_DEF("603e7v2", CPU_POWERPC_603E7v2, 603E),
8089 /* PowerPC 603p (aka PID7v) */
8090 POWERPC_DEF("603p", CPU_POWERPC_603P, 603E),
8091 /* PowerPC 603r (aka PID7t) */
8092 POWERPC_DEF("603r", CPU_POWERPC_603R, 603E),
8093 /* Code name for PowerPC 603r */
8094 POWERPC_DEF("Goldeneye", CPU_POWERPC_603R, 603E),
8095 /* PowerPC 604 */
8096 POWERPC_DEF("604", CPU_POWERPC_604, 604),
8097 /* PowerPC 604e (aka PID9) */
8098 POWERPC_DEF("604e", CPU_POWERPC_604E, 604E),
8099 /* Code name for PowerPC 604e */
8100 POWERPC_DEF("Sirocco", CPU_POWERPC_604E, 604E),
8101 /* PowerPC 604e v1.0 */
8102 POWERPC_DEF("604e_v1.0", CPU_POWERPC_604E_v10, 604E),
8103 /* PowerPC 604e v2.2 */
8104 POWERPC_DEF("604e_v2.2", CPU_POWERPC_604E_v22, 604E),
8105 /* PowerPC 604e v2.4 */
8106 POWERPC_DEF("604e_v2.4", CPU_POWERPC_604E_v24, 604E),
8107 /* PowerPC 604r (aka PIDA) */
8108 POWERPC_DEF("604r", CPU_POWERPC_604R, 604E),
8109 /* Code name for PowerPC 604r */
8110 POWERPC_DEF("Mach5", CPU_POWERPC_604R, 604E),
8111 #if defined(TODO)
8112 /* PowerPC 604ev */
8113 POWERPC_DEF("604ev", CPU_POWERPC_604EV, 604E),
8114 #endif
8115 /* PowerPC 7xx family */
8116 /* Generic PowerPC 740 (G3) */
8117 POWERPC_DEF("740", CPU_POWERPC_7x0, 740),
8118 /* Code name for PowerPC 740 */
8119 POWERPC_DEF("Arthur", CPU_POWERPC_7x0, 740),
8120 /* Generic PowerPC 750 (G3) */
8121 POWERPC_DEF("750", CPU_POWERPC_7x0, 750),
8122 /* Code name for PowerPC 750 */
8123 POWERPC_DEF("Typhoon", CPU_POWERPC_7x0, 750),
8124 /* PowerPC 740/750 is also known as G3 */
8125 POWERPC_DEF("G3", CPU_POWERPC_7x0, 750),
8126 /* PowerPC 740 v1.0 (G3) */
8127 POWERPC_DEF("740_v1.0", CPU_POWERPC_7x0_v10, 740),
8128 /* PowerPC 750 v1.0 (G3) */
8129 POWERPC_DEF("750_v1.0", CPU_POWERPC_7x0_v10, 750),
8130 /* PowerPC 740 v2.0 (G3) */
8131 POWERPC_DEF("740_v2.0", CPU_POWERPC_7x0_v20, 740),
8132 /* PowerPC 750 v2.0 (G3) */
8133 POWERPC_DEF("750_v2.0", CPU_POWERPC_7x0_v20, 750),
8134 /* PowerPC 740 v2.1 (G3) */
8135 POWERPC_DEF("740_v2.1", CPU_POWERPC_7x0_v21, 740),
8136 /* PowerPC 750 v2.1 (G3) */
8137 POWERPC_DEF("750_v2.1", CPU_POWERPC_7x0_v21, 750),
8138 /* PowerPC 740 v2.2 (G3) */
8139 POWERPC_DEF("740_v2.2", CPU_POWERPC_7x0_v22, 740),
8140 /* PowerPC 750 v2.2 (G3) */
8141 POWERPC_DEF("750_v2.2", CPU_POWERPC_7x0_v22, 750),
8142 /* PowerPC 740 v3.0 (G3) */
8143 POWERPC_DEF("740_v3.0", CPU_POWERPC_7x0_v30, 740),
8144 /* PowerPC 750 v3.0 (G3) */
8145 POWERPC_DEF("750_v3.0", CPU_POWERPC_7x0_v30, 750),
8146 /* PowerPC 740 v3.1 (G3) */
8147 POWERPC_DEF("740_v3.1", CPU_POWERPC_7x0_v31, 740),
8148 /* PowerPC 750 v3.1 (G3) */
8149 POWERPC_DEF("750_v3.1", CPU_POWERPC_7x0_v31, 750),
8150 /* PowerPC 740E (G3) */
8151 POWERPC_DEF("740e", CPU_POWERPC_740E, 740),
8152 /* PowerPC 750E (G3) */
8153 POWERPC_DEF("750e", CPU_POWERPC_750E, 750),
8154 /* PowerPC 740P (G3) */
8155 POWERPC_DEF("740p", CPU_POWERPC_7x0P, 740),
8156 /* PowerPC 750P (G3) */
8157 POWERPC_DEF("750p", CPU_POWERPC_7x0P, 750),
8158 /* Code name for PowerPC 740P/750P (G3) */
8159 POWERPC_DEF("Conan/Doyle", CPU_POWERPC_7x0P, 750),
8160 /* PowerPC 750CL (G3 embedded) */
8161 POWERPC_DEF("750cl", CPU_POWERPC_750CL, 750cl),
8162 /* PowerPC 750CL v1.0 */
8163 POWERPC_DEF("750cl_v1.0", CPU_POWERPC_750CL_v10, 750cl),
8164 /* PowerPC 750CL v2.0 */
8165 POWERPC_DEF("750cl_v2.0", CPU_POWERPC_750CL_v20, 750cl),
8166 /* PowerPC 750CX (G3 embedded) */
8167 POWERPC_DEF("750cx", CPU_POWERPC_750CX, 750cx),
8168 /* PowerPC 750CX v1.0 (G3 embedded) */
8169 POWERPC_DEF("750cx_v1.0", CPU_POWERPC_750CX_v10, 750cx),
8170 /* PowerPC 750CX v2.1 (G3 embedded) */
8171 POWERPC_DEF("750cx_v2.0", CPU_POWERPC_750CX_v20, 750cx),
8172 /* PowerPC 750CX v2.1 (G3 embedded) */
8173 POWERPC_DEF("750cx_v2.1", CPU_POWERPC_750CX_v21, 750cx),
8174 /* PowerPC 750CX v2.2 (G3 embedded) */
8175 POWERPC_DEF("750cx_v2.2", CPU_POWERPC_750CX_v22, 750cx),
8176 /* PowerPC 750CXe (G3 embedded) */
8177 POWERPC_DEF("750cxe", CPU_POWERPC_750CXE, 750cx),
8178 /* PowerPC 750CXe v2.1 (G3 embedded) */
8179 POWERPC_DEF("750cxe_v2.1", CPU_POWERPC_750CXE_v21, 750cx),
8180 /* PowerPC 750CXe v2.2 (G3 embedded) */
8181 POWERPC_DEF("750cxe_v2.2", CPU_POWERPC_750CXE_v22, 750cx),
8182 /* PowerPC 750CXe v2.3 (G3 embedded) */
8183 POWERPC_DEF("750cxe_v2.3", CPU_POWERPC_750CXE_v23, 750cx),
8184 /* PowerPC 750CXe v2.4 (G3 embedded) */
8185 POWERPC_DEF("750cxe_v2.4", CPU_POWERPC_750CXE_v24, 750cx),
8186 /* PowerPC 750CXe v2.4b (G3 embedded) */
8187 POWERPC_DEF("750cxe_v2.4b", CPU_POWERPC_750CXE_v24b, 750cx),
8188 /* PowerPC 750CXe v3.0 (G3 embedded) */
8189 POWERPC_DEF("750cxe_v3.0", CPU_POWERPC_750CXE_v30, 750cx),
8190 /* PowerPC 750CXe v3.1 (G3 embedded) */
8191 POWERPC_DEF("750cxe_v3.1", CPU_POWERPC_750CXE_v31, 750cx),
8192 /* PowerPC 750CXe v3.1b (G3 embedded) */
8193 POWERPC_DEF("750cxe_v3.1b", CPU_POWERPC_750CXE_v31b, 750cx),
8194 /* PowerPC 750CXr (G3 embedded) */
8195 POWERPC_DEF("750cxr", CPU_POWERPC_750CXR, 750cx),
8196 /* PowerPC 750FL (G3 embedded) */
8197 POWERPC_DEF("750fl", CPU_POWERPC_750FL, 750fx),
8198 /* PowerPC 750FX (G3 embedded) */
8199 POWERPC_DEF("750fx", CPU_POWERPC_750FX, 750fx),
8200 /* PowerPC 750FX v1.0 (G3 embedded) */
8201 POWERPC_DEF("750fx_v1.0", CPU_POWERPC_750FX_v10, 750fx),
8202 /* PowerPC 750FX v2.0 (G3 embedded) */
8203 POWERPC_DEF("750fx_v2.0", CPU_POWERPC_750FX_v20, 750fx),
8204 /* PowerPC 750FX v2.1 (G3 embedded) */
8205 POWERPC_DEF("750fx_v2.1", CPU_POWERPC_750FX_v21, 750fx),
8206 /* PowerPC 750FX v2.2 (G3 embedded) */
8207 POWERPC_DEF("750fx_v2.2", CPU_POWERPC_750FX_v22, 750fx),
8208 /* PowerPC 750FX v2.3 (G3 embedded) */
8209 POWERPC_DEF("750fx_v2.3", CPU_POWERPC_750FX_v23, 750fx),
8210 /* PowerPC 750GL (G3 embedded) */
8211 POWERPC_DEF("750gl", CPU_POWERPC_750GL, 750gx),
8212 /* PowerPC 750GX (G3 embedded) */
8213 POWERPC_DEF("750gx", CPU_POWERPC_750GX, 750gx),
8214 /* PowerPC 750GX v1.0 (G3 embedded) */
8215 POWERPC_DEF("750gx_v1.0", CPU_POWERPC_750GX_v10, 750gx),
8216 /* PowerPC 750GX v1.1 (G3 embedded) */
8217 POWERPC_DEF("750gx_v1.1", CPU_POWERPC_750GX_v11, 750gx),
8218 /* PowerPC 750GX v1.2 (G3 embedded) */
8219 POWERPC_DEF("750gx_v1.2", CPU_POWERPC_750GX_v12, 750gx),
8220 /* PowerPC 750L (G3 embedded) */
8221 POWERPC_DEF("750l", CPU_POWERPC_750L, 750),
8222 /* Code name for PowerPC 750L (G3 embedded) */
8223 POWERPC_DEF("LoneStar", CPU_POWERPC_750L, 750),
8224 /* PowerPC 750L v2.0 (G3 embedded) */
8225 POWERPC_DEF("750l_v2.0", CPU_POWERPC_750L_v20, 750),
8226 /* PowerPC 750L v2.1 (G3 embedded) */
8227 POWERPC_DEF("750l_v2.1", CPU_POWERPC_750L_v21, 750),
8228 /* PowerPC 750L v2.2 (G3 embedded) */
8229 POWERPC_DEF("750l_v2.2", CPU_POWERPC_750L_v22, 750),
8230 /* PowerPC 750L v3.0 (G3 embedded) */
8231 POWERPC_DEF("750l_v3.0", CPU_POWERPC_750L_v30, 750),
8232 /* PowerPC 750L v3.2 (G3 embedded) */
8233 POWERPC_DEF("750l_v3.2", CPU_POWERPC_750L_v32, 750),
8234 /* Generic PowerPC 745 */
8235 POWERPC_DEF("745", CPU_POWERPC_7x5, 745),
8236 /* Generic PowerPC 755 */
8237 POWERPC_DEF("755", CPU_POWERPC_7x5, 755),
8238 /* Code name for PowerPC 745/755 */
8239 POWERPC_DEF("Goldfinger", CPU_POWERPC_7x5, 755),
8240 /* PowerPC 745 v1.0 */
8241 POWERPC_DEF("745_v1.0", CPU_POWERPC_7x5_v10, 745),
8242 /* PowerPC 755 v1.0 */
8243 POWERPC_DEF("755_v1.0", CPU_POWERPC_7x5_v10, 755),
8244 /* PowerPC 745 v1.1 */
8245 POWERPC_DEF("745_v1.1", CPU_POWERPC_7x5_v11, 745),
8246 /* PowerPC 755 v1.1 */
8247 POWERPC_DEF("755_v1.1", CPU_POWERPC_7x5_v11, 755),
8248 /* PowerPC 745 v2.0 */
8249 POWERPC_DEF("745_v2.0", CPU_POWERPC_7x5_v20, 745),
8250 /* PowerPC 755 v2.0 */
8251 POWERPC_DEF("755_v2.0", CPU_POWERPC_7x5_v20, 755),
8252 /* PowerPC 745 v2.1 */
8253 POWERPC_DEF("745_v2.1", CPU_POWERPC_7x5_v21, 745),
8254 /* PowerPC 755 v2.1 */
8255 POWERPC_DEF("755_v2.1", CPU_POWERPC_7x5_v21, 755),
8256 /* PowerPC 745 v2.2 */
8257 POWERPC_DEF("745_v2.2", CPU_POWERPC_7x5_v22, 745),
8258 /* PowerPC 755 v2.2 */
8259 POWERPC_DEF("755_v2.2", CPU_POWERPC_7x5_v22, 755),
8260 /* PowerPC 745 v2.3 */
8261 POWERPC_DEF("745_v2.3", CPU_POWERPC_7x5_v23, 745),
8262 /* PowerPC 755 v2.3 */
8263 POWERPC_DEF("755_v2.3", CPU_POWERPC_7x5_v23, 755),
8264 /* PowerPC 745 v2.4 */
8265 POWERPC_DEF("745_v2.4", CPU_POWERPC_7x5_v24, 745),
8266 /* PowerPC 755 v2.4 */
8267 POWERPC_DEF("755_v2.4", CPU_POWERPC_7x5_v24, 755),
8268 /* PowerPC 745 v2.5 */
8269 POWERPC_DEF("745_v2.5", CPU_POWERPC_7x5_v25, 745),
8270 /* PowerPC 755 v2.5 */
8271 POWERPC_DEF("755_v2.5", CPU_POWERPC_7x5_v25, 755),
8272 /* PowerPC 745 v2.6 */
8273 POWERPC_DEF("745_v2.6", CPU_POWERPC_7x5_v26, 745),
8274 /* PowerPC 755 v2.6 */
8275 POWERPC_DEF("755_v2.6", CPU_POWERPC_7x5_v26, 755),
8276 /* PowerPC 745 v2.7 */
8277 POWERPC_DEF("745_v2.7", CPU_POWERPC_7x5_v27, 745),
8278 /* PowerPC 755 v2.7 */
8279 POWERPC_DEF("755_v2.7", CPU_POWERPC_7x5_v27, 755),
8280 /* PowerPC 745 v2.8 */
8281 POWERPC_DEF("745_v2.8", CPU_POWERPC_7x5_v28, 745),
8282 /* PowerPC 755 v2.8 */
8283 POWERPC_DEF("755_v2.8", CPU_POWERPC_7x5_v28, 755),
8284 #if defined (TODO)
8285 /* PowerPC 745P (G3) */
8286 POWERPC_DEF("745p", CPU_POWERPC_7x5P, 745),
8287 /* PowerPC 755P (G3) */
8288 POWERPC_DEF("755p", CPU_POWERPC_7x5P, 755),
8289 #endif
8290 /* PowerPC 74xx family */
8291 /* PowerPC 7400 (G4) */
8292 POWERPC_DEF("7400", CPU_POWERPC_7400, 7400),
8293 /* Code name for PowerPC 7400 */
8294 POWERPC_DEF("Max", CPU_POWERPC_7400, 7400),
8295 /* PowerPC 74xx is also well known as G4 */
8296 POWERPC_DEF("G4", CPU_POWERPC_7400, 7400),
8297 /* PowerPC 7400 v1.0 (G4) */
8298 POWERPC_DEF("7400_v1.0", CPU_POWERPC_7400_v10, 7400),
8299 /* PowerPC 7400 v1.1 (G4) */
8300 POWERPC_DEF("7400_v1.1", CPU_POWERPC_7400_v11, 7400),
8301 /* PowerPC 7400 v2.0 (G4) */
8302 POWERPC_DEF("7400_v2.0", CPU_POWERPC_7400_v20, 7400),
8303 /* PowerPC 7400 v2.2 (G4) */
8304 POWERPC_DEF("7400_v2.2", CPU_POWERPC_7400_v22, 7400),
8305 /* PowerPC 7400 v2.6 (G4) */
8306 POWERPC_DEF("7400_v2.6", CPU_POWERPC_7400_v26, 7400),
8307 /* PowerPC 7400 v2.7 (G4) */
8308 POWERPC_DEF("7400_v2.7", CPU_POWERPC_7400_v27, 7400),
8309 /* PowerPC 7400 v2.8 (G4) */
8310 POWERPC_DEF("7400_v2.8", CPU_POWERPC_7400_v28, 7400),
8311 /* PowerPC 7400 v2.9 (G4) */
8312 POWERPC_DEF("7400_v2.9", CPU_POWERPC_7400_v29, 7400),
8313 /* PowerPC 7410 (G4) */
8314 POWERPC_DEF("7410", CPU_POWERPC_7410, 7410),
8315 /* Code name for PowerPC 7410 */
8316 POWERPC_DEF("Nitro", CPU_POWERPC_7410, 7410),
8317 /* PowerPC 7410 v1.0 (G4) */
8318 POWERPC_DEF("7410_v1.0", CPU_POWERPC_7410_v10, 7410),
8319 /* PowerPC 7410 v1.1 (G4) */
8320 POWERPC_DEF("7410_v1.1", CPU_POWERPC_7410_v11, 7410),
8321 /* PowerPC 7410 v1.2 (G4) */
8322 POWERPC_DEF("7410_v1.2", CPU_POWERPC_7410_v12, 7410),
8323 /* PowerPC 7410 v1.3 (G4) */
8324 POWERPC_DEF("7410_v1.3", CPU_POWERPC_7410_v13, 7410),
8325 /* PowerPC 7410 v1.4 (G4) */
8326 POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410),
8327 /* PowerPC 7448 (G4) */
8328 POWERPC_DEF("7448", CPU_POWERPC_7448, 7400),
8329 /* PowerPC 7448 v1.0 (G4) */
8330 POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400),
8331 /* PowerPC 7448 v1.1 (G4) */
8332 POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400),
8333 /* PowerPC 7448 v2.0 (G4) */
8334 POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400),
8335 /* PowerPC 7448 v2.1 (G4) */
8336 POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400),
8337 /* PowerPC 7450 (G4) */
8338 POWERPC_DEF("7450", CPU_POWERPC_7450, 7450),
8339 /* Code name for PowerPC 7450 */
8340 POWERPC_DEF("Vger", CPU_POWERPC_7450, 7450),
8341 /* PowerPC 7450 v1.0 (G4) */
8342 POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450),
8343 /* PowerPC 7450 v1.1 (G4) */
8344 POWERPC_DEF("7450_v1.1", CPU_POWERPC_7450_v11, 7450),
8345 /* PowerPC 7450 v1.2 (G4) */
8346 POWERPC_DEF("7450_v1.2", CPU_POWERPC_7450_v12, 7450),
8347 /* PowerPC 7450 v2.0 (G4) */
8348 POWERPC_DEF("7450_v2.0", CPU_POWERPC_7450_v20, 7450),
8349 /* PowerPC 7450 v2.1 (G4) */
8350 POWERPC_DEF("7450_v2.1", CPU_POWERPC_7450_v21, 7450),
8351 /* PowerPC 7441 (G4) */
8352 POWERPC_DEF("7441", CPU_POWERPC_74x1, 7440),
8353 /* PowerPC 7451 (G4) */
8354 POWERPC_DEF("7451", CPU_POWERPC_74x1, 7450),
8355 /* PowerPC 7441g (G4) */
8356 POWERPC_DEF("7441g", CPU_POWERPC_74x1G, 7440),
8357 /* PowerPC 7451g (G4) */
8358 POWERPC_DEF("7451g", CPU_POWERPC_74x1G, 7450),
8359 /* PowerPC 7445 (G4) */
8360 POWERPC_DEF("7445", CPU_POWERPC_74x5, 7445),
8361 /* PowerPC 7455 (G4) */
8362 POWERPC_DEF("7455", CPU_POWERPC_74x5, 7455),
8363 /* Code name for PowerPC 7445/7455 */
8364 POWERPC_DEF("Apollo6", CPU_POWERPC_74x5, 7455),
8365 /* PowerPC 7445 v1.0 (G4) */
8366 POWERPC_DEF("7445_v1.0", CPU_POWERPC_74x5_v10, 7445),
8367 /* PowerPC 7455 v1.0 (G4) */
8368 POWERPC_DEF("7455_v1.0", CPU_POWERPC_74x5_v10, 7455),
8369 /* PowerPC 7445 v2.1 (G4) */
8370 POWERPC_DEF("7445_v2.1", CPU_POWERPC_74x5_v21, 7445),
8371 /* PowerPC 7455 v2.1 (G4) */
8372 POWERPC_DEF("7455_v2.1", CPU_POWERPC_74x5_v21, 7455),
8373 /* PowerPC 7445 v3.2 (G4) */
8374 POWERPC_DEF("7445_v3.2", CPU_POWERPC_74x5_v32, 7445),
8375 /* PowerPC 7455 v3.2 (G4) */
8376 POWERPC_DEF("7455_v3.2", CPU_POWERPC_74x5_v32, 7455),
8377 /* PowerPC 7445 v3.3 (G4) */
8378 POWERPC_DEF("7445_v3.3", CPU_POWERPC_74x5_v33, 7445),
8379 /* PowerPC 7455 v3.3 (G4) */
8380 POWERPC_DEF("7455_v3.3", CPU_POWERPC_74x5_v33, 7455),
8381 /* PowerPC 7445 v3.4 (G4) */
8382 POWERPC_DEF("7445_v3.4", CPU_POWERPC_74x5_v34, 7445),
8383 /* PowerPC 7455 v3.4 (G4) */
8384 POWERPC_DEF("7455_v3.4", CPU_POWERPC_74x5_v34, 7455),
8385 /* PowerPC 7447 (G4) */
8386 POWERPC_DEF("7447", CPU_POWERPC_74x7, 7445),
8387 /* PowerPC 7457 (G4) */
8388 POWERPC_DEF("7457", CPU_POWERPC_74x7, 7455),
8389 /* Code name for PowerPC 7447/7457 */
8390 POWERPC_DEF("Apollo7", CPU_POWERPC_74x7, 7455),
8391 /* PowerPC 7447 v1.0 (G4) */
8392 POWERPC_DEF("7447_v1.0", CPU_POWERPC_74x7_v10, 7445),
8393 /* PowerPC 7457 v1.0 (G4) */
8394 POWERPC_DEF("7457_v1.0", CPU_POWERPC_74x7_v10, 7455),
8395 /* PowerPC 7447 v1.1 (G4) */
8396 POWERPC_DEF("7447_v1.1", CPU_POWERPC_74x7_v11, 7445),
8397 /* PowerPC 7457 v1.1 (G4) */
8398 POWERPC_DEF("7457_v1.1", CPU_POWERPC_74x7_v11, 7455),
8399 /* PowerPC 7447 v1.2 (G4) */
8400 POWERPC_DEF("7447_v1.2", CPU_POWERPC_74x7_v12, 7445),
8401 /* PowerPC 7457 v1.2 (G4) */
8402 POWERPC_DEF("7457_v1.2", CPU_POWERPC_74x7_v12, 7455),
8403 /* PowerPC 7447A (G4) */
8404 POWERPC_DEF("7447A", CPU_POWERPC_74x7A, 7445),
8405 /* PowerPC 7457A (G4) */
8406 POWERPC_DEF("7457A", CPU_POWERPC_74x7A, 7455),
8407 /* PowerPC 7447A v1.0 (G4) */
8408 POWERPC_DEF("7447A_v1.0", CPU_POWERPC_74x7A_v10, 7445),
8409 /* PowerPC 7457A v1.0 (G4) */
8410 POWERPC_DEF("7457A_v1.0", CPU_POWERPC_74x7A_v10, 7455),
8411 /* Code name for PowerPC 7447A/7457A */
8412 POWERPC_DEF("Apollo7PM", CPU_POWERPC_74x7A_v10, 7455),
8413 /* PowerPC 7447A v1.1 (G4) */
8414 POWERPC_DEF("7447A_v1.1", CPU_POWERPC_74x7A_v11, 7445),
8415 /* PowerPC 7457A v1.1 (G4) */
8416 POWERPC_DEF("7457A_v1.1", CPU_POWERPC_74x7A_v11, 7455),
8417 /* PowerPC 7447A v1.2 (G4) */
8418 POWERPC_DEF("7447A_v1.2", CPU_POWERPC_74x7A_v12, 7445),
8419 /* PowerPC 7457A v1.2 (G4) */
8420 POWERPC_DEF("7457A_v1.2", CPU_POWERPC_74x7A_v12, 7455),
8421 /* 64 bits PowerPC */
8422 #if defined (TARGET_PPC64)
8423 /* PowerPC 620 */
8424 POWERPC_DEF("620", CPU_POWERPC_620, 620),
8425 /* Code name for PowerPC 620 */
8426 POWERPC_DEF("Trident", CPU_POWERPC_620, 620),
8427 #if defined (TODO)
8428 /* PowerPC 630 (POWER3) */
8429 POWERPC_DEF("630", CPU_POWERPC_630, 630),
8430 POWERPC_DEF("POWER3", CPU_POWERPC_630, 630),
8431 /* Code names for POWER3 */
8432 POWERPC_DEF("Boxer", CPU_POWERPC_630, 630),
8433 POWERPC_DEF("Dino", CPU_POWERPC_630, 630),
8434 #endif
8435 #if defined (TODO)
8436 /* PowerPC 631 (Power 3+) */
8437 POWERPC_DEF("631", CPU_POWERPC_631, 631),
8438 POWERPC_DEF("POWER3+", CPU_POWERPC_631, 631),
8439 #endif
8440 #if defined (TODO)
8441 /* POWER4 */
8442 POWERPC_DEF("POWER4", CPU_POWERPC_POWER4, POWER4),
8443 #endif
8444 #if defined (TODO)
8445 /* POWER4p */
8446 POWERPC_DEF("POWER4+", CPU_POWERPC_POWER4P, POWER4P),
8447 #endif
8448 #if defined (TODO)
8449 /* POWER5 */
8450 POWERPC_DEF("POWER5", CPU_POWERPC_POWER5, POWER5),
8451 /* POWER5GR */
8452 POWERPC_DEF("POWER5gr", CPU_POWERPC_POWER5GR, POWER5),
8453 #endif
8454 #if defined (TODO)
8455 /* POWER5+ */
8456 POWERPC_DEF("POWER5+", CPU_POWERPC_POWER5P, POWER5P),
8457 /* POWER5GS */
8458 POWERPC_DEF("POWER5gs", CPU_POWERPC_POWER5GS, POWER5P),
8459 #endif
8460 #if defined (TODO)
8461 /* POWER6 */
8462 POWERPC_DEF("POWER6", CPU_POWERPC_POWER6, POWER6),
8463 /* POWER6 running in POWER5 mode */
8464 POWERPC_DEF("POWER6_5", CPU_POWERPC_POWER6_5, POWER5),
8465 /* POWER6A */
8466 POWERPC_DEF("POWER6A", CPU_POWERPC_POWER6A, POWER6),
8467 #endif
8468 /* PowerPC 970 */
8469 POWERPC_DEF("970", CPU_POWERPC_970, 970),
8470 /* PowerPC 970FX (G5) */
8471 POWERPC_DEF("970fx", CPU_POWERPC_970FX, 970FX),
8472 /* PowerPC 970FX v1.0 (G5) */
8473 POWERPC_DEF("970fx_v1.0", CPU_POWERPC_970FX_v10, 970FX),
8474 /* PowerPC 970FX v2.0 (G5) */
8475 POWERPC_DEF("970fx_v2.0", CPU_POWERPC_970FX_v20, 970FX),
8476 /* PowerPC 970FX v2.1 (G5) */
8477 POWERPC_DEF("970fx_v2.1", CPU_POWERPC_970FX_v21, 970FX),
8478 /* PowerPC 970FX v3.0 (G5) */
8479 POWERPC_DEF("970fx_v3.0", CPU_POWERPC_970FX_v30, 970FX),
8480 /* PowerPC 970FX v3.1 (G5) */
8481 POWERPC_DEF("970fx_v3.1", CPU_POWERPC_970FX_v31, 970FX),
8482 /* PowerPC 970GX (G5) */
8483 POWERPC_DEF("970gx", CPU_POWERPC_970GX, 970GX),
8484 /* PowerPC 970MP */
8485 POWERPC_DEF("970mp", CPU_POWERPC_970MP, 970MP),
8486 /* PowerPC 970MP v1.0 */
8487 POWERPC_DEF("970mp_v1.0", CPU_POWERPC_970MP_v10, 970MP),
8488 /* PowerPC 970MP v1.1 */
8489 POWERPC_DEF("970mp_v1.1", CPU_POWERPC_970MP_v11, 970MP),
8490 #if defined (TODO)
8491 /* PowerPC Cell */
8492 POWERPC_DEF("Cell", CPU_POWERPC_CELL, 970),
8493 #endif
8494 #if defined (TODO)
8495 /* PowerPC Cell v1.0 */
8496 POWERPC_DEF("Cell_v1.0", CPU_POWERPC_CELL_v10, 970),
8497 #endif
8498 #if defined (TODO)
8499 /* PowerPC Cell v2.0 */
8500 POWERPC_DEF("Cell_v2.0", CPU_POWERPC_CELL_v20, 970),
8501 #endif
8502 #if defined (TODO)
8503 /* PowerPC Cell v3.0 */
8504 POWERPC_DEF("Cell_v3.0", CPU_POWERPC_CELL_v30, 970),
8505 #endif
8506 #if defined (TODO)
8507 /* PowerPC Cell v3.1 */
8508 POWERPC_DEF("Cell_v3.1", CPU_POWERPC_CELL_v31, 970),
8509 #endif
8510 #if defined (TODO)
8511 /* PowerPC Cell v3.2 */
8512 POWERPC_DEF("Cell_v3.2", CPU_POWERPC_CELL_v32, 970),
8513 #endif
8514 #if defined (TODO)
8515 /* RS64 (Apache/A35) */
8516 /* This one seems to support the whole POWER2 instruction set
8517 * and the PowerPC 64 one.
8518 */
8519 /* What about A10 & A30 ? */
8520 POWERPC_DEF("RS64", CPU_POWERPC_RS64, RS64),
8521 POWERPC_DEF("Apache", CPU_POWERPC_RS64, RS64),
8522 POWERPC_DEF("A35", CPU_POWERPC_RS64, RS64),
8523 #endif
8524 #if defined (TODO)
8525 /* RS64-II (NorthStar/A50) */
8526 POWERPC_DEF("RS64-II", CPU_POWERPC_RS64II, RS64),
8527 POWERPC_DEF("NorthStar", CPU_POWERPC_RS64II, RS64),
8528 POWERPC_DEF("A50", CPU_POWERPC_RS64II, RS64),
8529 #endif
8530 #if defined (TODO)
8531 /* RS64-III (Pulsar) */
8532 POWERPC_DEF("RS64-III", CPU_POWERPC_RS64III, RS64),
8533 POWERPC_DEF("Pulsar", CPU_POWERPC_RS64III, RS64),
8534 #endif
8535 #if defined (TODO)
8536 /* RS64-IV (IceStar/IStar/SStar) */
8537 POWERPC_DEF("RS64-IV", CPU_POWERPC_RS64IV, RS64),
8538 POWERPC_DEF("IceStar", CPU_POWERPC_RS64IV, RS64),
8539 POWERPC_DEF("IStar", CPU_POWERPC_RS64IV, RS64),
8540 POWERPC_DEF("SStar", CPU_POWERPC_RS64IV, RS64),
8541 #endif
8542 #endif /* defined (TARGET_PPC64) */
8543 /* POWER */
8544 #if defined (TODO)
8545 /* Original POWER */
8546 POWERPC_DEF("POWER", CPU_POWERPC_POWER, POWER),
8547 POWERPC_DEF("RIOS", CPU_POWERPC_POWER, POWER),
8548 POWERPC_DEF("RSC", CPU_POWERPC_POWER, POWER),
8549 POWERPC_DEF("RSC3308", CPU_POWERPC_POWER, POWER),
8550 POWERPC_DEF("RSC4608", CPU_POWERPC_POWER, POWER),
8551 #endif
8552 #if defined (TODO)
8553 /* POWER2 */
8554 POWERPC_DEF("POWER2", CPU_POWERPC_POWER2, POWER),
8555 POWERPC_DEF("RSC2", CPU_POWERPC_POWER2, POWER),
8556 POWERPC_DEF("P2SC", CPU_POWERPC_POWER2, POWER),
8557 #endif
8558 /* PA semi cores */
8559 #if defined (TODO)
8560 /* PA PA6T */
8561 POWERPC_DEF("PA6T", CPU_POWERPC_PA6T, PA6T),
8562 #endif
8563 /* Generic PowerPCs */
8564 #if defined (TARGET_PPC64)
8565 POWERPC_DEF("ppc64", CPU_POWERPC_PPC64, PPC64),
8566 #endif
8567 POWERPC_DEF("ppc32", CPU_POWERPC_PPC32, PPC32),
8568 POWERPC_DEF("ppc", CPU_POWERPC_DEFAULT, DEFAULT),
8569 /* Fallback */
8570 POWERPC_DEF("default", CPU_POWERPC_DEFAULT, DEFAULT),
8571 };
8572
8573 /*****************************************************************************/
8574 /* Generic CPU instanciation routine */
8575 static void init_ppc_proc (CPUPPCState *env, const ppc_def_t *def)
8576 {
8577 #if !defined(CONFIG_USER_ONLY)
8578 int i;
8579
8580 env->irq_inputs = NULL;
8581 /* Set all exception vectors to an invalid address */
8582 for (i = 0; i < POWERPC_EXCP_NB; i++)
8583 env->excp_vectors[i] = (target_ulong)(-1ULL);
8584 env->excp_prefix = 0x00000000;
8585 env->ivor_mask = 0x00000000;
8586 env->ivpr_mask = 0x00000000;
8587 /* Default MMU definitions */
8588 env->nb_BATs = 0;
8589 env->nb_tlb = 0;
8590 env->nb_ways = 0;
8591 #endif
8592 /* Register SPR common to all PowerPC implementations */
8593 gen_spr_generic(env);
8594 spr_register(env, SPR_PVR, "PVR",
8595 SPR_NOACCESS, SPR_NOACCESS,
8596 &spr_read_generic, SPR_NOACCESS,
8597 def->pvr);
8598 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8599 if (def->svr != POWERPC_SVR_NONE) {
8600 if (def->svr & POWERPC_SVR_E500) {
8601 spr_register(env, SPR_E500_SVR, "SVR",
8602 SPR_NOACCESS, SPR_NOACCESS,
8603 &spr_read_generic, SPR_NOACCESS,
8604 def->svr & ~POWERPC_SVR_E500);
8605 } else {
8606 spr_register(env, SPR_SVR, "SVR",
8607 SPR_NOACCESS, SPR_NOACCESS,
8608 &spr_read_generic, SPR_NOACCESS,
8609 def->svr);
8610 }
8611 }
8612 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8613 (*def->init_proc)(env);
8614 /* MSR bits & flags consistency checks */
8615 if (env->msr_mask & (1 << 25)) {
8616 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8617 case POWERPC_FLAG_SPE:
8618 case POWERPC_FLAG_VRE:
8619 break;
8620 default:
8621 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8622 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8623 exit(1);
8624 }
8625 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8626 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8627 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8628 exit(1);
8629 }
8630 if (env->msr_mask & (1 << 17)) {
8631 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8632 case POWERPC_FLAG_TGPR:
8633 case POWERPC_FLAG_CE:
8634 break;
8635 default:
8636 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8637 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8638 exit(1);
8639 }
8640 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8641 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8642 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8643 exit(1);
8644 }
8645 if (env->msr_mask & (1 << 10)) {
8646 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8647 POWERPC_FLAG_UBLE)) {
8648 case POWERPC_FLAG_SE:
8649 case POWERPC_FLAG_DWE:
8650 case POWERPC_FLAG_UBLE:
8651 break;
8652 default:
8653 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8654 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8655 "POWERPC_FLAG_UBLE\n");
8656 exit(1);
8657 }
8658 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8659 POWERPC_FLAG_UBLE)) {
8660 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8661 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8662 "POWERPC_FLAG_UBLE\n");
8663 exit(1);
8664 }
8665 if (env->msr_mask & (1 << 9)) {
8666 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8667 case POWERPC_FLAG_BE:
8668 case POWERPC_FLAG_DE:
8669 break;
8670 default:
8671 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8672 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8673 exit(1);
8674 }
8675 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8676 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8677 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8678 exit(1);
8679 }
8680 if (env->msr_mask & (1 << 2)) {
8681 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8682 case POWERPC_FLAG_PX:
8683 case POWERPC_FLAG_PMM:
8684 break;
8685 default:
8686 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8687 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8688 exit(1);
8689 }
8690 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8691 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8692 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8693 exit(1);
8694 }
8695 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8696 fprintf(stderr, "PowerPC flags inconsistency\n"
8697 "Should define the time-base and decrementer clock source\n");
8698 exit(1);
8699 }
8700 /* Allocate TLBs buffer when needed */
8701 #if !defined(CONFIG_USER_ONLY)
8702 if (env->nb_tlb != 0) {
8703 int nb_tlb = env->nb_tlb;
8704 if (env->id_tlbs != 0)
8705 nb_tlb *= 2;
8706 env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
8707 /* Pre-compute some useful values */
8708 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8709 }
8710 if (env->irq_inputs == NULL) {
8711 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8712 " Attempt Qemu to crash very soon !\n");
8713 }
8714 #endif
8715 if (env->check_pow == NULL) {
8716 fprintf(stderr, "WARNING: no power management check handler "
8717 "registered.\n"
8718 " Attempt Qemu to crash very soon !\n");
8719 }
8720 }
8721
8722 #if defined(PPC_DUMP_CPU)
8723 static void dump_ppc_sprs (CPUPPCState *env)
8724 {
8725 ppc_spr_t *spr;
8726 #if !defined(CONFIG_USER_ONLY)
8727 uint32_t sr, sw;
8728 #endif
8729 uint32_t ur, uw;
8730 int i, j, n;
8731
8732 printf("Special purpose registers:\n");
8733 for (i = 0; i < 32; i++) {
8734 for (j = 0; j < 32; j++) {
8735 n = (i << 5) | j;
8736 spr = &env->spr_cb[n];
8737 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8738 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8739 #if !defined(CONFIG_USER_ONLY)
8740 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8741 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8742 if (sw || sr || uw || ur) {
8743 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8744 (i << 5) | j, (i << 5) | j, spr->name,
8745 sw ? 'w' : '-', sr ? 'r' : '-',
8746 uw ? 'w' : '-', ur ? 'r' : '-');
8747 }
8748 #else
8749 if (uw || ur) {
8750 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8751 (i << 5) | j, (i << 5) | j, spr->name,
8752 uw ? 'w' : '-', ur ? 'r' : '-');
8753 }
8754 #endif
8755 }
8756 }
8757 fflush(stdout);
8758 fflush(stderr);
8759 }
8760 #endif
8761
8762 /*****************************************************************************/
8763 #include <stdlib.h>
8764 #include <string.h>
8765
8766 int fflush (FILE *stream);
8767
8768 /* Opcode types */
8769 enum {
8770 PPC_DIRECT = 0, /* Opcode routine */
8771 PPC_INDIRECT = 1, /* Indirect opcode table */
8772 };
8773
8774 static inline int is_indirect_opcode (void *handler)
8775 {
8776 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
8777 }
8778
8779 static inline opc_handler_t **ind_table(void *handler)
8780 {
8781 return (opc_handler_t **)((unsigned long)handler & ~3);
8782 }
8783
8784 /* Instruction table creation */
8785 /* Opcodes tables creation */
8786 static void fill_new_table (opc_handler_t **table, int len)
8787 {
8788 int i;
8789
8790 for (i = 0; i < len; i++)
8791 table[i] = &invalid_handler;
8792 }
8793
8794 static int create_new_table (opc_handler_t **table, unsigned char idx)
8795 {
8796 opc_handler_t **tmp;
8797
8798 tmp = malloc(0x20 * sizeof(opc_handler_t));
8799 if (tmp == NULL)
8800 return -1;
8801 fill_new_table(tmp, 0x20);
8802 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
8803
8804 return 0;
8805 }
8806
8807 static int insert_in_table (opc_handler_t **table, unsigned char idx,
8808 opc_handler_t *handler)
8809 {
8810 if (table[idx] != &invalid_handler)
8811 return -1;
8812 table[idx] = handler;
8813
8814 return 0;
8815 }
8816
8817 static int register_direct_insn (opc_handler_t **ppc_opcodes,
8818 unsigned char idx, opc_handler_t *handler)
8819 {
8820 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8821 printf("*** ERROR: opcode %02x already assigned in main "
8822 "opcode table\n", idx);
8823 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8824 printf(" Registered handler '%s' - new handler '%s'\n",
8825 ppc_opcodes[idx]->oname, handler->oname);
8826 #endif
8827 return -1;
8828 }
8829
8830 return 0;
8831 }
8832
8833 static int register_ind_in_table (opc_handler_t **table,
8834 unsigned char idx1, unsigned char idx2,
8835 opc_handler_t *handler)
8836 {
8837 if (table[idx1] == &invalid_handler) {
8838 if (create_new_table(table, idx1) < 0) {
8839 printf("*** ERROR: unable to create indirect table "
8840 "idx=%02x\n", idx1);
8841 return -1;
8842 }
8843 } else {
8844 if (!is_indirect_opcode(table[idx1])) {
8845 printf("*** ERROR: idx %02x already assigned to a direct "
8846 "opcode\n", idx1);
8847 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8848 printf(" Registered handler '%s' - new handler '%s'\n",
8849 ind_table(table[idx1])[idx2]->oname, handler->oname);
8850 #endif
8851 return -1;
8852 }
8853 }
8854 if (handler != NULL &&
8855 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8856 printf("*** ERROR: opcode %02x already assigned in "
8857 "opcode table %02x\n", idx2, idx1);
8858 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8859 printf(" Registered handler '%s' - new handler '%s'\n",
8860 ind_table(table[idx1])[idx2]->oname, handler->oname);
8861 #endif
8862 return -1;
8863 }
8864
8865 return 0;
8866 }
8867
8868 static int register_ind_insn (opc_handler_t **ppc_opcodes,
8869 unsigned char idx1, unsigned char idx2,
8870 opc_handler_t *handler)
8871 {
8872 int ret;
8873
8874 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8875
8876 return ret;
8877 }
8878
8879 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8880 unsigned char idx1, unsigned char idx2,
8881 unsigned char idx3, opc_handler_t *handler)
8882 {
8883 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8884 printf("*** ERROR: unable to join indirect table idx "
8885 "[%02x-%02x]\n", idx1, idx2);
8886 return -1;
8887 }
8888 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8889 handler) < 0) {
8890 printf("*** ERROR: unable to insert opcode "
8891 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8892 return -1;
8893 }
8894
8895 return 0;
8896 }
8897
8898 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8899 {
8900 if (insn->opc2 != 0xFF) {
8901 if (insn->opc3 != 0xFF) {
8902 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8903 insn->opc3, &insn->handler) < 0)
8904 return -1;
8905 } else {
8906 if (register_ind_insn(ppc_opcodes, insn->opc1,
8907 insn->opc2, &insn->handler) < 0)
8908 return -1;
8909 }
8910 } else {
8911 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8912 return -1;
8913 }
8914
8915 return 0;
8916 }
8917
8918 static int test_opcode_table (opc_handler_t **table, int len)
8919 {
8920 int i, count, tmp;
8921
8922 for (i = 0, count = 0; i < len; i++) {
8923 /* Consistency fixup */
8924 if (table[i] == NULL)
8925 table[i] = &invalid_handler;
8926 if (table[i] != &invalid_handler) {
8927 if (is_indirect_opcode(table[i])) {
8928 tmp = test_opcode_table(ind_table(table[i]), 0x20);
8929 if (tmp == 0) {
8930 free(table[i]);
8931 table[i] = &invalid_handler;
8932 } else {
8933 count++;
8934 }
8935 } else {
8936 count++;
8937 }
8938 }
8939 }
8940
8941 return count;
8942 }
8943
8944 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8945 {
8946 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
8947 printf("*** WARNING: no opcode defined !\n");
8948 }
8949
8950 /*****************************************************************************/
8951 static int create_ppc_opcodes (CPUPPCState *env, const ppc_def_t *def)
8952 {
8953 opcode_t *opc, *start, *end;
8954
8955 fill_new_table(env->opcodes, 0x40);
8956 if (&opc_start < &opc_end) {
8957 start = &opc_start;
8958 end = &opc_end;
8959 } else {
8960 start = &opc_end;
8961 end = &opc_start;
8962 }
8963 for (opc = start + 1; opc != end; opc++) {
8964 if ((opc->handler.type & def->insns_flags) != 0) {
8965 if (register_insn(env->opcodes, opc) < 0) {
8966 printf("*** ERROR initializing PowerPC instruction "
8967 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
8968 opc->opc3);
8969 return -1;
8970 }
8971 }
8972 }
8973 fix_opcode_tables(env->opcodes);
8974 fflush(stdout);
8975 fflush(stderr);
8976
8977 return 0;
8978 }
8979
8980 #if defined(PPC_DUMP_CPU)
8981 static void dump_ppc_insns (CPUPPCState *env)
8982 {
8983 opc_handler_t **table, *handler;
8984 const unsigned char *p, *q;
8985 uint8_t opc1, opc2, opc3;
8986
8987 printf("Instructions set:\n");
8988 /* opc1 is 6 bits long */
8989 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
8990 table = env->opcodes;
8991 handler = table[opc1];
8992 if (is_indirect_opcode(handler)) {
8993 /* opc2 is 5 bits long */
8994 for (opc2 = 0; opc2 < 0x20; opc2++) {
8995 table = env->opcodes;
8996 handler = env->opcodes[opc1];
8997 table = ind_table(handler);
8998 handler = table[opc2];
8999 if (is_indirect_opcode(handler)) {
9000 table = ind_table(handler);
9001 /* opc3 is 5 bits long */
9002 for (opc3 = 0; opc3 < 0x20; opc3++) {
9003 handler = table[opc3];
9004 if (handler->handler != &gen_invalid) {
9005 /* Special hack to properly dump SPE insns */
9006 p = strchr(handler->oname, '_');
9007 if (p == NULL) {
9008 printf("INSN: %02x %02x %02x (%02d %04d) : "
9009 "%s\n",
9010 opc1, opc2, opc3, opc1,
9011 (opc3 << 5) | opc2,
9012 handler->oname);
9013 } else {
9014 q = "speundef";
9015 if ((p - handler->oname) != strlen(q) ||
9016 memcmp(handler->oname, q, strlen(q)) != 0) {
9017 /* First instruction */
9018 printf("INSN: %02x %02x %02x (%02d %04d) : "
9019 "%.*s\n",
9020 opc1, opc2 << 1, opc3, opc1,
9021 (opc3 << 6) | (opc2 << 1),
9022 (int)(p - handler->oname),
9023 handler->oname);
9024 }
9025 if (strcmp(p + 1, q) != 0) {
9026 /* Second instruction */
9027 printf("INSN: %02x %02x %02x (%02d %04d) : "
9028 "%s\n",
9029 opc1, (opc2 << 1) | 1, opc3, opc1,
9030 (opc3 << 6) | (opc2 << 1) | 1,
9031 p + 1);
9032 }
9033 }
9034 }
9035 }
9036 } else {
9037 if (handler->handler != &gen_invalid) {
9038 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
9039 opc1, opc2, opc1, opc2, handler->oname);
9040 }
9041 }
9042 }
9043 } else {
9044 if (handler->handler != &gen_invalid) {
9045 printf("INSN: %02x -- -- (%02d ----) : %s\n",
9046 opc1, opc1, handler->oname);
9047 }
9048 }
9049 }
9050 }
9051 #endif
9052
9053 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
9054 {
9055 env->msr_mask = def->msr_mask;
9056 env->mmu_model = def->mmu_model;
9057 env->excp_model = def->excp_model;
9058 env->bus_model = def->bus_model;
9059 env->flags = def->flags;
9060 env->bfd_mach = def->bfd_mach;
9061 env->check_pow = def->check_pow;
9062 if (create_ppc_opcodes(env, def) < 0)
9063 return -1;
9064 init_ppc_proc(env, def);
9065 #if defined(PPC_DUMP_CPU)
9066 {
9067 const unsigned char *mmu_model, *excp_model, *bus_model;
9068 switch (env->mmu_model) {
9069 case POWERPC_MMU_32B:
9070 mmu_model = "PowerPC 32";
9071 break;
9072 case POWERPC_MMU_SOFT_6xx:
9073 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
9074 break;
9075 case POWERPC_MMU_SOFT_74xx:
9076 mmu_model = "PowerPC 74xx with software driven TLBs";
9077 break;
9078 case POWERPC_MMU_SOFT_4xx:
9079 mmu_model = "PowerPC 4xx with software driven TLBs";
9080 break;
9081 case POWERPC_MMU_SOFT_4xx_Z:
9082 mmu_model = "PowerPC 4xx with software driven TLBs "
9083 "and zones protections";
9084 break;
9085 case POWERPC_MMU_REAL:
9086 mmu_model = "PowerPC real mode only";
9087 break;
9088 case POWERPC_MMU_MPC8xx:
9089 mmu_model = "PowerPC MPC8xx";
9090 break;
9091 case POWERPC_MMU_BOOKE:
9092 mmu_model = "PowerPC BookE";
9093 break;
9094 case POWERPC_MMU_BOOKE_FSL:
9095 mmu_model = "PowerPC BookE FSL";
9096 break;
9097 case POWERPC_MMU_601:
9098 mmu_model = "PowerPC 601";
9099 break;
9100 #if defined (TARGET_PPC64)
9101 case POWERPC_MMU_64B:
9102 mmu_model = "PowerPC 64";
9103 break;
9104 case POWERPC_MMU_620:
9105 mmu_model = "PowerPC 620";
9106 break;
9107 #endif
9108 default:
9109 mmu_model = "Unknown or invalid";
9110 break;
9111 }
9112 switch (env->excp_model) {
9113 case POWERPC_EXCP_STD:
9114 excp_model = "PowerPC";
9115 break;
9116 case POWERPC_EXCP_40x:
9117 excp_model = "PowerPC 40x";
9118 break;
9119 case POWERPC_EXCP_601:
9120 excp_model = "PowerPC 601";
9121 break;
9122 case POWERPC_EXCP_602:
9123 excp_model = "PowerPC 602";
9124 break;
9125 case POWERPC_EXCP_603:
9126 excp_model = "PowerPC 603";
9127 break;
9128 case POWERPC_EXCP_603E:
9129 excp_model = "PowerPC 603e";
9130 break;
9131 case POWERPC_EXCP_604:
9132 excp_model = "PowerPC 604";
9133 break;
9134 case POWERPC_EXCP_7x0:
9135 excp_model = "PowerPC 740/750";
9136 break;
9137 case POWERPC_EXCP_7x5:
9138 excp_model = "PowerPC 745/755";
9139 break;
9140 case POWERPC_EXCP_74xx:
9141 excp_model = "PowerPC 74xx";
9142 break;
9143 case POWERPC_EXCP_BOOKE:
9144 excp_model = "PowerPC BookE";
9145 break;
9146 #if defined (TARGET_PPC64)
9147 case POWERPC_EXCP_970:
9148 excp_model = "PowerPC 970";
9149 break;
9150 #endif
9151 default:
9152 excp_model = "Unknown or invalid";
9153 break;
9154 }
9155 switch (env->bus_model) {
9156 case PPC_FLAGS_INPUT_6xx:
9157 bus_model = "PowerPC 6xx";
9158 break;
9159 case PPC_FLAGS_INPUT_BookE:
9160 bus_model = "PowerPC BookE";
9161 break;
9162 case PPC_FLAGS_INPUT_405:
9163 bus_model = "PowerPC 405";
9164 break;
9165 case PPC_FLAGS_INPUT_401:
9166 bus_model = "PowerPC 401/403";
9167 break;
9168 case PPC_FLAGS_INPUT_RCPU:
9169 bus_model = "RCPU / MPC8xx";
9170 break;
9171 #if defined (TARGET_PPC64)
9172 case PPC_FLAGS_INPUT_970:
9173 bus_model = "PowerPC 970";
9174 break;
9175 #endif
9176 default:
9177 bus_model = "Unknown or invalid";
9178 break;
9179 }
9180 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
9181 " MMU model : %s\n",
9182 def->name, def->pvr, def->msr_mask, mmu_model);
9183 #if !defined(CONFIG_USER_ONLY)
9184 if (env->tlb != NULL) {
9185 printf(" %d %s TLB in %d ways\n",
9186 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
9187 env->nb_ways);
9188 }
9189 #endif
9190 printf(" Exceptions model : %s\n"
9191 " Bus model : %s\n",
9192 excp_model, bus_model);
9193 printf(" MSR features :\n");
9194 if (env->flags & POWERPC_FLAG_SPE)
9195 printf(" signal processing engine enable"
9196 "\n");
9197 else if (env->flags & POWERPC_FLAG_VRE)
9198 printf(" vector processor enable\n");
9199 if (env->flags & POWERPC_FLAG_TGPR)
9200 printf(" temporary GPRs\n");
9201 else if (env->flags & POWERPC_FLAG_CE)
9202 printf(" critical input enable\n");
9203 if (env->flags & POWERPC_FLAG_SE)
9204 printf(" single-step trace mode\n");
9205 else if (env->flags & POWERPC_FLAG_DWE)
9206 printf(" debug wait enable\n");
9207 else if (env->flags & POWERPC_FLAG_UBLE)
9208 printf(" user BTB lock enable\n");
9209 if (env->flags & POWERPC_FLAG_BE)
9210 printf(" branch-step trace mode\n");
9211 else if (env->flags & POWERPC_FLAG_DE)
9212 printf(" debug interrupt enable\n");
9213 if (env->flags & POWERPC_FLAG_PX)
9214 printf(" inclusive protection\n");
9215 else if (env->flags & POWERPC_FLAG_PMM)
9216 printf(" performance monitor mark\n");
9217 if (env->flags == POWERPC_FLAG_NONE)
9218 printf(" none\n");
9219 printf(" Time-base/decrementer clock source: %s\n",
9220 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
9221 }
9222 dump_ppc_insns(env);
9223 dump_ppc_sprs(env);
9224 fflush(stdout);
9225 #endif
9226
9227 return 0;
9228 }
9229
9230 static const ppc_def_t *ppc_find_by_pvr (uint32_t pvr)
9231 {
9232 const ppc_def_t *ret;
9233 uint32_t pvr_rev;
9234 int i, best, match, best_match, max;
9235
9236 ret = NULL;
9237 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
9238 best = -1;
9239 pvr_rev = pvr & 0xFFFF;
9240 /* We want all specified bits to match */
9241 best_match = 32 - ctz32(pvr_rev);
9242 for (i = 0; i < max; i++) {
9243 /* We check that the 16 higher bits are the same to ensure the CPU
9244 * model will be the choosen one.
9245 */
9246 if (((pvr ^ ppc_defs[i].pvr) >> 16) == 0) {
9247 /* We want as much as possible of the low-level 16 bits
9248 * to be the same but we allow inexact matches.
9249 */
9250 match = clz32(pvr_rev ^ (ppc_defs[i].pvr & 0xFFFF));
9251 /* We check '>=' instead of '>' because the PPC_defs table
9252 * is ordered by increasing revision.
9253 * Then, we will match the higher revision compatible
9254 * with the requested PVR
9255 */
9256 if (match >= best_match) {
9257 best = i;
9258 best_match = match;
9259 }
9260 }
9261 }
9262 if (best != -1)
9263 ret = &ppc_defs[best];
9264
9265 return ret;
9266 }
9267
9268 #include <ctype.h>
9269
9270 const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name)
9271 {
9272 const ppc_def_t *ret;
9273 const unsigned char *p;
9274 int i, max, len;
9275
9276 /* Check if the given name is a PVR */
9277 len = strlen(name);
9278 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9279 p = name + 2;
9280 goto check_pvr;
9281 } else if (len == 8) {
9282 p = name;
9283 check_pvr:
9284 for (i = 0; i < 8; i++) {
9285 if (!isxdigit(*p++))
9286 break;
9287 }
9288 if (i == 8)
9289 return ppc_find_by_pvr(strtoul(name, NULL, 16));
9290 }
9291 ret = NULL;
9292 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
9293 for (i = 0; i < max; i++) {
9294 if (strcasecmp(name, ppc_defs[i].name) == 0) {
9295 ret = &ppc_defs[i];
9296 break;
9297 }
9298 }
9299
9300 return ret;
9301 }
9302
9303 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
9304 {
9305 int i, max;
9306
9307 max = sizeof(ppc_defs) / sizeof(ppc_def_t);
9308 for (i = 0; i < max; i++) {
9309 (*cpu_fprintf)(f, "PowerPC %-16s PVR %08x\n",
9310 ppc_defs[i].name, ppc_defs[i].pvr);
9311 }
9312 }
Samsung s3c2440 and arm920t support for the mini2440 dev board