2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag
;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env
->jmp_env
, 1);
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState
*env1
, void *puc
)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext
*uc
= puc
;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
73 longjmp(env
->jmp_env
, 1);
77 static TranslationBlock
*tb_find_slow(target_ulong pc
,
81 TranslationBlock
*tb
, **ptb1
;
84 target_ulong phys_pc
, phys_page1
, phys_page2
, virt_page2
;
89 tb_invalidated_flag
= 0;
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93 /* find translated block using physical mappings */
94 phys_pc
= get_phys_addr_code(env
, pc
);
95 phys_page1
= phys_pc
& TARGET_PAGE_MASK
;
97 h
= tb_phys_hash_func(phys_pc
);
98 ptb1
= &tb_phys_hash
[h
];
104 tb
->page_addr
[0] == phys_page1
&&
105 tb
->cs_base
== cs_base
&&
106 tb
->flags
== flags
) {
107 /* check next page if needed */
108 if (tb
->page_addr
[1] != -1) {
109 virt_page2
= (pc
& TARGET_PAGE_MASK
) +
111 phys_page2
= get_phys_addr_code(env
, virt_page2
);
112 if (tb
->page_addr
[1] == phys_page2
)
118 ptb1
= &tb
->phys_hash_next
;
121 /* if no translated code available, then translate it now */
124 /* flush must be done */
126 /* cannot fail at this point */
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag
= 1;
131 tc_ptr
= code_gen_ptr
;
133 tb
->cs_base
= cs_base
;
135 cpu_gen_code(env
, tb
, CODE_GEN_MAX_SIZE
, &code_gen_size
);
136 code_gen_ptr
= (void *)(((unsigned long)code_gen_ptr
+ code_gen_size
+ CODE_GEN_ALIGN
- 1) & ~(CODE_GEN_ALIGN
- 1));
138 /* check next page if needed */
139 virt_page2
= (pc
+ tb
->size
- 1) & TARGET_PAGE_MASK
;
141 if ((pc
& TARGET_PAGE_MASK
) != virt_page2
) {
142 phys_page2
= get_phys_addr_code(env
, virt_page2
);
144 tb_link_phys(tb
, phys_pc
, phys_page2
);
147 /* we add the TB in the virtual pc hash table */
148 env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)] = tb
;
149 spin_unlock(&tb_lock
);
153 static inline TranslationBlock
*tb_find_fast(void)
155 TranslationBlock
*tb
;
156 target_ulong cs_base
, pc
;
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
162 #if defined(TARGET_I386)
164 flags
|= (env
->eflags
& (IOPL_MASK
| TF_MASK
| VM_MASK
));
165 cs_base
= env
->segs
[R_CS
].base
;
166 pc
= cs_base
+ env
->eip
;
167 #elif defined(TARGET_ARM)
168 flags
= env
->thumb
| (env
->vfp
.vec_len
<< 1)
169 | (env
->vfp
.vec_stride
<< 4);
170 if ((env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
)
172 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30))
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags
= (((env
->pstate
& PS_PEF
) >> 1) | ((env
->fprs
& FPRS_FEF
) << 2))
180 | (env
->pstate
& PS_PRIV
) | ((env
->lsu
& (DMMU_E
| IMMU_E
)) >> 2);
182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags
= (env
->psref
<< 3) | ((env
->mmuregs
[0] & (MMU_E
| MMU_NF
)) << 1)
188 #elif defined(TARGET_PPC)
189 flags
= (msr_pr
<< MSR_PR
) | (msr_fp
<< MSR_FP
) |
190 (msr_se
<< MSR_SE
) | (msr_le
<< MSR_LE
);
193 #elif defined(TARGET_MIPS)
194 flags
= env
->hflags
& (MIPS_HFLAG_TMASK
| MIPS_HFLAG_BMASK
);
197 #elif defined(TARGET_M68K)
198 flags
= env
->fpcr
& M68K_FPCR_PREC
;
201 #elif defined(TARGET_SH4)
202 flags
= env
->sr
& (SR_MD
| SR_RB
);
203 cs_base
= 0; /* XXXXX */
206 #error unsupported CPU
208 tb
= env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)];
209 if (__builtin_expect(!tb
|| tb
->pc
!= pc
|| tb
->cs_base
!= cs_base
||
210 tb
->flags
!= flags
, 0)) {
211 tb
= tb_find_slow(pc
, cs_base
, flags
);
212 /* Note: we do it here to avoid a gcc bug on Mac OS X when
213 doing it in tb_find_slow */
214 if (tb_invalidated_flag
) {
215 /* as some TB could have been invalidated because
216 of memory exceptions while generating the code, we
217 must recompute the hash index here */
225 /* main execution loop */
227 int cpu_exec(CPUState
*env1
)
229 int saved_T0
, saved_T1
;
234 #if defined(TARGET_I386)
259 #elif defined(TARGET_SPARC)
260 #if defined(reg_REGWPTR)
261 uint32_t *saved_regwptr
;
264 #if defined(__sparc__) && !defined(HOST_SOLARIS)
265 int saved_i7
, tmp_T0
;
267 int ret
, interrupt_request
;
268 void (*gen_func
)(void);
269 TranslationBlock
*tb
;
272 #if defined(TARGET_I386)
273 /* handle exit of HALTED state */
274 if (env1
->hflags
& HF_HALTED_MASK
) {
275 /* disable halt condition */
276 if ((env1
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
277 (env1
->eflags
& IF_MASK
)) {
278 env1
->hflags
&= ~HF_HALTED_MASK
;
283 #elif defined(TARGET_PPC)
285 if (env1
->msr
[MSR_EE
] &&
286 (env1
->interrupt_request
&
287 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
))) {
293 #elif defined(TARGET_SPARC)
295 if ((env1
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
296 (env1
->psret
!= 0)) {
302 #elif defined(TARGET_ARM)
304 /* An interrupt wakes the CPU even if the I and F CPSR bits are
306 if (env1
->interrupt_request
307 & (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
)) {
313 #elif defined(TARGET_MIPS)
315 if (env1
->interrupt_request
&
316 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
)) {
324 cpu_single_env
= env1
;
326 /* first we save global registers */
334 #if defined(__sparc__) && !defined(HOST_SOLARIS)
335 /* we also save i7 because longjmp may not restore it */
336 asm volatile ("mov %%i7, %0" : "=r" (saved_i7
));
339 #if defined(TARGET_I386)
366 /* put eflags in CPU temporary format */
367 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
368 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
369 CC_OP
= CC_OP_EFLAGS
;
370 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
371 #elif defined(TARGET_ARM)
372 #elif defined(TARGET_SPARC)
373 #if defined(reg_REGWPTR)
374 saved_regwptr
= REGWPTR
;
376 #elif defined(TARGET_PPC)
377 #elif defined(TARGET_M68K)
378 env
->cc_op
= CC_OP_FLAGS
;
379 env
->cc_dest
= env
->sr
& 0xf;
380 env
->cc_x
= (env
->sr
>> 4) & 1;
381 #elif defined(TARGET_MIPS)
382 #elif defined(TARGET_SH4)
385 #error unsupported target CPU
387 env
->exception_index
= -1;
389 /* prepare setjmp context for exception handling */
391 if (setjmp(env
->jmp_env
) == 0) {
392 env
->current_tb
= NULL
;
393 /* if an exception is pending, we execute it here */
394 if (env
->exception_index
>= 0) {
395 if (env
->exception_index
>= EXCP_INTERRUPT
) {
396 /* exit request from the cpu execution loop */
397 ret
= env
->exception_index
;
399 } else if (env
->user_mode_only
) {
400 /* if user mode only, we simulate a fake exception
401 which will be handled outside the cpu execution
403 #if defined(TARGET_I386)
404 do_interrupt_user(env
->exception_index
,
405 env
->exception_is_int
,
407 env
->exception_next_eip
);
409 ret
= env
->exception_index
;
412 #if defined(TARGET_I386)
413 /* simulate a real cpu exception. On i386, it can
414 trigger new exceptions, but we do not handle
415 double or triple faults yet. */
416 do_interrupt(env
->exception_index
,
417 env
->exception_is_int
,
419 env
->exception_next_eip
, 0);
420 #elif defined(TARGET_PPC)
422 #elif defined(TARGET_MIPS)
424 #elif defined(TARGET_SPARC)
425 do_interrupt(env
->exception_index
);
426 #elif defined(TARGET_ARM)
428 #elif defined(TARGET_SH4)
432 env
->exception_index
= -1;
435 if (kqemu_is_ok(env
) && env
->interrupt_request
== 0) {
437 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
438 ret
= kqemu_cpu_exec(env
);
439 /* put eflags in CPU temporary format */
440 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
441 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
442 CC_OP
= CC_OP_EFLAGS
;
443 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
446 longjmp(env
->jmp_env
, 1);
447 } else if (ret
== 2) {
448 /* softmmu execution needed */
450 if (env
->interrupt_request
!= 0) {
451 /* hardware interrupt will be executed just after */
453 /* otherwise, we restart */
454 longjmp(env
->jmp_env
, 1);
460 T0
= 0; /* force lookup of first TB */
462 #if defined(__sparc__) && !defined(HOST_SOLARIS)
463 /* g1 can be modified by some libc? functions */
466 interrupt_request
= env
->interrupt_request
;
467 if (__builtin_expect(interrupt_request
, 0)) {
468 #if defined(TARGET_I386)
469 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
470 !(env
->hflags
& HF_SMM_MASK
)) {
471 env
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
473 #if defined(__sparc__) && !defined(HOST_SOLARIS)
478 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
479 (env
->eflags
& IF_MASK
) &&
480 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
482 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
483 intno
= cpu_get_pic_interrupt(env
);
484 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
485 fprintf(logfile
, "Servicing hardware INT=0x%02x\n", intno
);
487 do_interrupt(intno
, 0, 0, 0, 1);
488 /* ensure that no TB jump will be modified as
489 the program flow was changed */
490 #if defined(__sparc__) && !defined(HOST_SOLARIS)
496 #elif defined(TARGET_PPC)
498 if ((interrupt_request
& CPU_INTERRUPT_RESET
)) {
503 if ((interrupt_request
& CPU_INTERRUPT_HARD
)) {
505 env
->exception_index
= EXCP_EXTERNAL
;
508 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
509 #if defined(__sparc__) && !defined(HOST_SOLARIS)
514 } else if ((interrupt_request
& CPU_INTERRUPT_TIMER
)) {
516 env
->exception_index
= EXCP_DECR
;
519 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
520 #if defined(__sparc__) && !defined(HOST_SOLARIS)
527 #elif defined(TARGET_MIPS)
528 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
529 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
530 (env
->CP0_Status
& env
->CP0_Cause
& 0x0000FF00) &&
531 !(env
->hflags
& MIPS_HFLAG_EXL
) &&
532 !(env
->hflags
& MIPS_HFLAG_ERL
) &&
533 !(env
->hflags
& MIPS_HFLAG_DM
)) {
535 env
->exception_index
= EXCP_EXT_INTERRUPT
;
538 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
539 #if defined(__sparc__) && !defined(HOST_SOLARIS)
545 #elif defined(TARGET_SPARC)
546 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
548 int pil
= env
->interrupt_index
& 15;
549 int type
= env
->interrupt_index
& 0xf0;
551 if (((type
== TT_EXTINT
) &&
552 (pil
== 15 || pil
> env
->psrpil
)) ||
554 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
555 do_interrupt(env
->interrupt_index
);
556 env
->interrupt_index
= 0;
557 #if defined(__sparc__) && !defined(HOST_SOLARIS)
563 } else if (interrupt_request
& CPU_INTERRUPT_TIMER
) {
564 //do_interrupt(0, 0, 0, 0, 0);
565 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
566 } else if (interrupt_request
& CPU_INTERRUPT_HALT
) {
567 env
->interrupt_request
&= ~CPU_INTERRUPT_HALT
;
569 env
->exception_index
= EXCP_HLT
;
572 #elif defined(TARGET_ARM)
573 if (interrupt_request
& CPU_INTERRUPT_FIQ
574 && !(env
->uncached_cpsr
& CPSR_F
)) {
575 env
->exception_index
= EXCP_FIQ
;
578 if (interrupt_request
& CPU_INTERRUPT_HARD
579 && !(env
->uncached_cpsr
& CPSR_I
)) {
580 env
->exception_index
= EXCP_IRQ
;
583 #elif defined(TARGET_SH4)
586 /* Don't use the cached interupt_request value,
587 do_interrupt may have updated the EXITTB flag. */
588 if (env
->interrupt_request
& CPU_INTERRUPT_EXITTB
) {
589 env
->interrupt_request
&= ~CPU_INTERRUPT_EXITTB
;
590 /* ensure that no TB jump will be modified as
591 the program flow was changed */
592 #if defined(__sparc__) && !defined(HOST_SOLARIS)
598 if (interrupt_request
& CPU_INTERRUPT_EXIT
) {
599 env
->interrupt_request
&= ~CPU_INTERRUPT_EXIT
;
600 env
->exception_index
= EXCP_INTERRUPT
;
605 if ((loglevel
& CPU_LOG_TB_CPU
)) {
606 #if defined(TARGET_I386)
607 /* restore flags in standard format */
609 env
->regs
[R_EAX
] = EAX
;
612 env
->regs
[R_EBX
] = EBX
;
615 env
->regs
[R_ECX
] = ECX
;
618 env
->regs
[R_EDX
] = EDX
;
621 env
->regs
[R_ESI
] = ESI
;
624 env
->regs
[R_EDI
] = EDI
;
627 env
->regs
[R_EBP
] = EBP
;
630 env
->regs
[R_ESP
] = ESP
;
632 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
633 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
634 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
635 #elif defined(TARGET_ARM)
636 cpu_dump_state(env
, logfile
, fprintf
, 0);
637 #elif defined(TARGET_SPARC)
638 REGWPTR
= env
->regbase
+ (env
->cwp
* 16);
639 env
->regwptr
= REGWPTR
;
640 cpu_dump_state(env
, logfile
, fprintf
, 0);
641 #elif defined(TARGET_PPC)
642 cpu_dump_state(env
, logfile
, fprintf
, 0);
643 #elif defined(TARGET_M68K)
644 cpu_m68k_flush_flags(env
, env
->cc_op
);
645 env
->cc_op
= CC_OP_FLAGS
;
646 env
->sr
= (env
->sr
& 0xffe0)
647 | env
->cc_dest
| (env
->cc_x
<< 4);
648 cpu_dump_state(env
, logfile
, fprintf
, 0);
649 #elif defined(TARGET_MIPS)
650 cpu_dump_state(env
, logfile
, fprintf
, 0);
651 #elif defined(TARGET_SH4)
652 cpu_dump_state(env
, logfile
, fprintf
, 0);
654 #error unsupported target CPU
660 if ((loglevel
& CPU_LOG_EXEC
)) {
661 fprintf(logfile
, "Trace 0x%08lx [" TARGET_FMT_lx
"] %s\n",
662 (long)tb
->tc_ptr
, tb
->pc
,
663 lookup_symbol(tb
->pc
));
666 #if defined(__sparc__) && !defined(HOST_SOLARIS)
669 /* see if we can patch the calling TB. When the TB
670 spans two pages, we cannot safely do a direct
675 (env
->kqemu_enabled
!= 2) &&
677 tb
->page_addr
[1] == -1
678 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
679 && (tb
->cflags
& CF_CODE_COPY
) ==
680 (((TranslationBlock
*)(T0
& ~3))->cflags
& CF_CODE_COPY
)
684 tb_add_jump((TranslationBlock
*)(long)(T0
& ~3), T0
& 3, tb
);
685 #if defined(USE_CODE_COPY)
686 /* propagates the FP use info */
687 ((TranslationBlock
*)(T0
& ~3))->cflags
|=
688 (tb
->cflags
& CF_FP_USED
);
690 spin_unlock(&tb_lock
);
694 env
->current_tb
= tb
;
695 /* execute the generated code */
696 gen_func
= (void *)tc_ptr
;
697 #if defined(__sparc__)
698 __asm__
__volatile__("call %0\n\t"
702 : "i0", "i1", "i2", "i3", "i4", "i5",
703 "l0", "l1", "l2", "l3", "l4", "l5",
705 #elif defined(__arm__)
706 asm volatile ("mov pc, %0\n\t"
707 ".global exec_loop\n\t"
711 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
712 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
714 if (!(tb
->cflags
& CF_CODE_COPY
)) {
715 if ((tb
->cflags
& CF_FP_USED
) && env
->native_fp_regs
) {
716 save_native_fp_state(env
);
720 if ((tb
->cflags
& CF_FP_USED
) && !env
->native_fp_regs
) {
721 restore_native_fp_state(env
);
723 /* we work with native eflags */
724 CC_SRC
= cc_table
[CC_OP
].compute_all();
725 CC_OP
= CC_OP_EFLAGS
;
726 asm(".globl exec_loop\n"
731 " fs movl %11, %%eax\n"
732 " andl $0x400, %%eax\n"
733 " fs orl %8, %%eax\n"
736 " fs movl %%esp, %12\n"
737 " fs movl %0, %%eax\n"
738 " fs movl %1, %%ecx\n"
739 " fs movl %2, %%edx\n"
740 " fs movl %3, %%ebx\n"
741 " fs movl %4, %%esp\n"
742 " fs movl %5, %%ebp\n"
743 " fs movl %6, %%esi\n"
744 " fs movl %7, %%edi\n"
747 " fs movl %%esp, %4\n"
748 " fs movl %12, %%esp\n"
749 " fs movl %%eax, %0\n"
750 " fs movl %%ecx, %1\n"
751 " fs movl %%edx, %2\n"
752 " fs movl %%ebx, %3\n"
753 " fs movl %%ebp, %5\n"
754 " fs movl %%esi, %6\n"
755 " fs movl %%edi, %7\n"
758 " movl %%eax, %%ecx\n"
759 " andl $0x400, %%ecx\n"
761 " andl $0x8d5, %%eax\n"
762 " fs movl %%eax, %8\n"
764 " subl %%ecx, %%eax\n"
765 " fs movl %%eax, %11\n"
766 " fs movl %9, %%ebx\n" /* get T0 value */
769 : "m" (*(uint8_t *)offsetof(CPUState
, regs
[0])),
770 "m" (*(uint8_t *)offsetof(CPUState
, regs
[1])),
771 "m" (*(uint8_t *)offsetof(CPUState
, regs
[2])),
772 "m" (*(uint8_t *)offsetof(CPUState
, regs
[3])),
773 "m" (*(uint8_t *)offsetof(CPUState
, regs
[4])),
774 "m" (*(uint8_t *)offsetof(CPUState
, regs
[5])),
775 "m" (*(uint8_t *)offsetof(CPUState
, regs
[6])),
776 "m" (*(uint8_t *)offsetof(CPUState
, regs
[7])),
777 "m" (*(uint8_t *)offsetof(CPUState
, cc_src
)),
778 "m" (*(uint8_t *)offsetof(CPUState
, tmp0
)),
780 "m" (*(uint8_t *)offsetof(CPUState
, df
)),
781 "m" (*(uint8_t *)offsetof(CPUState
, saved_esp
))
786 #elif defined(__ia64)
793 fp
.gp
= code_gen_buffer
+ 2 * (1 << 20);
794 (*(void (*)(void)) &fp
)();
798 env
->current_tb
= NULL
;
799 /* reset soft MMU for next block (it can currently
800 only be set by a memory fault) */
801 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
802 if (env
->hflags
& HF_SOFTMMU_MASK
) {
803 env
->hflags
&= ~HF_SOFTMMU_MASK
;
804 /* do not allow linking to another block */
808 #if defined(USE_KQEMU)
809 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
810 if (kqemu_is_ok(env
) &&
811 (cpu_get_time_fast() - env
->last_io_time
) >= MIN_CYCLE_BEFORE_SWITCH
) {
822 #if defined(TARGET_I386)
823 #if defined(USE_CODE_COPY)
824 if (env
->native_fp_regs
) {
825 save_native_fp_state(env
);
828 /* restore flags in standard format */
829 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
831 /* restore global registers */
856 #elif defined(TARGET_ARM)
857 /* XXX: Save/restore host fpu exception state?. */
858 #elif defined(TARGET_SPARC)
859 #if defined(reg_REGWPTR)
860 REGWPTR
= saved_regwptr
;
862 #elif defined(TARGET_PPC)
863 #elif defined(TARGET_M68K)
864 cpu_m68k_flush_flags(env
, env
->cc_op
);
865 env
->cc_op
= CC_OP_FLAGS
;
866 env
->sr
= (env
->sr
& 0xffe0)
867 | env
->cc_dest
| (env
->cc_x
<< 4);
868 #elif defined(TARGET_MIPS)
869 #elif defined(TARGET_SH4)
872 #error unsupported target CPU
874 #if defined(__sparc__) && !defined(HOST_SOLARIS)
875 asm volatile ("mov %0, %%i7" : : "r" (saved_i7
));
883 /* fail safe : never use cpu_single_env outside cpu_exec() */
884 cpu_single_env
= NULL
;
888 /* must only be called from the generated code as an exception can be
890 void tb_invalidate_page_range(target_ulong start
, target_ulong end
)
892 /* XXX: cannot enable it yet because it yields to MMU exception
893 where NIP != read address on PowerPC */
895 target_ulong phys_addr
;
896 phys_addr
= get_phys_addr_code(env
, start
);
897 tb_invalidate_phys_page_range(phys_addr
, phys_addr
+ end
- start
, 0);
901 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
903 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
905 CPUX86State
*saved_env
;
909 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
911 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
912 (selector
<< 4), 0xffff, 0);
914 load_seg(seg_reg
, selector
);
919 void cpu_x86_fsave(CPUX86State
*s
, uint8_t *ptr
, int data32
)
921 CPUX86State
*saved_env
;
926 helper_fsave((target_ulong
)ptr
, data32
);
931 void cpu_x86_frstor(CPUX86State
*s
, uint8_t *ptr
, int data32
)
933 CPUX86State
*saved_env
;
938 helper_frstor((target_ulong
)ptr
, data32
);
943 #endif /* TARGET_I386 */
945 #if !defined(CONFIG_SOFTMMU)
947 #if defined(TARGET_I386)
949 /* 'pc' is the host PC at which the exception was raised. 'address' is
950 the effective address of the memory exception. 'is_write' is 1 if a
951 write caused the exception and otherwise 0'. 'old_set' is the
952 signal set which should be restored */
953 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
954 int is_write
, sigset_t
*old_set
,
957 TranslationBlock
*tb
;
961 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
962 #if defined(DEBUG_SIGNAL)
963 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
964 pc
, address
, is_write
, *(unsigned long *)old_set
);
966 /* XXX: locking issue */
967 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
971 /* see if it is an MMU fault */
972 ret
= cpu_x86_handle_mmu_fault(env
, address
, is_write
,
973 ((env
->hflags
& HF_CPL_MASK
) == 3), 0);
975 return 0; /* not an MMU fault */
977 return 1; /* the MMU fault was handled without causing real CPU fault */
978 /* now we have a real cpu fault */
981 /* the PC is inside the translated code. It means that we have
982 a virtual CPU fault */
983 cpu_restore_state(tb
, env
, pc
, puc
);
987 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
988 env
->eip
, env
->cr
[2], env
->error_code
);
990 /* we restore the process signal mask as the sigreturn should
991 do it (XXX: use sigsetjmp) */
992 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
993 raise_exception_err(env
->exception_index
, env
->error_code
);
995 /* activate soft MMU for this block */
996 env
->hflags
|= HF_SOFTMMU_MASK
;
997 cpu_resume_from_signal(env
, puc
);
999 /* never comes here */
1003 #elif defined(TARGET_ARM)
1004 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1005 int is_write
, sigset_t
*old_set
,
1008 TranslationBlock
*tb
;
1012 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1013 #if defined(DEBUG_SIGNAL)
1014 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1015 pc
, address
, is_write
, *(unsigned long *)old_set
);
1017 /* XXX: locking issue */
1018 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1021 /* see if it is an MMU fault */
1022 ret
= cpu_arm_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1024 return 0; /* not an MMU fault */
1026 return 1; /* the MMU fault was handled without causing real CPU fault */
1027 /* now we have a real cpu fault */
1028 tb
= tb_find_pc(pc
);
1030 /* the PC is inside the translated code. It means that we have
1031 a virtual CPU fault */
1032 cpu_restore_state(tb
, env
, pc
, puc
);
1034 /* we restore the process signal mask as the sigreturn should
1035 do it (XXX: use sigsetjmp) */
1036 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1039 #elif defined(TARGET_SPARC)
1040 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1041 int is_write
, sigset_t
*old_set
,
1044 TranslationBlock
*tb
;
1048 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1049 #if defined(DEBUG_SIGNAL)
1050 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1051 pc
, address
, is_write
, *(unsigned long *)old_set
);
1053 /* XXX: locking issue */
1054 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1057 /* see if it is an MMU fault */
1058 ret
= cpu_sparc_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1060 return 0; /* not an MMU fault */
1062 return 1; /* the MMU fault was handled without causing real CPU fault */
1063 /* now we have a real cpu fault */
1064 tb
= tb_find_pc(pc
);
1066 /* the PC is inside the translated code. It means that we have
1067 a virtual CPU fault */
1068 cpu_restore_state(tb
, env
, pc
, puc
);
1070 /* we restore the process signal mask as the sigreturn should
1071 do it (XXX: use sigsetjmp) */
1072 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1075 #elif defined (TARGET_PPC)
1076 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1077 int is_write
, sigset_t
*old_set
,
1080 TranslationBlock
*tb
;
1084 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1085 #if defined(DEBUG_SIGNAL)
1086 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1087 pc
, address
, is_write
, *(unsigned long *)old_set
);
1089 /* XXX: locking issue */
1090 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1094 /* see if it is an MMU fault */
1095 ret
= cpu_ppc_handle_mmu_fault(env
, address
, is_write
, msr_pr
, 0);
1097 return 0; /* not an MMU fault */
1099 return 1; /* the MMU fault was handled without causing real CPU fault */
1101 /* now we have a real cpu fault */
1102 tb
= tb_find_pc(pc
);
1104 /* the PC is inside the translated code. It means that we have
1105 a virtual CPU fault */
1106 cpu_restore_state(tb
, env
, pc
, puc
);
1110 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1111 env
->nip
, env
->error_code
, tb
);
1113 /* we restore the process signal mask as the sigreturn should
1114 do it (XXX: use sigsetjmp) */
1115 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1116 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1118 /* activate soft MMU for this block */
1119 cpu_resume_from_signal(env
, puc
);
1121 /* never comes here */
1125 #elif defined(TARGET_M68K)
1126 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1127 int is_write
, sigset_t
*old_set
,
1130 TranslationBlock
*tb
;
1134 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1135 #if defined(DEBUG_SIGNAL)
1136 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1137 pc
, address
, is_write
, *(unsigned long *)old_set
);
1139 /* XXX: locking issue */
1140 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
1143 /* see if it is an MMU fault */
1144 ret
= cpu_m68k_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1146 return 0; /* not an MMU fault */
1148 return 1; /* the MMU fault was handled without causing real CPU fault */
1149 /* now we have a real cpu fault */
1150 tb
= tb_find_pc(pc
);
1152 /* the PC is inside the translated code. It means that we have
1153 a virtual CPU fault */
1154 cpu_restore_state(tb
, env
, pc
, puc
);
1156 /* we restore the process signal mask as the sigreturn should
1157 do it (XXX: use sigsetjmp) */
1158 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1160 /* never comes here */
1164 #elif defined (TARGET_MIPS)
1165 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1166 int is_write
, sigset_t
*old_set
,
1169 TranslationBlock
*tb
;
1173 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1174 #if defined(DEBUG_SIGNAL)
1175 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1176 pc
, address
, is_write
, *(unsigned long *)old_set
);
1178 /* XXX: locking issue */
1179 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1183 /* see if it is an MMU fault */
1184 ret
= cpu_mips_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1186 return 0; /* not an MMU fault */
1188 return 1; /* the MMU fault was handled without causing real CPU fault */
1190 /* now we have a real cpu fault */
1191 tb
= tb_find_pc(pc
);
1193 /* the PC is inside the translated code. It means that we have
1194 a virtual CPU fault */
1195 cpu_restore_state(tb
, env
, pc
, puc
);
1199 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1200 env
->nip
, env
->error_code
, tb
);
1202 /* we restore the process signal mask as the sigreturn should
1203 do it (XXX: use sigsetjmp) */
1204 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1205 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1207 /* activate soft MMU for this block */
1208 cpu_resume_from_signal(env
, puc
);
1210 /* never comes here */
1214 #elif defined (TARGET_SH4)
1215 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1216 int is_write
, sigset_t
*old_set
,
1219 TranslationBlock
*tb
;
1223 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1224 #if defined(DEBUG_SIGNAL)
1225 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1226 pc
, address
, is_write
, *(unsigned long *)old_set
);
1228 /* XXX: locking issue */
1229 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1233 /* see if it is an MMU fault */
1234 ret
= cpu_sh4_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1236 return 0; /* not an MMU fault */
1238 return 1; /* the MMU fault was handled without causing real CPU fault */
1240 /* now we have a real cpu fault */
1241 tb
= tb_find_pc(pc
);
1243 /* the PC is inside the translated code. It means that we have
1244 a virtual CPU fault */
1245 cpu_restore_state(tb
, env
, pc
, puc
);
1248 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1249 env
->nip
, env
->error_code
, tb
);
1251 /* we restore the process signal mask as the sigreturn should
1252 do it (XXX: use sigsetjmp) */
1253 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1255 /* never comes here */
1259 #error unsupported target CPU
1262 #if defined(__i386__)
1264 #if defined(USE_CODE_COPY)
1265 static void cpu_send_trap(unsigned long pc
, int trap
,
1266 struct ucontext
*uc
)
1268 TranslationBlock
*tb
;
1271 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1272 /* now we have a real cpu fault */
1273 tb
= tb_find_pc(pc
);
1275 /* the PC is inside the translated code. It means that we have
1276 a virtual CPU fault */
1277 cpu_restore_state(tb
, env
, pc
, uc
);
1279 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
1280 raise_exception_err(trap
, env
->error_code
);
1284 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1287 struct ucontext
*uc
= puc
;
1295 #define REG_TRAPNO TRAPNO
1297 pc
= uc
->uc_mcontext
.gregs
[REG_EIP
];
1298 trapno
= uc
->uc_mcontext
.gregs
[REG_TRAPNO
];
1299 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1300 if (trapno
== 0x00 || trapno
== 0x05) {
1301 /* send division by zero or bound exception */
1302 cpu_send_trap(pc
, trapno
, uc
);
1306 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1308 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
1309 &uc
->uc_sigmask
, puc
);
1312 #elif defined(__x86_64__)
1314 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1317 struct ucontext
*uc
= puc
;
1320 pc
= uc
->uc_mcontext
.gregs
[REG_RIP
];
1321 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1322 uc
->uc_mcontext
.gregs
[REG_TRAPNO
] == 0xe ?
1323 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
1324 &uc
->uc_sigmask
, puc
);
1327 #elif defined(__powerpc__)
1329 /***********************************************************************
1330 * signal context platform-specific definitions
1334 /* All Registers access - only for local access */
1335 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1336 /* Gpr Registers access */
1337 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1338 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1339 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1340 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1341 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1342 # define LR_sig(context) REG_sig(link, context) /* Link register */
1343 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1344 /* Float Registers access */
1345 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1346 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1347 /* Exception Registers access */
1348 # define DAR_sig(context) REG_sig(dar, context)
1349 # define DSISR_sig(context) REG_sig(dsisr, context)
1350 # define TRAP_sig(context) REG_sig(trap, context)
1354 # include <sys/ucontext.h>
1355 typedef struct ucontext SIGCONTEXT
;
1356 /* All Registers access - only for local access */
1357 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1358 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1359 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1360 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1361 /* Gpr Registers access */
1362 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1363 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1364 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1365 # define CTR_sig(context) REG_sig(ctr, context)
1366 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1367 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1368 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1369 /* Float Registers access */
1370 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1371 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1372 /* Exception Registers access */
1373 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1374 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1375 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1376 #endif /* __APPLE__ */
1378 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1381 struct ucontext
*uc
= puc
;
1389 if (DSISR_sig(uc
) & 0x00800000)
1392 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000))
1395 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1396 is_write
, &uc
->uc_sigmask
, puc
);
1399 #elif defined(__alpha__)
1401 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1404 struct ucontext
*uc
= puc
;
1405 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
1406 uint32_t insn
= *pc
;
1409 /* XXX: need kernel patch to get write flag faster */
1410 switch (insn
>> 26) {
1425 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1426 is_write
, &uc
->uc_sigmask
, puc
);
1428 #elif defined(__sparc__)
1430 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1433 uint32_t *regs
= (uint32_t *)(info
+ 1);
1434 void *sigmask
= (regs
+ 20);
1439 /* XXX: is there a standard glibc define ? */
1441 /* XXX: need kernel patch to get write flag faster */
1443 insn
= *(uint32_t *)pc
;
1444 if ((insn
>> 30) == 3) {
1445 switch((insn
>> 19) & 0x3f) {
1457 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1458 is_write
, sigmask
, NULL
);
1461 #elif defined(__arm__)
1463 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1466 struct ucontext
*uc
= puc
;
1470 pc
= uc
->uc_mcontext
.gregs
[R15
];
1471 /* XXX: compute is_write */
1473 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1475 &uc
->uc_sigmask
, puc
);
1478 #elif defined(__mc68000)
1480 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1483 struct ucontext
*uc
= puc
;
1487 pc
= uc
->uc_mcontext
.gregs
[16];
1488 /* XXX: compute is_write */
1490 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1492 &uc
->uc_sigmask
, puc
);
1495 #elif defined(__ia64)
1498 /* This ought to be in <bits/siginfo.h>... */
1499 # define __ISR_VALID 1
1502 int cpu_signal_handler(int host_signum
, struct siginfo
*info
, void *puc
)
1504 struct ucontext
*uc
= puc
;
1508 ip
= uc
->uc_mcontext
.sc_ip
;
1509 switch (host_signum
) {
1515 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
))
1516 /* ISR.W (write-access) is bit 33: */
1517 is_write
= (info
->si_isr
>> 33) & 1;
1523 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
1525 &uc
->uc_sigmask
, puc
);
1528 #elif defined(__s390__)
1530 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1533 struct ucontext
*uc
= puc
;
1537 pc
= uc
->uc_mcontext
.psw
.addr
;
1538 /* XXX: compute is_write */
1540 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1542 &uc
->uc_sigmask
, puc
);
1547 #error host CPU specific signal handler needed
1551 #endif /* !defined(CONFIG_SOFTMMU) */