2 * ARM Versatile Platform/Application Baseboard System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
13 /* Primary interrupt controller. */
15 typedef struct vpb_sic_state
25 static void vpb_sic_update(vpb_sic_state
*s
)
29 flags
= s
->level
& s
->mask
;
30 qemu_set_irq(s
->parent
[s
->irq
], flags
!= 0);
33 static void vpb_sic_update_pic(vpb_sic_state
*s
)
38 for (i
= 21; i
<= 30; i
++) {
40 if (!(s
->pic_enable
& mask
))
42 qemu_set_irq(s
->parent
[i
], (s
->level
& mask
) != 0);
46 static void vpb_sic_set_irq(void *opaque
, int irq
, int level
)
48 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
50 s
->level
|= 1u << irq
;
52 s
->level
&= ~(1u << irq
);
53 if (s
->pic_enable
& (1u << irq
))
54 qemu_set_irq(s
->parent
[irq
], level
);
58 static uint32_t vpb_sic_read(void *opaque
, target_phys_addr_t offset
)
60 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
63 switch (offset
>> 2) {
65 return s
->level
& s
->mask
;
72 case 8: /* PICENABLE */
75 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset
);
80 static void vpb_sic_write(void *opaque
, target_phys_addr_t offset
,
83 vpb_sic_state
*s
= (vpb_sic_state
*)opaque
;
86 switch (offset
>> 2) {
93 case 4: /* SOFTINTSET */
97 case 5: /* SOFTINTCLR */
101 case 8: /* PICENSET */
102 s
->pic_enable
|= (value
& 0x7fe00000);
103 vpb_sic_update_pic(s
);
105 case 9: /* PICENCLR */
106 s
->pic_enable
&= ~value
;
107 vpb_sic_update_pic(s
);
110 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset
);
116 static CPUReadMemoryFunc
*vpb_sic_readfn
[] = {
122 static CPUWriteMemoryFunc
*vpb_sic_writefn
[] = {
128 static qemu_irq
*vpb_sic_init(uint32_t base
, qemu_irq
*parent
, int irq
)
134 s
= (vpb_sic_state
*)qemu_mallocz(sizeof(vpb_sic_state
));
137 qi
= qemu_allocate_irqs(vpb_sic_set_irq
, s
, 32);
141 iomemtype
= cpu_register_io_memory(0, vpb_sic_readfn
,
143 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
144 /* ??? Save/restore. */
150 /* The AB and PB boards both use the same core, just with different
151 peripherans and expansion busses. For now we emulate a subset of the
152 PB peripherals and just change the board ID. */
154 static void versatile_init(int ram_size
, int vga_ram_size
,
155 const char *boot_device
, DisplayState
*ds
,
156 const char **fd_filename
, int snapshot
,
157 const char *kernel_filename
, const char *kernel_cmdline
,
158 const char *initrd_filename
, const char *cpu_model
,
171 cpu_model
= "arm926";
172 env
= cpu_init(cpu_model
);
174 fprintf(stderr
, "Unable to find CPU definition\n");
177 /* ??? RAM shoud repeat to fill physical memory space. */
178 /* SDRAM at address zero. */
179 cpu_register_physical_memory(0, ram_size
, IO_MEM_RAM
);
181 arm_sysctl_init(0x10000000, 0x41007004);
182 pic
= arm_pic_init_cpu(env
);
183 pic
= pl190_init(0x10140000, pic
[0], pic
[1]);
184 sic
= vpb_sic_init(0x10003000, pic
, 31);
185 pl050_init(0x10006000, sic
[3], 0);
186 pl050_init(0x10007000, sic
[4], 1);
188 pci_bus
= pci_vpb_init(sic
, 27, 0);
189 /* The Versatile PCI bridge does not provide access to PCI IO space,
190 so many of the qemu PCI devices are not useable. */
191 for(n
= 0; n
< nb_nics
; n
++) {
194 nd
->model
= done_smc
? "rtl8139" : "smc91c111";
195 if (strcmp(nd
->model
, "smc91c111") == 0) {
196 smc91c111_init(nd
, 0x10010000, sic
[25]);
198 pci_nic_init(pci_bus
, nd
, -1);
202 usb_ohci_init_pci(pci_bus
, 3, -1);
204 scsi_hba
= lsi_scsi_init(pci_bus
, -1);
205 for (n
= 0; n
< MAX_DISKS
; n
++) {
207 lsi_scsi_attach(scsi_hba
, bs_table
[n
], n
);
211 pl011_init(0x101f1000, pic
[12], serial_hds
[0], PL011_ARM
);
212 pl011_init(0x101f2000, pic
[13], serial_hds
[1], PL011_ARM
);
213 pl011_init(0x101f3000, pic
[14], serial_hds
[2], PL011_ARM
);
214 pl011_init(0x10009000, sic
[6], serial_hds
[3], PL011_ARM
);
216 pl080_init(0x10130000, pic
[17], 8);
217 sp804_init(0x101e2000, pic
[4]);
218 sp804_init(0x101e3000, pic
[5]);
220 /* The versatile/PB actually has a modified Color LCD controller
221 that includes hardware cursor support from the PL111. */
222 pl110_init(ds
, 0x10120000, pic
[16], 1);
224 pl181_init(0x10005000, sd_bdrv
, sic
[22], sic
[1]);
226 /* Disabled because there's no way of specifying a block device. */
227 pl181_init(0x1000b000, NULL
, sic
, 23, 2);
230 /* Add PL031 Real Time Clock. */
231 pl031_init(0x101e8000,pic
[10]);
233 /* Memory map for Versatile/PB: */
234 /* 0x10000000 System registers. */
235 /* 0x10001000 PCI controller config registers. */
236 /* 0x10002000 Serial bus interface. */
237 /* 0x10003000 Secondary interrupt controller. */
238 /* 0x10004000 AACI (audio). */
239 /* 0x10005000 MMCI0. */
240 /* 0x10006000 KMI0 (keyboard). */
241 /* 0x10007000 KMI1 (mouse). */
242 /* 0x10008000 Character LCD Interface. */
243 /* 0x10009000 UART3. */
244 /* 0x1000a000 Smart card 1. */
245 /* 0x1000b000 MMCI1. */
246 /* 0x10010000 Ethernet. */
247 /* 0x10020000 USB. */
248 /* 0x10100000 SSMC. */
249 /* 0x10110000 MPMC. */
250 /* 0x10120000 CLCD Controller. */
251 /* 0x10130000 DMA Controller. */
252 /* 0x10140000 Vectored interrupt controller. */
253 /* 0x101d0000 AHB Monitor Interface. */
254 /* 0x101e0000 System Controller. */
255 /* 0x101e1000 Watchdog Interface. */
256 /* 0x101e2000 Timer 0/1. */
257 /* 0x101e3000 Timer 2/3. */
258 /* 0x101e4000 GPIO port 0. */
259 /* 0x101e5000 GPIO port 1. */
260 /* 0x101e6000 GPIO port 2. */
261 /* 0x101e7000 GPIO port 3. */
262 /* 0x101e8000 RTC. */
263 /* 0x101f0000 Smart card 0. */
264 /* 0x101f1000 UART0. */
265 /* 0x101f2000 UART1. */
266 /* 0x101f3000 UART2. */
267 /* 0x101f4000 SSPI. */
269 arm_load_kernel(env
, ram_size
, kernel_filename
, kernel_cmdline
,
270 initrd_filename
, board_id
, 0x0);
273 static void vpb_init(int ram_size
, int vga_ram_size
, const char *boot_device
,
274 DisplayState
*ds
, const char **fd_filename
, int snapshot
,
275 const char *kernel_filename
, const char *kernel_cmdline
,
276 const char *initrd_filename
, const char *cpu_model
)
278 versatile_init(ram_size
, vga_ram_size
, boot_device
,
279 ds
, fd_filename
, snapshot
,
280 kernel_filename
, kernel_cmdline
,
281 initrd_filename
, cpu_model
, 0x183);
284 static void vab_init(int ram_size
, int vga_ram_size
, const char *boot_device
,
285 DisplayState
*ds
, const char **fd_filename
, int snapshot
,
286 const char *kernel_filename
, const char *kernel_cmdline
,
287 const char *initrd_filename
, const char *cpu_model
)
289 versatile_init(ram_size
, vga_ram_size
, boot_device
,
290 ds
, fd_filename
, snapshot
,
291 kernel_filename
, kernel_cmdline
,
292 initrd_filename
, cpu_model
, 0x25e);
295 QEMUMachine versatilepb_machine
= {
297 "ARM Versatile/PB (ARM926EJ-S)",
301 QEMUMachine versatileab_machine
= {
303 "ARM Versatile/AB (ARM926EJ-S)",