hw/pl061.c

   1 /*
   2  * Arm PrimeCell PL061 General Purpose IO with additional
   3  * Luminary Micro Stellaris bits.
   4  *
   5  * Copyright (c) 2007 CodeSourcery.
   6  * Written by Paul Brook
   7  *
   8  * This code is licenced under the GPL.
   9  */
  10
  11 #include "vl.h"
  12
  13 //#define DEBUG_PL061 1
  14
  15 #ifdef DEBUG_PL061
  16 #define DPRINTF(fmt, args...) \
  17 do { printf("pl061: " fmt , ##args); } while (0)
  18 #define BADF(fmt, args...) \
  19 do { fprintf(stderr, "pl061: error: " fmt , ##args); exit(1);} while (0)
  20 #else
  21 #define DPRINTF(fmt, args...) do {} while(0)
  22 #define BADF(fmt, args...) \
  23 do { fprintf(stderr, "pl061: error: " fmt , ##args);} while (0)
  24 #endif
  25
  26 static const uint8_t pl061_id[12] =
  27   { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
  28
  29 typedef struct {
  30     uint32_t base;
  31     int locked;
  32     uint8_t data;
  33     uint8_t old_data;
  34     uint8_t dir;
  35     uint8_t isense;
  36     uint8_t ibe;
  37     uint8_t iev;
  38     uint8_t im;
  39     uint8_t istate;
  40     uint8_t afsel;
  41     uint8_t dr2r;
  42     uint8_t dr4r;
  43     uint8_t dr8r;
  44     uint8_t odr;
  45     uint8_t pur;
  46     uint8_t pdr;
  47     uint8_t slr;
  48     uint8_t den;
  49     uint8_t cr;
  50     qemu_irq irq;
  51     qemu_irq out[8];
  52 } pl061_state;
  53
  54 static void pl061_update(pl061_state *s)
  55 {
  56     uint8_t changed;
  57     uint8_t mask;
  58     int i;
  59
  60     changed = s->old_data ^ s->data;
  61     if (!changed)
  62         return;
  63
  64     s->old_data = s->data;
  65     for (i = 0; i < 8; i++) {
  66         mask = 1 << i;
  67         if ((changed & mask & s->dir) && s->out) {
  68             DPRINTF("Set output %d = %d\n", i, (s->data & mask) != 0);
  69             qemu_set_irq(s->out[i], (s->data & mask) != 0);
  70         }
  71     }
  72
  73     /* FIXME: Implement input interrupts.  */
  74 }
  75
  76 static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
  77 {
  78     pl061_state *s = (pl061_state *)opaque;
  79
  80     offset -= s->base;
  81     if (offset >= 0xfd0 && offset < 0x1000) {
  82         return pl061_id[(offset - 0xfd0) >> 2];
  83     }
  84     if (offset < 0x400) {
  85         return s->data & (offset >> 2);
  86     }
  87     switch (offset) {
  88     case 0x400: /* Direction */
  89         return s->dir;
  90     case 0x404: /* Interrupt sense */
  91         return s->isense;
  92     case 0x408: /* Interrupt both edges */
  93         return s->ibe;
  94     case 0x40c: /* Interupt event */
  95         return s->iev;
  96     case 0x410: /* Interrupt mask */
  97         return s->im;
  98     case 0x414: /* Raw interrupt status */
  99         return s->istate;
 100     case 0x418: /* Masked interrupt status */
 101         return s->istate | s->im;
 102     case 0x420: /* Alternate function select */
 103         return s->afsel;
 104     case 0x500: /* 2mA drive */
 105         return s->dr2r;
 106     case 0x504: /* 4mA drive */
 107         return s->dr4r;
 108     case 0x508: /* 8mA drive */
 109         return s->dr8r;
 110     case 0x50c: /* Open drain */
 111         return s->odr;
 112     case 0x510: /* Pull-up */
 113         return s->pur;
 114     case 0x514: /* Pull-down */
 115         return s->pdr;
 116     case 0x518: /* Slew rate control */
 117         return s->slr;
 118     case 0x51c: /* Digital enable */
 119         return s->den;
 120     case 0x520: /* Lock */
 121         return s->locked;
 122     case 0x524: /* Commit */
 123         return s->cr;
 124     default:
 125         cpu_abort (cpu_single_env, "pl061_read: Bad offset %x\n",
 126                    (int)offset);
 127         return 0;
 128     }
 129 }
 130
 131 static void pl061_write(void *opaque, target_phys_addr_t offset,
 132                         uint32_t value)
 133 {
 134     pl061_state *s = (pl061_state *)opaque;
 135     uint8_t mask;
 136
 137     offset -= s->base;
 138     if (offset < 0x400) {
 139         mask = (offset >> 2) & s->dir;
 140         s->data = (s->data & ~mask) | (value & mask);
 141         pl061_update(s);
 142         return;
 143     }
 144     switch (offset) {
 145     case 0x400: /* Direction */
 146         s->dir = value;
 147         break;
 148     case 0x404: /* Interrupt sense */
 149         s->isense = value;
 150         break;
 151     case 0x408: /* Interrupt both edges */
 152         s->ibe = value;
 153         break;
 154     case 0x40c: /* Interupt event */
 155         s->iev = value;
 156         break;
 157     case 0x410: /* Interrupt mask */
 158         s->im = value;
 159         break;
 160     case 0x41c: /* Interrupt clear */
 161         s->istate &= ~value;
 162         break;
 163     case 0x420: /* Alternate function select */
 164         mask = s->cr;
 165         s->afsel = (s->afsel & ~mask) | (value & mask);
 166         break;
 167     case 0x500: /* 2mA drive */
 168         s->dr2r = value;
 169         break;
 170     case 0x504: /* 4mA drive */
 171         s->dr4r = value;
 172         break;
 173     case 0x508: /* 8mA drive */
 174         s->dr8r = value;
 175         break;
 176     case 0x50c: /* Open drain */
 177         s->odr = value;
 178         break;
 179     case 0x510: /* Pull-up */
 180         s->pur = value;
 181         break;
 182     case 0x514: /* Pull-down */
 183         s->pdr = value;
 184         break;
 185     case 0x518: /* Slew rate control */
 186         s->slr = value;
 187         break;
 188     case 0x51c: /* Digital enable */
 189         s->den = value;
 190         break;
 191     case 0x520: /* Lock */
 192         s->locked = (value != 0xacce551);
 193         break;
 194     case 0x524: /* Commit */
 195         if (!s->locked)
 196             s->cr = value;
 197         break;
 198     default:
 199         cpu_abort (cpu_single_env, "pl061_write: Bad offset %x\n",
 200                    (int)offset);
 201     }
 202     pl061_update(s);
 203 }
 204
 205 static void pl061_reset(pl061_state *s)
 206 {
 207   s->locked = 1;
 208   s->cr = 0xff;
 209 }
 210
 211 void pl061_set_irq(void * opaque, int irq, int level)
 212 {
 213     pl061_state *s = (pl061_state *)opaque;
 214     uint8_t mask;
 215
 216     mask = 1 << irq;
 217     if ((s->dir & mask) == 0) {
 218         s->data &= ~mask;
 219         if (level)
 220             s->data |= mask;
 221         pl061_update(s);
 222     }
 223 }
 224
 225 static CPUReadMemoryFunc *pl061_readfn[] = {
 226    pl061_read,
 227    pl061_read,
 228    pl061_read
 229 };
 230
 231 static CPUWriteMemoryFunc *pl061_writefn[] = {
 232    pl061_write,
 233    pl061_write,
 234    pl061_write
 235 };
 236
 237 /* Returns an array of inputs.  */
 238 qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out)
 239 {
 240     int iomemtype;
 241     pl061_state *s;
 242
 243     s = (pl061_state *)qemu_mallocz(sizeof(pl061_state));
 244     iomemtype = cpu_register_io_memory(0, pl061_readfn,
 245                                        pl061_writefn, s);
 246     cpu_register_physical_memory(base, 0x00001000, iomemtype);
 247     s->base = base;
 248     s->irq = irq;
 249     pl061_reset(s);
 250     if (out)
 251         *out = s->out;
 252
 253     /* ??? Save/restore.  */
 254     return qemu_allocate_irqs(pl061_set_irq, s, 8);
 255 }
 256