2 * Arm PrimeCell PL022 Synchronous Serial Port
4 * Copyright (c) 2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
12 //#define DEBUG_PL022 1
15 #define DPRINTF(fmt, args...) \
16 do { printf("pl022: " fmt , ##args); } while (0)
17 #define BADF(fmt, args...) \
18 do { fprintf(stderr, "pl022: error: " fmt , ##args); exit(1);} while (0)
20 #define DPRINTF(fmt, args...) do {} while(0)
21 #define BADF(fmt, args...) \
22 do { fprintf(stderr, "pl022: error: " fmt , ##args);} while (0)
25 #define PL022_CR1_LBM 0x01
26 #define PL022_CR1_SSE 0x02
27 #define PL022_CR1_MS 0x04
28 #define PL022_CR1_SDO 0x08
30 #define PL022_SR_TFE 0x01
31 #define PL022_SR_TNF 0x02
32 #define PL022_SR_RNE 0x04
33 #define PL022_SR_RFF 0x08
34 #define PL022_SR_BSY 0x10
36 #define PL022_INT_ROR 0x01
37 #define PL022_INT_RT 0x04
38 #define PL022_INT_RX 0x04
39 #define PL022_INT_TX 0x08
50 /* The FIFO head points to the next empty entry. */
58 int (*xfer_cb
)(void *, int);
62 static const unsigned char pl022_id
[8] =
63 { 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
65 static void pl022_update(pl022_state
*s
)
68 if (s
->tx_fifo_len
== 0)
69 s
->sr
|= PL022_SR_TFE
;
70 if (s
->tx_fifo_len
!= 8)
71 s
->sr
|= PL022_SR_TNF
;
72 if (s
->rx_fifo_len
!= 0)
73 s
->sr
|= PL022_SR_RNE
;
74 if (s
->rx_fifo_len
== 8)
75 s
->sr
|= PL022_SR_RFF
;
77 s
->sr
|= PL022_SR_BSY
;
79 if (s
->rx_fifo_len
>= 4)
80 s
->is
|= PL022_INT_RX
;
81 if (s
->tx_fifo_len
<= 4)
82 s
->is
|= PL022_INT_TX
;
84 qemu_set_irq(s
->irq
, (s
->is
& s
->im
) != 0);
87 static void pl022_xfer(pl022_state
*s
)
93 if ((s
->cr1
& PL022_CR1_SSE
) == 0) {
95 DPRINTF("Disabled\n");
99 DPRINTF("Maybe xfer %d/%d\n", s
->tx_fifo_len
, s
->rx_fifo_len
);
100 i
= (s
->tx_fifo_head
- s
->tx_fifo_len
) & 7;
102 /* ??? We do not emulate the line speed.
103 This may break some applications. The are two problematic cases:
104 (a) A driver feeds data into the TX FIFO until it is full,
105 and only then drains the RX FIFO. On real hardware the CPU can
106 feed data fast enough that the RX fifo never gets chance to overflow.
107 (b) A driver transmits data, deliberately allowing the RX FIFO to
108 overflow because it ignores the RX data anyway.
110 We choose to support (a) by stalling the transmit engine if it would
111 cause the RX FIFO to overflow. In practice much transmit-only code
112 falls into (a) because it flushes the RX FIFO to determine when
113 the transfer has completed. */
114 while (s
->tx_fifo_len
&& s
->rx_fifo_len
< 8) {
117 if (s
->cr1
& PL022_CR1_LBM
) {
119 } else if (s
->xfer_cb
) {
120 val
= s
->xfer_cb(s
->opaque
, val
);
124 s
->rx_fifo
[o
] = val
& s
->bitmask
;
134 static uint32_t pl022_read(void *opaque
, target_phys_addr_t offset
)
136 pl022_state
*s
= (pl022_state
*)opaque
;
140 if (offset
>= 0xfe0 && offset
< 0x1000) {
141 return pl022_id
[(offset
- 0xfe0) >> 2];
149 if (s
->rx_fifo_len
) {
150 val
= s
->rx_fifo
[(s
->rx_fifo_head
- s
->rx_fifo_len
) & 7];
151 DPRINTF("RX %02x\n", val
);
160 case 0x10: /* CPSR */
162 case 0x14: /* IMSC */
167 return s
->im
& s
->is
;
168 case 0x20: /* DMACR */
169 /* Not implemented. */
172 cpu_abort (cpu_single_env
, "pl022_read: Bad offset %x\n",
178 static void pl022_write(void *opaque
, target_phys_addr_t offset
,
181 pl022_state
*s
= (pl022_state
*)opaque
;
187 /* Clock rate and format are ignored. */
188 s
->bitmask
= (1 << ((value
& 15) + 1)) - 1;
192 if ((s
->cr1
& (PL022_CR1_MS
| PL022_CR1_SSE
))
193 == (PL022_CR1_MS
| PL022_CR1_SSE
)) {
194 BADF("SPI slave mode not implemented\n");
199 if (s
->tx_fifo_len
< 8) {
200 DPRINTF("TX %02x\n", value
);
201 s
->tx_fifo
[s
->tx_fifo_head
] = value
& s
->bitmask
;
202 s
->tx_fifo_head
= (s
->tx_fifo_head
+ 1) & 7;
207 case 0x10: /* CPSR */
208 /* Prescaler. Ignored. */
209 s
->cpsr
= value
& 0xff;
211 case 0x14: /* IMSC */
215 case 0x20: /* DMACR */
217 cpu_abort (cpu_single_env
, "pl022: DMA not implemented\n");
220 cpu_abort (cpu_single_env
, "pl022_write: Bad offset %x\n",
225 static void pl022_reset(pl022_state
*s
)
230 s
->is
= PL022_INT_TX
;
231 s
->sr
= PL022_SR_TFE
| PL022_SR_TNF
;
234 static CPUReadMemoryFunc
*pl022_readfn
[] = {
240 static CPUWriteMemoryFunc
*pl022_writefn
[] = {
246 void pl022_init(uint32_t base
, qemu_irq irq
, int (*xfer_cb
)(void *, int),
252 s
= (pl022_state
*)qemu_mallocz(sizeof(pl022_state
));
253 iomemtype
= cpu_register_io_memory(0, pl022_readfn
,
255 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
258 s
->xfer_cb
= xfer_cb
;
261 /* ??? Save/restore. */