hw/armv7m_nvic.c

   1 /*
   2  * ARM Nested Vectored Interrupt Controller
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL.
   8  *
   9  * The ARMv7M System controller is fairly tightly tied in with the
  10  * NVIC.  Much of that is also implemented here.
  11  */
  12
  13 #include "vl.h"
  14 #include "arm_pic.h"
  15
  16 #define GIC_NIRQ 64
  17 #define NCPU 1
  18 #define NVIC 1
  19
  20 /* Only a single "CPU" interface is present.  */
  21 static inline int
  22 gic_get_current_cpu(void)
  23 {
  24     return 0;
  25 }
  26
  27 static uint32_t nvic_readl(void *opaque, uint32_t offset);
  28 static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);
  29
  30 #include "arm_gic.c"
  31
  32 typedef struct {
  33     struct {
  34         uint32_t control;
  35         uint32_t reload;
  36         int64_t tick;
  37         QEMUTimer *timer;
  38     } systick;
  39     gic_state *gic;
  40 } nvic_state;
  41
  42 /* qemu timers run at 1GHz.   We want something closer to 1MHz.  */
  43 #define SYSTICK_SCALE 1000ULL
  44
  45 #define SYSTICK_ENABLE    (1 << 0)
  46 #define SYSTICK_TICKINT   (1 << 1)
  47 #define SYSTICK_CLKSOURCE (1 << 2)
  48 #define SYSTICK_COUNTFLAG (1 << 16)
  49
  50 /* Conversion factor from qemu timer to SysTick frequencies.
  51    QEMU uses a base of 1GHz, so these give 20MHz and 1MHz for core and
  52    reference frequencies.  */
  53
  54 static inline int64_t systick_scale(nvic_state *s)
  55 {
  56     if (s->systick.control & SYSTICK_CLKSOURCE)
  57         return 50;
  58     else
  59         return 1000;
  60 }
  61
  62 static void systick_reload(nvic_state *s, int reset)
  63 {
  64     if (reset)
  65         s->systick.tick = qemu_get_clock(vm_clock);
  66     s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
  67     qemu_mod_timer(s->systick.timer, s->systick.tick);
  68 }
  69
  70 static void systick_timer_tick(void * opaque)
  71 {
  72     nvic_state *s = (nvic_state *)opaque;
  73     s->systick.control |= SYSTICK_COUNTFLAG;
  74     if (s->systick.control & SYSTICK_TICKINT) {
  75         /* Trigger the interrupt.  */
  76         armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
  77     }
  78     if (s->systick.reload == 0) {
  79         s->systick.control &= ~SYSTICK_ENABLE;
  80     } else {
  81         systick_reload(s, 0);
  82     }
  83 }
  84
  85 /* The external routines use the hardware vector numbering, ie. the first
  86    IRQ is #16.  The internal GIC routines use #32 as the first IRQ.  */
  87 void armv7m_nvic_set_pending(void *opaque, int irq)
  88 {
  89     nvic_state *s = (nvic_state *)opaque;
  90     if (irq >= 16)
  91         irq += 16;
  92     gic_set_pending_private(s->gic, 0, irq);
  93 }
  94
  95 /* Make pending IRQ active.  */
  96 int armv7m_nvic_acknowledge_irq(void *opaque)
  97 {
  98     nvic_state *s = (nvic_state *)opaque;
  99     uint32_t irq;
 100
 101     irq = gic_acknowledge_irq(s->gic, 0);
 102     if (irq == 1023)
 103         cpu_abort(cpu_single_env, "Interrupt but no vector\n");
 104     if (irq >= 32)
 105         irq -= 16;
 106     return irq;
 107 }
 108
 109 void armv7m_nvic_complete_irq(void *opaque, int irq)
 110 {
 111     nvic_state *s = (nvic_state *)opaque;
 112     if (irq >= 16)
 113         irq += 16;
 114     gic_complete_irq(s->gic, 0, irq);
 115 }
 116
 117 static uint32_t nvic_readl(void *opaque, uint32_t offset)
 118 {
 119     nvic_state *s = (nvic_state *)opaque;
 120     uint32_t val;
 121     int irq;
 122
 123     switch (offset) {
 124     case 4: /* Interrupt Control Type.  */
 125         return (GIC_NIRQ / 32) - 1;
 126     case 0x10: /* SysTick Control and Status.  */
 127         val = s->systick.control;
 128         s->systick.control &= ~SYSTICK_COUNTFLAG;
 129         return val;
 130     case 0x14: /* SysTick Reload Value.  */
 131         return s->systick.reload;
 132     case 0x18: /* SysTick Current Value.  */
 133         {
 134             int64_t t;
 135             if ((s->systick.control & SYSTICK_ENABLE) == 0)
 136                 return 0;
 137             t = qemu_get_clock(vm_clock);
 138             if (t >= s->systick.tick)
 139                 return 0;
 140             val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
 141             /* The interrupt in triggered when the timer reaches zero.
 142                However the counter is not reloaded until the next clock
 143                tick.  This is a hack to return zero during the first tick.  */
 144             if (val > s->systick.reload)
 145                 val = 0;
 146             return val;
 147         }
 148     case 0x1c: /* SysTick Calibration Value.  */
 149         return 10000;
 150     case 0xd00: /* CPUID Base.  */
 151         return cpu_single_env->cp15.c0_cpuid;
 152     case 0xd04: /* Interrypt Control State.  */
 153         /* VECTACTIVE */
 154         val = s->gic->running_irq[0];
 155         if (val == 1023) {
 156             val = 0;
 157         } else if (val >= 32) {
 158             val -= 16;
 159         }
 160         /* RETTOBASE */
 161         if (s->gic->running_irq[0] == 1023
 162                 || s->gic->last_active[s->gic->running_irq[0]][0] == 1023) {
 163             val |= (1 << 11);
 164         }
 165         /* VECTPENDING */
 166         if (s->gic->current_pending[0] != 1023)
 167             val |= (s->gic->current_pending[0] << 12);
 168         /* ISRPENDING */
 169         for (irq = 32; irq < GIC_NIRQ; irq++) {
 170             if (s->gic->irq_state[irq].pending) {
 171                 val |= (1 << 22);
 172                 break;
 173             }
 174         }
 175         /* PENDSTSET */
 176         if (s->gic->irq_state[ARMV7M_EXCP_SYSTICK].pending)
 177             val |= (1 << 26);
 178         /* PENDSVSET */
 179         if (s->gic->irq_state[ARMV7M_EXCP_PENDSV].pending)
 180             val |= (1 << 28);
 181         /* NMIPENDSET */
 182         if (s->gic->irq_state[ARMV7M_EXCP_NMI].pending)
 183             val |= (1 << 31);
 184         return val;
 185     case 0xd08: /* Vector Table Offset.  */
 186         return cpu_single_env->v7m.vecbase;
 187     case 0xd0c: /* Application Interrupt/Reset Control.  */
 188         return 0xfa05000;
 189     case 0xd10: /* System Control.  */
 190         /* TODO: Implement SLEEPONEXIT.  */
 191         return 0;
 192     case 0xd14: /* Configuration Control.  */
 193         /* TODO: Implement Configuration Control bits.  */
 194         return 0;
 195     case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
 196         irq = offset - 0xd14;
 197         val = 0;
 198         val = s->gic->priority1[irq++][0];
 199         val = s->gic->priority1[irq++][0] << 8;
 200         val = s->gic->priority1[irq++][0] << 16;
 201         val = s->gic->priority1[irq][0] << 24;
 202         return val;
 203     case 0xd24: /* System Handler Status.  */
 204         val = 0;
 205         if (s->gic->irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
 206         if (s->gic->irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
 207         if (s->gic->irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
 208         if (s->gic->irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
 209         if (s->gic->irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
 210         if (s->gic->irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
 211         if (s->gic->irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
 212         if (s->gic->irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
 213         if (s->gic->irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
 214         if (s->gic->irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
 215         if (s->gic->irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
 216         if (s->gic->irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
 217         if (s->gic->irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
 218         if (s->gic->irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
 219         return val;
 220     case 0xd28: /* Configurable Fault Status.  */
 221         /* TODO: Implement Fault Status.  */
 222         cpu_abort(cpu_single_env,
 223                   "Not implemented: Configurable Fault Status.");
 224         return 0;
 225     case 0xd2c: /* Hard Fault Status.  */
 226     case 0xd30: /* Debug Fault Status.  */
 227     case 0xd34: /* Mem Manage Address.  */
 228     case 0xd38: /* Bus Fault Address.  */
 229     case 0xd3c: /* Aux Fault Status.  */
 230         /* TODO: Implement fault status registers.  */
 231         goto bad_reg;
 232     case 0xd40: /* PFR0.  */
 233         return 0x00000030;
 234     case 0xd44: /* PRF1.  */
 235         return 0x00000200;
 236     case 0xd48: /* DFR0.  */
 237         return 0x00100000;
 238     case 0xd4c: /* AFR0.  */
 239         return 0x00000000;
 240     case 0xd50: /* MMFR0.  */
 241         return 0x00000030;
 242     case 0xd54: /* MMFR1.  */
 243         return 0x00000000;
 244     case 0xd58: /* MMFR2.  */
 245         return 0x00000000;
 246     case 0xd5c: /* MMFR3.  */
 247         return 0x00000000;
 248     case 0xd60: /* ISAR0.  */
 249         return 0x01141110;
 250     case 0xd64: /* ISAR1.  */
 251         return 0x02111000;
 252     case 0xd68: /* ISAR2.  */
 253         return 0x21112231;
 254     case 0xd6c: /* ISAR3.  */
 255         return 0x01111110;
 256     case 0xd70: /* ISAR4.  */
 257         return 0x01310102;
 258     /* TODO: Implement debug registers.  */
 259     default:
 260     bad_reg:
 261         cpu_abort(cpu_single_env, "NVIC: Bad read offset 0x%x\n", offset);
 262     }
 263 }
 264
 265 static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
 266 {
 267     nvic_state *s = (nvic_state *)opaque;
 268     uint32_t oldval;
 269     switch (offset) {
 270     case 0x10: /* SysTick Control and Status.  */
 271         oldval = s->systick.control;
 272         s->systick.control &= 0xfffffff8;
 273         s->systick.control |= value & 7;
 274         if ((oldval ^ value) & SYSTICK_ENABLE) {
 275             int64_t now = qemu_get_clock(vm_clock);
 276             if (value & SYSTICK_ENABLE) {
 277                 if (s->systick.tick) {
 278                     s->systick.tick += now;
 279                     qemu_mod_timer(s->systick.timer, s->systick.tick);
 280                 } else {
 281                     systick_reload(s, 1);
 282                 }
 283             } else {
 284                 qemu_del_timer(s->systick.timer);
 285                 s->systick.tick -= now;
 286                 if (s->systick.tick < 0)
 287                   s->systick.tick = 0;
 288             }
 289         } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
 290             /* This is a hack. Force the timer to be reloaded
 291                when the reference clock is changed.  */
 292             systick_reload(s, 1);
 293         }
 294         break;
 295     case 0x14: /* SysTick Reload Value.  */
 296         s->systick.reload = value;
 297         break;
 298     case 0x18: /* SysTick Current Value.  Writes reload the timer.  */
 299         systick_reload(s, 1);
 300         s->systick.control &= ~SYSTICK_COUNTFLAG;
 301         break;
 302     case 0xd04: /* Interrupt Control State.  */
 303         if (value & (1 << 31)) {
 304             armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
 305         }
 306         if (value & (1 << 28)) {
 307             armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
 308         } else if (value & (1 << 27)) {
 309             s->gic->irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
 310             gic_update(s->gic);
 311         }
 312         if (value & (1 << 26)) {
 313             armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
 314         } else if (value & (1 << 25)) {
 315             s->gic->irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
 316             gic_update(s->gic);
 317         }
 318         break;
 319     case 0xd08: /* Vector Table Offset.  */
 320         cpu_single_env->v7m.vecbase = value & 0xffffff80;
 321         break;
 322     case 0xd0c: /* Application Interrupt/Reset Control.  */
 323         if ((value >> 16) == 0x05fa) {
 324             if (value & 2) {
 325                 cpu_abort(cpu_single_env, "VECTCLRACTIVE not implemented");
 326             }
 327             if (value & 5) {
 328                 cpu_abort(cpu_single_env, "System reset");
 329             }
 330         }
 331         break;
 332     case 0xd10: /* System Control.  */
 333     case 0xd14: /* Configuration Control.  */
 334         /* TODO: Implement control registers.  */
 335         goto bad_reg;
 336     case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
 337         {
 338             int irq;
 339             irq = offset - 0xd14;
 340             s->gic->priority1[irq++][0] = value & 0xff;
 341             s->gic->priority1[irq++][0] = (value >> 8) & 0xff;
 342             s->gic->priority1[irq++][0] = (value >> 16) & 0xff;
 343             s->gic->priority1[irq][0] = (value >> 24) & 0xff;
 344             gic_update(s->gic);
 345         }
 346         break;
 347     case 0xd24: /* System Handler Control.  */
 348         /* TODO: Real hardware allows you to set/clear the active bits
 349            under some circumstances.  We don't implement this.  */
 350         s->gic->irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
 351         s->gic->irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
 352         s->gic->irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
 353         break;
 354     case 0xd28: /* Configurable Fault Status.  */
 355     case 0xd2c: /* Hard Fault Status.  */
 356     case 0xd30: /* Debug Fault Status.  */
 357     case 0xd34: /* Mem Manage Address.  */
 358     case 0xd38: /* Bus Fault Address.  */
 359     case 0xd3c: /* Aux Fault Status.  */
 360         goto bad_reg;
 361     default:
 362     bad_reg:
 363         cpu_abort(cpu_single_env, "NVIC: Bad write offset 0x%x\n", offset);
 364     }
 365 }
 366
 367 qemu_irq *armv7m_nvic_init(CPUState *env)
 368 {
 369     nvic_state *s;
 370     qemu_irq *parent;
 371
 372     parent = arm_pic_init_cpu(env);
 373     s = (nvic_state *)qemu_mallocz(sizeof(nvic_state));
 374     s->gic = gic_init(0xe000e000, &parent[ARM_PIC_CPU_IRQ]);
 375     s->gic->nvic = s;
 376     s->systick.timer = qemu_new_timer(vm_clock, systick_timer_tick, s);
 377     if (env->v7m.nvic)
 378         cpu_abort(env, "CPU can only have one NVIC\n");
 379     env->v7m.nvic = s;
 380     return s->gic->in;
 381 }